Semiconductor integrated circuit devices

Abstract

The terminal unit (C11) includes: nanosheets (122a, 123a) formed at the same positions as the nanosheets (22a, 23a) in the Y direction, and dummy gate wirings (143, 146) surrounding the outer peripheries of the nanosheets (122a, 123) in the Y direction. The surfaces of one side of the nanosheets (22a, 122a) in the Y direction are exposed from the gate wiring (41) and the dummy gate wiring (142). The surfaces of one side of the nanosheets (23a, 123a) in the Y direction are exposed from the gate wiring (43) and the dummy gate wiring (146).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit device including a standard cell (hereinafter also appropriately referred to as a cell), wherein the standard cell includes a nanosheet FET (Field Effect Transistor).

[0002] As a method for forming a semiconductor integrated circuit on a semiconductor substrate, a standard cell method is known. The standard cell method refers to the design of an LSI (large-scale integrated circuit) chip by preparing basic cells (such as inverters, latches, flip-flops, full adders, etc.) with specific logical functions as standard cells in advance, arranging multiple standard cells on a semiconductor substrate, and connecting these standard cells with wiring.

[0003] Transistors, the basic components of LSI, have achieved increased integration, lower operating voltage, and higher operating speed by reducing gate length (scaling). However, in recent years, the problem has arisen that excessive scaling will cause cutoff current, which in turn will cause a significant increase in power consumption. To solve this problem, people have begun to actively study three-dimensional transistors, that is, to change the transistor structure from the existing planar type to a three-dimensional type. Nanosheet FET (nanowire FET) has attracted much attention as one of the three-dimensional transistors.

[0004] Among nanosheet FETs, a fork sheet transistor having a fork-shaped gate electrode is advocated. Non-patent document 1 discloses a layout of an SRAM memory cell using a fork sheet transistor, which achieves a reduction in the area of ​​a semiconductor integrated circuit device (semiconductor memory device).

[0005] Non-patent literature 1: P. Weckx et al., “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm”, 2017 IEEE International Electron Devices Meeting (IEDM), December 2017, IEDM17-505~508 Summary of the invention

[0006] -Technical problem to be solved by the invention-

[0007] In this specification, a nanosheet FET with a forked gate electrode is referred to as a fork-sheet transistor according to the prior art.

[0008] Here, standard cells include cells without logic functions, in addition to cells with logic functions such as "NAND gates" and "NOR gates" (hereinafter appropriately referred to as logic cells). Cells without logic functions include "terminal cells". "Terminal cells" refer to cells that do not contribute to the logic functions of a circuit block and are used to terminate a circuit block. By arranging terminal cells, it is possible to suppress the deviation of the finished shape of the layout pattern of cells located on the inner side of the terminal cells, thereby suppressing the manufacturing deviation of semiconductor integrated circuit devices, improving the yield, and improving the reliability.

[0009] To date, no specific research has been conducted on the structure of a terminal unit using a fork-chip transistor or the layout of a semiconductor integrated circuit device including a terminal unit using a fork-chip transistor.

[0010] The present disclosure provides a layout of a semiconductor integrated circuit device including a terminal unit using a fork-chip transistor.

[0011] -Technical solutions to technical problems-

[0012] In a first aspect of the present disclosure, a semiconductor integrated circuit device includes a plurality of cell rows, each of which includes a plurality of standard cells arranged in a first direction, one of the plurality of cell rows, namely a first cell row, includes a first standard cell and a second standard cell, the first standard cell having a logic function, and the second standard cell being arranged at at least one of the two ends of the first cell row and not having a logic function. The first standard cell includes a first region, a second region, a first nanosheet, a second nanosheet, a first gate wiring, and a second gate wiring, the first region being a formation region of a first conductive type transistor, the second region being a formation region of a second conductive type transistor different from the first conductive type, the second region being adjacent to the first region in a second direction perpendicular to the first direction, the first nanosheet extending in the first direction and formed in the first region, the second nanosheet extending in the first direction and formed in the second region, the first gate wiring extending in the second direction and surrounding the outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions, and the second gate wiring extending in the second direction and surrounding the outer periphery of the second nanosheet in the second direction and in the third direction. The second standard cell includes a third nanosheet, a fourth nanosheet, a first dummy gate wiring, and a second dummy gate wiring. The third nanosheet extends in the first direction and is formed at the same position as the first nanosheet in the second direction. The fourth nanosheet extends in the first direction and is formed at the same position as the second nanosheet in the second direction. The first dummy gate wiring extends in the second direction and surrounds the outer periphery of the third nanosheet in the second and third directions. The second dummy gate wiring extends in the second direction and surrounds the outer periphery of the fourth nanosheet in the second and third directions. A surface of the first nanosheet on one side in the second direction, i.e., the first side, is exposed from the first gate wiring. A surface of the second nanosheet on one side in the second direction, i.e., the second side, is exposed from the second gate wiring. A surface of the first side in the second direction of the third nanosheet is exposed from the first dummy gate wiring. A surface of the second side in the second direction of the fourth nanosheet is exposed from the second dummy gate wiring.

[0013] According to this aspect, the second standard cell without logic function is arranged at least one of the two ends of the first cell row, and the first cell row is arranged with the first standard cell with logic function. The first standard cell includes a first nanosheet and a second nanosheet, and a first gate wiring and a second gate wiring respectively surrounding the outer periphery of the first nanosheet and the second nanosheet in the second direction. The second standard cell includes a third nanosheet and a fourth nanosheet, and a third gate wiring and a fourth gate wiring respectively surrounding the outer periphery of the third nanosheet and the fourth nanosheet in the second direction. The first nanosheet and the third nanosheet on one side in the second direction, that is, the first side of the surface is exposed from the first gate wiring and the first dummy gate wiring respectively. The second nanosheet and the fourth nanosheet on one side in the second direction, that is, the second side of the surface is exposed from the second gate wiring and the second dummy gate wiring respectively. That is, the first nanosheet and the third nanosheet on the same side of the surface in the second direction are exposed, and the second nanosheet and the fourth nanosheet on the same side of the surface in the second direction are exposed. In this way, it is possible to suppress the manufacturing deviation of the semiconductor integrated circuit device, improve the yield rate, and improve the reliability.

[0014] In a second aspect of the present disclosure, a plurality of cell rows are included, each of the plurality of cell rows includes a plurality of standard cells arranged along a first direction, the plurality of cell rows are arranged along a second direction perpendicular to the first direction, the plurality of cell rows include a first cell row and a second cell row, the first cell row includes a first standard cell having a logic function, the second cell row includes a second standard cell, in the plurality of cell rows, the second standard cell is arranged at either end of the two ends in the second direction and does not have a logic function. The first standard cell includes a first region, a second region, a first nanosheet, a second nanosheet, a first gate wiring, and a second gate wiring, the first region is a formation region of a first conductive type transistor, the second region is a formation region of a second conductive type transistor different from the first conductive type, the second region is adjacent to the first region in the second direction, the first nanosheet extends along the first direction and is formed in the first region, the second nanosheet extends along the first direction and is formed in the second region and is formed at the same position as the first nanosheet in the first direction, the first gate wiring extends along the second direction and surrounds the outer periphery of the first nanosheet in the second direction and the third direction, and the second gate wiring extends along the second direction and surrounds the outer periphery of the second nanosheet in the second direction and the third direction. The second standard cell includes a third nanosheet and a first dummy gate wiring, wherein the third nanosheet extends in a first direction and is formed at the same position as the first nanosheet in the first direction and is formed adjacent to the first nanosheet in the second direction, and the first dummy gate wiring extends in a second direction and surrounds the outer periphery of the third nanosheet in the second direction and the third direction. A surface of the first nanosheet on one side in the second direction, i.e., the first side, is exposed from the first gate wiring. A surface of the second nanosheet on one side in the second direction, i.e., the second side, is exposed from the second gate wiring. Surfaces of the first nanosheet and the third nanosheet on one side opposite to each other are exposed from the first gate wiring and the first dummy gate wiring, respectively, or surfaces of the first nanosheet and the third nanosheet on one side opposite to each other are not exposed from the first gate wiring and the first dummy gate wiring, respectively.

[0015] According to this aspect, in a plurality of cell rows including a cell row including a first standard cell having a logic function, a second standard cell without a logic function is arranged in a cell row at either end in the second direction. The first standard cell includes a first nanosheet, a second nanosheet, a first gate wiring, and a second gate wiring, the second nanosheet is formed at the same position as the first nanosheet in the first direction, and the first gate wiring and the second gate wiring surround the periphery of the first nanosheet and the second nanosheet, respectively. The second standard cell includes a third nanosheet and a first dummy gate wiring, the third nanosheet is formed at the same position as the first nanosheet in the first direction, and the first dummy gate wiring surrounds the periphery of the third nanosheet. A surface of one side of the first nanosheet in the second direction, that is, the first side, is exposed from the first gate wiring. A surface of one side of the second nanosheet in the second direction, that is, the second side, is exposed from the second gate wiring. The surfaces of the first nanosheet and the third nanosheet on one side opposite to each other are exposed from the first gate wiring and the first dummy gate wiring, respectively, or the surfaces of the first nanosheet and the third nanosheet on one side opposite to each other are not exposed from the first gate wiring and the first dummy gate wiring, respectively. That is, when the surface of the first nanosheet opposite to the third nanosheet is not surrounded by the first gate wiring, the surface of the third nanosheet opposite to the first nanosheet is not surrounded by the first dummy gate wiring. On the other hand, when the surface of the first nanosheet opposite to the third nanosheet is surrounded by the first gate wiring, the surface of the third nanosheet opposite to the first nanosheet is surrounded by the first dummy gate wiring. In this way, the manufacturing variation of the semiconductor integrated circuit device can be suppressed, the yield rate can be improved, and the reliability can be improved.

[0016] -Effects of the Invention-

[0017] According to the present disclosure, it is possible to suppress manufacturing variations, improve yield, and improve reliability of a semiconductor integrated circuit device including a terminal unit using a fork transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a top view showing an example of a layout structure of a circuit block using a standard cell;

[0019] Figure 2 is a top view showing the layout structure of the logic unit;

[0020] Figure 3 is a cross-sectional view showing the layout structure of a logic unit;

[0021] Figure 4 is a top view showing a specific example of the layout structure of a logic unit;

[0022] Figure 5is a cross-sectional view showing a specific example of the layout structure of a logic unit;

[0023] Figure 6 It is the circuit diagram of the logic unit;

[0024] Figure 7 is a plan view showing a layout structure of a semiconductor integrated circuit device according to the first embodiment;

[0025] Figure 8 is a cross-sectional view showing the layout structure of a terminal unit involved in the first embodiment;

[0026] Fig. 9 is a diagram showing a layout structure of a logic unit according to a modification of the first embodiment;

[0027] Fig.10 is a diagram showing a layout structure of a terminal unit according to a modified example of the first embodiment;

[0028] Fig.11 is a plan view showing a layout structure of a semiconductor integrated circuit device according to a second embodiment;

[0029] Fig.12 is a cross-sectional view showing a layout structure of a terminal unit according to a second embodiment;

[0030] Fig.13 is a plan view showing a change in the layout structure of the terminal unit involved in the second embodiment;

[0031] Fig.14 is a plan view showing a change in the layout structure of the terminal unit involved in the second embodiment;

[0032] Fig.15 : is a diagram showing the basic structure of a fork-piece FET. DETAILED DESCRIPTION

[0033] The following embodiments are described with reference to the accompanying drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (appropriately referred to as cells in this specification), and at least a portion of the plurality of standard cells includes a forked-sheet transistor whose gate electrode is forked in a nanosheet FET (nanowire FET). A nanosheet FET is a FET formed using a thin sheet (nanosheet) for current to flow. The nanosheet is formed of, for example, silicon. In the semiconductor integrated circuit device, a portion of the nanosheet FET is a forked-sheet FET whose gate electrode is forked.

[0034] In the present disclosure, the semiconductor layer portions formed at both ends of the nanosheet and constituting the terminals that become the source or drain of the nanosheet FET are referred to as "pads". Figure 1 In the top view, the horizontal direction of the drawing is set as the X direction (equivalent to the first direction), the vertical direction of the drawing is set as the Y direction (equivalent to the second direction), and the direction perpendicular to the substrate surface is set as the Z direction (equivalent to the third direction).

[0035] (Fork structure)

[0036] Fig.15 1 is a diagram showing the basic structure of a fork-chip FET, (a) is a top view, and (b) is a cross-sectional view taken along line YY' in (a). Fig.15 In the basic structure, two transistors TR1 and TR2 are arranged in the Y direction with a spacing S therebetween. A gate wiring 531 serving as the gate of the transistor TR1 and a gate wiring 532 serving as the gate of the transistor TR2 extend in the Y direction and are arranged at the same position in the X direction.

[0037] The channel portion 521 that becomes the channel region of the transistor TR1 and the channel portion 526 that becomes the channel region of the transistor TR2 are formed of nanosheets. Fig.15 In the embodiment, the channel portions 521 and 526 are respectively composed of nanosheets, and the nanosheets are formed of three sheet structures that overlap when viewed from above. On both sides of the channel portion 521 in the X direction, pads 522a and 522b that become the source region or drain region of the transistor TR1 are formed. On both sides of the channel portion 526 in the X direction, pads 527a and 527b that become the source region or drain region of the transistor TR2 are formed. The pads 522a and 522b are formed by epitaxial growth of the nanosheets that constitute the channel portion 521. The pads 527a and 527b are formed by epitaxial growth of the nanosheets that constitute the channel portion 526.

[0038] The gate wiring 531 surrounds the outer periphery of the channel portion 521 formed by the nanosheet in the Y direction and the Z direction via a gate insulating film (not shown). However, the surface of the nanosheet forming the channel portion 521 on the transistor TR2 side in the Y direction is not covered by the gate wiring 531 but is exposed from the gate wiring 531. Fig.15 In the cross-sectional view of (b), the gate wiring 531 does not cover the right side of the nanosheet constituting the channel portion 521, but covers the upper, left, and lower sides of the drawing. The gate wiring 531 overlaps the nanosheet constituting the channel portion 521 on the side opposite to the transistor TR2 in the Y direction, and the overlap amount is a length OL.

[0039] The gate wiring 532 surrounds the outer periphery of the channel portion 526 formed by the nanosheet in the Y direction and the Z direction via a gate insulating film (not shown). However, the surface of the nanosheet forming the channel portion 526 on the transistor TR1 side in the Y direction is not covered by the gate wiring 532 but is exposed from the gate wiring 532. Fig.15 In the cross-sectional view of (b), the gate wiring 532 does not cover the left side of the nanosheet constituting the channel portion 526, but covers the upper, right, and lower sides of the nanosheet constituting the channel portion 526. The gate wiring 532 overlaps the nanosheet constituting the channel portion 526 on the side opposite to the transistor TR1 in the Y direction, and the overlap amount is a length OL.

[0040] If the width (dimension in the Y direction) of each nanosheet is set to W and the height (dimension in the Z direction) is set to H, the gate effective width Weff is: Weff=2×W+H.

[0041] Since the channel portion 521 of the transistor TR1 and the channel portion 526 of the transistor TR2 are both composed of three nanosheets, the effective gate width of the transistors TR1 and TR2 is: 3×(2×W+H).

[0042] according to Fig.15 In the structure, the gate wiring 531 does not overlap the transistor TR2 side in the Y direction with respect to the nanosheet constituting the channel portion 521. The gate wiring 532 does not overlap the transistor TR1 side in the Y direction with respect to the nanosheet constituting the channel portion 526. In this way, the transistors TR1 and TR2 can be brought closer, thereby achieving a smaller area.

[0043] It should be noted that the number of nanosheets constituting the channel portion of the transistor is not limited to three. In other words, the nanosheet can be formed by a single sheet structure or by multiple sheet structures that overlap when viewed from above. Fig.15 In (b), the cross-sectional shape of the nanosheet is a rectangle, but the cross-sectional shape of the nanosheet is not limited thereto. For example, the cross-sectional shape of the nanosheet may be a square, a circle, an ellipse, or the like.

[0044] Forksheet FETs and nanosheet FETs may coexist in a semiconductor integrated circuit device, and the entire periphery of the nanosheet of the nanosheet FET is surrounded by gate wiring.

[0045] In this specification, "VDD" and "VSS" refer to power supply voltage or power supply itself. In this specification, expressions such as "same wiring width" and the like, which mean that the width is equal, include a range of manufacturing variations.

[0046] In the top view and cross-sectional view of the following embodiments, the insulating film and the like are sometimes omitted. In the top view and cross-sectional view of the following embodiments, the nanosheet and the pads on both sides thereof are sometimes shown in simplified straight line shapes. In this specification, expressions such as "same size" and the like, which mean that the size and the like are equal, include the range of deviation in manufacturing.

[0047] In this specification, the source and drain of a transistor are appropriately referred to as a “node” of the transistor. That is, one node of a transistor refers to the source or drain of the transistor, and two nodes of a transistor refer to the source and drain of the transistor.

[0048] In the following embodiments and their modifications, the same components and the like are denoted by the same reference numerals and their description may be omitted.

[0049] (Structure of circuit block)

[0050] Figure 1 FIG. 1 is a top view showing the layout structure of a circuit block using standard cells. Figure 1 In FIG. 1 , only the power supply wiring arranged in the standard unit is shown, and the rest are omitted. Figure 1 The solid line surrounding the cell in the plan view of FIG. 1 and the like represents the cell frame (the outer edge of the inverter cell C2 and the like).

[0051] exist Figure 1 In the layout of FIG. 1 , a plurality of cells arranged along the X direction constitute a cell row CR. Figure 1 The cells are arranged in the Y direction in six rows (in the figure). Power supply wiring is formed at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside through the power supply wiring. The power supply wiring for supplying power supply voltages VDD and VSS is turned upside down in the Y direction for every other cell row, and the entire cell is arranged so that every other cell row is turned upside down in the Y direction.

[0052] Figure 1 The multiple units in the circuit include units having logic functions (for example, inverter unit C2, etc.) and terminal units not having logic functions (for example, terminal unit C11, etc.).

[0053] In the present disclosure, a cell having a logic function such as a NAND gate or a NOR gate in the cell, like the inverter cell C2, is appropriately referred to as a "logic cell".

[0054] In the present disclosure, a "terminal unit" refers to a unit that is arranged at the terminal of a circuit block without contributing to the logical function of the circuit block. Here, the "terminal of the circuit block" refers to the two ends of the cell row that constitutes the circuit block (here, the two ends in the X direction), and the top row and the bottom row of the circuit block (here, the cell rows at both ends in the Y direction), etc. In other words, the "terminal unit" is arranged at the terminals of the circuit block, i.e., the two ends in the X direction of the cell row, and the cell rows at both ends in the Y direction, etc. By arranging the terminal unit, the deviation of the finished shape of the layout pattern of the unit located on the inner side of the terminal unit can be suppressed, thereby suppressing the manufacturing deviation of the semiconductor integrated circuit device, improving the yield, and improving the reliability.

[0055] In the present disclosure, a dummy gate wiring is arranged in the terminal unit. Here, the "dummy gate wiring" refers to a gate wiring that does not form a transistor, and a gate wiring that forms a transistor but does not contribute to the logic function of the circuit.

[0056] In the present disclosure, there is a case where an exposed portion is formed on the periphery of a nanosheet arranged in a standard cell. Here, the "exposed portion" refers to a portion of the nanosheet that is not surrounded by a gate wiring (including a dummy gate wiring) and is exposed from the gate wiring (a portion not covered by the gate wiring) in the periphery of the nanosheet in the Y direction and the Z direction.

[0057] exist Figure 1 In the layout of the circuit block, in the center (specifically Figure 1 The logic section LC is formed on the inner side of the thick solid line of FIG. The logic section LC includes a logic unit having a logic function and realizes the circuit function of the circuit block. A terminal unit section is formed along the outer side of the circuit block so as to surround the logic section LC.

[0058] exist Figure 1 In the embodiment, an inverter unit C2 is arranged in the logic unit LC, and terminal units C11, C11a to C11c, C21, C21a to C21c are arranged in the terminal unit unit. Terminal units C11a, C11b, and C11c are formed by turning terminal unit C11 upside down in the Y direction, turning it left and right in the X direction, and turning it upside down and left and right in the X and Y directions. Terminal unit C21a is formed by turning terminal unit C21 upside down in the Y direction.

[0059] In the topmost unit row CRT of the circuit block, a terminal unit C11a is arranged at the left end of the figure, a terminal unit C11c is arranged at the right end of the figure, and a plurality of terminal units C21 are arranged along the X direction between the terminal units C11a and C11c. In the bottommost unit row CRB of the circuit block, a terminal unit C11 is arranged at the left end of the figure, a terminal unit C11b is arranged at the right end of the figure, and a plurality of terminal units C21a are arranged along the X direction between the terminal units C11 and C11b.

[0060] A unit row CRC is arranged between the unit rows CRT and CRB. In the unit row CRC, the unit row CRCs with terminal cells C11 and C11b arranged at the left and right ends of the drawing, respectively, and the unit row CRCs with terminal cells C11a and C11c arranged at the left and right ends of the drawing, respectively, are arranged alternately along the Y direction.

[0061] Therefore, in Figure 1In the figure, terminal units having the same structure as terminal unit C11 are arranged along the left and right ends of the logic part LC, and terminal units having the same structure as terminal unit C21 are arranged along the upper and lower ends of the logic part LC.

[0062] (Logic unit layout structure)

[0063] Figure 2 is a top view showing the layout structure of the logic unit, Figure 3 is a cross-sectional view showing the layout structure of a logic unit. Specifically, Figure 3 Shown along Figure 2 A cross-sectional view taken along line Y1-Y1'.

[0064] like Figure 2 As shown, in the standard cell C1, an N well region 1 extending from the center of the drawing along the X direction to the upper side of the drawing and a P substrate region 2 extending from the center of the drawing along the X direction to the lower side of the drawing are formed.

[0065] At both ends in the Y direction, power supply wirings 11 and 12 extending in the X direction are formed. Both power supply wirings 11 and 12 are buried power rails (BPR) formed in a buried wiring layer. The power supply wiring 11 is formed in the N-well region 1 and supplies a power supply voltage VDD. The power supply wiring 12 is formed in the P-substrate region 2 and supplies a power supply voltage VSS.

[0066] In the standard cell C1, nanosheets 21a to 24a, 21b to 24b extending in the X direction and the Y direction are formed. Nanosheets 21a and 21b are arranged in a row in the X direction. Nanosheets 22a and 22b are arranged in a row in the X direction. Nanosheets 23a and 23b are arranged in a row in the X direction. Nanosheets 24a and 24b are arranged in a row in the X direction.

[0067] Nanosheets 21a and 22a overlap with gate wiring 41 in plan view. Nanosheets 21b and 22b overlap with gate wiring 42 in plan view. Nanosheets 23a and 24a overlap with gate wiring 43 in plan view. Nanosheets 23b and 24b overlap with gate wiring 44 in plan view.

[0068] The nanosheets 21a, 21b, 22a, and 22b constitute the channel portions of the transistors P1 to P4, respectively. The nanosheets 23a, 23b, 24a, and 24b constitute the channel portions of the transistors N1 to N4, respectively.

[0069] On the left side of the nanosheet 21a, between the nanosheets 21a and 21b, on the right side of the nanosheet 21b, on the left side of the nanosheet 22a, between the nanosheets 22a and 22b, and on the right side of the nanosheet 22b, pads 31a to 31c, 32a to 32c doped with P-type semiconductor are respectively formed.

[0070] On the left side of the nanosheet 23a, between the nanosheets 23a and 23b, on the right side of the nanosheet 23b, on the left side of the nanosheet 24a, between the nanosheets 24a and 24b, and on the right side of the nanosheet 24b, pads 33a to 33c, 34a to 34c doped with N-type semiconductor are respectively formed.

[0071] The pads 31a and 31b constitute a node of the transistor P1. The pads 31b and 31c constitute a node of the transistor P2. The pads 32a and 32b constitute a node of the transistor P3. The pads 32b and 32c constitute a node of the transistor P4. The pads 33a and 33b constitute a node of the transistor N1. The pads 33b and 33c constitute a node of the transistor N2. The pads 34a and 34b constitute a node of the transistor N3. The pads 34b and 34c constitute a node of the transistor N4.

[0072] In the standard cell C1, gate wirings 41 to 44 and dummy gate wirings 45 to 48 extending in the Y direction and the Z direction are formed. Specifically, the dummy gate wiring 45, the gate wirings 41 and 42, and the dummy gate wiring 46 are formed to be arranged at equal intervals in the X direction. The dummy gate wiring 47, the gate wirings 43 and 44, and the dummy gate wiring 48 are formed to be arranged at equal intervals in the X direction. The dummy gate wirings 45 and 47 are formed at the left end of the standard cell C1 in the drawing. The dummy gate wirings 46 and 48 are formed at the right end of the standard cell C1 in the drawing.

[0073] The gate wiring 41 serves as the gate of the transistors P1 and P3 , the gate wiring 42 serves as the gate of the transistors P2 and P4 , the gate wiring 43 serves as the gate of the transistors N1 and N3 , and the gate wiring 44 serves as the gate of the transistors N2 and N4 .

[0074] That is, transistor P1 is composed of nanosheet 21a, pads 31a, 31b and gate wiring 41. Transistor P2 is composed of nanosheet 21b, pads 31b, 31c and gate wiring 42. Transistor P3 is composed of nanosheet 22a, pads 32a, 32b and gate wiring 41. Transistor P4 is composed of nanosheet 22b, pads 32b, 32c and gate wiring 42. Transistor N1 is composed of nanosheet 23a, pads 33a, 33b and gate wiring 43. Transistor N2 is composed of nanosheet 23b, pads 33b, 33c and gate wiring 44. Transistor N3 is composed of nanosheet 24a, pads 34a, 34b and gate wiring 43. Transistor N4 is composed of nanosheet 24b, pads 34b, 34c and gate wiring 44.

[0075] like Figure 3 As shown, nanosheets 21b to 24b are respectively composed of three sheet-like semiconductors (nanosheets). In nanosheets 21b to 24b, the nanosheets constituting each nanosheet 21b to 24b are arranged in an overlapping manner when viewed from above, and are formed by being spaced apart from each other in the Z direction. Similar to nanosheets 21b to 24b, nanosheets 21a to 24a are also composed of three sheet-like semiconductor layers, which are omitted from the illustration. In other words, transistors P1 to P4 and N1 to N4 each contain three nanosheets.

[0076] Here, if Figure 3 As shown, exposed portions (portions not surrounded by gate wiring) are formed on the outer peripheries of the nanosheets 21b to 24b in the Y direction and the Z direction, respectively. Specifically, the side surface on the left side of the drawing of the nanosheet 21b is not covered by the gate wiring 42, and the side surface on the right side of the drawing of the nanosheet 22b is not covered by the gate wiring 42. The side surface on the left side of the drawing of the nanosheet 23b is not covered by the gate wiring 44, and the side surface on the right side of the drawing of the nanosheet 24b is not covered by the gate wiring 44.

[0077] That is, on the left side of the drawing of nanosheets 21b and 23b (in Figure 2 An exposed portion is formed on the right side of the nanosheets 22b and 24b (in the figure). Figure 2 In the figure, an exposed portion is formed. Figure 2 In the figure, the nanosheets 21a and 23a have exposed portions on the upper side of the drawing, and the nanosheets 22a and 24a have exposed portions on the lower side of the drawing.

[0078] Therefore, for the nanosheets 21a, 21b, 23a, and 23b, the surfaces on the same side ( Figure 2 The surface on the upper side in the figure) is exposed from the gate wiring. For the nanosheets 22a, 22b, 24a, and 24b, the surface on the same side (in Figure 2The surface on the lower side of the figure) is exposed from the gate wiring.

[0079] The upper ends of the nanosheets 21a and 21b are aligned in the Y direction. The lower ends of the nanosheets 22a and 22b are aligned in the Y direction. The upper ends of the nanosheets 23a and 23b are aligned in the Y direction. The lower ends of the nanosheets 24a and 24b are aligned in the Y direction.

[0080] The upper and lower ends of the gate wirings 41 and 42 and the dummy gate wirings 45 and 46 are aligned in the Y direction. The upper and lower ends of the gate wirings 43 and 44 and the dummy gate wirings 47 and 48 are aligned in the Y direction.

[0081] (Specific example of logic unit)

[0082] Figure 4 is a top view showing a specific example of the layout structure of a logic unit, Figure 5 is a cross-sectional view showing a specific example of the layout structure of a logic cell, Figure 6 is the circuit diagram of a logic unit. Specifically, Figure 4 (a) shows the layout structure of the inverter unit C2, Figure 4 (b) shows the layout structure of the NAND cell C3. Figure 5 (a) shows the Figure 4 (a) is a cross-sectional view taken along the line Y2-Y2', Figure 5 (b) shows the Figure 4 A cross-sectional view taken along line Y3-Y3' in (a). Figure 6 (a) Yes Figure 4 (a) is a circuit diagram of the inverter unit C2 shown in FIG. Figure 6 (b) Yes Figure 4 (b) is a circuit diagram of the NAND cell C3 shown.

[0083] First, the layout structure of the inverter cell C2 will be described.

[0084] like Figure 6 As shown in (a), the inverter unit C2 has transistors P11 and N11, forming an inverter circuit with input A1 and output Y1. The transistors P11 and N11 are each composed of two transistors, but Figure 6 Illustration is omitted in (a). It should be noted that the transistors P1 and P3 correspond to the transistor P11, and the transistors N1 and N3 correspond to the transistor N11. The wirings 71 and 72 correspond to the input A1 and the output Y1, respectively.

[0085] like Figure 4 (a) and Figure 5As shown in (a) and (b), the inverter cell C2 has a smaller cell width (cell size in the X direction) than the standard cell C1, and has no transistors P2, P4, N2, and N4.

[0086] Specifically, the nanosheets 21 b to 24 b , the pads 31 c to 34 c , and the gate wirings 42 and 44 are not formed in the inverter cell C2 . The gate wirings 41 and 43 are connected via the gate connection portion 49 .

[0087] Local wirings 51 to 53 extending in the Y direction are formed on the upper layers of the pads 31a to 34a and 31b to 34b. The local wiring 51 is connected to the pads 31a and 32a. The local wiring 52 is connected to the pads 31b to 34b. The local wiring 53 is connected to the pads 33a and 34a.

[0088] The local wiring 51 is connected to the power supply wiring 11 via a contact hole 61. The local wiring 53 is connected to the power supply wiring 12 via a contact hole 62.

[0089] The first metal wiring layer above the local wirings 51 to 53 includes wirings 71 and 72 extending in the X direction. The wiring 71 is connected to the gate connection portion 49 via a contact hole 81. The wiring 72 is connected to the local wiring 52 via a contact hole 82.

[0090] Next, the layout structure of the NAND cell C3 will be described.

[0091] like Figure 6 As shown in (b), the NAND cell C3 has transistors P21, P22, N21, and N22, forming a two-input NAND circuit with inputs A2 and B2 and output Y2. The transistors P21, P22, N21, and N22 are each composed of two transistors, but Figure 6 (a) is omitted. It should be noted that transistors P1 and P3 correspond to transistor P21, transistors P2 and P4 correspond to transistor P22, transistors N1 and N3 correspond to transistor N21, and transistors N2 and N4 correspond to transistor N22. Wiring 73 to 75 correspond to output Y2, input B2, and input A2, respectively.

[0092] like Figure 4 As shown in FIG. 5( b ), in the NAND cell C3 , the gate wirings 41 and 43 are connected via a gate connecting portion 49 , and the gate wirings 42 and 44 are connected via a gate connecting portion 50 .

[0093] Local wirings 54 to 58 extending in the Y direction are formed on the upper layers of the pads 31a to 34a, 31b to 34b, and 31c to 34c. The local wiring 54 is connected to the pads 31a and 32a. The local wiring 55 is connected to the pads 31b and 32b. The local wiring 56 is connected to the pads 31c to 34c. The local wiring 57 is connected to the pads 33a and 34a. The local wiring 58 is connected to the pads 33b and 34b.

[0094] The local wiring 55 is connected to the power supply wiring 11 via the contact hole 63. The local wiring 57 is connected to the power supply wiring 12 via the contact hole 64.

[0095] The first metal wiring layer above the local wirings 54 to 58 has wirings 73 to 75 extending in the X direction. The wiring 73 is connected to the local wiring 54 via a contact hole 83, and is connected to the local wiring 56 via a contact hole 84. The wiring 74 is connected to the gate connection portion 49 via a contact hole 85. The wiring 75 is connected to the gate connection portion 50 via a contact hole 86.

[0096] (First Embodiment)

[0097] Figure 7 is a plan view showing a layout structure of a semiconductor integrated circuit device according to the first embodiment, Figure 8 1 is a cross-sectional view showing the layout structure of the semiconductor integrated circuit device involved in the first embodiment. Specifically, Figure 7 yes Figure 1 Magnified view of the W1 portion in FIG. Figure 8 (a) shows the Figure 7 The cross-sectional view taken along the line Y4-Y4' in FIG. Figure 8 (b) shows the Figure 7 A sectional view taken along line Y5-Y5'.

[0098] like Figure 1 and Figure 7 As shown, the terminal cell C11 is arranged adjacent to the left side of the inverter cell C2 at the left end of the cell row CR in the drawing.

[0099] Specifically, in the terminal cell C11, an N well region 101 extending from the center of the drawing to the upper side in the X direction is formed, and a P substrate region 102 extending from the center of the drawing to the lower side in the X direction is formed.

[0100] At both ends in the Y direction, power wirings 111 and 112 extending in the X direction are formed. Both power wirings 111 and 112 are buried power wirings (BPR) formed in a buried wiring layer. The power wiring 111 is formed in the N-well region 101 and supplies a power voltage VDD. The power wiring 112 is formed in the P-substrate region 102 and supplies a power voltage VSS.

[0101] In the terminal unit C11, nanosheets 121a to 124a extending in the X direction and the Y direction are formed.

[0102] The nanosheets 121a and 122a overlap with the dummy gate wiring 143 in a plan view. The nanosheets 123a and 124a overlap with the dummy gate wiring 146 in a plan view. The nanosheets 121a to 124a constitute the channel portions of the dummy transistors DP11, DP12, DN11, and DN12, respectively.

[0103] Dummy pads 131a, 131b, 132a, 132b doped with P-type semiconductor are formed on the left side of the nanosheet 121a, the right side of the nanosheet 121a, the left side of the nanosheet 122a, and the right side of the nanosheet 122a, respectively.

[0104] Dummy pads 133a, 133b, 134a, 134b doped with N-type semiconductor are formed on the left side of the nanosheet 123a, the right side of the nanosheet 123a, the left side of the nanosheet 124a, and the right side of the nanosheet 124a, respectively.

[0105] Dummy pads 131a and 131b constitute a node of dummy transistor DP11. Dummy pads 132a and 132b constitute a node of dummy transistor DP12. Dummy pads 133a and 133b constitute a node of dummy transistor DN11. Dummy pads 134a and 134b constitute a node of dummy transistor DN12.

[0106] In the terminal cell C11, dummy gate wirings 141 to 146 extending in the Y direction and the Z direction are formed. The dummy gate wirings 141 and 144 are formed at the left end of the terminal cell C11 in the drawing. The dummy gate wirings 45 and 47 are formed at the cell boundary between the terminal cell C11 and the inverter cell C2. The dummy gate wiring 143 becomes the gate of the dummy transistors DP11 and DP12, and the dummy gate wiring 146 becomes the gate of the dummy transistors DN11 and DN12.

[0107] Local wirings 151 to 154 extending in the Y direction are formed on the upper layer of the dummy pads 131a to 134a, 131b to 134b. Local wiring 151 is connected to the dummy pads 131a and 132a. Local wiring 152 is connected to the dummy pads 131b and 132b. Local wiring 153 is connected to the dummy pads 133a and 134a. Local wiring 154 is connected to the dummy pads 133b and 134b.

[0108] like Figure 8 As shown in (a), exposed portions (portions not surrounded by dummy gate wirings) are formed on the outer peripheries of the nanosheets 121a to 124a in the Y direction and the Z direction, respectively. Specifically, the side surface on the left side of the drawing of the nanosheet 121a is not covered by the dummy gate wiring 143, and the side surface on the right side of the drawing of the nanosheet 122a is not covered by the dummy gate wiring 143. The side surface on the left side of the drawing of the nanosheet 123a is not covered by the dummy gate wiring 146, and the side surface on the right side of the drawing of the nanosheet 124a is not covered by the dummy gate wiring 146.

[0109] That is, on the left side of the drawing of the nanosheets 121a and 123a (in Figure 7 On the right side of the drawing (in the middle) of the nanosheets 122a and 124a, exposed portions are formed. Figure 7 An exposed portion is formed (in the lower side of the figure).

[0110] Therefore, the surface of the nanosheet 121a on the same side as the nanosheet 21a of the inverter unit C2 (at Figure 7 The surface of the nanosheet 122a on the same side as the nanosheet 22a of the inverter unit C2 (in the figure) is exposed from the dummy gate wiring 143. Figure 7 The surface of the nanosheet 123a on the same side as the nanosheet 23a of the inverter unit C2 (the surface on the lower side in the figure) is exposed from the dummy gate wiring 143. Figure 7 The surface of the nanosheet 124a on the same side as the nanosheet 24a of the inverter unit C2 (in the figure) is exposed from the dummy gate wiring 146. Figure 7 The surface (the lower side of the figure) is exposed from the dummy gate wiring 146.

[0111] exist Figure 7 In the embodiment, the nanosheets 121a to 124a and the nanosheets 21a to 24a are formed on the same layer.

[0112] Nanosheet 121a is formed at the same position as nanosheet 21a in the Y direction. Nanosheet 122a is formed at the same position as nanosheet 22a in the Y direction. Nanosheet 123a is formed at the same position as nanosheet 23a in the Y direction. Nanosheet 124a is formed at the same position as nanosheet 24a in the Y direction.

[0113] The upper end of the nanosheet 121a in the drawing is aligned with the upper end of the nanosheet 21a in the drawing in the Y direction. The lower end of the nanosheet 122a in the drawing is aligned with the lower end of the nanosheet 22a in the drawing in the Y direction. The upper end of the nanosheet 123a in the drawing is aligned with the upper end of the nanosheet 23a in the drawing in the Y direction. The lower end of the nanosheet 124a in the drawing is aligned with the lower end of the nanosheet 24a in the drawing in the Y direction.

[0114] The dummy pads 131a to 134a and 131b to 134b are formed on the same layer as the pads 31a to 34a and 31b to 34b.

[0115] Dummy pads 131a, 131b are formed at the same positions as pads 31a, 31b in the Y direction. Dummy pads 132a, 132b are formed at the same positions as pads 32a, 32b in the Y direction. Dummy pads 133a, 133b are formed at the same positions as pads 33a, 33b in the Y direction. Dummy pads 134a, 134b are formed at the same positions as pads 34a, 34b in the Y direction.

[0116] The dummy pads 131a, 131b and the pads 31a, 31b are arranged at equal intervals in the X direction. The dummy pads 132a, 132b and the pads 32a, 32b are arranged at equal intervals in the X direction. The dummy pads 133a, 133b and the pads 33a, 33b are arranged at equal intervals in the X direction. The dummy pads 134a, 134b and the pads 34a, 34b are arranged at equal intervals in the X direction.

[0117] The dummy gate wirings 141 to 146 are formed on the same layer as the gate wirings 41 and 43 and the dummy gate wirings 45 to 48 .

[0118] Dummy gate wirings 141 to 143 are formed at the same positions in the Y direction as gate wiring 41 and dummy gate wirings 45 and 46. Dummy gate wirings 144 to 146 are formed at the same positions in the Y direction as gate wiring 43 and dummy gate wirings 47 and 48.

[0119] The dummy gate wirings 141 to 143 and 45 , the gate wiring 41 , and the dummy gate wiring 46 are arranged at equal intervals in the X direction. The dummy gate wirings 144 to 146 and 47 , the gate wiring 43 , and the dummy gate wiring 48 are arranged at equal intervals in the X direction.

[0120] The upper and lower ends of the dummy gate wirings 141 to 143 are aligned in the Y direction with the upper and lower ends of the gate wiring 41 and the dummy gate wirings 45 and 46. The upper and lower ends of the dummy gate wirings 144 to 146 are aligned in the Y direction with the upper and lower ends of the gate wiring 43 and the dummy gate wirings 47 and 48.

[0121] Local wirings 151 to 154 are formed on the same layer as local wirings 51 to 53 .

[0122] The local wirings 151, 152, 51-52 are arranged at equal intervals in the X direction. The local wirings 153, 154, 53, 52 are arranged at equal intervals in the X direction.

[0123] According to the above structure, the semiconductor integrated circuit device includes a plurality of cell rows CR, each of which includes a plurality of standard cells arranged in an X direction. The cell row CR includes an inverter cell C2 having a logic function and a terminal cell C11 arranged at the left end of the cell row CR in the drawing. The terminal cell C11 is arranged adjacent to the left side of the inverter cell C2 in the drawing at the left end of the cell row CR in the drawing. The inverter cell C2 includes an N-well region 1, a P-substrate region 2, a nanosheet 22a, a nanosheet 23a, a gate wiring 41, and a gate wiring 43, wherein the N-well region 1 is a formation region of a P-type transistor, the P-substrate region 2 is a formation region of an N-type transistor, the nanosheet 22a extends in the X direction and is formed in the N-well region 1, the nanosheet 23a extends in the X direction and is formed in the P-substrate region 2, the gate wiring 41 extends in the Y direction and surrounds the outer periphery of the nanosheet 22a in the Y direction and the Z direction, and the gate wiring 43 extends in the Y direction and surrounds the outer periphery of the nanosheet 23a in the Y direction and the Z direction. The terminal unit C11 includes a nanosheet 122a, a nanosheet 123a, a dummy gate wiring 143, and a dummy gate wiring 146, wherein the nanosheet 122a extends in the X direction and is formed at the same position as the nanosheet 22a in the Y direction, the nanosheet 123a extends in the X direction and is formed at the same position as the nanosheet 23a in the Y direction, the dummy gate wiring 143 extends in the Y direction and surrounds the outer periphery of the nanosheet 122a in the Y direction and the Z direction, and the dummy gate wiring 146 extends in the Y direction and surrounds the outer periphery of the nanosheet 123a in the Y direction and the Z direction. The lower side of the nanosheet 22a in the drawing is exposed from the gate wiring 41, and the upper side of the nanosheet 23a in the drawing is exposed from the gate wiring 43. The lower side of the nanosheet 122a in the drawing is exposed from the dummy gate wiring 143, and the upper side of the nanosheet 123a in the drawing is exposed from the dummy gate wiring 146.

[0124] That is, the surfaces on the same side in the Y direction of the nanosheets 22a and 122a arranged at the same position in the Y direction are exposed from the gate wiring 41 and the dummy gate wiring 143. The surfaces on the same side in the Y direction of the nanosheets 23a and 123a arranged at the same position in the Y direction are exposed from the gate wiring 43 and the dummy gate wiring 146. In this way, it is possible to suppress manufacturing variations of semiconductor integrated circuit devices, improve yields, and improve reliability.

[0125] The surfaces of the nanosheets 22a and 23a facing each other are exposed from the gate wirings 41 and 43. The surfaces of the nanosheets 122a and 123a facing each other are exposed from the dummy gate wirings 143 and 146. In this way, the gate wiring including the dummy gate wiring does not need to overlap between the nanosheets 22a and 23a and between the nanosheets 122a and 123a, so that the area of ​​the semiconductor integrated circuit device can be reduced.

[0126] The inverter unit C2 includes nanosheets 21a and 24a extending in the X direction and formed in the N well region 1 and the P substrate region 2, respectively. The terminal unit C11 includes nanosheets 121a and 124a extending in the X direction and formed in the same positions as the nanosheets 21a and 24a in the Y direction. The gate wirings 41 and 43 and the dummy gate wirings 143 and 146 surround the outer peripheries of the nanosheets 21a, 24a, 121a and 124a in the Y direction and the Z direction, respectively. The upper surface of the nanosheet 21a in the drawing is exposed from the gate wiring 41. The lower surface of the nanosheet 24a in the drawing is exposed from the gate wiring 43. The upper surface of the nanosheet 121a in the drawing is exposed from the dummy gate wiring 143. The lower surface of the nanosheet 124a in the drawing is exposed from the dummy gate wiring 146.

[0127] That is, the surfaces on the same side in the Y direction of the nanosheets 21a and 121a arranged at the same position in the Y direction are exposed from the gate wiring 41 and the dummy gate wiring 143. The surfaces on the same side in the Y direction of the nanosheets 24a and 124a arranged at the same position in the Y direction are exposed from the gate wiring 43 and the dummy gate wiring 146. In this way, it is possible to suppress manufacturing variations of semiconductor integrated circuit devices, improve yields, and improve reliability.

[0128] The upper end of the nanosheet 121a in the drawing is aligned with the upper end of the nanosheet 21a in the drawing in the Y direction. The lower end of the nanosheet 122a in the drawing is aligned with the lower end of the nanosheet 22a in the drawing in the Y direction. The upper end of the nanosheet 123a in the drawing is aligned with the upper end of the nanosheet 23a in the drawing in the Y direction. The lower end of the nanosheet 124a in the drawing is aligned with the lower end of the nanosheet 24a in the drawing in the Y direction. In this way, it is possible to suppress the manufacturing deviation of the semiconductor integrated circuit device, improve the yield rate, and improve the reliability.

[0129] Nanosheets 121a to 124a are formed on the same layer as nanosheets 21a to 24a. Dummy pads 131a to 134a, 131b to 134b are formed on the same layer as pads 31a to 34a, 31b to 34b. Dummy gate wirings 141 to 146 are formed on the same layer as gate wirings 41, 43 and dummy gate wirings 45 to 48. Local wirings 151 to 154 are formed on the same layer as local wirings 51 to 53. That is, by forming nanosheets, dummy pads, dummy gate wirings, and local wirings in terminal units, pads including dummy pads, gate wirings including dummy gate wirings, and local wirings are arranged regularly. In this way, the deviation of the finished shape of the layout pattern of the unit arranged inside the terminal unit can be suppressed, thereby suppressing the manufacturing deviation of the semiconductor integrated circuit device, improving the yield rate, and improving the reliability.

[0130] The dummy transistors DP11, DP12, DN11, and DN12 are arranged close to the gate wirings 45 and 47 arranged at the boundary between the inverter unit C2 and the terminal unit C11. That is, the terminal unit includes a dummy transistor close to the dummy gate wiring arranged at the boundary between the terminal unit and the logic unit, thereby making it possible to make the distance from the unit arranged at the end of the logic unit to the closest transistor constant, thereby improving the performance predictability of the logic unit.

[0131] It should be noted that the unit width of the terminal unit C11 can be larger than Figure 7 Dimensions shown are wider and may be wider than Figure 7 Size shown is narrow.

[0132] The terminal cell C11 is provided with four dummy transistors, namely, DP11, DP12, DN11, and DN12. However, the number of dummy transistors provided in the terminal cell C11 is not limited to four.

[0133] Although eight dummy gate wirings, namely, dummy gate wirings 45, 47, and 141 to 146, are formed in the terminal cell C11, the number of dummy gate wirings provided in the terminal cell C11 is not limited to eight.

[0134] Although four local wirings 151 to 154 are provided in the terminal cell C11, the number of local wirings provided in the terminal cell C11 is not limited to four.

[0135] In the logic unit (in Figure 7 In the inverter unit C2 in the embodiment, three or more nanosheet FETs may be provided relative to one gate wiring (including a dummy gate wiring). In this case, the nanosheet of the terminal unit is formed at the same position as the nanosheet of the logic unit in the Y direction. When the lower side of the nanosheet of the logic unit is exposed from the gate wiring, the lower side of the nanosheet of the terminal unit is exposed from the dummy gate wiring, and when the upper side of the nanosheet of the logic unit is exposed from the gate wiring, the upper side of the nanosheet of the terminal unit is exposed from the dummy gate wiring.

[0136] (Variation Example)

[0137] Fig. 9 is a diagram showing a layout structure of a logic cell according to a modification of the first embodiment, Fig.10 : is a diagram showing a layout structure of a terminal unit according to a modified example of the first embodiment. Specifically, Fig. 9 (a) is a top view showing the layout structure of the standard cell C4. Fig. 9 (b) shows the Fig. 9 A cross-sectional view taken along line Y6-Y6' in (a). Fig.10 (a) is a top view showing the layout structure of the terminal unit C12, Fig.10 (b) shows the Fig.10 (a) is a cross-sectional view taken along the line Y7a-Y7a', Fig.10 (c) shows the Fig.10 A cross-sectional view taken along line Y7b-Y7b' in (a).

[0138] Figure 1 In the case where the standard cell C4 is arranged instead of the inverter cell C2, the terminal cell C12 is arranged instead of the terminal cell C11.

[0139] In the standard cell C1 (inverter cell C2) and the terminal cell C11, two nanosheet FETs are provided for one gate wiring, but in the standard cell C4 and the terminal cell C12, one nanosheet FET is provided for one gate wiring.

[0140] (About standard cell C4)

[0141] like Fig. 9As shown in (a), nanosheets 22c, 22d, 23c, and 23d extending in the X direction and the Y direction are formed in the standard cell C4. The nanosheets 22c, 22d, 23c, and 23d overlap with the gate wirings 41 to 44 in a plan view. The nanosheets 22c, 22d, 23c, and 23d constitute the channel portions of the transistors P5, P6, N5, and N6, respectively.

[0142] Pads 32d to 32f doped with a P-type semiconductor are formed on the left side of the nanosheet 22c, between the nanosheets 22c and 22d, and on the right side of the nanosheet 22d.

[0143] On the left side of the nanosheet 23c in the drawing, between the nanosheets 23c and 23d, and on the right side of the nanosheet 23d in the drawing, pads 33d to 33f doped with an N-type semiconductor are respectively formed.

[0144] The pads 32d and 32e constitute a node of the transistor P5. The pads 32e and 32f constitute a node of the transistor P6. The pads 33d and 33e constitute a node of the transistor N5. The pads 33e and 33f constitute a node of the transistor N6.

[0145] The gate wiring 41 serves as a gate of the transistor P5 , the gate wiring 42 serves as a gate of the transistor P6 , the gate wiring 43 serves as a gate of the transistor N5 , and the gate wiring 44 serves as a gate of the transistor N6 .

[0146] like Fig. 9 As shown in (a) and (b), the outer peripheries of the nanosheets 22c, 22d, 23c, and 23d in the Y direction and the Z direction are respectively formed with exposed portions. Fig. 9 In (a), the exposed portion is formed on the lower side of the nanosheets 22c and 22d. The exposed portion is formed on the upper side of the nanosheets 23c and 23d. That is, in the standard cell C4, the surfaces of the nanosheets 22c and 22d on the same side (in Fig. 9 (a) is the upper side of the figure) exposed from the gate wiring. The same side of the nanosheets 23c and 23d (on the Fig. 9 (a) is the lower side of the figure) exposed from the gate wiring.

[0147] exist Fig. 9 In (a), the upper surfaces of the nanosheets 22c and 22d are covered by the gate wirings 41 and 42, respectively, and the lower surfaces of the nanosheets 23c and 23d are covered by the gate wirings 43 and 44, respectively. In other words, the upper surfaces of the nanosheets 22c and 22d are not exposed from the gate wiring, and the lower surfaces of the nanosheets 23c and 23d are not exposed from the gate wiring.

[0148] Based on the layout structure of the standard cell C4, vias or wiring (local wiring, metal wiring) are formed to connect the transistors, thereby forming a standard cell that realizes a logic function. It should be noted that in the following description, the standard cell C4 that realizes the logic function by forming vias or wiring is sometimes referred to as a standard cell C4 with a logic function.

[0149] (About terminal unit C12)

[0150] like Fig.10 As shown in (a), nanosheets 122c and 123c extending in the X and Y directions are formed in the terminal unit C12. The nanosheets 122c and 123c overlap with the dummy gate wirings 143 and 146 in a plan view. The nanosheets 122c and 123c constitute the channel portions of the dummy transistors DP13 and DN13, respectively.

[0151] Dummy pads 132c and 132d doped with a P-type semiconductor are formed on the left side and the right side of the nanosheet 122c, respectively.

[0152] Dummy pads 133c and 133d doped with an N-type semiconductor are formed on the left side and the right side of the nanosheet 123c, respectively.

[0153] The dummy pads 132c and 132d constitute the nodes of the dummy transistor DP13. The dummy pads 133c and 133d constitute the nodes of the dummy transistor DN13.

[0154] The dummy gate wiring 143 serves as a gate of the dummy transistor DP13 , and the dummy gate wiring 146 serves as a gate of the dummy transistor DN13 .

[0155] Local wirings 155 to 158 extending in the Y direction are formed on the upper layer of the dummy pads 132c, 132d, 133c, and 133d. The local wirings 155 to 158 are connected to the dummy pads 132c, 132d, 133c, and 133d, respectively.

[0156] like Fig.10 As shown in (a) to (c), exposed portions are formed on the outer peripheries of the nanosheets 122c and 123c in the Y direction and the Z direction. Fig.10 In (a), an exposed portion is formed on the lower side of the nanosheet 122c. An exposed portion is formed on the upper side of the nanosheet 123c. That is, in the terminal unit C12, the surface of the nanosheet 122c on the same side as the nanosheets 22c and 22d of the standard unit C4 having a logic function (in Fig.10(a) is the lower side of the drawing) exposed from the dummy gate wiring 143. The surface of the nanosheet 123c on the same side as the nanosheets 23c and 23d of the standard cell C4 having a logic function (at Fig.10 (a) is the upper side of the drawing) and is exposed from the dummy gate wiring 146.

[0157] exist Figure 1 In the case where a standard cell C4 having a logic function is arranged instead of the inverter cell C2, the same effect as that of the terminal cell C11 can be obtained by arranging the terminal cell C12 instead of the terminal cell C11.

[0158] exist Fig.10 In (a), the side surface of the nanosheet 122c on the upper side of the drawing is covered by the dummy gate wiring 143. The side surface of the nanosheet 123c on the lower side of the drawing is covered by the dummy gate wiring 146. That is, the side surface of the nanosheet 122c on the same side as the nanosheets 22c and 22d (at Fig. 9 (a) and Fig.10 (a) is the upper side of the drawing) is not exposed from the dummy gate wiring 143. The side surface of the nanosheet 123c on the same side as the nanosheets 23c and 23d (on the Fig. 9 (a) and Fig.10 (a) is the lower side of the drawing) is not exposed from the dummy gate wiring 146. In this way, it is possible to suppress manufacturing variations of semiconductor integrated circuit devices, improve yield, and improve reliability.

[0159] It should be noted that in Fig. 9 In the standard cell C4 of (a), the upper surfaces of the nanosheets 22c and 22d are not exposed from the gate wirings 41 and 42, respectively, and the lower surfaces of the nanosheets 22c and 22d are exposed from the gate wirings 41 and 42, respectively, but the present invention is not limited thereto. Alternatively, the upper surfaces of the nanosheets 22c and 22d are exposed from the gate wirings 41 and 42, respectively, and the lower surfaces of the nanosheets 22c and 22d are not exposed from the gate wirings 41 and 42, respectively. In this case, Fig.10 In the terminal cell C12 of (a), the upper surface of the nanosheet 122 c in the drawing is exposed from the dummy gate wiring 143 , while the lower surface of the nanosheet 122 c in the drawing is not exposed from the dummy gate wiring 143 .

[0160] The upper surfaces of the nanosheets 23c and 23d are exposed from the gate wirings 43 and 44, respectively, and the lower surfaces of the nanosheets 23c and 23d are not exposed from the gate wirings 43 and 44, respectively, but the present invention is not limited thereto. Alternatively, the upper surfaces of the nanosheets 23c and 23d are not exposed from the gate wirings 43 and 44, respectively, and the lower surfaces of the nanosheets 23c and 23d are exposed from the gate wirings 43 and 44, respectively. In this case, Fig.10In the terminal cell C12 of (a), the upper surface of the nanosheet 123 c in the drawing is exposed from the dummy gate wiring 146 , while the lower surface of the nanosheet 123 c in the drawing is not exposed from the dummy gate wiring 146 .

[0161] (Second Embodiment)

[0162] Fig.11 is a plan view showing a layout structure of a semiconductor integrated circuit device according to a second embodiment. Fig.12 2 is a cross-sectional view showing the layout structure of the terminal unit involved in the second embodiment. Specifically, Fig.11 yes Figure 1 An enlarged view of the W2 portion in FIG. Fig.12 (a) shows the Fig.11 The cross-sectional view taken along the line Y8-Y8' in FIG. Fig.12 (b) shows the Fig.11 A sectional view taken along line Y9-Y9'.

[0163] like Figure 1 and 11 As shown in FIG. 1 , the terminal unit C21 is arranged in the uppermost unit row CRT. The terminal unit C21 is arranged adjacent to the upper side of the inverter unit C2 in the figure.

[0164] like Fig.11 As shown, a P substrate region 201 extending from the center of the cell to the upper side of the drawing along the X direction is formed in the terminal cell C21. An N well region 202 extending from the center of the cell to the lower side of the drawing along the X direction is also formed in the terminal cell C21.

[0165] At both ends in the Y direction, power wirings 211 and 212 extending in the X direction are formed. Both power wirings 211 and 212 are buried power wirings (BPR) formed in a buried wiring layer. The power wiring 211 is formed in the P substrate region 201 and supplies a power voltage VSS. The power wiring 212 is formed in the N well region 202 and supplies a power voltage VDD.

[0166] In the terminal unit C21, nanosheets 221a to 224a and 221b to 224b extending in the X direction and the Y direction are formed.

[0167] The nanosheets 221a and 222a overlap with the dummy gate wiring 242 when viewed from above. The nanosheets 221b and 222b overlap with the dummy gate wiring 243 when viewed from above. The nanosheets 223a and 224a overlap with the dummy gate wiring 246 when viewed from above. The nanosheets 223b and 224b overlap with the dummy gate wiring 247 when viewed from above. The nanosheets 221a, 221b, 222a, and 222b respectively constitute the channel portions of the dummy transistors DN21, DN22, DN23, and DN24. The nanosheets 223a, 223b, 224a, and 224b respectively constitute the channel portions of the dummy transistors DP21, DP22, DP23, and DP24.

[0168] On the left side of the drawing of nanosheet 221a, between nanosheets 221a and 221b, on the right side of the drawing of nanosheet 221b, on the left side of the drawing of nanosheet 222a, between nanosheets 222a and 222b, and on the right side of the drawing of nanosheet 222b, pads 231a to 231c, 232a to 232c doped with N-type semiconductor are formed respectively. Dummy pads 231a and 231b constitute the node of dummy transistor DN21. Dummy pads 231b and 231c constitute the node of dummy transistor DN22. Dummy pads 232a and 232b constitute the node of dummy transistor DN23. Dummy pads 232b and 232c constitute the node of dummy transistor DN24.

[0169] On the left side of the drawing of nanosheet 223a, between nanosheets 223a and 223b, on the right side of the drawing of nanosheet 223b, on the left side of the drawing of nanosheet 224a, between nanosheets 224a and 224b, and on the right side of the drawing of nanosheet 224b, pads 233a to 233c, 234a to 234c doped with P-type semiconductor are formed respectively. Dummy pads 233a and 233b constitute nodes of dummy transistor DP21. Dummy pads 233b and 233c constitute nodes of dummy transistor DP22. Dummy pads 234a and 234b constitute nodes of dummy transistor DP23. Dummy pads 234b and 234c constitute nodes of dummy transistor DP24.

[0170] In the terminal cell C21, dummy gate wirings 241 to 248 extending in the Y direction and the Z direction are formed. The dummy gate wirings 241 and 245 are formed at the cell boundary between the terminal cell C21 and the cell arranged adjacent to the left side of the drawing of the terminal cell C21. The dummy gate wirings 244 and 248 are formed at the cell boundary between the terminal cell C21 and the cell arranged adjacent to the right side of the drawing of the terminal cell C21. The dummy gate wiring 242 becomes the gate of the dummy transistors DN21 and DN23, and the dummy gate wiring 243 becomes the gate of the dummy transistors DN22 and DN24. The dummy gate wiring 246 becomes the gate of the dummy transistors DP21 and DP23, and the dummy gate wiring 247 becomes the gate of the dummy transistors DP22 and DP24.

[0171] Local wirings 251 to 256 extending in the Y direction are formed on the upper layers of the dummy pads 231a to 234a, 231b to 234b, and 231c to 234c. Local wiring 251 is connected to the dummy pads 231a and 232a. Local wiring 252 is connected to the dummy pads 231b and 232b. Local wiring 253 is connected to the dummy pads 231c and 232c. Local wiring 254 is connected to the dummy pads 233a and 234a. Local wiring 255 is connected to the dummy pads 233b and 234b. Local wiring 256 is connected to the dummy pads 233c and 234c.

[0172] like Fig.12 As shown in (a), exposed portions (portions not surrounded by dummy gate wirings) are formed on the outer peripheries of the nanosheets 221b to 224b in the Y direction and the Z direction, respectively. Specifically, the side surface on the left side of the drawing of the nanosheet 221b is not covered by the dummy gate wiring 243, and the side surface on the right side of the drawing of the nanosheet 222b is not covered by the dummy gate wiring 243. The side surface on the left side of the drawing of the nanosheet 223b is not covered by the dummy gate wiring 247, and the side surface on the right side of the drawing of the nanosheet 224b is not covered by the dummy gate wiring 247.

[0173] That is, on the left side of the drawing of nanosheets 221b and 223b (in Fig.11 On the right side of the drawing (in the middle) of the nanosheets 222b and 224b, an exposed portion is formed. Fig.11 In the figure, the exposed portion is formed. Fig.11 In the figure, the nanosheets 221a and 223a have exposed portions on the upper side of the drawing, and the nanosheets 222a and 224a have exposed portions on the lower side of the drawing.

[0174] Therefore, the surface of the nanosheets 224a, 224b opposite to the nanosheet 21a of the inverter unit C2 (at Fig.11The lower side of the figure in the middle) is exposed from the dummy gate wirings 246 and 247 respectively.

[0175] exist Fig.11 In the embodiment, the nanosheets 221a to 224a and 221b to 224b are formed on the same layer as the nanosheets 21a to 24a.

[0176] The nanosheets 221 a to 224 a are formed at the same positions as the nanosheets 21 a to 24 a in the X direction.

[0177] The dummy pads 231a to 234a, 231b to 234b, and 231c to 234c are formed on the same layer as the pads 31a to 34a and 31b to 34b.

[0178] The dummy pads 231a-231c are formed at the same position in the Y direction and are arranged at equal intervals in the X direction. The dummy pads 232a-232c are formed at the same position in the Y direction and are arranged at equal intervals in the X direction. The dummy pads 233a-233c are formed at the same position in the Y direction and are arranged at equal intervals in the X direction. The dummy pads 234a-234c are formed at the same position in the Y direction and are arranged at equal intervals in the X direction.

[0179] The dummy pads 231a to 234a are formed at the same positions as the pads 31a to 34a in the X direction. The dummy pads 231b to 234b are formed at the same positions as the pads 31b to 34b in the X direction.

[0180] The dummy gate wirings 241 to 248 are formed on the same layer as the gate wirings 41 and 43 and the dummy gate wirings 45 to 48 .

[0181] The dummy gate wirings 241 to 244 are formed at the same position in the Y direction and are arranged at equal intervals in the X direction. The dummy gate wirings 245 to 248 are formed at the same position in the Y direction and are arranged at equal intervals in the X direction.

[0182] The upper ends and lower ends of the dummy gate wirings 241 to 244 are aligned in the Y direction. The upper ends and lower ends of the dummy gate wirings 245 to 248 are aligned in the Y direction.

[0183] Dummy gate wirings 241 and 245 are formed at the same positions in the X direction as dummy gate wirings 45 and 47. Dummy gate wirings 242 and 246 are formed at the same positions in the X direction as dummy gate wirings 41 and 43. Dummy gate wirings 243 and 247 are formed at the same positions in the X direction as dummy gate wirings 46 and 48.

[0184] Local wirings 251 to 256 are formed on the same layer as local wirings 51 to 53 .

[0185] The local wirings 251 to 253 are formed at the same position in the Y direction and are arranged at equal intervals in the X direction. The local wirings 254 to 256 are formed at the same position in the Y direction and are arranged at equal intervals in the X direction.

[0186] The local wirings 251 and 254 are formed at the same positions in the X direction as the local wirings 51 and 53. The local wirings 252 and 255 are formed at the same positions in the X direction as the local wiring 52.

[0187] According to the above structure, the semiconductor integrated circuit device includes a plurality of cell rows CR, each of which includes a plurality of standard cells arranged along the X direction. The cell row CRC includes an inverter cell C2 having a logic function, and the uppermost cell row CRT includes a terminal cell C21 having no logic function. The terminal cell C21 is arranged adjacent to the upper side of the inverter cell C2 in the figure. The inverter unit C2 includes an N-well region 202, a P-substrate region 201, a nanosheet 21a, a nanosheet 24a, a gate wiring 41, and a gate wiring 43, wherein the N-well region 202 is a formation region for a P-type transistor, the P-substrate region 201 is a formation region for an N-type transistor, the nanosheet 21a extends along the X direction and is formed in the N-well region 202, the nanosheet 24a extends along the X direction and is formed in the P-substrate region 201, and is formed at the same position in the X direction as the nanosheet 21a, the gate wiring 41 extends along the Y direction and surrounds the outer periphery of the nanosheet 21a in the Y and Z directions, and the gate wiring 43 extends along the Y direction and surrounds the outer periphery of the nanosheet 24a in the Y and Z directions. The terminal unit C21 includes a nanosheet 224a and a dummy gate wiring 246, wherein the nanosheet 224a extends in the X direction and is formed at the same position as the nanosheet 21a in the Y direction and is arranged adjacent to the nanosheet 21a in the Y direction, and the dummy gate wiring 246 extends in the Y direction and surrounds the outer periphery of the nanosheet 224a in the Y direction and the Z direction. The upper surface of the nanosheet 21a in the drawing is exposed from the gate wiring 41. The lower surface of the nanosheet 24a in the drawing is exposed from the gate wiring 43. The lower surface of the nanosheet 224a in the drawing is exposed from the dummy gate wiring 246.

[0188] That is, the mutually opposing surfaces of the nanosheets 21a and 244a arranged adjacent to each other in the Y direction are exposed from the gate wiring 41 and the dummy gate wiring 246. This can suppress manufacturing variations of semiconductor integrated circuit devices, improve yield, and improve reliability.

[0189] The nanosheets 21a and 224a are formed adjacent to each other in the Y direction. In this way, gate wiring including dummy gate wiring does not need to overlap between the nanosheets 21a and 224a, so that the area of ​​the semiconductor integrated circuit device can be reduced.

[0190] The mutually opposing surfaces of the nanosheets 222a and 223a are exposed from the dummy gate wirings 242 and 246. Thus, the gate wiring (dummy gate wiring) does not need to overlap between the nanosheets 222a and 223a, thereby reducing the area of ​​the semiconductor integrated circuit device.

[0191] Nanosheets 221a to 224a, 221b to 224b are formed on the same layer as nanosheets 21a to 24a. Dummy pads 231a to 234a, 231b to 234b, 231c to 234c are formed on the same layer as pads 31a to 34a, 31b to 34b. Dummy gate wirings 241 to 248 are formed on the same layer as gate wirings 41, 43 and dummy gate wirings 45 to 48. Local wirings 251 to 256 are formed on the same layer as local wirings 51 to 53. That is, by forming nanosheets, dummy pads, dummy gate wirings, and local wirings in terminal units, pads including dummy pads, gate wirings including dummy gate wirings, and local wirings are arranged regularly. In this way, the deviation of the finished shape of the layout pattern of the unit arranged inside the terminal unit can be suppressed, thereby suppressing the manufacturing deviation of the semiconductor integrated circuit device, improving the yield rate, and improving the reliability.

[0192] Nanosheets 221a to 224a are formed at the same positions as nanosheets 21a to 24a in the X direction. Dummy pads 231a to 234a are formed at the same positions as pads 31a to 34a in the X direction, and dummy pads 231b to 234b are formed at the same positions as pads 31b to 34b in the X direction. Dummy gate wirings 241 and 245 are formed at the same positions as dummy gate wirings 45 and 47 in the X direction, dummy gate wirings 242 and 246 are formed at the same positions as gate wirings 41 and 43 in the X direction, and dummy gate wirings 243 and 247 are formed at the same positions as dummy gate wirings 46 and 48 in the X direction. Local wirings 251 and 254 are formed at the same positions as local wirings 51 and 53 in the X direction, and local wirings 252 and 255 are formed at the same positions as local wirings 52 in the X direction. That is, nanosheets, dummy pads, dummy gate wirings, and local wirings are formed in the terminal unit 21, and these nanosheets, dummy pads, dummy gate wirings, and local wirings are spread over the entire unit width of the terminal unit 21. In this way, the deviation of the finished shape of the layout pattern of the unit arranged inside the terminal unit can be suppressed, thereby suppressing the manufacturing deviation of the semiconductor integrated circuit device, improving the yield, and improving the reliability.

[0193] It should be noted that the unit width of the terminal unit C21 can be larger than Fig.11 Dimensions shown are wider and may be wider than Figure 7 Size shown is narrow.

[0194] Although eight dummy transistors DP21 to DP24 and DN21 to DN24 are provided in the terminal cell C21 , the number of dummy transistors provided in the terminal cell C21 is not limited to eight.

[0195] Although eight dummy gate wirings 241 to 248 are formed in the terminal cell C21, the number of dummy gate wirings provided in the terminal cell C21 is not limited to eight.

[0196] Six local wirings, namely local wirings 251 to 256, are provided in the terminal cell C21, but the number of local wirings provided in the terminal cell C21 is not limited to six.

[0197] exist Figure 1 In the embodiment, the terminal unit C21 may be arranged to replace the terminal units C11a and C11c of the uppermost unit row CRT, or the terminal unit C21a which is inverted upside down in the Y direction may be arranged to replace the terminal units C11 and C11b of the lowermost unit row CRB.

[0198] (One of the variations of terminal unit C21)

[0199] Fig.13 is a top view showing a change in the layout structure of the terminal unit involved in the second embodiment. Specifically, Fig.13 (a) is a top view showing the layout structure of the terminal unit C22, Fig.13 (b) is a top view showing the layout structure of the terminal unit C23.

[0200] like Fig.13 As shown in (a), the terminal unit C22 has a unit size in the Y direction that is half that of the terminal unit C21, and dummy transistors DN21 to DN24, DP21, and DP22 are not formed. Specifically, the P substrate region 201, power wiring 211, nanosheets 221a to 221b, 222a to 222b, 223a to 223b, dummy pads 231a to 231c, 232a to 232c, 233a to 233c, dummy gate wirings 241 to 244, and local wirings 251 to 253 are not formed in the terminal unit C22.

[0201] By Figure 1 Arranging the terminal unit C22 in place of the terminal unit C21 can achieve the same effect as the terminal unit C21. Since the unit size of the terminal unit C22 in the Y direction is smaller than that of the terminal unit C21, the area of ​​the semiconductor integrated circuit can be reduced.

[0202] like Fig.13 As shown in (b), since the terminal unit C23 is a unit formed by turning the terminal unit C22 upside down along the Y direction, the dummy transistor DP23 is omitted. Specifically, the nanosheet 224a, the dummy pad 234a and the local wiring 254 are not formed in the terminal unit C23.

[0203] By Figure 1 Arranging the terminal cell C23 in place of the terminal cell C11 at the left end of the bottom row of the cell row CRB can achieve the same effect as the terminal cell C21 (terminal cell C11). Since the cell size of the terminal cell C23 in the Y direction is smaller than that of the terminal cell C21, the area of ​​the semiconductor integrated circuit can be reduced.

[0204] It should be noted that in Figure 1 In the embodiment, the terminal unit C22 may be arranged to replace the terminal units C11a and C11c of the uppermost unit row CRT, or the terminal unit C22 may be arranged to replace the terminal units C11 and C11b of the lowermost unit row CRB by inverting the terminal unit C22 in the Y direction.

[0205] (Change 2 of terminal unit C21)

[0206] Fig.14 is a top view showing a change in the layout structure of the terminal unit involved in the second embodiment. Specifically, Fig.14 (a) shows a top view of the terminal unit C24, Fig.14 (b) shows a top view of the terminal unit C25, Fig.14 (c) shows a top view of the terminal unit C26.

[0207] When Figure 1 When a standard cell C4 having a logic function is arranged to replace the inverter cell C2, terminal cells C24 to C26 are arranged to replace the terminal cell C21.

[0208] In the terminal cell C21, two nanosheet FETs are provided for one dummy gate wiring, but in the terminal cells C24 to C26, one nanosheet is provided for one dummy gate wiring.

[0209] like Fig.14 As shown in (a), nanosheets 222c, 222d, 223c, and 223d extending in the X direction and the Y direction are formed in the terminal unit C24. The nanosheets 222c, 222d, 223c, and 223d overlap with the dummy gate wirings 242, 243, 246, and 247, respectively, when viewed from above. The nanosheets 222c, 222d, 223c, and 223d constitute the channel portions of the dummy transistors DN25, DN26, DP25, and DP26, respectively.

[0210] Dummy pads 232d to 232f doped with N-type semiconductor are respectively formed on the left side of the nanosheet 222c, between the nanosheets 222c and 222d, and on the right side of the nanosheet 222d.

[0211] Dummy pads 233d to 233f doped with a P-type semiconductor are formed on the left side of the nanosheet 223c, between the nanosheets 223c and 223d, and on the right side of the nanosheet 223d.

[0212] Dummy pads 232d and 232e constitute a node of dummy transistor DN25. Dummy pads 232e and 232f constitute a node of dummy transistor DN26. Dummy pads 233d and 233e constitute a node of dummy transistor DP25. Dummy pads 233e and 233f constitute a node of dummy transistor DP26.

[0213] The dummy gate wiring 242 serves as the gate of the dummy transistor DN25, and the dummy gate wiring 243 serves as the gate of the dummy transistor DN26. The dummy gate wiring 246 serves as the gate of the dummy transistor DP25, and the dummy gate wiring 247 serves as the gate of the dummy transistor DP26.

[0214] The local wirings 251 to 256 are connected to the dummy pads 232d to 232f and 233d to 233f, respectively.

[0215] like Fig.14 As shown in (a), the outer peripheries of the nanosheets 222c, 222d, 223c, and 223d in the Y direction and the Z direction are respectively formed with exposed portions. Specifically, the exposed portions are formed on the lower side of the nanosheets 222c and 222d in the drawing. The exposed portions are formed on the upper side of the nanosheets 223c and 223d in the drawing.

[0216] That is, in the terminal cell C24, the mutually facing surfaces of the nanosheets 222c and 223c are exposed from the dummy gate wirings 242 and 246, respectively. The mutually facing surfaces of the nanosheets 222d and 223d are exposed from the dummy gate wirings 243 and 247, respectively.

[0217] When Figure 1 In the case where a standard cell C4 having a logic function is arranged instead of the inverter cell C2, by arranging the terminal cell C24 instead of the terminal cell C21, the same effect as that of the terminal cell C21 can be obtained.

[0218] exist Fig.14 In (a), the side surfaces of the nanosheets 223c and 223d on the lower side of the drawing are covered by the dummy gate wirings 246 and 247, respectively. That is, the mutually opposite sides of the nanosheets 222c and 222d of the standard cell C4 and the nanosheets 22c and 22d of the terminal cell C24 are not exposed from the gate wiring including the dummy gate wiring. In this way, the manufacturing variation of the semiconductor integrated circuit device can be suppressed, the yield rate can be improved, and the reliability can be improved.

[0219] like Fig.14 As shown in (b), the terminal unit C25 has a unit size in the Y direction that is half that of the terminal unit C24, and dummy transistors DN25 and DN26 are not formed. Specifically, the P substrate region 201, power wiring 211, nanosheets 222c, 222d, dummy pads 232d to 232f, dummy gate wirings 241 to 244, and local wirings 251 to 253 are not formed in the terminal unit C25.

[0220] When Figure 1 When the standard cell C4 with logic function is arranged to replace the inverter cell C2, the terminal cell C25 is arranged to replace the terminal cell C21, thereby obtaining the same effect as the terminal cell C24. Since the cell size of the terminal cell C25 in the Y direction is smaller than that of the terminal cell C21, the area of ​​the semiconductor integrated circuit can be reduced.

[0221] like Fig.14 As shown in (c), the terminal unit C26 has a unit size in the Y direction that is half that of the terminal unit C25, and no exposed portion is formed on the outer periphery of the nanosheets 223c and 223d in the Y direction and the Z direction. In other words, the outer periphery of the nanosheets 223c and 223d in the Y direction and the Z direction is not surrounded by the dummy gate wirings 245 to 248.

[0222] When Figure 1 When the standard cell C4 with logic function is arranged to replace the inverter cell C2, the terminal cell C26 is arranged to replace the terminal cell C21, thereby obtaining the same effect as the terminal cell C24. Since the cell size of the terminal cell C26 in the Y direction is smaller than that of the terminal cell C21, the area of ​​the semiconductor integrated circuit can be reduced.

[0223] It should be noted that in Figure 1 In the embodiment, any one of the terminal units C24 to C26 may be arranged to replace the terminal unit C21a by turning it upside down in the Y direction. Any one of the terminal units C24 to C26 may be arranged to replace the terminal units C11a and C11c of the uppermost unit row CRT, and any one of the terminal units C24 to C26 may be arranged to replace the terminal units C11 and C11b of the lowermost unit row CRB by turning it upside down in the Y direction.

[0224] In the above-mentioned embodiments, each terminal unit is arranged adjacent to the inverter unit C2, but the present invention is not limited thereto and each terminal unit may be arranged adjacent to other standard units.

[0225] In the above-mentioned embodiments, the number of nanosheets included in one nanosheet FET is not limited to three, and may be less than two or more than four.

[0226] In the above embodiments, the cross-sectional shape of the nanosheet is a rectangle, but is not limited thereto and may be, for example, a square, a circle, an ellipse, or the like.

[0227] In each of the above-mentioned embodiments, Figure 1 In the embodiment, the circuit block is rectangular, but is not limited thereto. The number of cell rows CR arranged in the circuit block is not limited to six rows.

[0228] -Industrial Applicability-

[0229] The present disclosure can be applied to a semiconductor integrated circuit device including a standard cell using a fork-piece transistor, and thus can suppress manufacturing variations in the semiconductor integrated circuit device, improve yield, and improve reliability.

[0230] -Explanation of symbols-

[0231] C1, C4 standard units

[0232] C2 Inverter Unit

[0233] C3 NAND Cell

[0234] C11, C12, C21 to C26 terminal units

[0235] 1. 101, 202 N-well region

[0236] 2, 102, 201 P substrate area

[0237] 11, 21, 111, 112, 211, 212 Power wiring

[0238] 21a-24a, 21b-24b, 22c, 22d, 23c, 23d, 121a-124a, 122c, 123c, 221a-224a, 221b-224b, 222c, 222d, 223c, 223d nanosheets

[0239] 31a~34a、31b~34b、31c~34c、32d~32f、33d~33f pads

[0240] 131a-134a, 131b-134b, 132c, 132d, 133c, 133d, 231a-234a, 231b-234b, 231c-234c, 232d-232f, 233d-233f Dummy pads

[0241] 41~44 Gate wiring

[0242] 45-48, 141-146, 241-248 Dummy gate wiring

[0243] 51~58、151~158、251~256 Local wiring

[0244] P1~P6、N1~N6 transistors

[0245] DP11~DP13、DP21~DP26、DN11~DN13、DN21~DN26 Dummy transistor

Claims

1. A semiconductor integrated circuit device, characterized in that: The semiconductor integrated circuit device includes a plurality of cell rows, each of the plurality of cell rows includes a plurality of standard cells arranged in a row along a first direction. One of the plurality of cell rows, namely a first cell row, includes a first standard cell and a second standard cell, wherein the first standard cell has a logic function, and the second standard cell is arranged at at least one of two ends of the first cell row and does not have a logic function, The first standard cell includes a first region, a second region, a first nanosheet, a second nanosheet, a first gate wiring, and a second gate wiring. The first region is a formation region of a first conductivity type transistor, The second region is a region where a transistor of a second conductivity type different from the first conductivity type is formed, and the second region is adjacent to the first region in a second direction perpendicular to the first direction. The first nanosheet extends along the first direction and is formed in the first region. The second nanosheet extends along the first direction and is formed in the second region. The first gate wiring extends along the second direction and surrounds the outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction. The second gate wiring extends along the second direction and surrounds the outer periphery of the second nanosheet in the second direction and the third direction. The second standard cell includes a third nanosheet, a fourth nanosheet, a first dummy gate wiring, and a second dummy gate wiring, The third nanosheet extends along the first direction and is formed at the same position as the first nanosheet in the second direction, The fourth nanosheet extends along the first direction and is formed at the same position as the second nanosheet in the second direction, The first dummy gate wiring extends along the second direction and surrounds the outer periphery of the third nanosheet in the second direction and the third direction. The second dummy gate wiring extends along the second direction and surrounds the outer periphery of the fourth nanosheet in the second direction and the third direction. A surface of the first nanosheet on one side in the second direction, that is, a first side, is exposed from the first gate wiring. A surface of the second nanosheet on one side in the second direction, that is, a second side, is exposed from the second gate wiring. The surface of the third nanosheet on the first side in the second direction is exposed from the first dummy gate wiring. The surface of the fourth nanosheet on the second side in the second direction is exposed from the second dummy gate wiring.

2. The semiconductor integrated circuit device according to claim 1, wherein: The first side is a side of the first nanosheet close to the second region, The second side is a side of the second nanosheet close to the first region.

3. The semiconductor integrated circuit device according to claim 1, wherein: The first side is a side of the first nanosheet opposite to the second region, The second side is a side of the second nanosheet opposite to the first region.

4. The semiconductor integrated circuit device according to claim 1, wherein: The first standard cell further includes a fifth nanosheet and a sixth nanosheet, The fifth nanosheet extends along the first direction and is formed in the first region. The sixth nanosheet extends along the first direction and is formed in the second region, The second standard cell further includes a seventh nanosheet and an eighth nanosheet, The seventh nanosheet extends along the first direction and is formed at the same position as the fifth nanosheet in the second direction, The eighth nanosheet extends along the first direction and is formed at the same position as the sixth nanosheet in the second direction, The first gate wiring surrounds the outer periphery of the fifth nanosheet in the second direction and the third direction. The second gate wiring surrounds the outer periphery of the sixth nanosheet in the second direction and the third direction. The first dummy gate wiring surrounds the outer periphery of the seventh nanosheet in the second direction and the third direction. The second dummy gate wiring surrounds the outer periphery of the eighth nanosheet in the second direction and the third direction. A surface of the fifth nanosheet on the side opposite to the first side in the second direction is exposed from the first gate wiring. A surface of the sixth nanosheet on the side opposite to the second side in the second direction is exposed from the second gate wiring. A surface of the seventh nanosheet on the side opposite to the first side in the second direction is exposed from the first dummy gate wiring. A surface of the eighth nanosheet on the side opposite to the second side in the second direction is exposed from the second dummy gate wiring.

5. The semiconductor integrated circuit device according to claim 4, wherein: A third dummy gate wiring and a fourth dummy gate wiring extending along the second direction are formed at the cell boundary between the first standard cell and the second standard cell. The first gate wiring, the first dummy gate wiring, and the third dummy gate wiring are arranged at equal intervals in the first direction, The second gate wiring, the second dummy gate wiring, and the fourth dummy gate wiring are arranged at equal intervals in the first direction.

6. A semiconductor integrated circuit device, characterized in that: The semiconductor integrated circuit device includes a plurality of cell rows, each of the plurality of cell rows includes a plurality of standard cells arranged along a first direction, and the plurality of cell rows are arranged along a second direction perpendicular to the first direction. The plurality of cell rows include a first cell row and a second cell row, the first cell row includes a first standard cell having a logic function, the second cell row includes a second standard cell, in the plurality of cell rows, the second standard cell is arranged at either end of the two ends in the second direction and does not have a logic function, The first standard cell includes a first region, a second region, a first nanosheet, a second nanosheet, a first gate wiring, and a second gate wiring. The first region is a formation region of a first conductivity type transistor, The second region is a region where a transistor of a second conductivity type different from the first conductivity type is formed, and the second region is adjacent to the first region in the second direction. The first nanosheet extends along the first direction and is formed in the first region. The second nanosheet extends along the first direction and is formed in the second region and is formed at the same position as the first nanosheet in the first direction. The first gate wiring extends along the second direction and surrounds the outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction. The second gate wiring extends along the second direction and surrounds the outer periphery of the second nanosheet in the second direction and the third direction. The second standard cell includes a third nanosheet and a first dummy gate wiring, The third nanosheet extends along the first direction and is formed at the same position as the first nanosheet in the first direction, and is formed adjacent to the first nanosheet in the second direction. The first dummy gate wiring extends along the second direction and surrounds the outer periphery of the third nanosheet in the second direction and the third direction. A surface of the first nanosheet on one side in the second direction, that is, a first side, is exposed from the first gate wiring. A second side of the second nanosheet in the second direction is exposed from the second gate wiring. The surfaces of the first nanosheet and the third nanosheet facing each other are exposed from the first gate wiring and the first dummy gate wiring, respectively, or the surfaces of the first nanosheet and the third nanosheet facing each other are not exposed from the first gate wiring and the first dummy gate wiring, respectively.

7. The semiconductor integrated circuit device according to claim 6, wherein: The first side is a side of the first nanosheet opposite to the third nanosheet, A surface of the third nanosheet opposite to the first nanosheet is exposed from the first dummy gate wiring.

8. The semiconductor integrated circuit device according to claim 6, wherein: The first side is a side of the first nanosheet opposite to the third nanosheet, A surface of the third nanosheet opposite to the first nanosheet is exposed from the first dummy gate wiring.

9. The semiconductor integrated circuit device according to claim 6, wherein: The second standard cell further includes a fourth nanosheet and a second dummy gate wiring, The fourth nanosheet extends along the first direction and is formed at the same position as the first nanosheet in the first direction, The second dummy gate wiring extends along the second direction and surrounds the outer periphery of the fourth nanosheet in the second direction and the third direction. A surface of the third nanosheet on the side opposite to the first side in the second direction is exposed from the first dummy gate wiring. A surface of the fourth nanosheet on the side opposite to the second side in the second direction is exposed from the second dummy gate wiring.

10. The semiconductor integrated circuit device according to claim 9, wherein: The first standard cell further includes a fifth nanosheet and a sixth nanosheet, The fifth nanosheet extends along the first direction and is formed in the first region and is formed at the same position as the first nanosheet in the first direction. The sixth nanosheet extends along the first direction and is formed in the second region and is formed at the same position as the first nanosheet in the first direction. The second standard cell further includes a seventh nanosheet and an eighth nanosheet, The seventh nanosheet extends along the first direction and is formed at the same position as the first nanosheet in the first direction, The eighth nanosheet extends along the first direction and is formed at the same position as the first nanosheet in the first direction, The first gate wiring surrounds the outer periphery of the fifth nanosheet in the second direction and the third direction. The second gate wiring surrounds the outer periphery of the sixth nanosheet in the second direction and the third direction. The first dummy gate wiring surrounds the outer periphery of the seventh nanosheet in the second direction and the third direction. The second dummy gate wiring surrounds the outer periphery of the eighth nanosheet in the second direction and the third direction. A surface of the fifth nanosheet on the side opposite to the first side in the second direction is exposed from the first gate wiring. A surface of the sixth nanosheet on the side opposite to the second side in the second direction is exposed from the second gate wiring. The surface of the seventh nanosheet on the first side in the second direction is exposed from the first dummy gate wiring. The surface of the eighth nanosheet on the second side in the second direction is exposed from the second dummy gate wiring.

11. The semiconductor integrated circuit device according to claim 6, wherein: The first gate wiring, the second gate wiring, and the first dummy gate wiring are formed at the same position in the first direction.

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