Switched capacitor circuit

Abstract

The invention relates to a switched capacitor circuit comprising a metal oxide semiconductor field effect transistor based switch comprising a first metal oxide semiconductor field effect transistor (1) having a gate, a source and a drain, wherein the source is connected to a first node (T1) and the drain is connected to a second node (T2), or the drain is connected to the first node (T1) and the source is connected to the second node (T2), a second metal oxide semiconductor field effect transistor (2) having a gate, a source and a drain, wherein the source is connected to the drain and the source and drain together are connected to the second node (T2), a first capacitor (C1) connected between the first node (T1) and a third node (T3), and a second capacitor (C2) connected between the second node (T2) and the third node (T3).

Description

TECHNICAL FIELD

[0001] The present invention relates to a switched-capacitor circuit comprising metal-oxide-semiconductor field-effect transistors. BACKGROUND

[0002] Switched-capacitor circuits are widely used in various analog and mixed-signal circuits, such as sample-and-hold circuits and analog-to-digital converters. The accuracy of switched-capacitor circuits is typically limited by charge injection and clock feedthrough caused by switches made of metal-oxide-semiconductor field-effect transistors (MOSFETs or MOS). Charge injection occurs when a switching MOS is turned off, and the remaining channel charge in the switching MOS is injected into its source terminal and drain terminal. Clock feedthrough is caused by the gate-source / gate-drain capacitance of the switching MOS, which is the undesired capacitive coupling between the digital signal connected to the gate of the switching MOS and the analog signal at the source or drain of the switching MOS. Both charge injection and clock feedthrough cause errors in the analog signal at the source terminal or drain terminal of the switching MOS.

[0003] There are several known techniques that attempt to address the effects of charge injection and clock feedthrough. These prior art solutions are described below with reference to Figure 1A , Figure 1B , Figure 4 .

[0004] Figure 1A The circuit shown in (not fully shown in the figure) uses a pair of complementary MOSFETs, consisting of one N-type MOS (or NMOS) and one P-type MOS (or PMOS) connected in parallel between two terminals or nodes T1 and T2, both complementary MOSFETs being controlled by two inverted signals S1 and S2. This circuit is used to let the charge injected by the NMOS cancel the charge injected by the PMOS when both the NMOS and PMOS are turned off at the same time. By matching the gate-source / gate-drain capacitances between the NMOS and PMOS, the effects of clock feedthrough can be minimized. However, the amount of charge injected by the NMOS and PMOS depends on the channel potentials before both are turned off, as well as on process variations. The matching of the gate-source / gate-drain capacitances between the NMOS and PMOS is also affected by process variations. Therefore, in practice, it is usually not possible to completely cancel the injected charge and clock feedthrough.

[0005] Figure 1BThe circuit (not fully shown in the figure) uses a single MOS as a switch and a dummy MOS that is about half the size of the switch MOS. The switch MOS and the dummy MOS belong to the same type (i.e. NMOS or PMOS) but are controlled by inverse signals S1 and S2, wherein the first signal S1 controls the gate of the switch MOS and the second signal S2 controls the gate of the dummy MOS. The source and drain terminals of the dummy MOS are both connected to one terminal T2 of the switch MOS, wherein the injected charge will be cancelled. As the switch MOS turns off, the dummy MOS turns on. Assuming that the switch MOS has exactly half of its channel charge injected to each of its source and drain terminals at the time it turns off, the dummy MOS should be able to exactly absorb the amount of injected charge at the time it turns on. If the width of the switch MOS is twice the width of the dummy MOS, the gate-source / gate-drain capacitance of one terminal of the switch MOS matches the gate-source / gate-drain capacitance of both terminals of the dummy MOS. Thus, the clock feedthrough effect of the switch MOS is cancelled by the dummy MOS. However, the assumption that exactly half of the channel charge of the switch MOS is injected to each of the terminals T1 or T2 at the time the switch MOS turns off is often not feasible in practice. Therefore, this circuit does not guarantee a complete cancellation of the charge injection in practice.

[0006] In US5479121, Figure 2 The circuit shown consists of a switch MOS, a dummy MOS, an inverter and three capacitors C1, C2, C3 and is designed to compensate for the charge injection of the switch MOS. However, despite its relative complexity and energy consumption, this compensation mechanism relies on the assumption that the distribution of the channel charge of the switch MOS injected into each of its source and drain terminals T1 and T2 is identical to the distribution of the channel charge of the dummy MOS. Since the charge distribution depends on the impedance ratio of both terminals of the MOS, this assumption often fails in practice due to different terminal impedance ratios of the switch MOS and the dummy MOS, resulting in an incomplete compensation of the charge injection.

[0007] In US6850098, a circuit as Figure 3 shown and a method for nullifying the charge injection are proposed, which circuit comprises a switch MOS, two dummy MOSes and two capacitors C1, C2. However, this circuit also relies on the assumption that the proportion of channel charge injected by the switch MOS and absorbed by the dummy MOSes is equal. This assumption cannot be guaranteed in practice either, which leads to an incomplete compensation of the charge injection.

[0008] In US7663424, a circuit as Figure 4A dual switch circuit with low charge injection and clock feedthrough is shown, which includes coarse switch MOS and fine switch MOS and optional buffer circuit. The dual switch circuit opens both coarse switch MOS and fine switch MOS simultaneously for coarse sampling duration and closes coarse switch MOS while keeping fine switch MOS open, thereby correcting the charge injection and clock feedthrough caused by coarse switch MOS. Charge injection and clock feedthrough still occur when fine switch MOS is off. By properly adjusting the size of the transistors of coarse switch MOS and properly selecting the coarse sampling duration, the size of fine switch MOS can be reduced. Therefore, its charge injection and clock feedthrough can be reduced compared to using only coarse switch MOS at the same sampling speed. However, this circuit relies on the assumption that the size of fine switch MOS can be small enough so that the effect of charge injection and clock feedthrough from fine switch MOS is within an acceptable range. In practice, for compact design, when a single MOS switch made of minimum size (allowed by manufacturing process) provides sufficient sampling speed, this circuit does not further reduce the charge injection and clock feedthrough of MOS switch with minimum size.

[0009] In summary, in switched capacitor circuits, the need for practical and effective circuit design to cancel out switch charge injection and / or clock feedthrough has not been met. The circuit design should address and / or achieve one, some or all of the following objectives: effectively reduce or cancel charge injection and / or clock feedthrough of MOS switch (especially small or minimum size MOS switch), require low power consumption, low complexity and / or small chip area to implement the circuit. SUMMARY

[0010] According to the present invention, these objectives are achieved by providing a switched capacitor circuit as follows.

[0011] Based on, for example, in Figure 1B In the circuit shown, the prior art MOSFET circuit solution of pseudo-MOS absorbs and thus compensates for the channel charge injected by the switch MOS, the basic idea of the present invention is to determine the distribution or split ratio of the channel charge of the switch MOS according to the impedance of terminals T1 and T2 during the off period. Therefore, such a circuit cannot achieve complete charge injection cancellation unless the impedance on both sides of the switch is matched during the off period. Therefore, in the switched capacitor circuit according to the present invention, the first node and the second node corresponding to the source terminal and the drain terminal of the switch MOS are connected to a common third terminal through known impedance (i.e. first capacitor and second capacitor) respectively.

[0012] Thus, according to the present application, the switched capacitor circuit comprises a metal oxide semiconductor field effect transistor based switch. The switch comprises a first metal oxide semiconductor field effect transistor, hereinafter possibly abbreviated as MOS, and a second MOS. In the first MOS, the source or drain is connected to a first node of the circuit, and vice versa, the drain or source is connected to a second node of the circuit. In contrast, in the second MOS, the source is connected to the drain, and the source and drain together are connected to the second node. The first MOS can act as a switch MOS, as it is responsible for the actual switching action between the first node and the second node, while the second MOS can act as a dummy MOS, which is in a short-circuit state and has the effect of absorbing charge injection of the switch MOS when it is turned off to counteract the charge injection.

[0013] The small signal ground, which can also be referred to as AC (alternating current) ground, can refer to any stable node that is not affected by the AC signal of interest. This includes nodes such as the circuit ground node GND or the circuit supply voltage node VDD. Here, it means that the impedance between the first node and the small signal ground should match the impedance between the second node and the small signal ground, as long as it is required to match the impedance between the first node and the second node.

[0014] Since the impedances of the two capacitors are known and can be freely preselected, they can be chosen such that during switching of the switch MOS, the corresponding total impedance between each of the first node and the second node and the small signal ground is matched. By correctly choosing the values of the two capacitors, the impedance between the first node and the second node can be negligible compared to any impedance between the first node, the second node or the third node and the small signal ground, including any parasitic impedance at the first node, the second node or the third node.

[0015] According to a preferred embodiment, the switched capacitor circuit is designed such that the gate of the first MOS receives a first gate signal and the gate of the second MOS receives a second gate signal, wherein the first gate signal and the second gate signal are formed such that the second MOS is turned on after the first MOS is turned off. As explained above in connection with the prior art shown in Figure 1B Turning on the second MOS after the first MOS is turned off, as explained above in connection with the prior art shown in Fig. 1, results in a relatively predictable portion of the channel charge injected into the second node by the first MOS when it is turned off, thus making the compensation of the second MOS more reliable.

[0016] According to a preferred embodiment, the switched-capacitor circuit is designed such that the gate of the first MOS receives a first gate signal and the gate of the second MOS receives a second gate signal, which is the inverted first gate signal. In other words, the first gate signal is complementary to the second gate signal, such that the second gate signal carries a logic 1 while the first gate signal carries a logic 0, or vice versa. The first or second gate signal can be obtained by passing the other gate signal through an inverter circuit. The use of the inverted gate signal has the effect that the second MOS is turned on while the first MOS is turned off, thereby allowing the second MOS to absorb the residual channel charge of the first MOS injected into the second node.

[0017] Preferably, there is a delay between the falling edge of the first gate signal and the rising edge of the second gate signal and / or between the rising edge of the first gate signal and the falling edge of the second gate signal. When both MOS are of the N-type, the rising edge of the second gate signal follows the falling edge of the first gate signal. When both MOS are of the P-type, the falling edge of the second gate signal follows the rising edge of the first gate signal. This delay can guarantee that the first MOS is fully turned off and that charge injection is created and distributed before the second MOS is turned on to absorb the injected charge on the second node. In particular, the switched-capacitor circuit can be designed such that the first gate signal has passed at least 50%, 70% or 90% of its respective signal edge (either falling or rising) before the second gate signal has passed at most 10%, 30% or 50% of its respective signal edge. As an example, when the rising edge of the second gate signal follows the falling edge of the first gate signal, advantageously the first gate signal will have fallen at least 90% before the second gate signal has risen 10% of its maximum value.

[0018] Ideally, the channels of the first and second MOS have exactly or almost the same length, or have substantially equal lengths. However, even if not optimal, the present application can work if the channel length of the second MOS is between 90% and 110% of the channel length of the first MOS, or even between 75% and 125% of the channel length of the first MOS.

[0019] Preferably, the channel width of the second MOS is between 30% and 70% of the channel width of the first MOS, or between 40% and 60% of the channel width of the first MOS, or substantially equal to half of the channel width of the first MOS. In combination with the channel lengths of the two MOSes being substantially or substantially equal, the channel width of the second MOS being substantially or substantially half of the channel width of the first MOS means that the second MOS can absorb substantially or substantially half of the channel charge of the first MOS. When the first MOS is turned off, it injects half of the channel charge into its source and the other half into its drain. Therefore, the present embodiment will have the effect that the second MOS can absorb all of the channel charge injected into the second node.

[0020] According to an advantageous embodiment, the first capacitance of the first capacitor and the second capacitance of the second capacitor are of the same order of magnitude or substantially equal. The first and second capacitances being of the same order of magnitude especially means that their difference does not exceed a factor of 10. Preferably, the first and second capacitances only differ by a factor of five or two. More preferably, their values differ by less than 10% or 5%.

[0021] In a preferred embodiment, the first capacitor and / or the second capacitor has a capacitance of at least 10 fF, 32 fF, 100 fF or 320 fF. A higher capacitance has the advantage that the impedance between the first and second nodes becomes more negligible compared to any impedance between the first, second or third node and the small signal ground, including any parasitic impedance at the first, second or third node. Any impedance value mentioned here and in the following, including any parasitic impedance, refers to the impedance determined at the gate signal frequency, which is the main frequency component of the gate signal provided to the gate of the MOSes inside the circuit, such as the first and second switching signals provided to the first and second MOSes.

[0022] According to another preferred embodiment, the capacitance of the first capacitor and / or the second capacitor is at least 5 times, 10 times, 20 times or 100 times the first parasitic capacitance of the first node, the second parasitic capacitance of the second node and / or the third parasitic capacitance of the third node. It would be even more preferable if the capacitances of the first and second capacitor are at least 5 times, 10 times, 20 times or 100 times the largest of the three parasitic capacitances. Each parasitic capacitance can be measured as the capacitance between the respective node and the small signal ground.

[0023] Advantageously, the switched capacitor circuit is configured such that the second node or the third node is held at a virtual ground. This especially means that the potential of this second node or third node is stable or fixed for signal frequencies lying within a predefined signal frequency range. When the signal frequency lies outside of said predefined signal frequency range, this second node or third node can have a floating potential.

[0024] According to a preferred embodiment, the switched capacitor circuit is configured as a sample-and-hold circuit comprising an input buffer connected to the first node and a virtual ground buffer connected to the third node, whereby the second node is configured as an output of the sample-and-hold circuit. In this embodiment, the input signal of the sample-and-hold circuit is provided to the input terminal of the input buffer, while the input terminal of the virtual ground buffer is provided with a reference signal. Due to the virtual ground buffer, the third node is thus held at a virtual ground potential.

[0025] According to an alternative embodiment, the switched capacitor circuit can be configured as a capacitive feedback amplifier circuit, in particular for a delta-sigma modulator, comprising an input buffer connected to the third node and an amplifier and a third capacitor connected in parallel between the first node and the second node, wherein the second node is connected to an input of the amplifier and the first node is configured as an output of the capacitive feedback amplifier circuit. Here, the input buffer again provides the input signal at its input terminal. In this configuration, the second node connected to the input of the amplifier operates at a virtual ground potential. The third capacitor serves as a feedback loop for the amplifier. The first MOS serves as a reset switch for the capacitive feedback amplifier.

[0026] Advantageously, for both embodiments described above, the capacitance of the first capacitor and / or the second capacitor is equal to at least 5 times, 10 times, 20 or 100 times the value of 1 / (2-pi-f-R). Wherein f is a dominant frequency component of a gate signal provided to a gate of the first and / or second MOS, and R is a small signal node resistance of the first node, a small signal node resistance of the third node, or the smaller of these two small signal node resistances. The node resistance can in particular be measured between the respective node and a small signal ground. As mentioned above, the small signal ground comprises the circuit ground GND and the circuit supply voltage node VDD, as they are stable nodes in the frequency range of interest.

[0027] If the switched capacitor circuit is configured as a sample-and-hold circuit as described above, R can thus be a small signal output resistance of the input buffer, a small signal output resistance of the virtual ground buffer, or the smaller of these two small signal output resistances. On the other hand, if the switched capacitor circuit is configured as a capacitive feedback amplifier circuit as described above, R can thus be a small signal output resistance of the input buffer, a small signal output resistance of the amplifier, or the smaller of these two small signal output resistances.

[0028] Preferably, the first MOS and the second MOS belong to the same type, i.e. are both configured as NMOS or PMOS. BRIEF DESCRIPTION OF DRAWINGS

[0029] Some examples of embodiments of the present application will be explained in more detail in the following description in connection with the attached drawings, in which:

[0030] Figure 1A A first MOSFET circuit for minimizing charge injection and clock feedthrough according to the prior art is shown;

[0031] Figure 1B A second MOSFET circuit for minimizing charge injection and clock feedthrough according to the prior art is shown;

[0032] Figure 2 A third MOSFET circuit for minimizing charge injection and clock feedthrough according to the prior art is shown;

[0033] Figure 3 A fourth MOSFET circuit for minimizing charge injection and clock feedthrough according to the prior art is shown;

[0034] Figure 4 A fifth MOSFET circuit for minimizing charge injection and clock feedthrough according to the prior art is shown;

[0035] Figure 5 A MOSFET-based switch according to one preferred embodiment is shown;

[0036] Figure 6 A switch for embedding in a switched-capacitor circuit configured as a sample-and-hold circuit is shown; Figure 5

[0037] Figure 7 A small-signal equivalent circuit for injecting charge for the switched-capacitor circuit shown in Figure 6

[0038] Figure 8 Gate signals provided to a first MOS and a second MOS and their respective rise and fall times are shown;

[0039] Figure 9 A switch for embedding in a switched-capacitor circuit configured as a capacitive feedback amplifier circuit is shown; and Figure 5

[0040] Figure 10 A small-signal equivalent circuit for injecting charge for the switched-capacitor circuit shown in Figure 9 DETAILED DESCRIPTION

[0041] Figure 5 ​​​​A metal oxide semiconductor field effect transistor based switch according to a preferred embodiment is shown. The switch comprises a first metal oxide semiconductor field effect transistor 1 (hereinafter referred to as MOS), a second MOS 2, a first capacitor CI and a second capacitor C2. The first MOS 1, which acts as a switch MOS, connects a first node T1 to a second node T2. The source or drain of the first MOS 1 can be connected to the first node T1, with the other end connected to the second node T2. The source of the second MOS 2, which acts as a dummy MOS, is connected to its drain, and both are connected only to the second node T2. The first MOS 1 and the second MOS 2 are of the same type, but are controlled by inverse signals SI and S2. The first MOS 1 and the second MOS 2 can be either N-type or P-type, and only N-type will be exemplified below. The second MOS 2 has a channel area that is half that of the first MOS 1. In particular, the second MOS 2 has the same channel length as the first MOS 1, but its channel width is half that of the first MOS 1. The first node T1 is connected to a third node T3 through the first capacitor CI, while the second node T2 is connected to the third node T3 through the second capacitor C2.

[0042] The working principle of the switch shown in Figure 6 and Figure 9 will be explained below in connection with two different switched capacitor circuits. Figure 5

[0043] Figure 6 A switched capacitor circuit is shown, which is configured as a sample and hold circuit. It can be regarded as a general sample and hold circuit, in which an input signal is provided to a first node T1 through an input buffer Bi, and an output signal is provided at a second node T2, which samples and holds an analog signal on a second capacitor C2. A third node T3 is a virtual ground terminal, which is driven by a virtual ground buffer Bvg connected to a stable reference signal. The input buffer Bi and the virtual ground buffer Bvg are both analog buffers.

[0044] The small signal output resistance R1 of the input buffer Bi is:

[0045]

[0046] where V AP and VAN are the initial voltage values of the NMOS and PMOS within the input buffer Bi driving the first node T1, I DS1 is the drain-source current of the NMOS and PMOS within the input buffer Bi driving the first node T1. || is an operator that calculates the total resistance or total impedance value of two parallel resistances or impedances.

[0047] Similarly, the small signal output resistance R2 of the virtual ground buffer Bvg is:​

[0048]

[0049] where V AP and VANare the initial voltage values of the NMOS and PMOS within the virtual ground buffer Bvgdriving the third node T3, I DS2 is the drain-source current of the NMOS and PMOS within the virtual ground buffer Bvgdriving the third node T3.

[0050] The dominant frequency component of the first and second switching signals S1 and S2 connected to the gates of the first and second MOS 1 and 2 is f. Therefore, the dominant frequency component of the injected charge by the first MOS 1 is also f. For the injected charge, the small signal impedance of the first capacitor C1 is Z1 and the small signal impedance of the second capacitor C2 is Z2 (where i represents 1 or 2, and Ci represents the capacitance of the first or second capacitor C1, C2, respectively):

[0051]

[0052] The small signal equivalent circuit of the injected charge is shown in Figure 7 The parasitic impedances ZP1, ZP2 or ZP3 (drawn with dashed lines) are the corresponding parasitic impedances between the first, second or third node T1, T2 or T3 and the small signal ground, respectively. They are caused by the equivalent total parasitic capacitances CP1, CP2, CP3 between the three nodes T1, T2, T3 and the small signal ground (where i represents 1, 2 or 3):

[0053]

[0054] The desired values of the capacitances of the first and second capacitors C1 and C2 can be determined by two conditions. The first condition is that the values of Z1 and Z2 must be smaller than 1 / 10 (one tenth) of the values of each of ZP1, ZP2 and ZP3. Therefore, each of the capacitances denoted here also by C1 and C2 should satisfy the following constraint, where max(CP1, CP2, CP3) represents the maximum of the three capacitance values CP1, CP2 and CP3 (where i represents 1 or 2): Ci > 10 · max(CP1, CP2, CP3).

[0055] In fact, the parasitic capacitance values of CP1, CP2, CP3 are themselves affected by the capacitance values of C1 and C2. The two capacitors C1 and C2 are usually constructed as metal-insulator-metal (MIM) capacitors or metal-oxide-metal (MOM) capacitors. Generally, if the values of C1 and C2 are less than 10 fF, the minimum capacitance values of CP1, CP2, CP3 are in the range of about 1 fF. Therefore, the values of C1 and C2 should generally be at least 10 fF. The values of CP1, CP2, CP3 increase with the increase of the values of C1 and C2. With a reasonable layout design, the values of CP1, CP2, CP3 can be kept below 1 / 10 of the values of C1, C2. Therefore, with a proper layout design of the capacitors C1 and C2, the impedances Z1 and Z2 are kept below 1 / 10 of the parasitic impedances ZP1, ZP2, ZP3.

[0056] In addition, the second condition is that the values of Z1 and Z2 must also be less than 1 / 10 of R1 and R2. For a low-power sample-and-hold circuit, I DS1 and I DS2 are usually between 1 nA and 1 mA. Assuming V AP and V AN are both 10 V, then R1 and R2 are usually between 5 kOhm and 5 x 10 9 Ohm. If I DS1 and I DS2 are about 1 mA, then R1 and R2 are about 5 kOhm. Therefore, the constraints for the respective C1 and C2 can be determined by the following equations, where min(R1, R2) represents the smaller one of R1 and R2, and f is usually 10 GHz, which means the rise time and fall time of the switching signals S1 and S2 are about 100 ps (here, i represents 1 or 2):

[0057]

[0058] Therefore, if I DS1 and I DS2 are both about 1 mA, then C1 and C2 should be at least 32 fF. If I DS1 and I DS2 are about 1 nA, then R1 and R2 are about 5 x 10 9 Ohm. In this case, the second condition only requires C1 and C2 to be greater than 3.2 x 10 -20 F.

[0059] Overall, the above two conditions require that, for I DS1 and I DS2For a low-power sample-and-hold circuit between 1 nA and 1 mA, C1 and C2 should be at least 32 fF. However, it is desirable to satisfy and even exceed the above two conditions to provide better cancellation of charge injection (which will be explained in more detail below). For example, if C1 and C2 are chosen to be at least 320 fF and CP1, CP2, CP3 are kept less than 3.2 fF, and Z1 and Z2 are kept less than 1 / 100 of ZP1, ZP2, ZP3, and R1 and R2, then better cancellation of charge injection can be achieved.

[0060] As a non-limiting example, assume V AP and V AN are both 10 V, and f is 10 GHz. The following values can be chosen: I DS1 is 1 μA, I DS2 is 10 μA, so that R1 is 5 MOhm and R2 is 500 kOhm, R1 is greater than R2; C1 and C2 are both 100 fF, so that Z1 and Z2 are both about 160 Ohm, which is less than 1 / 1000 of R1 and R2. And CP1, CP2, CP3 are kept below 5 fF by layout design, so that Z1, Z2 are 20 times less than each of ZP1, ZP2, ZP3.

[0061] During the sampling phase, the first MOS 1 is on and the second MOS 2 is off. If both the first MOS 1 and the second MOS 2 are N-type, then the gate of the first MOS 1 is high voltage (S1 = VDD) and the gate of the second MOS 2 is low voltage (S2 = GND). If both the first MOS 1 and the second MOS 2 are P-type, then the gate of the first MOS 1 is low voltage (S1 = GND) and the gate of the second MOS 2 is high voltage (S2 = VDD). Thus, during the sampling phase, the second node T2, which is the output, is connected to the first node T1, which is the input, and follows any input signal within the bandwidth of the input buffer (Bi).

[0062] To end the sampling phase and enter the hold phase, the first MOS 1 is turned off and then the second MOS 2 is turned on. If both the first MOS 1 and the second MOS 2 are N-type, then the gate of the first MOS 1 is transitioned from high voltage (S1 = VDD) to low voltage (S1 = GND) and then the gate of the second MOS 2 is transitioned from low voltage (S2 = GND) to high voltage (S2 = VDD). If both the first MOS 1 and the second MOS 2 are P-type, then the gate of the first MOS 1 is transitioned from low voltage (S1 = GND) to high voltage (S1 = VDD) and then the gate of the second MOS 2 is transitioned from high voltage (S2 = VDD) to low voltage (S2 = GND).

[0063] When the first MOS transistor 1 transitions from the on state to the off state, its remaining channel charge is injected into the first node T1 and the second node T2. For the injected charge, the total impedance between the first node T1 and the small-signal ground is ZT1, and the total impedance between the second node T2 and the small-signal ground is ZT2. Because Z1 and Z2 are both much smaller than each of R1, R2, and ZP1, ZP2, and ZP3, the following relationship holds: ZT1≈ZT2≈R1||R2||ZP1||ZP2||ZP3.

[0064] The tolerance of this approximate equation depends on the margin of the design exceeding the two conditions for determining C1 and C2 mentioned earlier. For example, if Z1 and Z2 are approximately 1 / 10 of ZP1, ZP2, ZP3, and R1 and R2, then ZT1 may differ from ZT2 by 10%; while if Z1 and Z2 are approximately 1 / 100 of ZP1, ZP2, ZP3, and R1 and R2, then ZT1 may differ from ZT2 by only 1%.

[0065] If the remaining channel charge of the first MOS 1 shows that ZT1 and ZT2 are approximately equal, then approximately half of the remaining channel charge of the first MOS 1 is injected into each of the first node T1 and the second node T2.

[0066] like Figure 8 As shown, after the first MOS 1 is turned off, the second MOS 2 immediately begins to transition from the off state to the on state. The first gate signal S1 driving the gate of the first MOS 1 is represented by a solid line, and the second gate signal S2 driving the gate of the second MOS 2 is represented by a dashed line. As mentioned above, approximately half of the remaining channel charge of the first MOS 1 is injected into the second node T2. Because the channel area of ​​the second MOS 2 is half that of the first MOS 1, during the transition of the second MOS 2 from the off state to the on state, the channel of the second MOS 2 absorbs half of the remaining channel charge of the first MOS 1. Therefore, after the second MOS 2 is turned on, the charge injected by the first MOS 1 into the second node T2 is almost completely absorbed by the second MOS 2, achieving effective charge injection cancellation at the circuit output. The larger the margin exceeding the two conditions for determining the values ​​of C1 and C2 mentioned above in this design, the more effective the charge injection cancellation.

[0067] Furthermore, because the channel width of the second MOS 2 is half that of the first MOS 1, the total capacitance between the gate of the second MOS 2 and the second node T2 (i.e. the sum of the gate-source and gate-drain capacitances) is approximately equal to the gate-source (or gate-drain, depending on whether the source or drain of the first MOS 1 is connected to the second node T2) capacitance between the gate of the first MOS 1 and the second node T2. Thus, the clock feedthrough effects from the gate signal S1 of the first MOS 1 and the gate signal S2 of the second MOS 2 also effectively cancel each other out on the second node T2.

[0068] The charge injection and clock feedthrough effects on the first node T1 are irrelevant because the first node T1, as the input terminal, is driven and thus can eventually overcome these charge injection and clock feedthrough effects. In the hold phase, the first MOS 1 is off and the second MOS 2 is on. The output terminal of the second node T2 holds its voltage signal. R1 is designed to be larger than R2, which means that I DS2 is larger than I DS1 Thus the virtual buffer Vbg has more driving strength and higher bandwidth than the input buffer Bi. Therefore, the second node T2 is effectively isolated from the first node T1.

[0069] The charge injection and clock feedthrough effects on the first node T1 and the second node T2 are irrelevant when transitioning from the hold phase to the sample phase because both the first node T1 and the second node T2 are driven in the sample phase and thus can eventually overcome the charge injection and clock feedthrough effects.

[0070] A single-input capacitive feedback amplifier circuit is used in a delta-sigma modulator analog-to-digital converter. In patent publication US 7,728,269 B2 entitled "Photoarray for detecting time-dependent image data", a capacitive feedback amplifier is used to encode an analog signal related to light intensity using delta modulation in each photosensing pixel. The capacitive feedback amplifier amplifies the difference of the analog signal since the last reset. A reset switch resets the capacitive feedback amplifier and sets a new reference level to the current analog signal value. However, in practice, the reset switch made of a single MOS introduces charge injection and clock feedthrough every time it is turned off at the end of the reset period. The injected charge and clock feedthrough cause the output of the capacitive feedback amplifier to deviate from its reset level, resulting in severe inaccuracies in the subsequent quantization stage.

[0071] Figure 9A switched capacitor circuit is shown, configured as a capacitive feedback amplifier circuit. In this configuration, the first node T1 serves as an output terminal, connected to the output terminal of the capacitive feedback amplifier. The third node T3 serves as an input terminal, driven by an input buffer Bi connected to an analog buffer of an input signal. The second node T2 serves as a virtual ground terminal, connected to the input terminal of the amplifier A.

[0072] The small signal output resistance of the input buffer Bi is R1:

[0073]

[0074] where V AP and V AN are the initial voltage values of the NMOS and PMOS within the input buffer Bi driving the third node T3, I DS1 is the drain-source current of the NMOS and PMOS within the input buffer Bi driving the third node T3. Also, || is an operator for calculating the total resistance or total impedance value of two parallel resistances or impedances.

[0075] The small signal output resistance of the amplifier A is R2:

[0076]

[0077] where V AP and V AN are the initial voltage values of the NMOS and PMOS within the amplifier A driving the first node T1, I DS2 is the drain-source current of the NMOS and PMOS within the amplifier A driving the first node T1.

[0078] The dominant frequency component of the switching signals S1 and S2 connected to the gates of the first MOS 1 and the second MOS 2 is f, so the dominant frequency component of the injected charge is also f. For the injected charge, the small signal impedance of the first capacitor C1 is Z1, the small signal impedance of the second capacitor C2 is Z2, and the small signal impedance of the third capacitor C3 is Z3 (where i represents 1, 2, or 3, and Ci represents the capacitance of the first, second, or third capacitor C1, C2, or C3, respectively):

[0079]

[0080] The small signal equivalent circuit of the injected charge is shown in Figure 10 The parasitic impedances ZP1, ZP2, or ZP3 (drawn with dashed lines) are the corresponding parasitic impedances between the first, second, or third node T1, T2, or T3 and the small signal ground, respectively. They are caused by the equivalent total parasitic capacitances CP1, CP2, CP3 (where i represents 1, 2, or 3) between the three nodes T1, T2, T3 and the small signal ground:

[0081]

[0082] The desired values of the capacitances of the first and second capacitors C1 and C2 can be determined by two conditions. The first condition is that the values of Z1 and Z2 must be less than 1 / 10 of the values of each of ZP1, ZP2 and ZP3. Thus, each of the capacitances represented here also by C1 and C2 should satisfy the following constraint, where max(CP1, CP2, CP3) represents the maximum of the three capacitance values CP1, CP2 and CP3 (where i represents 1 or 2):

[0083] Ci > 10 · max(CP1, CP2, CP3)

[0084] In practice, the parasitic capacitance values of CP1, CP2, CP3 are themselves influenced by the capacitance values C1 and C2. The two capacitors C1 and C2 are typically built as metal-insulator-metal (MIM) capacitors or metal-oxide-metal (MOM) capacitors. In general, if the values of C1 and C2 are less than 10 fF, the minimum capacitance values of CP1, CP2, CP3 are in the range of approximately 1 fF. Thus, the values of C1 and C2 should typically be at least 10 fF. The values of CP1, CP2, CP3 increase with increasing values of C1 and C2. With a reasonable layout design, the values of CP1, CP2, CP3 can be kept below 1 / 10 of the values of C1, C2. Thus, with a proper layout design of the capacitors C1 and C2, the impedances Z1 and Z2 are kept below 1 / 10 of the parasitic impedances ZP1, ZP2, ZP3.

[0085] Furthermore, the second condition is that the values of Z1 and Z2 must also be less than 1 / 10 of R1 and R2. For low power single input capacitive feedback amplifier circuits, particularly implemented as a two-dimensional array in US 7728269 B2, I DS1 and I DS2 are typically between 1 pA and 1 μA, assuming V AP and V AN are 10 V, then R1 and R2 are typically between 5 MOhm and 5 x 10 12 Ohm. If I DS1 and I DS2 are approximately 1 μA, then R1 and R2 are approximately 5 MOhm. Thus, the constraint conditions for the respective C1 and C2 can be determined by the following equations, where min(R1, R2) represents the smaller of R1 and R2, and f is typically 10 GHz, which means that the rise and fall times of the switching signals S1 and S2 are approximately 100 ps (where i represents 1 or 2):

[0086]

[0087] Thus, if I DS1 and I DS2 are both around 1 pA, then C1 and C2 should be at least 3.2 x 10 -17 F. If I DS1 and I DS2 are around 1 nA, then R1 and R2 should be around 5 x 10 12 Ohm. In this case, the second condition only requires that C1 and C2 be greater than 3.2 x 10 -23 F.

[0088] In general, the above two conditions require that, for I DS1 and I DS2 a low power single input capacitance feedback amplifier circuit between 1 pA and 1 nA, C1 and C2 should be at least 10 fF. However, it is desirable to satisfy, and even exceed, the above two conditions to provide better cancellation of charge injection (which will be explained in more detail below). For example, if C1 and C2 are chosen to be at least 100 fF and CP1, CP2, CP3 are kept less than 1 fF, and Z1 and Z2 are kept less than 1 / 100 of ZP1, ZP2, ZP3, and R1 and R2, then better cancellation of charge injection can be achieved.

[0089] As a non-limiting example, assume that V AP and V AN are both 10 V, and f is 10 GHz, then the following values can be chosen: I DS1 is 1 nA, I DS2 is 10 nA, so that R1 is 5 GOhm and R2 is 500 MOhm, R1 is greater than R2; C1 and C2 are both 100 fF, so that Z1 and Z2 are both around 160 Ohm, which is less than 1 / 1,000,000 of R1 and R2. And CP1, CP2, CP3 are kept below 5 fF by layout design, so that Z1, Z2 are 20 times smaller than ZP1, ZP2, ZP3. C3 is 5 fF, so the ratio of C2 to C3 is 20, then the gain of the capacitance feedback amplifier is set to 20.

[0090] During the sampling phase, the first MOS 1 is on and the second MOS 2 is off. If both the first MOS 1 and the second MOS 2 are N-type, then the gate of the first MOS 1 is high voltage (S1 = VDD) and the gate of the second MOS 2 is low voltage (S2 = GND). If both the first MOS 1 and the second MOS 2 are P-type, then the gate of the first MOS 1 is low voltage (S1 = GND) and the gate of the second MOS 2 is high voltage (S2 = VDD). Thus, during the reset phase, the potential of the first node T1 is driven to be equal to the potential of the second node T2. R1 is designed to be greater than R2, which means that I DS2 is greater than IDS1 Thus, the virtual buffer Bvg has more drive strength and higher bandwidth than the input buffer Bi. Therefore, the first node T1 and the second node T2 maintain their reset levels regardless of the input signal.

[0091] To end the reset phase, the first MOS 1 is turned off and then the second MOS 2 is turned on. If the first MOS 1 and the second MOS 2 are both N-type, then the gate of the first MOS 1 transitions from a high voltage (S1 = VDD) to a low voltage (S1 = GND), and then the gate of the second MOS 2 transitions from a low voltage (S2 = GND) to a high voltage (S2 = VDD). If the first MOS 1 and the second MOS 2 are both P-type, then the gate of the first MOS 1 transitions from a low voltage (S1 = GND) to a high voltage (S1 = VDD), and then the gate of the second MOS 2 transitions from a high voltage (S2 = VDD) to a low voltage (S2 = GND).

[0092] When the first MOS 1 transitions from the on state to the off state, its remaining channel charge is injected into the first node T1 and the second node T2. For the injected charge, the total impedance between the first node T1 and the small-signal ground is ZT1, and the total impedance between the second node T2 and the small-signal ground is ZT2. Because Z1 and Z2 are both much smaller than each of R1, R2, and ZP1, ZP2, and ZP3, the following relationship holds: ZT1 « ZT2 « R1 || R2 || ZP1 || ZP2 || ZP3.

[0093] The tolerance of this approximation depends on how much the design exceeds the two conditions mentioned above for determining C1 and C2. For example, if Z1 and Z2 are about 1 / 10 of ZP1, ZP2, ZP3, and R1 and R2, then ZT1 can differ from ZT2 by 10%; whereas if Z1 and Z2 are about 1 / 100 of ZP1, ZP2, ZP3, and R1 and R2, then ZT1 can differ from ZT2 by only 1%.

[0094] If ZT1 and ZT2 are approximately equal from the remaining channel charge of the first MOS 1, then about half of the remaining channel charge of the first MOS 1 is injected into each of the first node T1 and the second node T2.

[0095] As Figure 8As shown, after the first MOS 1 is turned off, the second MOS 2 is subsequently turned on from an off state to an on state. As mentioned above, about half of the remaining channel charge of the first MOS 1 is injected into the second node T2. Because the channel area of the second MOS 2 is half of the channel area of the first MOS 1, during the transition of the second MOS 2 from the off state to the on state, the channel of the second MOS 2 absorbs half of the remaining channel charge of the first MOS 1. Thus, after the second MOS 2 is turned on, the charge injected into the second node T2 by the first MOS 1 is almost completely absorbed by the second MOS 2, achieving an effective charge injection cancellation for the second node T2. The greater the margin over the two conditions mentioned above for determining the values of C1 and C2, the more effective the charge injection cancellation.

[0096] Furthermore, because the channel width of the second MOS 2 is half of the channel width of the first MOS 1, the total capacitance between the gate of the second MOS 2 and the second node T2 (i.e., the sum of the gate-source and gate-drain capacitances) is about equal to the gate-source (or gate-drain, depending on whether the source or drain of the first MOS 1 is connected to the second node T2) capacitance between the gate of the first MOS 1 and the second node T2. Thus, the clock feedthrough effect from the gate signal S1 of the first MOS 1 and the gate signal S2 of the second MOS 2 is also effectively cancelled out on the second node T2.

[0097] The charge injection and clock feedthrough effect on the first node T1 is not a concern because the first node T1, which is the output of the amplifier A, is driven and thus can eventually overcome the charge injection and clock feedthrough effect.

[0098] During the amplification phase, the first MOS 1 is turned off and the second MOS 2 is turned on. The second node T2 maintains its signal. The output T2 produces an output signal that amplifies the variations of the input signal within the bandwidth of the capacitive feedback amplifier, the gain of which is determined by the ratio between C2 and C3.

[0099] During the transition from the amplification phase to the reset phase, both the charge injection and clock feedthrough effect on the second node T2 and the first node T1 are not a concern because both the second node T2 and the first node T1 are driven during the reset phase and thus can eventually overcome the charge injection and clock feedthrough effect.

[0100] Reference Signs

[0101] 1 first metal oxide semiconductor field effect transistor (first MOS)

[0102] 2 second metal oxide semiconductor field effect transistor (second MOS)

[0103] C1 first capacitor

[0104] C2 second capacitor

[0105] C3 third capacitor

[0106] S1 first gate signal

[0107] S2 second gate signal

[0108] T1 first node

[0109] T2 second node

[0110] T3 third node

[0111] Bi input buffer

[0112] Bvg virtual ground buffer

[0113] A amplifier

[0114] CP1, CP2, CP3 parasitic capacitance

[0115] ZP1, ZP2, ZP3 parasitic impedance

Claims

1. A capacitance feedback amplifier circuit for a delta modulator, characterized by: comprises a switched capacitor circuit comprising metal oxide semiconductor field effect transistor based switches; the metal oxide semiconductor field effect transistor based switches comprise: a first metal oxide semiconductor field effect transistor (1) having a gate, a source and a drain, wherein the source is connected to a first node (T1) and the drain is connected to a second node (T2), or the drain is connected to the first node (T1) and the source is connected to the second node (T2), a second metal oxide semiconductor field effect transistor (2) having a gate, a source and a drain, wherein the source is connected to the drain and the source and the drain together are connected to the second node (T2), a first capacitor (C1) connected between the first node (T1) and a third node (T3), and a second capacitor (C2) connected between the second node (T2) and the third node (T3); and the capacitive feedback amplifier circuit further comprises: an input buffer (Bi) connected to the third node (T3), and an amplifier (A) and a third capacitor (C3) connected in parallel between the first node (T1) and the second node (T2); and the second node (T2) is connected to an input of the amplifier (A) and the first node (T1) is configured as an output of the capacitive feedback amplifier circuit.

2. The capacitively- feedback amplifier circuit of claim 1, wherein, the gate of the first metal oxide semiconductor field effect transistor (1) receives a first gate signal and the gate of the second metal oxide semiconductor field effect transistor (2) receives a second gate signal, wherein the first gate signal and the second gate signal are formed such that the second metal oxide semiconductor field effect transistor (2) turns on after the first metal oxide semiconductor field effect transistor (1) turns off.

3. A capacitively feedbacked amplifier circuit according to claim 1 or 2, characterised in that, the gate of the first metal oxide semiconductor field effect transistor (1) receives a first gate signal and the gate of the second metal oxide semiconductor field effect transistor (2) receives a second gate signal, the second gate signal being the first gate signal inverted.

4. The capacitively- feedbacked amplifier circuit of claim 3, wherein, a delay is present between a falling edge of the first gate signal and a rising edge of the second gate signal and / or between a rising edge of the first gate signal and a falling edge of the second gate signal.

5. The capacitive feedback amplifier circuit according to the preceding claim 4, characterized in that, the first metal oxide semiconductor field effect transistor (1) and the second metal oxide semiconductor field effect transistor (2) belong to the same type.

6. The capacitive feedback amplifier circuit according to any of the preceding claims 1-2, 4-5, characterized by, the channel length of the second metal oxide semiconductor field effect transistor (2) is between 90% and 110% of the channel length of the first metal oxide semiconductor field effect transistor (1), or the channel length of the second metal oxide semiconductor field effect transistor (2) is equal to the channel length of the first metal oxide semiconductor field effect transistor (1).

7. The capacitive feedback amplifier circuit according to any of the preceding claims 1-2, 4-5, characterized by, the channel width of the second metal oxide semiconductor field effect transistor (2) is between 40% and 60% of the channel width of the first metal oxide semiconductor field effect transistor (1), or the channel width of the second metal oxide semiconductor field effect transistor (2) is equal to half of the channel width of the first metal oxide semiconductor field effect transistor (1).

8. The capacitive feedback amplifier circuit according to any of the preceding claims 1-2, 4-5, characterized by, The capacitance value of the first capacitor (C1) and the capacitance value of the second capacitor (C2) are in the same order of magnitude.

9. The capacitively- feedback amplifier circuit of the previous claim 8, characterized in that, The first capacitor (C1) and / or the second capacitor (C2) has a capacitance of at least 10 fF, 32 fF, 100 fF or 320 fF.

10. The capacitive feedback amplifier circuit according to any of the preceding claims 1-2, 4-5, characterized by, The capacitance of the first capacitor (C1) and / or the second capacitor (C2) is at least 5 times, 10 times or 20 times the first parasitic capacitance (CP1) of the first node (T1), the second parasitic capacitance (CP2) of the second node (T2) and / or the third parasitic capacitance (CP3) of the third node (T3).

11. The capacitive feedback amplifier circuit according to any of the preceding claims 1-2, 4-5, characterized by, The second node (T2) or the third node (T3) is held at a virtual ground.

12. The capacitively- feedback amplifier circuit of claim 11, wherein, The capacitance value of the first capacitor and / or the second capacitor is equal to at least 5 times, 10 times or 20 times the following value: 1 / (2pifR); wherein f is the main frequency component of the gate signal provided to the gate of the first metal oxide semiconductor field effect transistor (1) and / or the gate of the second metal oxide semiconductor field effect transistor (2); R is the small signal output resistance of the input buffer (Bi), the small signal output resistance of the amplifier (A) or the smallest of these small signal output resistances.

13. A sample-and-hold circuit, characterized by: comprises a switched capacitor circuit, the switched capacitor circuit comprising metal oxide semiconductor field effect transistor based switches; the metal oxide semiconductor field effect transistor based switches comprise: a first metal oxide semiconductor field effect transistor (1) having a gate, a source and a drain, wherein the source is connected to a first node (T1) and the drain is connected to a second node (T2) or the drain is connected to the first node (T1) and the source is connected to the second node (T2), a second metal oxide semiconductor field effect transistor (2) having a gate, a source and a drain, wherein the source is connected to the drain and the source and drain together are connected to a second node (T2), a first capacitor (C1) connected between the first node (T1) and a third node (T3), and a second capacitor (C2) connected between the second node (T2) and the third node (T3); and the sample-and-hold circuit further comprises: an input buffer (Bi) connected to the first node (T1), and a virtual ground buffer (Bvg) connected to the third node (T3); and the input signal of the sample-and-hold circuit is provided to the input of the input buffer (Bi) and the second node (T2) is configured as the output of the sample-and-hold circuit.

14. The sample-and-hold circuit according to claim 13, characterized in that: the channel length of the second metal oxide semiconductor field effect transistor (2) is between 90% and 110% of the channel length of the first metal oxide semiconductor field effect transistor (1), the channel width of the second metal oxide semiconductor field effect transistor (2) is between 40% and 60% of the channel width of the first metal oxide semiconductor field effect transistor (1), the channel width of the second metal oxide semiconductor field effect transistor (2) is between 40% and 60% of the channel width of the first metal oxide semiconductor field effect transistor (1). The capacitance value of the first capacitor (C1) and the capacitance value of the second capacitor (C2) are in the same order of magnitude.

15. The sample-and-hold circuit according to claim 13 or 14, characterized in that: The capacitance value of the first capacitor and / or the second capacitor is equal to at least 5, 10 or 20 times the value of 1 / (2πfR); wherein f is the main frequency component of the gate signal provided to the gate of the first metal oxide semiconductor field effect transistor (1) and / or the gate of the second metal oxide semiconductor field effect transistor (2); R is the small signal output resistance of the input buffer (Bi), the small signal output resistance of the virtual ground buffer (Bvg), or the minimum of these small signal output resistance values.

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