Memory system and method of operating the same

Abstract

Embodiments of the present disclosure relate to a memory system and an operation method thereof. According to embodiments of the present disclosure, the memory system may extract a first command from a host into a command queue, suspend execution of the first command when a lock request for the first command is received from the host, and resume execution of the first command when an unlock request for the first command is received or after the first command is suspended for an amount of time corresponding to a pause time value sent together with the lock request.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0162017, filed on November 27, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a memory system and an operating method thereof. Background Art

[0004] Memory systems include data storage devices that store data based on requests from a host, such as a computer, server, smart phone, tablet PC, or other electronic device. Examples of memory systems range from traditional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices, such as solid-state drives (SSDs), universal flash memory devices (UFS), or embedded MMC (eMMC) devices.

[0005] The memory system may also include a memory controller for controlling the memory device. The memory controller may receive commands from the host, and based on the received commands, may execute commands or control read / write / erase operations on the memory devices in the memory system. The memory controller may be used to execute firmware operations to perform logic operations for controlling such operations.

[0006] Generally, the memory system can process commands received from the host according to the order in which they are input, so commands input to the memory system later can be processed after commands input to the memory system earlier are processed. Summary of the invention

[0007] Embodiments of the present disclosure may provide a memory system and an operating method thereof that enable a host to control an execution order of commands.

[0008] Furthermore, embodiments of the present disclosure may provide a memory system and an operating method thereof that are capable of preventing a problem in which the execution time of other commands is delayed due to a command that is processing a large amount of data.

[0009] In one aspect, an embodiment of the present disclosure may provide a memory system including a memory device and a memory controller for communicating with the memory device and controlling the memory device to process a command requested by a host.

[0010] The memory controller may fetch the first command from the host into a command queue.

[0011] The memory controller may suspend execution of the first command when receiving a lock request for the first command from the host.

[0012] The memory controller may resume execution of the first command upon receiving the unlock request for the first command or after execution of the first command is suspended for an amount of time corresponding to a suspension time value sent with the lock request.

[0013] As an example, the memory controller may include a locker, which is a buffer for storing commands for which the host sends a lock request, and when a lock request for a first command is received from the host, the first command may also be stored in the locker. In this case, the memory controller may pop the first command from the locker when resuming execution of the first command.

[0014] As another example, when the memory controller receives a lock request for the first command from the host, it can suspend the first command. In this case, when the memory controller resumes the execution of the first command, it can extract the first command into the command queue again.

[0015] In another aspect, embodiments of the present disclosure may provide an operating method of a memory system.

[0016] The operating method of the memory system may include fetching a first command from a host into a command queue.

[0017] Furthermore, the operating method of the memory system may include receiving a lock request for the first command from the host.

[0018] Furthermore, the operating method of the memory system may include suspending execution of the first command when a lock request for the first command is received from the host.

[0019] Furthermore, the operating method of the memory system may include resuming execution of the first command when an unlock request for the first command is received or after execution of the first command is suspended for an amount of time corresponding to a suspension time value sent with the lock request.

[0020] As an example, suspending execution of the first command may include: storing the first command in a lock when a lock request for the first command is received from the host, and the lock may be a buffer for storing commands for which the host sends the lock request. In this case, the operating method of the memory system may also include popping the first command from the lock when resuming execution of the first command.

[0021] As another example, suspending execution of the first command may include suspending the first command when a lock request for the first command is received from the host. In this case, the operating method of the memory system may further include retrieving the first command into the command queue when resuming execution of the first command.

[0022] In another aspect, embodiments of the present disclosure may provide an operating method of a controller.

[0023] The operating method of the controller may include scheduling commands.

[0024] The method of operation of the controller may include executing the scheduled command.

[0025] Executing the scheduled commands may include executing subsequent commands of the scheduled commands when execution of a current command of the scheduled commands is interrupted in response to the first request from the host.

[0026] Executing the scheduled command may include executing the command whose execution was interrupted after execution of the subsequent command in response to a second request from the host or after a predetermined amount of time.

[0027] According to the embodiments of the present disclosure, the host can be enabled to control the execution order of commands.

[0028] Furthermore, according to the embodiments of the present disclosure, it is possible to prevent the problem that the execution time of other commands is delayed due to a command that is processing a large amount of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram showing the configuration of a memory system based on an embodiment of the disclosed technology.

[0030] Figure 2 is a block diagram schematically illustrating a memory device according to an embodiment of the disclosed technology.

[0031] Figure 3 is a diagram showing the structure of word lines and bit lines of a memory device based on an embodiment of the disclosed technology.

[0032] Figure 4 is a diagram schematically illustrating the operation of a memory system according to an embodiment of the present disclosure.

[0033] Figure 5 is a diagram illustrating an example of executing a command by a memory controller according to an embodiment of the present disclosure.

[0034] Figure 6 is a diagram illustrating an example in which a memory controller suspends execution of a first command based on a lock request according to an embodiment of the present disclosure.

[0035] Figure 7 is a diagram illustrating an example in which a memory controller resumes execution of a first command according to an embodiment of the present disclosure.

[0036] Figure 8is a diagram illustrating another example in which a memory controller resumes execution of a first command according to an embodiment of the present disclosure.

[0037] Fig. 9 is a diagram illustrating an example in which a memory controller processes a lock request according to an embodiment of the present disclosure.

[0038] Fig.10 is a diagram illustrating an example of the operation of a memory controller.

[0039] Fig.11 It is shown Fig. 9 FIG. 5 is a diagram of an example in which a memory controller described in FIG. 5 resumes execution of a first command.

[0040] Fig.12 It is shown Fig. 9 A diagram of an example in which a memory controller described in processes a second command after suspending execution of a first command.

[0041] Fig.13 It is shown Fig.12 0047] Figure 2 is a diagram of an example of a state of a memory controller described in FIG.

[0042] Fig.14 is a diagram illustrating another example of a memory controller processing a lock request according to an embodiment of the present disclosure.

[0043] Fig.15 It is shown Fig.14 FIG. 5 is a diagram of an example in which a memory controller described in FIG. 5 resumes execution of a first command.

[0044] Fig.16 is a diagram illustrating an operating method of a memory system according to an embodiment of the present disclosure.

[0045] Fig.17 is a diagram showing the configuration of a computing system based on some embodiments of the disclosed technology. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the specification, references to "an embodiment," "another embodiment," etc. do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments.

[0047] Figure 1 is a diagram showing a schematic configuration of a memory system 100 based on an embodiment of the disclosed technology.

[0048] In some implementations, the memory system 100 may include a memory device 110 configured to store data, and a memory controller 120 configured to control the memory device 110 .

[0049] The memory device 110 may include a plurality of memory blocks, each memory block including a plurality of memory cells for storing data. The memory device 110 may be configured to operate in response to a control signal received from the memory controller 120. For example, the operation of the memory device 110 may include a read operation, a program operation (also referred to as a "write operation"), an erase operation, etc.

[0050] The memory cells in the memory device 110 are used to store data and may be arranged in a memory cell array. The memory cell array may be divided into memory blocks of memory cells, and each block includes different pages of memory cells. In a typical implementation of a NAND flash memory device, a page of memory cells is the smallest memory unit that can be programmed or written, and data stored in the memory cells may be erased at a block level.

[0051] In some implementations, the memory device 110 may be implemented as various types, such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphic double data rate (GDDR) SDRAM, low power DDR (LPDDR), rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM).

[0052] The memory device 110 may be implemented in a three-dimensional array structure. Some embodiments of the disclosed technology are applicable to any type of flash memory device having a charge storage layer. In an implementation, the charge storage layer may be formed of a conductive material, and such a charge storage layer may be referred to as a floating gate. In another implementation, the charge storage layer may be formed of an insulating material, and such a flash memory device may be referred to as a charge trap flash memory (CTF).

[0053] The memory device 110 may be configured to receive a command and an address from the memory controller 120 to access a region of the memory cell array selected using the address. That is, the memory device 110 may perform an operation corresponding to the received command on a memory region of the memory device having a physical address corresponding to the address received from the memory controller 120.

[0054] In some implementations, the memory device 110 may perform a programming operation, a read operation, an erase operation, etc. During a programming operation, the memory device 110 may write data in an area selected by an address. During a read operation, the memory device 110 may read data from a memory area selected by an address. During an erase operation, the memory device 110 may erase data stored in a memory area selected by an address.

[0055] The memory controller 120 may control write (program) operations, read operations, erase operations, and background operations performed on the memory device 110. For example, the background operations may include operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0056] The memory controller 120 may control the operation of the memory device 110 at the request of the host. Alternatively, when the memory controller 120 performs such background operation of the memory device, the memory controller 120 may control the operation of the memory device 110 even without a request from the host.

[0057] The memory controller 120 and the host may be separate devices. In some implementations, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, as an example, the memory controller 120 and the host will be discussed as separate devices.

[0058] refer to Figure 1 , the memory controller 120 may include a memory interface 122 , a control circuit 123 , and a host interface 121 .

[0059] The host interface 121 may be configured to provide an interface for communicating with a host.

[0060] When receiving a command from the host HOST, the control circuit 123 may receive the command through the host interface 121 and may perform an operation of processing the received command.

[0061] The memory interface 122 may be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 may be configured to provide an interface for the memory device 110 and the memory controller 120 for the memory controller 120 to perform memory operations on the memory device 110 based on control signals and instructions from the control circuit 123.

[0062] The control circuit 123 may be configured to control the operation of the memory device 110 through the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may also include an error detection / correction circuit (ECC circuit) 126 and the like.

[0063] The processor 124 may control the overall operation of the memory controller 12 . The processor 124 may perform logic operations. The processor 124 may communicate with the host HOST through the host interface 121 . The processor 124 may communicate with the memory device 110 through the memory interface 122 .

[0064] Processor 124 may be used to perform operations associated with a flash translation layer (FTL) to efficiently manage memory operations on memory system 100. Processor 124 may convert a logical block address (LBA) provided by a host into a physical block address (PBA) through FTL. FTL may receive LBA and convert LBA into PBA by using a mapping table.

[0065] Based on the mapping unit, there are a variety of address mapping methods that can be adopted by the FTL. Typical address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

[0066] The processor 124 may be configured to randomize data received from the host to write the randomized data into the memory cell array. For example, the processor 124 may randomize the data received from the host by using a randomization seed. The randomized data is provided to the memory device 110 and written into the memory cell array.

[0067] The processor 124 may be configured to derandomize data received from the memory device 110 during a read operation. For example, the processor 124 may derandomize the data received from the memory device 110 by using a derandomization seed. The derandomized data may be output to the host HOST.

[0068] The processor 124 may execute firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 may control the overall operation of the memory controller 120, and may execute (drive) the firmware loaded into the working memory 125 during booting in order to perform a logic operation.

[0069] Firmware refers to a program or software stored on some non-volatile memory and executed within the memory system 100 .

[0070] In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of the following: a flash translation layer (FTL) configured to convert a logical address in a host HOST request into a physical address of the memory device 110; a host interface layer (HIL) configured to interpret a command issued by the host HOST to a data storage device (such as the memory system 100) and transmit the command to the FTL; and a flash interface layer (FTL) configured to transmit a command issued by the FTL to the memory device 110.

[0071] For example, firmware may be stored in the memory device 110 and then loaded into the working memory 125 .

[0072] The working memory 125 may store firmware, program codes, commands or data segments required to operate the memory controller 120. For example, the working memory 125 may include at least one of static RAM (SRAM), dynamic RAM (DRAM) and synchronous RAM (SDRAM) as a volatile memory.

[0073] Error detection / correction circuit 126 may be configured to detect and correct one or more erroneous bits in data by using error detection and correction codes. In some implementations, the data subject to error detection and correction may include data stored in working memory 125 and data retrieved from memory device 110 .

[0074] The error detection / correction circuit 126 may be implemented to decode data by using an error correction code. The error detection / correction circuit 126 may be implemented by using various decoding schemes. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding may be used.

[0075] In some implementations, the error detection / correction circuit 126 can detect one or more error bits on a sector basis. That is, each segment of read data can include multiple sectors. In the present disclosure, a sector can refer to a data unit that is smaller than a read unit (e.g., a page) of a flash memory. The sectors that constitute each segment of read data can be mapped based on an address.

[0076] In some implementations, the error detection / correction circuit 126 may calculate a bit error rate (BER) on a sector-by-sector basis and determine whether the number of error bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 may determine that the error bits in the corresponding sector are uncorrectable and the corresponding sector is marked as "failed". If the BER is less than or equal to the reference value, the error detection / correction circuit 126 may determine that the corresponding sector is correctable, or the corresponding sector may be marked as "passed".

[0077] The error detection / correction circuit 126 may sequentially perform error detection and correction operations on all read data. When a sector included in the read data is correctable, the error detection / correction circuit 126 may move to the next sector to detect whether an error correction operation is required for the next sector. After completing the error detection and correction operations on all read data in this manner, the error detection / correction circuit 126 may obtain information about which sector in the read data is uncorrectable. The error detection / correction circuit 126 may provide such information (e.g., the address of the uncorrectable bit) to the processor 124.

[0078] The memory system 100 may further include a bus 127 to provide a channel between the constituent elements 121, 122, 124, 125, and 126 of the memory controller 120. For example, the bus 127 may include a control bus for transmitting various types of control signals and commands and a data bus for transmitting various types of data.

[0079] For example, Figure 1 The above-mentioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 are shown. Note that some of those elements shown in the figure may be omitted, or some of the above-mentioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. Furthermore, in some implementations, one or more other constituent elements may be added to the above-mentioned constituent elements of the memory controller 120.

[0080] Figure 2 is a block diagram schematically illustrating a memory device 110 based on an embodiment of the disclosed technology.

[0081] In some implementations, a memory device 110 based on an embodiment of the disclosed technology may include a memory cell array 210 , an address decoder 220 , a read / write circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0082] The memory cell array 210 may include a plurality of memory blocks BLK1 -BLKz, where z is a natural number equal to or greater than 2.

[0083] In the plurality of memory blocks BLK1 -BLKz, a plurality of word lines WL and a plurality of bit lines BL may be provided in rows and columns, and a plurality of memory cells MC may be arranged.

[0084] The plurality of memory blocks BLK1-BLKz may be connected to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1-BLKz may be connected to the read / write circuit 230 through a plurality of bit lines BL.

[0085] Each memory block in the plurality of memory blocks BLK1-BLKz may include a plurality of memory cells. For example, the plurality of memory cells are non-volatile memory cells. In some implementations, such non-volatile memory cells may be arranged in a vertical channel structure.

[0086] The memory cell array 210 may be configured as a memory cell array having a two-dimensional structure. In some implementations, the memory cell array 210 may be arranged in a three-dimensional structure.

[0087] Each of the plurality of memory cells included in the memory cell array 210 may store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-level cell (SLC) configured to store one bit of data. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-level cell (TLC) configured to store three bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-level cell (QLC) configured to store four bits of data per memory cell. As another example, the memory cell array 210 may include a plurality of memory cells, each of the plurality of memory cells may be configured to store at least five bits of data per memory cell.

[0088] refer to Figure 2 , the address decoder 220 , the read / write circuit 230 , the control logic 240 , and the voltage generating circuit 250 may operate as a peripheral circuit configured to drive the memory cell array 210 .

[0089] The address decoder 220 may be connected to the memory cell array 210 through a plurality of word lines WL.

[0090] The address decoder 220 may be configured to operate in response to commands and control signals from the control logic 240 .

[0091] The address decoder 220 may receive the address through an input / output buffer inside the memory device 110. The address decoder 220 may be configured to decode a block address in the received address. The address decoder 220 may select at least one memory block based on the decoded block address.

[0092] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0093] During a read operation, the address decoder 220 may apply a read voltage Vread to a selected word line WL inside a selected memory block and apply a pass voltage Vpass to the remaining unselected word lines WL.

[0094] During a program verification operation, the address decoder 220 may apply a verification voltage generated by the voltage generation circuit 250 to a selected word line WL inside a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL.

[0095] The address decoder 220 may be configured to decode a column address from among the received addresses. The address decoder 220 may send the decoded column address to the read / write circuit 230.

[0096] The memory device 110 may perform a read operation and a program operation on a page-by-page basis. When a read operation and a program operation are requested, a received address may include at least one of a block address, a row address, and a column address.

[0097] The address decoder 220 may select a memory block and a word line based on the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read / write circuit 230.

[0098] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0099] The read / write circuit 230 may include a plurality of page buffers PB. The read / write circuit 230 may operate as a “read circuit” when the memory cell array 210 performs a read operation, and operate as a “write circuit” when the memory cell array 210 performs a write operation.

[0100] The above-mentioned read / write circuit 230 is also referred to as a page buffer circuit including a plurality of page buffers PB or a data register circuit. The read / write circuit 230 may include a data buffer participating in data processing functions, and in some implementations, may also include a cache buffer for data caching.

[0101] A plurality of page buffers PB may be connected to the memory cell array 210 through a plurality of bit lines BL. In order to detect or sense a threshold voltage Vth of a memory cell during a read operation and a program verification operation, the plurality of page buffers PB may continuously supply a sensing current to the bit lines BL connected to the memory cell to detect a change at a sensing node in proportion to an amount of current that changes depending on a programming state of the corresponding memory cell, and the plurality of page buffers PB may hold or latch a corresponding voltage as sensing data.

[0102] The read / write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0103] During a read operation, the read / write circuit 230 senses a voltage value of a memory cell, and the voltage value is read out as data. The read / write circuit 230 temporarily stores the retrieved data, and outputs the data DATA to an input / output buffer of the memory device 110. In an embodiment, the read / write circuit 230 may further include a column selection circuit in addition to the page buffer PB or the page register.

[0104] The control logic 240 may be connected to the address decoder 220, the read / write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory device 110.

[0105] The control logic 240 may be configured to control the overall operation of the memory device 110 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting the voltage level of the sensing nodes of the plurality of page buffers PB to a precharge voltage level.

[0106] The control logic 240 may control the read / write circuit 230 to perform a read operation in the memory cell array 210. The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used during a read operation in response to a voltage generation circuit control signal output from the control logic 240.

[0107] The memory block BLK included in the memory device 110 may include a plurality of pages PG. In some implementations, a plurality of memory cells arranged in columns form a memory cell string, and a plurality of memory cells arranged in rows form a memory block. Each of the plurality of pages PG is coupled to one of the word lines WL, and each of the memory cell strings STR is coupled to one of the bit lines BL.

[0108] In the memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged in rows and columns. For example, each of the plurality of word lines WL may be arranged in a row direction, and each of the plurality of bit lines BL may be arranged in a column direction. As another example, each of the plurality of word lines WL may be arranged in a column direction, and each of the plurality of bit lines BL may be arranged in a row direction.

[0109] In some implementations, multiple word lines WL and multiple bit lines BL may cross each other to address a single memory cell in an array of multiple memory cells MC. In some implementations, each memory cell MC may include a transistor TR including a material layer capable of holding charge.

[0110] For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected to the corresponding bit line BL directly or via another transistor TR. The source (or drain) of the transistor TR may be connected to a source line (which may be grounded) directly or via another transistor TR. The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from a word line WL.

[0111] In each of the multiple memory blocks BLK1-BLKz, a first selection line (also called a source selection line or a drain selection line) may be additionally arranged outside a first outermost word line of the two outermost word lines, which is closer to the read / write circuit 230, and a second selection line (also called a drain selection line or a source selection line) may be additionally arranged outside the other second outermost word line.

[0112] In some implementations, at least one dummy word line may be additionally disposed between the first outermost word line and the first selection line. In addition, at least one dummy word line may be additionally disposed between the second outermost word line and the second selection line.

[0113] A read operation and a program operation (write operation) of a memory block may be performed page by page, and an erase operation may be performed memory block by memory block.

[0114] Figure 3 is a diagram showing the structure of word lines WL and bit lines BL of a memory device 110 based on an embodiment of the disclosed technology.

[0115] refer to Figure 3 The memory device 110 has a core region in which memory cells MC are arranged and an auxiliary region (a remaining region other than the core region) for including circuit devices used to perform operations of the memory cell array 210 .

[0116] In the core region, a certain number of memory cells arranged in one direction may be referred to as a 'page' PG, and a certain number of memory cells coupled in series may be referred to as a 'memory cell string' STR.

[0117] The word lines WL1-WL9 may be connected to the row decoder 310. The bit lines BL may be connected to the column decoder 320. Figure 2 A data register 330 corresponding to the read / write circuit 230 may exist between the plurality of bit lines BL and the column decoder 320 .

[0118] The plurality of word lines WL1 - WL9 may correspond to the plurality of pages PG.

[0119] For example, each of the plurality of word lines WL1-WL9 may correspond to Figure 3 One page PG is shown. When each of the plurality of word lines WL1-WL9 has a large size, each of the plurality of word lines WL1-WL9 may correspond to at least two (e.g., two or four) page PGs. Each page PG is the minimum unit in a programming operation and a reading operation, and when performing a programming operation and a reading operation, all memory cells MC within the same page PG may perform simultaneous operations.

[0120] The plurality of bit lines BL may be connected to the column decoder 320 . In some implementations, the plurality of bit lines BL may be divided into odd bit lines BL and even bit lines BL such that pairs of odd bit lines and even bit lines are commonly coupled to the column decoder 320 .

[0121] In accessing the memory cell MC, the row decoder 310 and the column decoder 320 are used to locate a desired memory cell based on an address.

[0122] In some implementations, the data register 330 plays an important role because all data processing (including programming operations and reading operations) performed by the memory device 110 occurs via the data register 330. If the data processed by the data register 330 is delayed, all other areas need to wait until the data register 330 completes the data processing, thereby reducing the overall performance of the memory device 110.

[0123] refer to Figure 3 In the example shown, in one memory cell string STR, a plurality of transistors TR1-TR9 may be connected to a plurality of word lines WL1-WL9, respectively. In some implementations, the plurality of transistors TR1-TR9 correspond to memory cells MC. In this example, the plurality of transistors TR1-TR9 include a control gate CG and a floating gate FG.

[0124] The plurality of word lines WL1-WL9 include two outermost word lines WL1 and WL9. A first selection line DSL may be additionally arranged outside the first outermost word line WL1, which is closer to the data register 330 and has a shorter signal path than another outermost word line WL9. A second selection line SSL may be additionally arranged outside another second outermost word line WL9.

[0125] The first selection transistor D-TR whose on / off is controlled by the first selection line DSL has a gate electrode connected to the first selection line DSL but does not include a floating gate FG. The second selection transistor S-TR whose on / off is controlled by the second selection line SSL has a gate electrode connected to the second selection line SSL but does not include a floating gate FG.

[0126] The first selection transistor D-TR is used as a switch circuit that connects the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR is used as a switch that connects the corresponding memory cell string STR to the source line SL. That is, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0127] In some implementations, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR, thereby turning on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR, thereby turning off the second selection transistor S-TR.

[0128] The memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR during a read operation or a verification operation. Therefore, during a read operation or a verification operation, a current can flow through the corresponding memory cell string STR and to the source line SL corresponding to the ground, so that the voltage level of the bit line BL can be measured. However, during a read operation, there may be a time difference in the turn-on / off timing between the first selection transistor D-TR and the second selection transistor S-TR.

[0129] During the erase operation, the memory system 100 may apply a predetermined voltage (e.g., +20V) to the substrate through the source line SL. The memory system 100 applies a certain voltage to allow the first selection transistor D-TR and the second selection transistor S-TR to float during the erase operation. As a result, the applied erase voltage may remove charge from the floating gate FG of the selected memory cell.

[0130] Figure 4 is a diagram schematically illustrating the operation of the memory system 100 according to an embodiment of the present disclosure.

[0131] refer to Figure 4 , the memory controller 120 of the memory system 100 may extract the command CMD from the host HOST into the command queue CMD_Q. In this case, the memory controller 120 may extract the command CMD into the command queue CMD_Q through the host interface 121 .

[0132] The command queue CMD_Q may be located on the working memory 125 of the memory controller 120 , and may be implemented using a data structure such as a linear queue, a circular queue, and a linked list.

[0133] Furthermore, the memory controller 120 extracting the command to the command queue CMD_Q may mean that the memory controller 120 copies the command stored in a specific area of ​​the host and stores it in the command queue CMD_Q.

[0134] In addition, the processor 124 of the memory controller 120 may dequeue and execute the command CMD stored in the command queue CMD_Q. For example, if the command to be executed is a read command, the processor 124 may read data from the memory device 110, and if the command to be executed is a write command, the processor 124 may write data to the memory device 110.

[0135] In addition, the memory controller 120 may receive a lock request or an unlock request for the command CMD from the host HOST. The lock request for the command is a request to instruct to suspend the execution of the command, and the unlock request for the command is a request to instruct to resume the execution of the command. Figure 6 to Figure 7 Details of the lock request and unlock request for the command are described in detail. In this case, the memory controller 120 may receive a lock request or an unlock request for the command CMD through the host interface 121 and transmit the received lock request or unlock request to the processor 124 .

[0136] Figure 5 is a diagram illustrating an example of executing a command by the memory controller 120 according to an embodiment of the present disclosure.

[0137] refer to Figure 5 , the memory controller 120 of the memory system 100 may extract the first command CMD_1 and the second command CMD_2 from the host HOST.

[0138] As an example, the host HOST may include a separate host command queue therein, and the command may be stored in the host command queue by an internal scheduler. In addition, the host may store the command in the host command queue and then set the doorbell register to notify the memory system 100 that the command to be processed is stored in the host command queue.

[0139] After confirming that the doorbell register is set, the memory controller 120 may extract the command from the host command queue into the command queue CMD_Q. In this case, the memory controller 120 may store the command received from the host in the command queue CMD_Q according to a preset scheduling policy.

[0140] In addition, the processor 124 of the memory controller 120 may execute the first command CMD_1 and the second command CMD_2 extracted from the host HOST. In this case, the order of execution of the first command CMD_1 and the second command CMD_2 may be scheduled by the memory controller 120. Therefore, in general, the host cannot control the order in which the commands are executed by the memory controller 120 except for the method of sending a request to abort the command.

[0141] However, if the command execution order is determined only by the memory controller 120, the timing of executing a specific command by the memory system 100 may be delayed. Therefore, there may be a problem in that the performance experienced by a user using the host may be degraded.

[0142] For example, the host can download large data (e.g., software, video files, image files) while simultaneously processing small data (e.g., web pages). In this case, the memory system 100 can execute a large data command from the host for processing the large data, and then execute a small data command for processing the small data.

[0143] Therefore, the small data command may be executed after the memory system 100 completes the execution of the large data command. Therefore, the response time to the small data command may be delayed by the time required to execute the large data command.

[0144] However, the user of the host may generally intend to process small data quickly. Therefore, if the operation of processing small data is delayed, the user using the host may feel that the performance of the host has deteriorated.

[0145] Therefore, in order to solve this problem, a method may be needed in which the host can control the memory system 100 so as to process small data commands before processing large data commands. Hereinafter, in an embodiment of the present invention, an operation of the host sending a lock request to the memory system 100 will be described.

[0146] Figure 6is a diagram illustrating an example in which the memory controller 120 suspends execution of the first command CMD_1 based on a lock request according to an embodiment of the present disclosure.

[0147] refer to Figure 6 , the host HOST may send a lock request for the first command CMD_1 to the memory controller 120 of the memory system 100. The lock request for the first command CMD_1 is a request to instruct to suspend the execution of the first command CMD_1. For example, the host may send the lock request to the memory controller 120 through a separate command or an electrical signal.

[0148] When receiving a lock request for the first command CMD_1 from the host, the processor 124 of the memory controller 120 may suspend execution of the first command CMD_1 .

[0149] Figure 6 Only the case where a lock request for the first command CMD_1 is received from the host HOST when the processor 124 is executing the first command CMD_1 is shown. However, before the first command CMD_1 is executed, a lock request for the first command CMD_1 may be received from the host. In this case, the processor 124 may change the first command CMD_1 to an unexecutable state, or prohibit the first command CMD_1 from being enqueued to the command queue CMD_Q if the first command CMD_1 has not been enqueued to the command queue CMD_Q, or dequeue the first command CMD_1 from the command queue and then store it in a lock described later.

[0150] In the following cases, the memory controller 120 may resume the execution of the first command CMD_1 which has been suspended.

[0151] Figure 7 is a diagram illustrating an example in which the memory controller 120 resumes execution of the first command CMD_1 according to an embodiment of the present disclosure.

[0152] refer to Figure 7 , after the execution of the first command CMD_1 is suspended by the lock request from the host, the host HOST may send an unlock request for the first command CMD_1 whose execution is suspended to the memory controller 120. The unlock request for the first command CMD_1 refers to a request to resume the execution of the suspended first command CMD_1. Similar to the lock request, the host may send the unlock request to the memory controller 120 through a separate command or electrical signal.

[0153] When receiving an unlock request for the first command CMD_1 from the host HOST, the processor 124 of the memory controller 120 may resume the execution of the suspended first command CMD_1. If the first command CMD_1 has not been executed and is therefore in an unexecutable state due to the lock request, the processor 124 may change the first command CMD_1 to an executable state due to the unlock request.

[0154] Figure 8 is a diagram illustrating another example in which the memory controller 120 resumes execution of the first command CMD_1 according to an embodiment of the present disclosure.

[0155] refer to Figure 8 , instead of Figure 7 As shown, the unlock request is explicitly sent to the memory controller 120, and the host HOST can indicate a time point for resuming the execution of the first command CMD_1 by also sending information about the suspend time SUSPEND_TIME, which is the maximum time that the execution of the first command CMD_1 can be suspended when the lock request is sent.

[0156] In this case, if a time exceeding the suspend time SUSPEND_TIME has passed after suspending the execution of the first command CMD_1, the memory controller 120 may automatically resume the execution of the first command CMD_1 even without an unlock request from the host HOST. If the first command CMD_1 is in a state before being executed, the processor 124 may change the first command CMD_1 to an executable state.

[0157] When the execution of the first command CMD_1 is completed after resuming the execution of the first command CMD_1 , the processor 124 may send a response message for the execution result of the first command CMD_1 to the host HOST.

[0158] like Figures 6 to 8 As described in the above, the host HOST may control the execution of the first command CMD_1 based on the lock request for the first command CMD_1 to the memory controller 120. If the first command CMD_1 is a command for processing a large amount of data, the host HOST may send the lock request for the first command CMD_1 to the memory controller 120 to suspend the execution of the first command CMD_1 to control the memory controller 120 to process other commands. As a result, the host may indirectly control the execution order of the commands and prevent delays in the execution of other commands that require fast processing QoS satisfaction due to the first command CMD_1.

[0159] Hereinafter, detailed operations of the memory controller 120 processing a lock request and an unlock request received from the host HOST will be described.

[0160] Fig. 9 is a diagram illustrating an example in which the memory controller 120 processes a lock request according to an embodiment of the present disclosure.

[0161] refer to Fig. 9 , the host HOST may send a lock request for the first command CMD_1 to the memory controller 120. When the processor 124 of the memory controller 120 receives the lock request for the first command CMD_1 from the host HOST, the processor 124 may suspend the execution of the first command CMD_1.

[0162] In this case, after suspending the execution of the first command CMD_1, the processor 124 may store the first command CMD_1 in the locker. On the other hand, if the processor 124 receives a lock request for the first command CMD_1 from the host before executing the first command CMD_1, the processor 124 may move the first command CMD_1 from the command queue CMD_Q to the locker LOCKER.

[0163] The locker is an area for storing commands for which the host sends a lock request, and may be located inside the memory controller 120. The commands stored in the locker LOCKER may be executed after the host sends an unlock request for the command or after the execution of the command is suspended for an amount of time corresponding to the suspension time value sent together with the lock request for the command. In addition, when the corresponding command is stored in the locker, the memory controller 120 may not execute the corresponding command, but may execute other commands.

[0164] When sending a lock request for a command to the memory controller 120, the host HOST may also send key information for the command. In this case, the memory controller 120 may store the key information for the corresponding command together with the command in the locker. In addition, when processing an unlock request for the corresponding command, the memory controller 120 may determine whether to unlock the corresponding command by comparing the key information sent with the unlock request with the key information stored in the locker.

[0165] Fig.10 is a diagram showing an example of the operation of the memory controller 120 .

[0166] refer to Fig.10, the processor 124 of the memory controller 120 may dequeue and execute the first command CMD_1 in the command queue CMD_Q (①). In addition, when a lock request for the first command CMD_1 is received from the host HOST (②), the processor 124 may suspend the execution of the first command CMD_1 and store the first command CMD_1 in the locker LOCKER (③).

[0167] In this case, when the first command CMD_1 is stored in the locker LOCKER, the processor 124 may further store execution state information EXE_STATE indicating a state of the first command CMD_1 before suspending the execution of the first command CMD_1 in the locker LOCKER.

[0168] For example, the execution state information EXE_STATE of the first command CMD_1 may include information related to the first command CMD_1 (e.g., LBA / length / time slot information), size information of processed data (e.g., the size of data written to the memory device 110), or meta information (e.g., if the first command CMD_1 is a read command, the location where the cache hit occurs, if the first command CMD_1 is a write command, information about opening a memory block, and page information (PI)).

[0169] When resuming the execution of the first command CMD_1, the processor 124 can determine the location where the execution of the first command CMD_1 is to be resumed based on the execution state information EXE_STATE of the first command CMD_1 stored in the lock LOCKER, and can skip operations on already processed data when resuming the execution of the first command CMD_1, and only perform operations on unprocessed data.

[0170] Fig.11 It is shown Fig. 9 2 is a diagram of an example in which the memory controller 120 resumes execution of the first command CMD_1 described in FIG.

[0171] refer to Fig.11 When executing the first command CMD_1, the host HOST may send a lock request for the first command CMD_1 to the memory controller 120. When receiving the lock request for the first command CMD_1 from the host HOST, the processor 124 of the memory controller 120 may suspend the execution of the first command CMD_1 and store the first command CMD_1 in the locker LOCKER.

[0172] Thereafter, the host HOST may send an unlock request for the first command CMD_1 to the memory controller 120. When the processor 124 of the memory controller 120 receives the unlock request for the first command CMD_1 from the host and resumes the execution of the first command CMD_1, the processor 124 may perform an operation of retrieving the first command CMD_1 from the lock and then removing it, or perform an operation of invalidating the first command CMD_1 stored in the lock. The execution of the first command CMD_1 may be resumed due to the unlock request for the first command CMD_1.

[0173] Furthermore, the processor 124 of the memory controller 120 may remove the first command CMD_1 from the lock even when the first command CMD_1 is resumed after execution of the first command CMD_1 is suspended for an amount of time corresponding to the suspension time value sent with the lock request for the first command CMD_1 .

[0174] Fig.12 It is shown Fig. 9 2 is a diagram of an example in which the memory controller 120 processes a second command CMD_2 after suspending execution of a first command CMD_1 .

[0175] refer to Fig.12 When the first command CMD_1 is being executed, the host HOST may send a lock request for the first command CMD_1 to the memory controller 120. When receiving the lock request for the first command CMD_1 from the host HOST, the processor 124 of the memory controller 120 may suspend the execution of the first command CMD_1 and store the first command CMD_1 in the locker LOCKER.

[0176] Thereafter, the processor 124 of the memory controller 120 may dequeue the second command CMD_2 from the command queue CMD_Q and execute it. Therefore, even if the execution of the second command CMD_2 is not directly requested, the host HOST may advance the execution time of the second command CMD_2 by suspending the execution of the first command CMD_1.

[0177] Fig.13 It is shown Fig.12 2 is a diagram of an example of a state of the memory controller 120 described in FIG.

[0178] refer to Fig.13 , when a lock request for the first command CMD_1 is received from the host (①), the processor 124 of the memory controller 120 may suspend the execution of the first command CMD_1 and store the first command CMD_1 in the locker LOCKER (②).

[0179] The processor 124 may dequeue the second command CMD_2 from the command queue CMD_Q and then execute the second command CMD_2 (③).

[0180] Fig.14 is a diagram illustrating another example of processing a lock request by the memory controller 120 according to an embodiment of the present disclosure.

[0181] refer to Fig.14 When the first command CMD_1 is being executed, the host HOST may send a lock request for the first command CMD_1 to the memory controller 120. When receiving the lock request for the first command CMD_1 from the host, the processor 124 of the memory controller 120 may suspend the execution of the first command CMD_1.

[0182] Thereafter, the processor 124 may abort the first command CMD_1 instead of storing the first command CMD_1 in the Fig. 9 When the first command CMD_1 is aborted, information related to the first command CMD_1 can be erased from the memory controller 120 except for the execution interruption point of the first command CMD_1. In this case, the memory controller 120 has no need to maintain Figure 7 However, in order to execute the first command CMD_1 again from the interruption point of the execution of the first command CMD_1, it is necessary to fetch the first command CMD_1 from the host HOST again.

[0183] Fig.15 It is shown Fig.14 FIG. 1 is a diagram of an example in which the memory controller 120 resumes execution of the first command described in FIG.

[0184] refer to Fig.15 When the first command CMD_1 is being executed, the host HOST may send a lock request for the first command CMD_1 to the memory controller 120. When receiving the lock request for the first command CMD_1 from the host HOST, the processor 124 of the memory controller 120 may suspend the execution of the first command CMD_1 and terminate the first command CMD_1.

[0185] Thereafter, the host HOST may send an unlock request for the first command CMD_1 to the memory controller 120. When receiving the unlock request for the first command CMD_1 from the host, the processor 124 of the memory controller 120 may fetch the first command CMD_1 into the command queue CMD_Q again to execute the aborted first command CMD_1 again.

[0186] Even when execution of the first command CMD_1 is resumed after execution of the first command CMD_1 was suspended for an amount of time corresponding to the suspension time value sent with the lock request for the first command CMD_1 , the processor of the memory controller 120 may extract the first command CMD_1 back to the command queue CMD_Q.

[0187] Fig.16 is a diagram illustrating an operating method of the memory system 100 according to an embodiment of the present disclosure.

[0188] refer to Fig.16 , the operating method of the memory system 100 may include extracting a first command CMD_1 received from a host HOST into a command queue CMD_Q ( S1610 ).

[0189] Furthermore, the operating method of the memory system 100 may include receiving a lock request for the first command CMD_1 from the host HOST ( S1620 ).

[0190] Furthermore, the operating method of the memory system 100 may include, when a lock request for the first command CMD_1 is received from the host HOST, suspending execution of the first command CMD_1 ( S1630 ).

[0191] Furthermore, the operating method of the memory system 100 may include resuming execution of the first command when an unlock request for the first command is received or after execution of the first command CMD_1 is suspended for an amount of time corresponding to a suspension time value sent with the lock request ( S1640 ).

[0192] As an example, in operation S1630, when a lock request for the first command CMD_1 is received from the host HOST, the memory system 100 may store the first command CMD_1 in a locker. The locker is a buffer for storing a command for which the host sends a lock request.

[0193] When the first command CMD_1 is stored in the lock, information about the execution state of the first command CMD_1 may be stored together in the lock.

[0194] In this case, the operating method of the memory system 100 may further include popping the first command CMD_1 from the lock when resuming the execution of the first command CMD_1.

[0195] In addition, the operating method of the memory system 100 may further include executing a second command CMD_2 after storing the first command CMD_1 in the lock, the second command CMD_2 being one of the commands stored in the command queue CMD_Q.

[0196] As another example, when a lock request for the first command CMD_1 is received from the host in operation S1620 , the memory system 100 may abort the first command CMD_1 .

[0197] In this case, the operating method of the memory system 100 may further include: when resuming the execution of the first command CMD_1 , fetching the first command CMD_1 into the command queue CMD_Q again.

[0198] In some implementations, the operations of the above-mentioned memory controller 120 may be controlled by the control circuit 123 and may be performed in a manner that the processor 124 executes (drives) firmware in which the overall operations of the memory controller 120 are programmed.

[0199] Fig.17 is a diagram showing a configuration of a computing system 1700 based on an embodiment of the disclosed technology.

[0200] refer to Fig.17 , a computing system 1700 based on an embodiment of the disclosed technology may include: a memory system 1700, electrically connected to a system bus 1760; a CPU 1710, configured to control the overall operation of the computing system 1700; a RAM 1720, configured to store data and information related to the operation of the computing system 1700; a user interface / user experience (UI / UX) module 1730, configured to provide a user environment to a user; a communication module 1740, configured to communicate with external devices in a wired and / or wireless manner; and a power management module 1750, configured to manage the power used by the computing system 1700.

[0201] The computing system 1700 may be a personal computer (PC) or may include a mobile terminal such as a smart phone, a tablet computer, or various electronic devices.

[0202] The computing system 1700 may further include a battery for supplying an operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and a DRAM. Other elements will be apparent to those skilled in the art.

[0203] The memory system 100 may include not only a device configured to store data in a disk (such as a hard disk drive (HDD)), but also a device configured to store data in a non-volatile memory (such as a solid state drive (SSD), a universal flash memory device, or an embedded MMC (eMMC) device). The non-volatile memory may include: a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. In addition, the memory system 100 may be implemented as various types of storage devices and installed inside various electronic devices.

[0204] Method described herein, process and / or operation can be performed by the code or instruction to be performed by computer, processor, controller or other signal processing equipment.Computer, processor, controller or other signal processing equipment can be those computers, processors, controller or other signal processing equipment described herein or can be the computer, processor, controller or other signal processing equipment outside the element described herein.Because the algorithm forming the basis of method (or the operation of computer, processor, controller or other signal processing equipment) is described in detail, the code or instruction for realizing the operation of method embodiment can be transformed into the special processor for performing the method herein by computer, processor, controller or other signal processing equipment.

[0205] For example, when implemented at least in part with software, controllers, processors, engines, devices, modules, units, interfaces, drivers, generators, and other signal generation and signal processing features may include a memory or other storage device for storing, for example, a code or instruction executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be one of those described herein, or may be one of the elements outside of the elements described herein. Because the algorithm forming the basis of the method (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) is described in detail, the code or instruction for implementing the operation of the method embodiment may transform a computer, processor, microprocessor, controller, or other signal processing device into a dedicated processor for executing the method herein.

[0206] Based on the embodiments of the above disclosed technology, the operation delay time of the memory system can be advantageously reduced or minimized. In addition, based on the embodiments of the disclosed technology, the overhead incurred in the process of calling a specific function can be advantageously reduced or minimized. Although various embodiments of the disclosed technology have been described with specific details and varying details for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions can be made based on the content disclosed or described in this disclosure.

[0207] The above embodiments of the present invention are intended to illustrate rather than limit the present invention. Various alternatives and equivalents are possible. The present invention is not limited by the embodiments described herein. Other additions, deletions or modifications that are apparent in view of the present disclosure are intended to fall within the scope of the appended claims.

Claims

1. A memory system, comprising: Memory devices; as well as a memory controller for communicating with the memory device and controlling the memory device to process a command requested by a host, wherein the memory controller: fetching a first command from the host into a command queue, When a lock request for the first command is received from the host, suspending execution of the first command, In response to receiving the lock request for the first command from the host, aborting the execution of the first command, after the first command is suspended, executing a second command stored in the command queue after the first command is stored in the command queue, the second command being an operation in which a size of data processed is smaller than a size of data processed by the first command, After executing the second command, in response to receiving an unlock request, fetching the first command from the host into the command queue again, and The execution of the first command is resumed after the first command is fetched again and the execution of the first command is paused for an amount of time corresponding to a pause time value that was sent with the lock request.

2. The memory system according to claim 1, wherein the memory controller includes a lock, which is a buffer for storing a command for which the host sends the lock request, and when the lock request for the first command is received from the host, the first command is also stored in the lock.

3. The memory system of claim 2, wherein the memory controller, when storing the first command in the lock, further stores execution status information in the lock, the execution status information indicating a state of the first command before suspending the execution of the first command. 4 . The memory system of claim 2 , wherein the memory controller, when resuming the execution of the first command, also retrieves the first command from the lock. 5 . The memory system of claim 2 , wherein the memory controller further executes the second command after storing the first command in the lock.

6. A method for operating a memory system, comprising: fetching a first command from the host into a command queue; receiving a lock request for the first command from the host; When receiving the lock request for the first command from the host, suspending execution of the first command; in response to receiving the lock request for the first command from the host, aborting the execution of the first command; After the first command is suspended, executing a second command stored in the command queue after the first command is stored in the command queue, the second command being an operation in which a size of data processed is smaller than a size of data processed by the first command; After executing the second command, in response to receiving an unlock request, extracting the first command from the host into the command queue again; as well as The execution of the first command is resumed after the first command is fetched again and the execution of the first command is paused for an amount of time corresponding to a pause time value that was sent with the lock request.

7. The operating method of the memory system according to claim 6, wherein suspending the execution of the first command comprises: When the lock request for the first command is received from the host, the first command is stored in a locker, which is a buffer for storing the command for which the host sends the lock request.

8. The operating method of the memory system according to claim 7, wherein storing the first command in the lock comprises: Execution status information is stored in the lock, the execution status information indicating a status of the first command before suspending the execution of the first command.

9. The method for operating the memory system according to claim 7, further comprising: When the execution of the first command is resumed, the first command is retrieved from the lock.

10. The method for operating the memory system according to claim 7, further comprising: The second command is executed after the first command is stored in the lock.

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