Inter-core communication method, device and medium for heterogeneous multi-core chips

Abstract

The present invention discloses a method, device, and medium for inter-core communication in a heterogeneous multi-core chip. The method creates an inter-core shared area in memory through a master core in a target heterogeneous multi-core chip. The master core sends the address of the inter-core shared area to a slave core based on an interrupt module in a built inter-core interaction framework. The master core then creates a first linked list and a second linked list in the inter-core shared area based on a linked list module in the inter-core interaction framework. The master core transmits data to at least one slave core in the target heterogeneous multi-core chip through the first linked list and the second linked list, thereby achieving data transmission between the master core and each slave core in the heterogeneous multi-core chip, solving the technical problem of the complexity and difficulty of achieving inter-core communication in heterogeneous multi-core chips, and improving the development efficiency and versatility of inter-core communication in heterogeneous multi-core chips. In addition, the method can also achieve mutual communication between cores running different operating systems in a heterogeneous multi-core chip.

Description

Technical Field

[0001] The present invention relates to the field of embedded chip technology, and in particular to an inter-core communication method, device and medium for a heterogeneous multi-core chip. Background Art

[0002] With the continuous advancement of integrated circuit technology and the development of processor architectures, heterogeneous multi-core processors have been widely used in the embedded field. On-chip communication design is one of the key technologies to improve the performance of heterogeneous multi-core systems. Currently, various on-chip communication designs for multi-core processors have been developed, but none of them effectively solve the problem of collaboration between processing cores.

[0003] For example, the existing technology is usually based on the design of heterogeneous multi-core communication modules of DspLink, which is based on the ARM (Advanced RISC Machines) of the DaVinci architecture processor and the DSP (Digital Signal Processing) end for communication. DspLink provides a set of universal application programming interfaces, abstracting the physical connection characteristics of ARM and DSP from the application layer, thereby reducing the complexity of user development programs. It provides basic processor control, data transmission based on logical channels and a message passing mechanism based on the MSGQ (Message Queue) module of DSP / BIOS, supporting message passing of both Zero Copy and ProcessorCopy physical mechanisms. However, the method based on the DspLink architecture cannot guarantee communication between two cores running different operating systems, and the implementation process is relatively complicated and the development efficiency is low. Summary of the Invention

[0004] The present invention provides a method, device and medium for inter-core communication of heterogeneous multi-core chips, which solves the technical problems of complexity and difficulty in implementing inter-core communication in heterogeneous multi-core chips and improves the development efficiency and versatility of inter-core communication in heterogeneous multi-core chips.

[0005] According to one aspect of the present invention, a method for inter-core communication of a heterogeneous multi-core chip is provided. The target heterogeneous multi-core chip includes a master core and at least one slave core. The method includes:

[0006] The master core creates an inter-core shared area in the memory of the target heterogeneous multi-core chip, and sends the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework;

[0007] The main core creates a first linked list and a second linked list in the inter-core shared area based on the linked list module in the inter-core interaction framework;

[0008] The master core accesses the first linked list and the second linked list through the address of the inter-core shared area, so as to transmit data to at least one of the slave cores based on the first linked list and the second linked list.

[0009] Optionally, the master core creates an inter-core shared area in the memory of the target heterogeneous multi-core chip, and sends the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework, including:

[0010] The main core obtains a pointer to the shared memory area of ​​the target heterogeneous multi-core chip by calling an acquisition function of the inter-core memory sharing module in the inter-core interaction framework;

[0011] The main core creates an inter-core shared area in the shared memory area by calling an allocation function in the inter-core memory sharing module, and determines an address of the inter-core shared area;

[0012] The master core initiates an event to be transmitted through the interrupt module and the address of the inter-core shared area, and sends the event to be transmitted to the slave core.

[0013] Optionally, the method further includes:

[0014] The master core calls a process communication control function to send a connection request to the slave core, so that the slave core calls a process communication start function to start a process communication module, and calls a communication identifier acquisition function to establish a remote connection with the master core;

[0015] The main core registers notification events to build an interrupt module in the inter-core interaction framework;

[0016] The main core binds the message to the linked list queue to build the linked list module in the inter-core interaction framework.

[0017] Optionally, transmitting data to at least one of the slave cores based on the first linked list and the second linked list includes:

[0018] The main core detects whether the second linked list is empty, and if not, retrieves a preset data structure from the second linked list;

[0019] The data to be transmitted is written into the preset data structure, and the preset data structure in which the data is written is placed into the head of the first linked list, so that when the slave core detects that the first linked list is not empty, it takes out the data from the head of the first linked list and places the preset data structure of the taken out data into the head of the second linked list.

[0020] According to another aspect of the present invention, a method for inter-core communication of a heterogeneous multi-core chip is provided, wherein the target heterogeneous multi-core chip includes a master core and at least one slave core, and the method includes:

[0021] The slave core receives an address of an inter-core shared area sent by the master core based on an interrupt module in the established inter-core interaction framework, wherein the inter-core shared area is created by the master core in the memory of the target heterogeneous multi-core chip;

[0022] The slave core accesses the first linked list and the second linked list created by the master core in the inter-core shared area through the address of the inter-core shared area, so as to transmit data to the master core based on the first linked list and the second linked list;

[0023] The first linked list and the second linked list are created by the main core in the inter-core shared area based on the linked list module in the inter-core interaction framework.

[0024] Optionally, the method further includes:

[0025] If the slave core obtains the connection request sent by the master core by calling the process communication control function, it calls the process communication start function to start the process communication module, and calls the communication identifier acquisition function to establish a remote connection with the master core;

[0026] The slave core registers notification events to build an interrupt module in the inter-core interaction framework;

[0027] The slave core binds the message to the linked list queue to build the linked list module in the inter-core interaction framework.

[0028] Optionally, transmitting data to the main core based on the first linked list and the second linked list includes:

[0029] The slave core detects whether the first linked list is empty, and if not, retrieves a preset data structure from the first linked list;

[0030] The data to be transmitted is written into the preset data structure, and the preset data structure in which the data is written is placed into the head of the second linked list, so that when the main core detects that the second linked list is not empty, it takes out the data from the head of the second linked list and places the preset data structure of the taken out data into the head of the first linked list.

[0031] According to another aspect of the present invention, there is provided an inter-core communication device for a heterogeneous multi-core chip, the device being configured in a master core of a target heterogeneous multi-core chip, the target heterogeneous multi-core chip also including at least one slave core, the device comprising:

[0032] A shared area creation module, configured to create an inter-core shared area in the memory of the target heterogeneous multi-core chip, and send the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework;

[0033] A linked list creation module, configured to create a first linked list and a second linked list in the inter-core shared area based on the linked list module in the inter-core interaction framework;

[0034] The data transmission module is used to access the first linked list and the second linked list through the address of the inter-core shared area, so as to transmit data to at least one of the slave cores based on the first linked list and the second linked list.

[0035] According to another aspect of the present invention, there is provided an inter-core communication device for a heterogeneous multi-core chip, the device being configured in a slave core of a target heterogeneous multi-core chip, the target heterogeneous multi-core chip also including a master core, the device comprising:

[0036] an address receiving module, configured to receive an address of an inter-core shared area sent by the master core based on an interrupt module in the established inter-core interaction framework, wherein the inter-core shared area is created by the master core in the memory of the target heterogeneous multi-core chip;

[0037] a data transmission module, configured to access a first linked list and a second linked list created by the master core in the inter-core shared area through the address of the inter-core shared area, so as to transmit data to the master core based on the first linked list and the second linked list;

[0038] The first linked list and the second linked list are created by the main core in the inter-core shared area based on the linked list module in the inter-core interaction framework.

[0039] According to another aspect of the present invention, an electronic device is provided, comprising:

[0040] at least one processor; and

[0041] a memory communicatively connected to the at least one processor; wherein,

[0042] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the inter-core communication method of the heterogeneous multi-core chip described in any embodiment of the present invention.

[0043] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the inter-core communication method of a heterogeneous multi-core chip described in any embodiment of the present invention when executed.

[0044] The technical solution of the embodiment of the present invention is to create an inter-core shared area in the memory of the target heterogeneous multi-core chip through the master core in the target heterogeneous multi-core chip. The master core sends the address of the inter-core shared area to the slave core according to the interrupt module in the established inter-core interaction framework. Then, the master core creates a first linked list and a second linked list in the inter-core shared area according to the linked list module in the inter-core interaction framework, and accesses the first linked list and the second linked list by address, so as to transmit data to at least one slave core in the target heterogeneous multi-core chip through the first linked list and the second linked list, thereby realizing data transmission between the master core and each slave core in the heterogeneous multi-core chip, solving the technical problem of the complexity and difficulty of realizing inter-core communication in heterogeneous multi-core chips, and improving the development efficiency and versatility of inter-core communication in heterogeneous multi-core chips. In addition, the method can also realize mutual communication between cores running different operating systems in heterogeneous multi-core chips.

[0045] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1A This is a flow chart of a method for inter-core communication in a heterogeneous multi-core chip provided in the first embodiment of the present invention;

[0048] Figure 1B This is a schematic diagram of the structure of a target heterogeneous multi-core chip provided in the first embodiment of the present invention;

[0049] Figure 2A This is a flow chart of a method for inter-core communication in a heterogeneous multi-core chip provided in the second embodiment of the present invention;

[0050] Figure 2B This is a schematic diagram of a process for transmitting data from a core to a master core provided by the second embodiment of the present invention;

[0051] Figure 3 This is a flow chart of a method for inter-core communication in a heterogeneous multi-core chip provided in a third embodiment of the present invention;

[0052] Figure 4 This is a schematic structural diagram of an inter-core communication device for a heterogeneous multi-core chip provided by a fourth embodiment of the present invention;

[0053] Figure 5 This is a structural diagram of an inter-core communication device for a heterogeneous multi-core chip provided by the fifth embodiment of the present invention.

[0054] Figure 6 This is a structural diagram of an electronic device provided in Example 6 of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] Example 1

[0058] Figure 1A The present invention provides a flowchart of an inter-core communication method for heterogeneous multi-core chips. This embodiment is applicable to situations where data transmission between a master core and a slave core is required in heterogeneous multi-core chips such as DAVINCI structure chips. The method can be executed by an inter-core communication device of a heterogeneous multi-core chip. The inter-core communication device of the heterogeneous multi-core chip can be implemented in the form of hardware and / or software and configured in the master core of the target heterogeneous multi-core chip. The inter-core communication device of the heterogeneous multi-core chip can be configured in electronic devices such as mobile phones, computers, and tablets. Figure 1A As shown, the method includes:

[0059] S110. The master core creates an inter-core shared area in the memory of the target heterogeneous multi-core chip, and sends the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework.

[0060] In this embodiment, the target heterogeneous multi-core chip may be a chip including at least two processors, such as a TMS320DM814x chip, an OMAP L138 chip, and the like.

[0061] The master core may be the main processor in the target heterogeneous multi-core chip. For example, in a DAVINCI chip, the master core may be an ARM processor. The slave core may be a slave processor in the target heterogeneous multi-core chip. Specifically, the slave core may perform corresponding data processing according to the control instructions issued by the master core. The number of slave cores may be one or multiple. For example, in a DAVINCI chip, the slave core may be a DSP processor.

[0062] Specifically, if data needs to be transferred between the master core and slave cores in a target heterogeneous multi-core chip, the master core must first create an inter-core shared area in the target heterogeneous multi-core chip's memory. The target heterogeneous multi-core chip's memory can be on-chip memory or external memory, such as an external high-speed flash memory chip.

[0063] For example, Figure 1B As shown, a schematic diagram of the structure of a target heterogeneous multi-core chip is shown. Figure 1B The target heterogeneous multi-core chip in the example can be an OMAPL138 chip, which includes a master core (the ARM processor core in the ARM module) and a slave core (the C6748 signal processing core in the DSP module). In the underlying structure, both the master core and the slave core are connected to a high-speed flash memory chip as runtime memory. The connection is achieved through an address bus and a data bus. The bus can be divided into several ports, some of which are private to the slave core, some are private to the master core, and the remaining ports can be shared by the master and slave cores. These shared ports point to a shared memory area in the high-speed flash memory. Therefore, data transmission between the cores of the target heterogeneous multi-core chip can be achieved through the shared memory area. When implementing actual multi-core communication, the slave core can directly write data to this shared memory area, and the master core can directly read from the shared memory area, and vice versa.

[0064] In this embodiment, the master core may first determine the shared memory area from the memory of the target heterogeneous multi-core chip, and then create an inter-core shared area in the shared memory area; alternatively, the master core may directly use the entire shared memory area as the inter-core shared area.

[0065] Furthermore, after establishing the inter-core shared area, the master core can send the address to at least one slave core based on the interrupt module in the established inter-core interaction framework. The inter-core interaction framework can be a pre-established SysLink framework, which provides the underlying communication interface for the target heterogeneous multi-core chip.

[0066] The interrupt module can be the Notify module in the SysLink framework. Hardware-level interrupt signals on the master and slave cores can be defined at the software level using Notify, facilitating software development. The data size is typically less than 32 bits, abstracting a hardware-level interrupt event into multiple events, each with its own callback function.

[0067] That is, the master core can send the address of the inter-core shared area as an event to the slave core through the interrupt module.

[0068] In an optional embodiment, the master core creates an inter-core shared area in the memory of the target heterogeneous multi-core chip, and sends the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework, including: the master core obtains a pointer to the shared memory area of ​​the target heterogeneous multi-core chip by calling the acquisition function of the inter-core memory sharing module in the inter-core interaction framework; the master core creates an inter-core shared area in the shared memory area and determines the address of the inter-core shared area by calling the allocation function in the inter-core memory sharing module; the master core initiates a to-be-transmitted event through the interrupt module and the address of the inter-core shared area, and sends the to-be-transmitted event to the slave core.

[0069] The inter-core memory sharing module may be a ShareRegion module in a SysLink framework.

[0070] Specifically, the master core can obtain a pointer to the shared memory area by calling the acquisition function in the ShareRegion module (such as the SharedRegion_getHeap() function); further, the master core can access the shared memory area through the pointer, open up an inter-core shared area in the shared memory area by calling the allocation function in the ShareRegion module (such as the Memory_calloc() function), and obtain the address of the inter-core shared area; by calling the Notify module in the SysLink framework, generate a transmission event based on the address and send it to the slave core.

[0071] S120 : The master core creates a first linked list and a second linked list in the inter-core shared area based on the linked list module in the inter-core interaction framework.

[0072] The linked list module in the inter-core interaction framework can be a ListMP module, which implements a bidirectional circular linked list structure at the bottom layer, supports multiple readers and writers, and is suitable for multi-host scenarios. Optionally, the inter-core interaction framework can also include a MessageQ module, which implements a blocking queue structure at the bottom layer, suitable for scenarios where a single consumer has multiple producers.

[0073] Specifically, the main core may create the first linked list and the second linked list in the inter-core shared area by calling the linked list module.

[0074] The following is an example of the process of building an inter-core interaction framework. The process of building an inter-core interaction framework may include the following steps: the master core calls the process communication control function to send a connection request to the slave core, so that the slave core calls the process communication start function to start the process communication module, and calls the communication identifier acquisition function to establish a remote connection with the master core; the master core registers notification events to build the interrupt module in the inter-core interaction framework; the master core binds messages to the linked list queue to build the linked list module in the inter-core interaction framework.

[0075] Among them, the process communication control function can be the Ipc_Control() function. Specifically, the master core can call the Ipc_Control() function to connect to the remote core (i.e., the slave core), and then the slave core calls the process communication start function (such as the Ipc_start() function) to start the process communication module, and calls the communication identification acquisition function (such as the Ipc_attach_ID() function) to complete the remote connection with the master core. At this point, the preliminary construction of the inter-core interaction framework has been completed. Further, the master core registers the notification event (Notify event), and shakes hands with the slave core to complete the protocol connection, so as to build the interrupt module in the inter-core interaction framework, and bind the message to the linked list queue (ListMP queue) to build the linked list module in the inter-core interaction framework.

[0076] Optionally, before the master core calls the process communication control function to send a connection request to the slave core, the master core may obtain the core number corresponding to each slave core, for example, by calling the MultiProc_getId() function to obtain the core number.

[0077] S130 : The master core accesses the first linked list and the second linked list through the address of the inter-core shared area, so as to transmit data to at least one slave core based on the first linked list and the second linked list.

[0078] Specifically, after the main core creates the first linked list and the second linked list, the main core can access the first linked list and the second linked list in the inter-core shared area through the address of the inter-core shared area, and obtain the data transmitted by the slave core through the first linked list or the second linked list by detecting the first linked list or the second linked list, or transmit data to the slave core by writing the data into the first linked list or the second linked list.

[0079] In a specific embodiment, the steps of transmitting data from the master core to the slave core are as follows: the master core detects whether the second linked list is empty, and if not, takes out a preset data structure from the second linked list; writes the data to be transmitted into the preset data structure, and puts the preset data structure with the data written into the head of the first linked list, so that when the slave core detects that the first linked list is not empty, it takes out the data from the head of the first linked list and puts the preset data structure of the taken out data into the head of the second linked list.

[0080] The preset data structure may be a blank node data structure (such as an empty Node data structure). The master core may perform a spin test on the second linked list. When detecting that the second linked list is not empty, the master core may retrieve the preset data structure from the second linked list, write the data to be transmitted into the preset data structure, and place the preset data structure after writing the data into the head of the first linked list. The slave core may perform a spin test on the first linked list. When detecting that the head of the first linked list is not empty, the slave core may retrieve the data from the head of the first linked list, and place the preset data structure after the data is retrieved into the head of the second linked list.

[0081] Exemplarily, the steps for the main core to receive data transmitted from the slave core can be as follows: the slave core can write the data to be transmitted into the head of the second linked list, and the main core can perform spin detection on the second linked list. When it is detected that the head of the second linked list is not empty, the preset data structure storing the data in the head is taken out, the data is extracted from the preset data structure, and the extracted preset data structure is placed into the head of the first linked list.

[0082] The inter-core communication method for heterogeneous multi-core chips provided in this embodiment is applicable to DAVINCI chips. Based on the underlying SysLink interface, it is highly compatible with DAVINCI chips and enables more efficient inter-core communication. This method utilizes shared memory for data transmission, effectively supporting the transmission of large amounts of data. During the transmission process, blocking queues and spin locks are used to control data transmission and reception, effectively ensuring the orderly transmission of data. By designing shared memory processing logic and message queue processing logic, efficient and orderly inter-core communication is ensured.

[0083] The technical solution of this embodiment is to create an inter-core shared area in the memory of the target heterogeneous multi-core chip through the master core in the target heterogeneous multi-core chip. The master core sends the address of the inter-core shared area to the slave core according to the interrupt module in the established inter-core interaction framework. Then, the master core creates a first linked list and a second linked list in the inter-core shared area according to the linked list module in the inter-core interaction framework, and accesses the first linked list and the second linked list by address, so as to transmit data to at least one slave core in the target heterogeneous multi-core chip through the first linked list and the second linked list, thereby realizing data transmission between the master core and each slave core in the heterogeneous multi-core chip, solving the technical problem of the complexity and difficulty of realizing inter-core communication in heterogeneous multi-core chips, and improving the development efficiency and versatility of inter-core communication in heterogeneous multi-core chips. In addition, this method can also realize mutual communication between cores running different operating systems in heterogeneous multi-core chips.

[0084] Example 2

[0085] Figure 2A The second embodiment of the present invention provides a flow chart of an inter-core communication method for a heterogeneous multi-core chip. This embodiment is applicable to situations where data transmission between a master core and a slave core is required in a heterogeneous multi-core chip such as a DAVINCI structure chip. The method can be executed by an inter-core communication device of a heterogeneous multi-core chip. The inter-core communication device of the heterogeneous multi-core chip can be implemented in the form of hardware and / or software and configured in a slave core in the target heterogeneous multi-core chip. The inter-core communication device of the heterogeneous multi-core chip can be configured in electronic devices such as mobile phones, computers, and tablets. Figure 2A As shown, the method includes:

[0086] S210. The slave core receives the address of the inter-core shared area sent by the master core based on the interrupt module in the established inter-core interaction framework, wherein the inter-core shared area is created by the master core in the memory of the target heterogeneous multi-core chip.

[0087] S220 : The slave core accesses the first linked list and the second linked list created by the master core in the inter-core shared area through the address of the inter-core shared area, so as to transmit data to the master core based on the first linked list and the second linked list.

[0088] The first linked list and the second linked list are created by the main core in the inter-core shared area based on the linked list module in the inter-core interaction framework.

[0089] In this embodiment, exemplarily, the process of building the inter-core interaction framework is as follows: if the slave core obtains the connection request sent by the master core by calling the process communication control function, the process communication start function is called to start the process communication module, and the communication identifier acquisition function is called to establish a remote connection with the master core; the slave core registers notification events to build the interrupt module in the inter-core interaction framework; the slave core binds the message to the linked list queue to build the linked list module in the inter-core interaction framework.

[0090] In a specific embodiment, the steps of transmitting data from the core to the main core are as follows: the slave core detects whether the first linked list is empty, and if not, takes out a preset data structure from the first linked list; writes the data to be transmitted into the preset data structure, and puts the preset data structure with the data written into the head of the second linked list, so that when the main core detects that the second linked list is not empty, it takes out the data from the head of the second linked list and puts the preset data structure of the taken out data into the head of the first linked list.

[0091] The slave core may perform a spin test on the first linked list. When detecting that the first linked list is not empty, the slave core may retrieve a preset data structure from the first linked list, write the data to be transmitted into the preset data structure, and place the preset data structure after the data is written into the head of the second linked list. The master core may perform a spin test on the second linked list. When detecting that the head of the second linked list is not empty, the slave core may retrieve data from the head of the second linked list, and place the preset data structure after the data is retrieved into the head of the first linked list.

[0092] Exemplarily, the steps for the slave core to receive data transmitted by the main core can be as follows: the main core can write the data to be transmitted into the head of the first linked list, and the slave core can perform spin detection on the first linked list. When it is detected that the head of the first linked list is not empty, the preset data structure storing the data in the head is taken out, the data is extracted from the preset data structure, and the extracted preset data structure is placed into the head of the second linked list.

[0093] For example, Figure 2B The figure shows a process diagram for transmitting data from the core to the main core. The DSP side spins to check whether the first linked list is empty. If it is not empty, it obtains an empty Node, packages the processed data into the Node's data structure, and then places the Node at the head of the second linked list. The ARM side spins to check whether the second linked list is empty. If it is not empty, it obtains the Node storing the data and extracts the data from the Node. This completes the data transmission from the DSP to the ARM. The ARM side then sends the Node to the DSP side.

[0094] The technical solution of this embodiment is to receive the address of the inter-core shared area sent by the master core based on the interrupt module in the established inter-core interaction framework through the slave core in the target heterogeneous multi-core chip. The slave core then accesses the first linked list and the second linked list created by the master core in the inter-core shared area through the address of the inter-core shared area, so as to transmit data to the master core through the first linked list and the second linked list. This realizes data transmission between the master core and each slave core in the heterogeneous multi-core chip, solves the technical problems of the complexity and difficulty of realizing inter-core communication in heterogeneous multi-core chips, and improves the development efficiency and versatility of inter-core communication in heterogeneous multi-core chips. In addition, this method can also realize mutual communication between cores running different operating systems in heterogeneous multi-core chips.

[0095] Example 3

[0096] Figure 3 This is a flow chart of a method for inter-core communication of a heterogeneous multi-core chip provided in the third embodiment of the present invention. Figure 3 As shown, the method includes:

[0097] S310. Establish the system structure engineering of the target heterogeneous multi-core chip, add relevant dependencies, add the framework files of the inter-core interaction framework, and introduce the dependent packages.

[0098] The system architecture engineering can be SYS / BIOS architecture engineering. SYS / BIOS can be a real-time operating system kernel for various digital signal processors (DSPs) and microcontrollers (MCUs), providing a wide range of system services for embedded applications, including preemptive multitasking, memory management, and real-time analysis. Using SYS / BIOS architecture engineering facilitates real-time data processing, expanding the applicable scenarios of this method.

[0099] Optionally, after importing the dependency packages, you can also configure the hardware of the master core and slave core.

[0100] S320: The master core and the slave core in the target heterogeneous multi-core chip respectively perform initialization operations on the inter-core interaction framework and call the core number acquisition function to respectively acquire the core number of the other party.

[0101] The core number acquisition function may be the MultiProc_getId() function.

[0102] S330 , the master core calls the process communication control function to send a connection request to the slave core, and the slave core calls the process communication start function to start the process communication module.

[0103] S340: The slave core calls a communication identification acquisition function to establish a remote connection with the master core, and calls a system startup function to start the system of the target heterogeneous multi-core chip.

[0104] The system startup function may be a BIOS_start() function, and the system of the target heterogeneous multi-core chip may be a SYS / BIOS system.

[0105] S350: The master core and the slave core register notification events respectively and bind messages to the linked list queue.

[0106] S360, the master core obtains a pointer to the shared memory area in the target heterogeneous multi-core chip, establishes an inter-core shared area in the shared memory area, and initiates a transmission event through the interrupt module to send the address of the inter-core shared area to the slave core.

[0107] S370 : The master core creates a first linked list and a second linked list in the inter-core shared area, and the master core and the slave core perform data transmission through the first linked list and the second linked list.

[0108] Optionally, if the master core and the slave core need to be disconnected, the master core may initiate a close request to close the inter-core shared area in the shared memory area, close the transmission events, and related variables.

[0109] The technical solution of this embodiment, by creating a first linked list and a second linked list in an inter-core shared area, enables data transmission between at least one slave core and a master core in a heterogeneous multi-core chip through the first and second linked lists. This solves the technical problem of the complexity and difficulty of implementing inter-core communication in heterogeneous multi-core chips, improving the development efficiency and versatility of inter-core communication in heterogeneous multi-core chips. Furthermore, this method can also enable communication between cores running different operating systems in a heterogeneous multi-core chip.

[0110] Example 4

[0111] Figure 4 This is a schematic diagram of the structure of an inter-core communication device for a heterogeneous multi-core chip provided by the fourth embodiment of the present invention. The device is configured in the master core of a target heterogeneous multi-core chip, and the target heterogeneous multi-core chip also includes at least one slave core. Figure 4 As shown, the apparatus includes: a shared area creation module 410 , a linked list creation module 420 and a data transmission module 430 .

[0112] A shared area creation module 410 is configured to create an inter-core shared area in the memory of the target heterogeneous multi-core chip, and send the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework;

[0113] A linked list creation module 420, configured to create a first linked list and a second linked list in the inter-core shared area based on the linked list module in the inter-core interaction framework;

[0114] The data transmission module 430 is configured to access the first linked list and the second linked list through the address of the inter-core shared area, so as to transmit data to at least one of the slave cores based on the first linked list and the second linked list.

[0115] Optionally, the shared area creation module 410 is specifically configured to:

[0116] By calling the acquisition function of the inter-core memory sharing module in the inter-core interaction framework, a pointer to the shared memory area of ​​the target heterogeneous multi-core chip is obtained; by calling the allocation function in the inter-core memory sharing module, an inter-core shared area is created in the shared memory area, and the address of the inter-core shared area is determined; an event to be transmitted is initiated through the interrupt module and the address of the inter-core shared area, and the event to be transmitted is sent to the slave core.

[0117] Optionally, the device also includes a framework building module, which is used to call the process communication control function to send a connection request to the slave core, so that the slave core calls the process communication start function to start the process communication module, and calls the communication identifier acquisition function to establish a remote connection with the master core; registers notification events to build an interrupt module in the inter-core interaction framework; binds messages to a linked list queue to build a linked list module in the inter-core interaction framework.

[0118] Optionally, the data transmission module 430 is also used to detect whether the second linked list is empty. If not, take out a preset data structure from the second linked list; write the data to be transmitted into the preset data structure, and put the preset data structure in which the data is written into the head of the first linked list, so that when the slave core detects that the first linked list is not empty, it takes out the data from the head of the first linked list and puts the preset data structure of the taken out data into the head of the second linked list.

[0119] In this embodiment, an inter-core shared area is created in the memory of the target heterogeneous multi-core chip by the master core in the target heterogeneous multi-core chip. The master core sends the address of the inter-core shared area to the slave core according to the interrupt module in the established inter-core interaction framework. Then, the master core creates a first linked list and a second linked list in the inter-core shared area according to the linked list module in the inter-core interaction framework, and accesses the first linked list and the second linked list by address, so as to transmit data to at least one slave core in the target heterogeneous multi-core chip through the first linked list and the second linked list, thereby realizing data transmission between the master core and each slave core in the heterogeneous multi-core chip, solving the technical problem of the complexity and difficulty of realizing inter-core communication in heterogeneous multi-core chips, and improving the development efficiency and versatility of inter-core communication in heterogeneous multi-core chips. In addition, this method can also realize mutual communication between cores running different operating systems in heterogeneous multi-core chips.

[0120] The inter-core communication device for a heterogeneous multi-core chip provided in an embodiment of the present invention can execute the inter-core communication method for a heterogeneous multi-core chip provided in any embodiment of the present invention, and has functional modules and beneficial effects corresponding to the execution method.

[0121] Example 5

[0122] Figure 5 This is a schematic diagram of the structure of an inter-core communication device for a heterogeneous multi-core chip provided by the fifth embodiment of the present invention. The device is configured in each slave core in the target heterogeneous multi-core chip, and the target heterogeneous multi-core chip also includes a master core. Figure 5 As shown, the device includes: an address receiving module 510 and a data transmission module 520.

[0123] An address receiving module 510 is configured to receive an address of an inter-core shared area sent by the master core based on an interrupt module in the established inter-core interaction framework, wherein the inter-core shared area is created by the master core in the memory of the target heterogeneous multi-core chip;

[0124] The data transmission module 520 is used to access the first linked list and the second linked list created by the main core in the inter-core shared area through the address of the inter-core shared area, so as to transmit data to the main core based on the first linked list and the second linked list; wherein, the first linked list and the second linked list are created by the main core in the inter-core shared area based on the linked list module in the inter-core interaction framework.

[0125] Optionally, the device also includes a framework building module, which is used to call the process communication start function to start the process communication module if the connection request sent by the main core by calling the process communication control function is obtained, and call the communication identifier acquisition function to establish a remote connection with the main core; register notification events to build an interrupt module in the inter-core interaction framework; bind messages to the linked list queue to build a linked list module in the inter-core interaction framework.

[0126] Optionally, the data transmission module 520 is also used to detect whether the first linked list is empty. If not, take out a preset data structure from the first linked list; write the data to be transmitted into the preset data structure, and put the preset data structure in which the data is written into the head of the second linked list, so that when the main core detects that the second linked list is not empty, it takes out the data from the head of the second linked list and puts the preset data structure of the taken out data into the head of the first linked list.

[0127] Example 6

[0128] Figure 6 This is a structural diagram of an electronic device provided in Example 6 of the present invention. Figure 6 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0129] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0130] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0131] The processor 11 may be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as inter-core communication methods for heterogeneous multi-core chips.

[0132] In some embodiments, the inter-core communication method of the heterogeneous multi-core chip can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the inter-core communication method of the heterogeneous multi-core chip described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the inter-core communication method of the heterogeneous multi-core chip by any other appropriate means (for example, by means of firmware).

[0133] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0134] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0135] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0136] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0137] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0138] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0139] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0140] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for inter-core communication of a heterogeneous multi-core chip, characterized in that: The target heterogeneous multi-core chip includes a master core and at least one slave core. The method includes: The master core creates an inter-core shared area in the memory of the target heterogeneous multi-core chip, and sends the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework; The main core creates a first linked list and a second linked list in the inter-core shared area based on the linked list module in the inter-core interaction framework; The master core accesses the first linked list and the second linked list through the address of the inter-core shared area, so as to transmit data to at least one of the slave cores based on the first linked list and the second linked list; The transmitting data to at least one of the slave cores based on the first linked list and the second linked list includes: The main core detects whether the second linked list is empty, and if not, retrieves a preset data structure from the second linked list; The data to be transmitted is written into the preset data structure, and the preset data structure in which the data is written is placed into the head of the first linked list, so that when the slave core detects that the first linked list is not empty, it takes out the data from the head of the first linked list and places the preset data structure of the taken out data into the head of the second linked list.

2. The method according to claim 1, characterized in that The master core creates an inter-core shared area in the memory of the target heterogeneous multi-core chip, and sends the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework, including: The main core obtains a pointer to the shared memory area of ​​the target heterogeneous multi-core chip by calling an acquisition function of the inter-core memory sharing module in the inter-core interaction framework; The main core creates an inter-core shared area in the shared memory area by calling an allocation function in the inter-core memory sharing module, and determines an address of the inter-core shared area; The master core initiates an event to be transmitted through the interrupt module and the address of the inter-core shared area, and sends the event to be transmitted to the slave core.

3. The method according to claim 1, characterized in that The method further comprises: The master core calls a process communication control function to send a connection request to the slave core, so that the slave core calls a process communication start function to start a process communication module, and calls a communication identifier acquisition function to establish a remote connection with the master core; The main core registers notification events to build an interrupt module in the inter-core interaction framework; The main core binds the message to the linked list queue to build the linked list module in the inter-core interaction framework.

4. A method for inter-core communication of a heterogeneous multi-core chip, characterized in that: The target heterogeneous multi-core chip includes a master core and at least one slave core. The method includes: The slave core receives an address of an inter-core shared area sent by the master core based on an interrupt module in the established inter-core interaction framework, wherein the inter-core shared area is created by the master core in the memory of the target heterogeneous multi-core chip; The slave core accesses the first linked list and the second linked list created by the master core in the inter-core shared area through the address of the inter-core shared area, so as to transmit data to the master core based on the first linked list and the second linked list; The first linked list and the second linked list are created by the main core in the inter-core shared area based on the linked list module in the inter-core interaction framework; The transmitting data to the main core based on the first linked list and the second linked list includes: The slave core detects whether the first linked list is empty, and if not, retrieves a preset data structure from the first linked list; The data to be transmitted is written into the preset data structure, and the preset data structure in which the data is written is placed into the head of the second linked list, so that when the main core detects that the second linked list is not empty, it takes out the data from the head of the second linked list and places the preset data structure of the taken out data into the head of the first linked list.

5. The method according to claim 4, characterized in that The method further comprises: If the slave core obtains the connection request sent by the master core by calling the process communication control function, it calls the process communication start function to start the process communication module, and calls the communication identifier acquisition function to establish a remote connection with the master core; The slave core registers notification events to build an interrupt module in the inter-core interaction framework; The slave core binds the message to the linked list queue to build the linked list module in the inter-core interaction framework.

6. An inter-core communication device for a heterogeneous multi-core chip, characterized in that: A master core configured in a target heterogeneous multi-core chip, wherein the target heterogeneous multi-core chip further includes at least one slave core, the apparatus comprising: A shared area creation module, configured to create an inter-core shared area in the memory of the target heterogeneous multi-core chip, and send the address of the inter-core shared area to the slave core based on the interrupt module in the established inter-core interaction framework; A linked list creation module, configured to create a first linked list and a second linked list in the inter-core shared area based on the linked list module in the inter-core interaction framework; a data transmission module, configured to access the first linked list and the second linked list through the address of the inter-core shared area, so as to transmit data to at least one of the slave cores based on the first linked list and the second linked list; The data transmission module is specifically configured for the main core to detect whether the second linked list is empty, and if not, to retrieve a preset data structure from the second linked list; The data to be transmitted is written into the preset data structure, and the preset data structure in which the data is written is placed into the head of the first linked list, so that when the slave core detects that the first linked list is not empty, it takes out the data from the head of the first linked list and places the preset data structure of the taken out data into the head of the second linked list.

7. An inter-core communication device for a heterogeneous multi-core chip, characterized in that: A slave core configured in a target heterogeneous multi-core chip, the target heterogeneous multi-core chip also including a master core, the device comprising: an address receiving module, configured to receive an address of an inter-core shared area sent by the master core based on an interrupt module in the established inter-core interaction framework, wherein the inter-core shared area is created by the master core in the memory of the target heterogeneous multi-core chip; a data transmission module, configured to access a first linked list and a second linked list created by the master core in the inter-core shared area through the address of the inter-core shared area, so as to transmit data to the master core based on the first linked list and the second linked list; The first linked list and the second linked list are created by the main core in the inter-core shared area based on the linked list module in the inter-core interaction framework; The data transmission module is specifically configured to detect whether the first linked list is empty in the slave core, and if not, retrieve a preset data structure from the first linked list; The data to be transmitted is written into the preset data structure, and the preset data structure in which the data is written is placed into the head of the second linked list, so that when the main core detects that the second linked list is not empty, it takes out the data from the head of the second linked list and places the preset data structure of the taken out data into the head of the first linked list.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the inter-core communication method of a heterogeneous multi-core chip according to any one of claims 1-3 or 4-5 when executed.

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