Device, method and readable storage medium supporting multiple access modes

Abstract

The present invention relates to an apparatus, method, and readable storage medium supporting multiple access modes. The computing device of the present invention is included in an integrated circuit device, which includes a universal interconnect interface and other processing devices. The computing device interacts with the other processing devices to jointly complete user-specified computing operations. The integrated circuit device may also include a storage device, each of which is connected to the computing device and the other processing devices and is used to store data for the computing device and the other processing devices.

Description

Technical Field

[0001] The present invention generally relates to the field of computers and, more particularly, to a device, method, and readable storage medium supporting multiple access modes. Background Art

[0002] A neural network is a computational model composed of a large number of interconnected nodes (or neurons). Each node represents a specific output function, called an activation function. Each connection between two nodes represents a weighted value for the signal passing through that connection, called a weight, which acts as the memory of the artificial neural network. The network's output varies depending on the network's connections, weights, and activation function. The network itself is often an approximation of a natural algorithm or function, or it may express a logical strategy.

[0003] The core operation in convolutional neural networks is the convolution operation. The convolution kernel slides across the image matrix to obtain various eigenvalues, which requires a significant amount of hardware resources. Due to the limited number of multipliers and adders in AI processing chips, convolution operations are typically divided into multiple small regions for accumulation. Each accumulation result is temporarily stored in a register file, and after each region is calculated, the accumulated results are integrated. This operation requires a large number of register accesses.

[0004] Moreover, when performing some convolution operations (such as depthwise separation convolution), the write is performed in the order of the depth dimension, but the read may be based on the order of another dimension. After a large number of accesses, the idle and usable space in the register stack will be scattered irregularly throughout the stack, making register stack access very complex and inefficient.

[0005] Furthermore, current convolution operations require multiple access modes, including sequential access and jump access. Sequential access reads or writes multiple results sequentially, while jump access reads or writes multiple data points across several registers. These access modes are often used interchangeably during neural network inference. When operations continue for a period of time, register file access becomes very complex and inefficient.

[0006] Therefore, a technical solution that supports multiple access modes is urgently needed. Summary of the Invention

[0007] In order to at least partially solve the technical problems mentioned in the background technology, the solution of the present invention provides a device, method and readable storage medium that support multiple access modes.

[0008] In one aspect, the present invention discloses a register file that supports multiple access modes, including a register array having a P group and a Q bank. The multiple access modes include a skip write mode, in which N data are written to the register array each time, with each data stored M registers apart. The multiple access modes utilize the (M+1)×N groups and R banks of the register array for storage, where (M+1)×N is not greater than P and R is not greater than Q.

[0009] In another aspect, the present invention discloses a computing device supporting multiple access modes, wherein the multiple access modes include multiple skip write modes, wherein the i-th skip write mode writes N i data, each data interval is M i The computing device includes a register array having a P group and a Q bank, and the multiple access modes utilize (M q +1)×N q Group and R library storage, where (M q +1)×N q Not greater than P, R not greater than Q. Among them, (M q +1)×N q is one of the plurality of jump write modes (M i +1)×N i The maximum value of .

[0010] In another aspect, the present invention discloses an integrated circuit device including the aforementioned computing device, and also discloses a board including the aforementioned integrated circuit device.

[0011] In another aspect, the present invention provides a method for supporting a skip write mode using a register array. The register array has P groups and Q banks. The skip write mode writes N data to the register array at a time, with each data stored M registers apart. The method includes: setting an (M+1)×N group and R bank of the register array as a subarray, where (M+1)×N is not greater than P and R is not greater than Q; synchronously enabling registers in one bank of the subarray; and selectively inputting the N data into N registers in the group.

[0012] In another aspect, the present invention provides a method for supporting multiple access modes using a register array, wherein the register array has a P group and a Q bank, wherein the multiple access modes include multiple skip write modes, wherein the i-th skip write mode is to write N i data, each data interval is M i The method includes: setting the register array (M q +1)×N q The group and R library are subarrays, where (Mq +1)×N q is not greater than P, R is not greater than Q; synchronously enable the register of one bank of the subarray; and select the N i The data are input into the N i registers. Among them, (M q +1)×N q is one of the plurality of jump write modes (M i +1)×N i The maximum value of .

[0013] In another aspect, the present invention provides a computer-readable storage medium having stored thereon a computer program code for utilizing a register array to support an access mode. When the computer program code is executed by a processing device, the aforementioned method is performed.

[0014] The present invention reduces the read and write ports of the registers by properly planning the groups and banks of the register array, that is, reduces the data of the read and write ports, and effectively reduces the power consumption of the register array by adding the selection logic of the access mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts.

[0016] Figure 1 is a structural diagram showing a board according to an embodiment of the present invention;

[0017] Figure 2 is a structural diagram showing an integrated circuit device according to an embodiment of the present invention;

[0018] Figure 3 is a schematic diagram showing the internal structure of a computing device according to an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram showing the internal structure of a processor core according to an embodiment of the present invention;

[0020] Figure 5 is a schematic diagram showing when a processor core wants to write data to a processor core of another cluster;

[0021] Figure 6 1 is a schematic diagram illustrating a register file in an NRAM according to an embodiment of the present invention;

[0022] Figure 7 is a schematic diagram illustrating a 16×4 subarray according to an embodiment of the present invention;

[0023] Figure 8 is a schematic diagram illustrating accessing a subarray in ORDER 1 mode according to an embodiment of the present invention;

[0024] Figure 9 is a schematic diagram illustrating accessing a subarray in ORDER2 mode according to an embodiment of the present invention;

[0025] Figure 10 is a schematic diagram illustrating accessing a subarray in ORDER 4 mode according to an embodiment of the present invention;

[0026] Figure 11 is a schematic diagram illustrating accessing a subarray in STRIDE 3_2 mode according to an embodiment of the present invention;

[0027] Figure 12 is a schematic diagram illustrating accessing a subarray in STRIDE 3_4 mode according to an embodiment of the present invention;

[0028] Figure 13 is a schematic diagram illustrating accessing a subarray in STRIDE 1_2 mode according to an embodiment of the present invention;

[0029] Figure 14 is a schematic diagram illustrating accessing a subarray in STRIDE 1_4 mode according to an embodiment of the present invention; and

[0030] Figure 15 is a flow chart illustrating a method for utilizing the aforementioned register array to support multiple access modes according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0032] It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present invention are used to distinguish different objects, rather than to describe a specific order. The terms "comprise" and "comprising" used in the description and claims of the present invention indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0033] It should also be understood that the terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the present invention. As used in the specification and claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should further be understood that the term "and / or" as used in the specification and claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0034] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context.

[0035] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 FIG. 1 is a schematic diagram showing the structure of a board 10 according to an embodiment of the present invention. Figure 1 As shown, board 10 includes chip 101, which is a system-on-chip (SoC), or system-on-chip, integrated with one or more combined processing devices. The combined processing device is an artificial intelligence computing unit that supports various deep learning and machine learning algorithms to meet the intelligent processing needs in complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in the field of cloud intelligence. A notable feature of cloud-based intelligent applications is the large amount of input data, which places high demands on the platform's storage and computing capabilities. Board 10 of this embodiment is suitable for cloud-based intelligent applications and has extensive off-chip storage, on-chip storage, and powerful computing capabilities.

[0037] Chip 101 is connected to external device 103 via external interface device 102. External device 103 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from external device 103 to chip 101 via external interface device 102. Calculation results from chip 101 can be transmitted back to external device 103 via external interface device 102. Depending on the application scenario, external interface device 102 may have different interface formats, such as a PCIe interface.

[0038] Board 10 also includes a memory device 104 for storing data, which includes one or more storage units 105. Memory device 104 is connected to a control device 106 and chip 101 via a bus for data transmission. Control device 106 in board 10 is configured to control the state of chip 101. To this end, in one application scenario, control device 106 may include a microcontroller (MCU).

[0039] Figure 2 FIG. 1 is a block diagram showing the combined processing device in the chip 101 of this embodiment. Figure 2 As shown in , the combined processing device 20 includes a computing device 201 , an interface device 202 , a processing device 203 and a DRAM 204 .

[0040] The computing device 201 is configured to perform user-specified operations and is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0041] Interface device 202 is used to transmit data and control instructions between computing device 201 and processing device 203. For example, computing device 201 can obtain input data from processing device 203 via interface device 202 and write it to a storage device on-chip of computing device 201. Furthermore, computing device 201 can obtain control instructions from processing device 203 via interface device 202 and write them to a control cache on-chip of computing device 201. Alternatively or optionally, interface device 202 can also read data from the storage device of computing device 201 and transmit it to processing device 203.

[0042] The processing device 203 is a general processing device that performs basic controls including but not limited to data handling, starting and / or stopping the computing device 201. Depending on the implementation, the processing device 203 can be a central processing unit (CPU), a graphics processing unit (GPU), or one or more types of processors among other general and / or special processors. These processors include but are not limited to digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, with respect to the computing device 201 of the present invention, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 201 and the processing device 203 are integrated and considered together, the two are regarded as forming a heterogeneous multi-core structure.

[0043] The DRAM 204 is used to store data to be processed. It is a DDR memory, typically 16G or larger, and is used to store data of the computing device 201 and / or the processing device 203 .

[0044] Figure 3 Figure 2 shows a schematic diagram of the internal structure of computing device 201. Computing device 201 is used to process input data for computer vision, speech, natural language processing, data mining, and other applications. The computing device 201 in the figure adopts a multi-core layered architecture. As a system-on-chip (SoC), computing device 201 includes multiple clusters, each of which includes multiple processor cores. In other words, computing device 201 is constructed in a hierarchy of SoC-cluster-processor cores.

[0045] At the system-on-chip level, Figure 3 As shown, the computing device 201 includes an external storage controller 301 , a peripheral communication module 302 , an on-chip interconnect module 303 , a synchronization module 304 and multiple clusters 305 .

[0046] There can be multiple external storage controllers 301, and two are shown in the figure as an example. They are used to respond to access requests issued by the processor core and access external storage devices, such as Figure 2DRAM 204 in the chip, thereby reading data from or writing data to the chip. The peripheral communication module 302 is used to receive control signals from the processing device 203 through the interface device 202 to start the computing device 201 to perform tasks. The on-chip interconnect module 303 connects the external storage controller 301, the peripheral communication module 302 and multiple clusters 305 to transmit data and control signals between each module. The synchronization module 304 is a global synchronization barrier controller (GBC) used to coordinate the work progress of each cluster and ensure information synchronization. Multiple clusters 305 are the computing cores of the computing device 201. Four are shown as an example in the figure. With the development of hardware, the computing device 201 of the present invention can also include 8, 16, 64, or even more clusters 305. Clusters 305 are used to efficiently execute deep learning algorithms.

[0047] At the cluster level, Figure 3 As shown, each cluster 305 includes multiple processor cores (IPU cores) 306 and a memory core (MEM core) 307 .

[0048] The figure shows four processor cores 306 as an example, but the present invention does not limit the number of processor cores 306. Figure 4 Each processor core 306 includes three modules: a control module 41 , a calculation module 42 and a storage module 43 .

[0049] The control module 41 coordinates and controls the operations of the computing module 42 and the storage module 43 to complete deep learning tasks. It includes an instruction fetch unit (IFU) 411 and an instruction decode unit (IDU) 412. The instruction fetch unit 411 retrieves instructions from the processing device 203, while the instruction decode unit 412 decodes the retrieved instructions and sends the decoded results as control information to the computing module 42 and the storage module 43.

[0050] The operation module 42 includes a vector operation unit 421 and a matrix operation unit 422. The vector operation unit 421 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformation. The matrix operation unit 422 is responsible for the core calculations of the deep learning algorithm, namely matrix multiplication and convolution.

[0051] The storage module 43 is used to store or move related data and includes a neuron RAM (NRAM) 431, a weight RAM (WRAM) 432, an input / output direct memory access module (IODMA) 433, and a move direct memory access module (MVDMA) 434. NRAM 431 is used to store feature maps and intermediate results calculated by the processor core 306; WRAM 432 is used to store the weights of the deep learning network; IODMA 433 controls memory access between NRAM 431 / WRAM 432 and DRAM 204 via the broadcast bus 309; and MVDMA 434 controls memory access between NRAM 431 / WRAM 432 and SRAM 308.

[0052] Back to Figure 3 The storage core 307 is primarily used for storage and communication, namely, storing shared data or intermediate results between the processor cores 306, and performing communication between the cluster 305 and the DRAM 204, between the clusters 305, and between the processor cores 306. In other embodiments, the storage core 307 has scalar operation capabilities and is used to perform scalar operations.

[0053] The storage core 307 includes a shared memory unit (SRAM) 308, a broadcast bus 309, a cluster direct memory access module (CDMA) 310, and a global direct memory access module (GDMA) 311. The SRAM 308 acts as a high-performance data transfer station. Data reused between different processor cores 306 within the same cluster 305 does not need to be obtained from the DRAM 204 by each processor core 306. Instead, it is transferred between the processor cores 306 via the SRAM 308. The storage core 307 only needs to quickly distribute the reused data from the SRAM 308 to multiple processor cores 306, thereby improving inter-core communication efficiency and significantly reducing on-chip and off-chip input / output access.

[0054] The broadcast bus 309, CDMA 310, and GDMA 311 are used for communication between the processor cores 306, communication between the clusters 305, and data transmission between the clusters 305 and the DRAM 204, respectively. Each of these will be described below.

[0055] The broadcast bus 309 facilitates high-speed communication between the processor cores 306 within the cluster 305. In this embodiment, the broadcast bus 309 supports inter-core communication methods including unicast, multicast, and broadcast. Unicast refers to point-to-point data transmission (i.e., single-core to single-core data transmission). Multicast transfers a copy of data from the SRAM 308 to a specific number of processor cores 306. Broadcast transfers a copy of data from the SRAM 308 to all processor cores 306 and is a special case of multicast.

[0056] The CDMA 310 is used to control memory access to the SRAM 308 between different clusters 305 within the same computing device 201 . Figure 5 This diagram illustrates the operation of CDMA 310 when one processor core attempts to write data to a processor core in another cluster. In this scenario, the same computing device includes multiple clusters. For ease of illustration, only Cluster 0 and Cluster 1 are shown. Cluster 0 and Cluster 1 each include multiple processor cores. Similarly, for ease of illustration, only Core 0 is shown in Cluster 0, and Core 1 is shown in Cluster 1. Core 0 attempts to write data to Core 1.

[0057] First, processor core 0 sends a unicast write request to write data to local SRAM 0. CDMA 0 acts as the master and CDMA 1 acts as the slave. The master pushes the write request to the slave. That is, the master sends the write address AW and write data W to transfer the data to SRAM 1 of cluster 1. The slave then sends a write response B in response. Finally, processor core 1 of cluster 1 sends a unicast read request to read the data from SRAM 1.

[0058] Back to Figure 3GDMA 311 works with external memory controller 301 to control memory access from cluster 305's SRAM 308 to DRAM 204, or to read data from DRAM 204 to SRAM 308. As previously mentioned, communication between DRAM 204 and NRAM 431 or WRAM 432 can be achieved through two channels. The first channel directly connects DRAM 204 and NRAM 431 or WRAM 432 via IODAM 433. The second channel first transfers data between DRAM 204 and SRAM 308 via GDMA 311, and then transfers data between SRAM 308 and NRAM 431 or WRAM 432 via MVDMA 434. While the second channel may appear to require more components and result in a longer data flow, in some embodiments, the bandwidth of the second channel is significantly greater than the first channel. Therefore, communication between DRAM 204 and NRAM 431 or WRAM 432 through the second channel may be more efficient. The embodiment of the present invention can select a data transmission channel according to its own hardware conditions.

[0059] In other embodiments, the functions of GDMA 311 and IODMA 433 can be integrated into the same component. For ease of description, the present invention treats GDMA 311 and IODMA 433 as separate components. For those skilled in the art, as long as the functions implemented and the technical effects achieved are similar to those of the present invention, they fall within the scope of protection of the present invention. Furthermore, the functions of GDMA 311, IODMA 433, CDMA 310, and MVDMA 434 can also be implemented by the same component.

[0060] Because the number of multipliers and adders in the matrix operation unit 422 is limited, when the matrix operation unit 422 performs a convolution calculation, the storage core 307 will cut the image to be calculated into multiple small blocks and assign them to each processor core 306. The matrix operation unit 422 processes one small block at a time, thus performing a large number of multiplication and addition operations, and then accumulating these multiplication and addition results until the accumulation is complete. To accommodate this operation method, the specific structure of NRAM 431 and WRAM 432 in this embodiment is a register file for temporarily storing the accumulated results. The matrix operation unit 422 will continue to access NRAM 431 and WRAM 432 at a high frequency to update the accumulated results until the accumulation operation is completed, and then output the accumulated results to SRAM 308.

[0061] Figure 6A schematic diagram of a register file in NRAM 431 is shown. As shown, register file 600 includes a register array 601, an enable logic group 602, and a read / write logic group 603. Register array 601 includes multiple registers 604, logically arranged in a P×Q array. That is, register array 601 has P groups and Q banks. Each row in the figure represents a group, and each column represents a bank. Enable logic group 602 includes Q enable logic gates 605, each of which is used to control all registers 604 in a bank to be enabled for reading and writing registers 604 in that bank. Read / write logic group 603 includes P read / write logic gates 606, each of which is used to write data to or read data from a specific bank. Register array 601 operates based on a clock signal CLK.

[0062] This embodiment supports multiple access modes to the register file 600 . These access modes can be roughly divided into two types: a jump access mode and a sequential access mode.

[0063] The jump access mode includes a jump write mode and an update read mode, wherein the jump write mode STRIDE M_N means that each time the register file 600 is accessed, N data are written to the register array 601 with M registers between them, and the update read mode means that N data are read from the register array 601 with M registers between them each time.

[0064] The following exemplifies the STRIDE 3_2, STRIDE 3_4, STRIDE 1_2, and STRIDE 1_4 modes in the skip write mode.

[0065] STRIDE 3_2 writes two data points at a time, jumping every three registers. In the first clock cycle, based on the pointer being i, the first data point is written to the i-th register of the specified bank, and the second data point is written to the i+4th register of the specified bank. The pointer increments by 1 after each write. In the second clock cycle, based on the pointer being i+1, the first data point is written to the i+1th register of the specified bank, and the second data point is written to the i+5th register of the specified bank. The pointer increments by 1 after each write. In the third clock cycle, based on the pointer being i+2, the first data point is written to the i+2th register of the specified bank, and the second data point is written to the i+6th register of the specified bank. The pointer increments by 1 after each write. In the fourth clock cycle, based on the pointer being i+3, the first data point is written to the i+3th register of the specified bank, and the second data point is written to the i+7th register of the specified bank. At this time, if the pointer increases by 1, it will become i+4, and the i+4th register has been used in the first clock cycle. Pointing to the i+4th register again will overwrite the data written in the first clock cycle. Therefore, in the fourth clock cycle, the pointer increases by 5 after writing and becomes i+8, so that the first data of the next clock cycle is written to the i+8th register of the specific bank.

[0066] STRIDE 3_4 writes or reads four pieces of data at a time, jumping three registers at a time. In the first clock cycle, based on pointer i, the first piece of data is written to register i of the specified bank, the second piece of data is written to register i+4 of the specified bank, the third piece of data is written to register i+8 of the specified bank, and the fourth piece of data is written to register i+12 of the specified bank. The pointer increments by 1 after each write. In the second clock cycle, based on pointer i+1, the first piece of data is written to register i+1 of the specified bank, the second piece of data is written to register i+5 of the specified bank, the third piece of data is written to register i+9 of the specified bank, and the fourth piece of data is written to register i+13 of the specified bank. The pointer increments by 1 after each write. In the third clock cycle, based on the pointer being i+2, the first data is written into the i+2th register of the specific bank, the second data is written into the i+6th register of the specific bank, the third data is written into the i+10th register of the specific bank, and the fourth data is written into the i+14th register of the specific bank. After writing, the pointer is incremented by 1. In the fourth clock cycle, based on the pointer being i+3, the first data is written into the i+3th register of the specific bank, the second data is written into the i+7th register of the specific bank, the third data is written into the i+11th register of the specific bank, and the fourth data is written into the i+15th register of the specific bank. In the S×(M+1)th clock cycle, the pointer is incremented by (S+1)×N×(M+1) after writing.

[0067] At this time, if the pointer increases by 1, it will become i+4, and the i+4th register has been used in the first clock cycle. Pointing to the i+4th register again will overwrite the data written in the first clock cycle. Therefore, in the fourth clock cycle, the pointer increases by 13 after writing and becomes i+16, so that the first data of the next clock cycle is written to the i+16th register of the specific bank.

[0068] STRIDE 1_2 writes two data items at a time, jumping one register at a time. In the first clock cycle, based on the pointer being i, the first data item is written to the i-th register of the specific bank, and the second data item is written to the i+2-th register of the specific bank. The pointer increments by 1 after writing. In the second clock cycle, based on the pointer being i+1, the first data item is written to the i+1-th register of the specific bank, and the second data item is written to the i+3-th register of the specific bank. At this time, if the pointer increments by 1, the data written in the first clock cycle will be overwritten. Therefore, in the third clock cycle, the pointer increments by 3 after writing, becoming i+4, so that the first data item of the next clock cycle is written to the i+4-th register of the specific bank.

[0069] STRIDE 1_4 writes four data points at a time, jumping one register at a time. In the first clock cycle, based on the pointer being i, the first data point is written to the i-th register of the specified bank, the second data point is written to the i+2th register of the specified bank, the third data point is written to the i+4th register of the specified bank, and the fourth data point is written to the i+6th register of the specified bank. The pointer is incremented by 1 after each write. In the second clock cycle, based on the pointer being i+1, the first data point is written to the i+1th register of the specified bank, the second data point is written to the i+3th register of the specified bank, the third data point is written to the i+5th register of the specified bank, and the fourth data point is written to the i+7th register of the specified bank. At this time, if the pointer is incremented by 1, the data written in the first clock cycle will be overwritten. Therefore, in the third clock cycle, the pointer is incremented by 7 after the write, becoming i+8, so that the first data point of the next clock cycle is written to the i+8th register of the specified bank.

[0070] In summary, when an integer number (M+1) of clock cycles is encountered, the pointer is not incremented by 1, but must be incremented by an integer number (M+1)×NM.

[0071] When the access mode is STRIDE M_N, register array 601 only requires the (M+1)×N group plus the R bank subarray 607 to meet the storage requirements. Since register array 601 is P×Q, (M+1)×N cannot be greater than P, and R can be any number but not greater than Q. In other words, the P×Q register array 601 can be logically divided into ((M+1)×N)×R subarrays 607 for storage of the STRIDE M_N access mode. It can be understood that when (M+1)×N=P and R=Q, the entire register array 601 will be used for storage of STRIDE M_N.

[0072] During the accumulation process, the update read mode is used to temporarily store the intermediate results of partial sums in register array 601. The vector operation unit 421 or matrix operation unit 422 reads the intermediate results, adds them to a data point, and then stores the updated intermediate results back in the original registers. The accumulation process repeatedly utilizes the update read mode to update the intermediate results in the registers. The following details how the update read mode operates for fixed-point and floating-point numbers.

[0073] If the operation involves fixed-point numbers, the addition operation of this embodiment can be completed within a single clock cycle. The register for reading the intermediate result is the same register for writing the updated intermediate result. Therefore, the operation of the update read mode is similar to that of the skip write module. Each time, N data are read from the register array 601 at intervals of M registers. The pointer increment method is also the same as the pointer increment method of the skip write module, so it will not be repeated here.

[0074] For operations involving floating-point numbers, such as 32-bit floating-point numbers (float 32), addition requires two clock cycles to complete. This means that the intermediate result of the partial sum is read in the current cycle, and the updated intermediate result is written in the second clock cycle. Therefore, the operation is largely the same as for fixed-point numbers, but the pointer for the updated read mode involving floating-point numbers must be set one clock cycle ahead of the pointer for the jump write module.

[0075] The sequential access mode means that each time the register file 600 is accessed, multiple data are read or written from consecutive registers in the register array 601 along the bank direction. The sequential access mode can be further divided into a sequential write mode and a sequential read mode.

[0076] In this embodiment, the sequential write mode is used to write S data to consecutive registers of the register array 601 at a time, where S is no greater than P. In one application scenario, when the multiple access modes include skip write and sequential write, S is no greater than (M+1)×N. The sequential write modes illustratively include ORDER1, ORDER2, and ORDER4 modes, where ORDER1 sequentially writes one data item and the post-access pointer increments by 1; ORDER2 sequentially writes two data items and the post-access pointer increments by 2; and ORDER4 sequentially writes four data items and the post-access pointer increments by 4.

[0077] The sequential read mode is used to read T data from consecutive registers of the register array 601 at a time, where T is no greater than P. In one application scenario, when the multiple access modes include update read and sequential read, T is no greater than (M+1)×N. The sequential read mode is commonly used in convolution calculations in neural networks. After the convolution calculation is completed, the calculation result is read from the NRAM 431 and sent to the SRAM 308. At this time, the sequential read mode is used. Sequential read modes include ROUT1, ROUT2, and ROUT4. ROUT1 sequentially reads data from one register at a time, and the pointer increments by 1. ROUT2 sequentially reads data from two registers at a time, and the pointer increments by 2. ROUT4 sequentially reads data from four registers at a time, and the pointer increments by 4.

[0078] As neural network models become increasingly complex, the register access operations required by various operators may be inconsistent, resulting in the computing device 201 involving multiple access modes when performing neural network inference. In one application scenario, the computing device 201 of this embodiment needs to simultaneously support the seven access modes described above, namely, ORDER1, ORDER2, ORDER4, STRIDE 3_2, STRIDE 3_4, STRIDE 1_2, and STRIDE 1_4. Before performing inference, the control module 41 first identifies the minimum unit of the number of groups required for each library in these access modes.

[0079] ORDER1 writes one data item at a time, ORDER2 writes two data items at a time, and ORDER4 writes four data items at a time. For these three modes, the minimum unit of each bank only requires four registers, which can accommodate four write cycles for ORDER1, two write cycles for ORDER2, and one write cycle for ORDER4.

[0080] Considering various jump write modes, STRIDE 3_2 writes two pieces of data every three registers, so one round (i.e., the pointer increments to 5 instead of 1) requires eight registers. STRIDE 3_4 writes four pieces of data every three registers, so one round (i.e., the pointer increments to 13 instead of 1) requires 16 registers. STRIDE 1_2 writes two pieces of data every one register, so one round (i.e., the pointer increments to 3 instead of 1) requires four registers. STRIDE 1_4 writes four pieces of data every one register, so one round (i.e., the pointer increments to 7 instead of 1) requires eight registers. For these four modes, the minimum unit of each bank is 16 registers, which can accommodate two rounds of writing for STRIDE 3_2, one round for writing for STRIDE 3_4, four rounds for writing for STRIDE 1_2, and two rounds for writing for STRIDE 1_4.

[0081] In sequential write mode, the minimum unit per bank is 4 registers, and in skip write mode, the minimum unit per bank is 16 registers. 16 registers is an integer multiple of 4 registers, so 16 registers allows both sequential and skip write modes to write an integer number of rounds per bank.

[0082] In addition to judging all sequential write modes and jump write modes, the control module 41 also includes sequential read and update read modes in the evaluation, but the number of registers occupied by each round of the sequential read and update read modes is no different from that of the sequential write mode and jump write mode, respectively. Furthermore, under normal circumstances, the number of registers occupied by each round in the sequential write mode is not large, and the minimum number of registers for each bank is usually determined by the jump write mode, and the number of registers occupied by each round of each jump write mode is mostly an integer multiple of each other. In summary, when the control module 41 wants to judge the number of registers required for each round of each mode, in theory, the lowest common denominator of the number of registers occupied by each round of all access modes is taken as the number of registers for each bank (that is, the number of groups). In practice, it is only necessary to judge the number of registers occupied by all jump write modes STRIDE M i _N i (M i +1)×N i The maximum value (M q +1)×N q , it can be ensured that each mode accesses an integer number of rounds in each bank. Each mode accesses an integer number of rounds in each bank to avoid the problem that when the operation continues for a period of time, the unused space in the register file is scattered irregularly throughout the register file. Furthermore, since the subarray 607 only needs (M q +1)×N qInstead of all P read-write logic gates 606 participating in the operation, the number of read-write logic gates 606 that the NRAM 431 needs to control is reduced, making the control easier.

[0083] In order to support the above 7 access modes at the same time, such as Figure 7 As shown, the control module 41 logically sets the subarray 607 to 16×4, that is, an array with 16 groups and 4 banks. Correspondingly, there are 4 enable logic gates 701-704 for synchronously enabling the registers of a bank respectively, and 16 read / write logic gates 705-720 for selecting up to 4 data to be input to 4 registers in each of the 16 groups. For convenience of explanation, R x,y Refers to the register of the xth group and the yth bank.

[0084] Figure 8 The mechanism of accessing a subarray in ORDER1 mode is shown. Assume that all registers (R 0,0 to R 15,0 ) and Bank 1 Group 0 to Group 5 (R 0,1 to R 5,1 ) is already occupied, as shown by the register marked at the bottom of the net in the figure. At this time, the pointer points to R 6,1 Taking the example of writing 8 data in the queue of control module 41 in ORDER1 mode, the enable logic gate 702 enables all registers in bank 1 to be opened and ready to receive data, while the other enable logic gates disable all registers in the other banks. Since ORDER1 writes 1 data sequentially each time, when the first data is written for the first time, the first data is transmitted to all read-write logic gates 705-720. According to the pointer, only the read-write logic gate 711 allows the first data to be written to R 6,1 , the pointer increases by 1 and points to R 7,1 When the second data is written for the second time, the second data is also transmitted to all read-write logic gates 705-720. According to the pointer, only the read-write logic gate 712 allows the second data to be written to R 7,1 , the pointer increases by 1 and points to R 8,1 Similarly, 8 data are written into R 6,1 to R 13,1 The number i in the figure represents the i-th write.

[0085] Figure 9 The following diagram shows the mechanism for accessing a subarray in ORDER2 mode. Assume that no register is occupied and the pointer points to R 0,0Taking the example of writing 16 data in the queue of control module 41 in ORDER2 mode, the enable logic gate 701 enables all registers in bank 0 to be opened and ready to receive data, while the other enable logic gates disable all registers in the other banks. Since ORDER2 writes 2 data in sequence each time, the first write is based on the pointer, and the read-write logic gate 705 allows the first data to be written into R 0,0 , and the read-write logic gate 706 allows the second data to be written into R 1,0 , the pointer increases by 2 and points to R 2,0 , the second write is based on the pointer, the read-write logic gate 707 allows the third data to be written into R 2,0 , and the read-write logic gate 708 allows the fourth data to be written into R 3,0 , the pointer increases by 2 and points to R 4,0 Similarly, 16 data are written into R 0,0 to R 15,0 , just fill up the bank 0, and finally the pointer points to R 0,1 .

[0086] Figure 10 The mechanism of accessing subarrays in ORDER4 mode is shown. Assume that all registers of Bank 0, Bank 1 and Bank 2 Group 0 to Group 11 (R 0,2 to R 11,2 ) is already occupied, as shown by the register marked at the bottom of the net in the figure. At this time, the pointer points to R 12,2 Taking the example of writing 8 data in the queue of control module 41 in ORDER4 mode, the enable logic gate 703 enables all registers in bank 2 to be opened and ready to receive data, while the other enable logic gates disable all registers in the other banks. Since ORDER4 writes 4 data in sequence each time, the first write writes the first data to R according to the pointer read / write logic gate 717. 12,2 , read-write logic gate 718 allows the second data to be written into R 13,2 , read-write logic gate 719 allows the third data to be written into R 14,2 , the read-write logic gate 720 allows the fourth data to be written into R 15,2 , the pointer increases by 4 and points to R 0,3 At this time, the enable logic gate 704 enables all registers in bank 3 to be opened and ready to receive data, while the other enable logic gates disable all registers in the other banks. The second write is based on the pointer read-write logic gate 705 to write the fifth data into R 0,3 , read-write logic gate 706 allows the sixth data to be written into R 1,3 , read-write logic gate 707 allows the seventh data to be written into R 2,3 , read-write logic gate 708 allows the 8th data to be written into R 3,3 , the pointer increases by 4 and points to R 4,3 .

[0087] Figure 11 Shows the mechanism for accessing subarrays in STRIDE 3_2 mode. Assume R 0,0 to R 7,0 The register is occupied, as shown in the register marked at the bottom of the net in the figure. At this time, the pointer points to R 8,0 Taking the example of 16 data to be written in STRIDE 3_2 mode in the queue of control module 41, the enable logic gate 701 enables all registers in bank 0 to be opened and ready to receive data, while the other enable logic gates disable all registers in the other banks. The first write is based on the pointer read / write logic gate 713 to write the first data into R 8,0 , read-write logic gate 717 allows the second data to be written into R 12,0 , the pointer increases by 1 and points to R 9,0 The second write is based on the pointer read-write logic gate 714 to write the third data into R 9,0 , read-write logic gate 718 allows the fourth data to be written into R 13,0 , the pointer increases by 1 and points to R 10,0 And so on, the writing of 16 data is completed as shown in the figure.

[0088] Figure 12 The following figure shows the mechanism for accessing a subarray in STRIDE 3_4 mode. Assume that no register is occupied and the pointer points to R 0,0 Taking the queue of control module 41 as an example, the write of 16 data in STRIDE 3_4 mode should be executed, the enable logic gate 701 enables all registers of bank 0 to be opened and ready to receive data, while the other enable logic gates disable all registers of the other banks. The first write is based on the pointer read / write logic gate 705 to write the first data into R 0,0 , read-write logic gate 709 allows the second data to be written into R 4,0 , read-write logic gate 713 allows the third data to be written into R 8,0 , read-write logic gate 717 allows the fourth data to be written into R 12,0 , the pointer increases by 1 and points to R 1,0 , when writing for the second time, the read-write logic gate 706 writes the fifth data into R 1,0 , the read-write logic gate 710 allows the sixth data to be written into R 5,0 , read-write logic gate 714 allows the seventh data to be written into R 9,0 , read-write logic gate 718 allows the 8th data to be written into R 13,0 , the pointer increases by 1 and points to R 2,0 And so on, the writing of 16 data is completed as shown in the figure.

[0089] Figure 13The mechanism of accessing subarrays in STRIDE 1_2 mode is shown. Assume that Bank 0, Bank 1, Bank 2 all and Bank 3 Group 0 to Group 3 (R 0,3 to R 3,3 ) is already occupied, as shown by the register marked at the bottom of the net in the figure. At this time, the pointer points to R 4,3 Taking the queue of control module 41 as an example, the write of 8 data in STRIDE 1_2 mode should be executed, the enable logic gate 704 enables all registers of bank 3 to be opened and ready to receive data, while the other enable logic gates disable all registers of the other banks. The first write is based on the pointer read-write logic gate 709 to write the first data into R 4,3 , read-write logic gate 711 allows the second data to be written into R 6,3 , the pointer increases by 1 and points to R 5,3 , when writing for the second time, the read-write logic gate 710 allows the third data to be written into R 5,3 , read-write logic gate 712 allows the fourth data to be written into R 7,3 , then the pointer increases by 3 and points to R 8,3 , read-write logic gate 713 allows the fifth data to be written into R 8,3 , read-write logic gate 715 allows the sixth data to be written into R 10,3 And so on, the writing of 8 data is completed as shown in the figure.

[0090] Figure 14 The mechanism of accessing subarrays in STRIDE 1_4 mode is shown. Assume that Bank 0 Group 0 to Group 11 (R 0,0 to R 11,0 ) is already occupied, as shown by the register marked at the bottom of the net in the figure. At this time, the pointer points to R 12,0 Taking the example of writing 8 data in STRIDE 1_4 mode in the queue of control module 41, first enable logic gate 701 enables all registers in bank 0 to be opened and ready to receive data, while the other enable logic gates disable all registers in the other banks. The first write is based on the pointer read / write logic gate 717 to write the first data into R 12,0 , read-write logic gate 719 allows the second data to be written into R 14,0 , then enable logic gate 702 enables all registers in bank 1 to be opened and ready to receive data, while the other enable logic gates disable all registers in the other banks, and read / write logic gate 705 allows the third data to be written into R 0,1 , read-write logic gate 707 allows the fourth data to be written into R 2,1 , the pointer increases by 1 and points to R 13,0 At this time, the enable logic gate 701 enables all registers in bank 0 to be reopened and ready to receive data, while the other enable logic gates disable all registers in the other banks. When writing for the second time, the read / write logic gate 718 allows the fifth data to be written into R 13,0, the read-write logic gate 720 allows the sixth data to be written into R 15,0 , then enable logic gate 702 re-enables all registers in bank 1 to start and prepare to receive data, while the remaining enable logic gates disable all registers in the remaining banks, and read / write logic gate 706 allows the seventh data to be written into R 1,1 , read-write logic gate 708 allows the 8th data to be written into R 3,1 The writing of 8 data is completed as shown in the figure.

[0091] The register access method of sequential read mode and update read mode is basically the same as that of sequential write and jump write. The difference is that the data in the register is read instead of writing data to the register. Those skilled in the art can easily understand the register access method of sequential read mode and update read mode based on the aforementioned write modes, so it will not be repeated here.

[0092] The enable logic group 602 and the read / write logic group 603 are logic gate combinations to implement the aforementioned control method. The logic gate combinations for implementing such control methods are well known to those skilled in the art and will not be described in detail.

[0093] This embodiment reduces the read and write ports of the registers by properly planning the groups and banks of the register array, that is, reduces the data of the read and write ports. In addition, the access mode selection logic is added to effectively reduce the power consumption of the register array.

[0094] Another embodiment of the present invention is a method for utilizing the aforementioned register array to support multiple access modes, wherein the method is executed by the computing device 201, such as Figure 15 As shown, the following steps are included.

[0095] In step 1501 , the (M+1)×N group and the R bank of the register array are set as subarrays, where (M+1)×N is not greater than P and R is not greater than Q.

[0096] The computing device 201 of this embodiment also needs to support the aforementioned seven access modes, namely ORDER1, ORDER2, ORDER4, STRIDE 3_2, STRIDE 3_4, STRIDE 1_2, and STRIDE 1_4. Before performing inference, the control module 41 first identifies the minimum unit of the number of groups required for each library in these access modes.

[0097] ORDER1 writes one data item at a time, ORDER2 writes two data items at a time, and ORDER4 writes four data items at a time. For these three modes, the minimum unit of each bank only requires four registers, which can accommodate four write cycles for ORDER1, two write cycles for ORDER2, and one write cycle for ORDER4.

[0098] Considering various skip write patterns, when the access pattern is STRIDE M_N, register array 601 only needs the (M+1)×N group plus the R bank subarray 607 to meet the storage requirements. Since register array 601 is P×Q, (M+1)×N cannot be greater than P, and R can be any number but not greater than Q. In other words, the P×Q register array 601 can be logically divided into ((M+1)×N)×R subarrays 607 to store the STRIDE M_N access pattern.

[0099] STRIDE 3_2 writes two pieces of data every three registers, so one round (i.e., the pointer increments to 5 instead of 1) requires eight registers. STRIDE 3_4 writes four pieces of data every three registers, so one round (i.e., the pointer increments to 13 instead of 1) requires 16 registers. STRIDE 1_2 writes two pieces of data every one register, so one round (i.e., the pointer increments to 3 instead of 1) requires four registers. STRIDE 1_4 writes four pieces of data every one register, so one round (i.e., the pointer increments to 7 instead of 1) requires eight registers. For these four modes, the minimum unit of each bank is 16 registers, which can accommodate two rounds of writing with STRIDE 3_2, one round with STRIDE 3_4, four rounds with STRIDE 1_2, and two rounds with STRIDE 1_4.

[0100] In sequential write mode, the minimum unit per bank is 4 registers, and in skip write mode, the minimum unit per bank is 16 registers. 16 registers is an integer multiple of 4 registers, so 16 registers allows both sequential and skip write modes to write an integer number of rounds per bank.

[0101] In addition to judging all sequential write modes and jump write modes, the control module 41 also includes sequential read and update read modes in the evaluation, but the number of registers occupied by each round of the sequential read and update read modes is no different from that of the sequential write mode and jump write mode, respectively. Furthermore, under normal circumstances, the number of registers occupied by each round in the sequential write mode is not large, and the minimum number of registers for each bank is usually determined by the jump write mode, and the number of registers occupied by each round of each jump write mode is mostly an integer multiple of each other. In summary, when the control module 41 wants to judge the number of registers required for each round of each mode, in theory, the lowest common denominator of the number of registers occupied by each round of all access modes is taken as the number of registers for each bank (that is, the number of groups). In practice, it is only necessary to judge the number of registers occupied by all jump write modes STRIDE M i _N i (M i +1)×Ni The maximum value (M q +1)×N q , it can be ensured that each mode accesses an integer number of rounds in each bank. Each mode accesses an integer number of rounds in each bank to avoid the problem that when the operation continues for a period of time, the unused space in the register file is scattered irregularly throughout the register file. Furthermore, since the subarray 607 only needs (M q +1)×N q Instead of all P read-write logic gates 606 participating in the operation, the number of read-write logic gates 606 that the NRAM 431 needs to control is reduced, making the control easier.

[0102] In step 1502, the registers of one bank of the subarray are synchronously enabled. In step 1503, N data are selected and inputted into the N registers in the group. To support the seven access modes described above, control module 41 logically configures subarray 607 as a 16×4 array, i.e., an array with 16 groups and 4 banks. This corresponds to four enable logic gates 701-704 for synchronously enabling the registers of one bank, and 16 read / write logic gates 705-720 for selecting up to four data at a time to be inputted into four registers in each of the 16 groups.

[0103] Another embodiment of the present invention is a computer-readable storage medium having stored thereon a computer program code that utilizes a register array to support an access mode, and when the computer program code is executed by a processor, the method of each embodiment described above is executed. In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the solution of the present invention is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions for causing a computer device (such as a personal computer, a server or a network device, etc.) to execute some or all of the steps of the method described in the embodiment of the present invention. The aforementioned memory may include, but is not limited to, various media that can store program code, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0104] The present invention reduces the read and write ports of the registers by properly planning the groups and banks of the register array, that is, reduces the data of the read and write ports, and effectively reduces the power consumption of the register array by adding the selection logic of the access mode.

[0105] Depending on the application scenario, the electronic device or device of the present invention may include a server, a cloud server, a server cluster, a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, an Internet of Things terminal, a mobile terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a visual terminal, an automatic driving terminal, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric light, a gas stove, and a range hood; the medical device includes an MRI, an ultrasound machine and / or an electrocardiograph. The electronic device or device of the present invention may also be applied to the Internet, the Internet of Things, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, medical care and other fields. Furthermore, the electronic device or device of the present invention may also be used in application scenarios related to artificial intelligence, big data and / or cloud computing, such as the cloud, edge, and terminal. In one or more embodiments, electronic devices or apparatuses with high computing power according to the solution of the present invention can be applied to cloud devices (such as cloud servers), while electronic devices or apparatuses with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0106] It should be noted that, for the purpose of simplicity, the present invention describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will understand that the scheme of the present invention is not limited by the order of the described actions. Therefore, based on the disclosure or teachings of the present invention, those skilled in the art will understand that some of the steps therein can be performed in other orders or simultaneously. Further, those skilled in the art will understand that the embodiments described in the present invention can be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the implementation of one or more schemes of the present invention. In addition, depending on the different schemes, the present invention also has different emphases on the description of some embodiments. In view of this, those skilled in the art will understand that the parts that are not described in detail in a certain embodiment of the present invention may also refer to the relevant descriptions of other embodiments.

[0107] In terms of specific implementation, based on the disclosure and teachings of the present invention, those skilled in the art can understand that several embodiments disclosed in the present invention can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article splits them based on the consideration of logical functions, and there may be other ways of splitting them in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in the units or components can be selectively disabled. With respect to the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0108] In the present invention, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network elements. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solutions described in the embodiments of the present invention. In addition, in some scenarios, multiple units in the embodiments of the present invention may be integrated into a single unit or each unit may exist physically separately.

[0109] In some other implementation scenarios, the above-mentioned integrated units can also be implemented in the form of hardware, that is, as specific hardware circuits, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0110] The foregoing content can be better understood in accordance with the following terms:

[0111] Item A1. A register file supporting multiple access modes, comprising a register array having a P group and a Q bank, wherein the multiple access modes include a jump write mode, wherein the jump write mode writes N data to the register array each time, and each data is stored M registers apart, and the multiple access modes utilize the (M+1)×N groups and R banks of the register array for storage, wherein (M+1)×N is not greater than P, and R is not greater than Q.

[0112] Item A2. The register file of Item A1, further comprising R enable logic gates, each enable logic gate being used to synchronously enable registers of a bank.

[0113] Item A3. The register file according to Item A1, further comprising (M+1)×N write logic gates for selecting the N data to be input into N registers in the (M+1)×N group.

[0114] Item A4. The register file of Item A1, wherein the plurality of access modes further comprises a sequential write mode for writing S data at a time into consecutive registers of the register array, wherein S is not greater than P.

[0115] Item A5. The register file of Item A1, wherein the plurality of access modes further comprises a sequential read mode for reading T data at a time from consecutive registers of the register array, wherein T is not greater than P.

[0116] Item A6. The register file of Item A1, wherein the plurality of access modes further comprises an update read mode for reading N data from every other M registers in the register array at a time.

[0117] Item A7. A computing device supporting multiple access modes, wherein the multiple access modes include multiple skip write modes, wherein the i-th skip write mode is to write N i data, each data interval is M i register storage, the computing device includes: a register array, having a P group and a Q bank, the multiple access modes utilize (M q +1)×N q Group and R library storage, where (M q +1)×N q Not greater than P, R not greater than Q; where (M q +1)×N q is one of the plurality of jump write modes (M i +1)×N i The maximum value of .

[0118] Item A8. The computing device according to Item A7, further comprising R enable logic gates, each enable logic gate being used to synchronously enable registers of a bank.

[0119] Clause A9. The computing device according to clause A7, further comprising (M q +1)×N q Write logic gates to select the N i Data input to (M q +1)×N q N in the group i registers.

[0120] Item A10. The computing device of Item A7, wherein the plurality of access modes further comprises a plurality of sequential write modes, the i-th sequential write mode being used to write S each time. i data into the consecutive registers of the register array, where S i Not greater than P.

[0121] Clause A11. The computing device of clause A7, wherein the plurality of access modes further comprises a plurality of sequential read modes, the i-th sequential read mode being used to read T from consecutive registers of the register array each time. i data, among which Ti Not greater than P.

[0122] Clause A12. The computing device of clause A7, wherein the plurality of access modes further comprises a plurality of update read modes, the i-th update read mode being used to read the register array at intervals of M at a time. i Register read N i data.

[0123] Clause A13. The computing device according to clause A7, further comprising a control module for identifying (M q +1)×N q .

[0124] Clause A14. An integrated circuit device comprising a computing device according to any one of clauses A7 to A13.

[0125] Item A15. A card comprising the integrated circuit device of Item A14.

[0126] Item A16. A method of using a register array to support a skip write mode, the register array having P groups and Q banks, the skip write mode being to write N data to the register array at a time, with each data stored M registers apart, the method comprising: setting the (M+1)×N group and R bank of the register array as a subarray, where (M+1)×N is not greater than P, and R is not greater than Q; synchronously enabling registers in one bank of the subarray; and selectively inputting the N data into N registers in the group, respectively.

[0127] Item A17. A method for supporting multiple access modes using a register array, the register array having a P group and a Q bank, the multiple access modes including a plurality of skip write modes, wherein the i-th skip write mode is a mode in which N is written each time. i data, each data interval is M i registers for storage, the method comprising: setting the register array (M q +1)×N q The group and R library are subarrays, where (M q +1)×N q is not greater than P, R is not greater than Q; synchronously enable the register of one bank of the subarray; and select the N i The data are input into the N i registers; among them, (M q +1)×N q is one of the plurality of jump write modes (M i +1)×N i The maximum value of .

[0128] Item A18. A computer-readable storage medium having stored thereon a computer program code for utilizing a register array to support an access mode, wherein when the computer program code is executed by a processing device, the method of any one of Items A16 to A17 is performed.

[0129] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A register file supporting multiple access modes, comprising a register array having P groups and Q banks. The multiple access modes include a skip write mode, wherein the skip write mode writes N data to the register array at a time, each data being stored M registers apart. The multiple access modes utilize (M+1)×N groups and R banks of the register array for storage, where (M+1)×N is not greater than P, and R is not greater than Q.

2. The register file according to claim 1, further comprising R enable logic gates, each enable logic gate being used to synchronously enable registers of a bank. 3 . The register file according to claim 1 , further comprising (M+1)×N write logic gates for selecting the N data to be input into N registers in the (M+1)×N group. 4 . The register file according to claim 1 , wherein the plurality of access modes further comprises a sequential write mode for writing S data at a time into consecutive registers of the register array, wherein S is not greater than P. 5 . The register file according to claim 1 , wherein the plurality of access modes further comprises a sequential read mode for reading T data from consecutive registers of the register array each time, wherein T is not greater than P. 6 . The register file according to claim 1 , wherein the plurality of access modes further comprises an update read mode for reading N data from every other M registers in the register array each time.

7. A computing device supporting multiple access modes, wherein the multiple access modes include multiple skip write modes, wherein the i-th skip write mode writes N i data, each data interval is M i register storage, the computing device includes: Register array, having P group and Q bank, the multiple access modes utilize (M q +1)×N q Group and R library storage, where (M q +1)×N q Not greater than P, R not greater than Q; Among them, (M q +1)×N q is one of the plurality of jump write modes (M i +1)×N i The maximum value of .

8. The computing device according to claim 7, further comprising R enable logic gates, each enable logic gate being used to synchronously enable registers of a bank.

9. The computing device according to claim 7, further comprising (M q +1)×N q Write logic gates to select the N i Data input to (M q +1)×N q N in the group i registers.

10. The computing device according to claim 7, wherein the plurality of access modes further comprises a plurality of sequential write modes, wherein the i-th sequential write mode is used to write S i data into the consecutive registers of the register array, where S i Not greater than P.

11. The computing device according to claim 7, wherein the plurality of access modes further comprises a plurality of sequential read modes, wherein the i-th sequential read mode is used to read T from consecutive registers of the register array each time. i data, among which T i Not greater than P.

12. The computing device according to claim 7, wherein the plurality of access modes further comprises a plurality of update read modes, wherein the i-th update read mode is used to read M bytes from the register array at a time. i Register read N i data.

13. The computing device according to claim 7, further comprising a control module for identifying (M q +1)×N q .

14. An integrated circuit device comprising a computing device according to any one of claims 7 to 13.

15. A board comprising the integrated circuit device according to claim 14.

16. A method for supporting a skip write mode using a register array, the register array having P groups and Q banks, wherein the skip write mode writes N data to the register array at a time, each data being stored at intervals of M registers, the method comprising: Set the (M+1)×N group and R bank of the register array as subarrays, where (M+1)×N is not greater than P and R is not greater than Q; Synchronously enabling a register of one bank of the subarray; as well as The N data are selected to be input into the N registers in the group respectively.

17. A method for supporting multiple access modes using a register array, wherein the register array has a P group and a Q bank, wherein the multiple access modes include a plurality of skip write modes, wherein the i-th skip write mode writes N i data, each data interval is M i register storage, the method comprising: Set the register array (M q +1)×N q The group and R library are subarrays, where (M q +1)×N q Not greater than P, R not greater than Q; Synchronously enabling a register of one bank of the subarray; as well as Select the N i The data are input into the N i registers; Among them, (M q +1)×N q is one of the plurality of jump write modes (M i +1)×N i The maximum value of .

18. A computer-readable storage medium having stored thereon a computer program code for utilizing a register array to support an access mode, wherein when the computer program code is executed by a processing device, the method according to any one of claims 16 to 17 is performed.

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