read reference circuit, read operation circuit, and memory cell

Abstract

The application provides a read reference circuit, a read operation circuit and a storage unit. The read reference circuit comprises one or more parallel reference modules. The reference module comprises two first and second reference units which are connected in series and have different written data. The current directions of the first and second reference units are the same during the write operation and the read operation. The read reference circuit, the read operation circuit and the storage unit can avoid the interference of MRAM during the read operation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a read reference circuit, a read operation circuit, and a memory cell. Background Technology

[0002] Magnetic Random Access Memory (MRAM) boasts high read / write speeds, high density, low power consumption, long data retention time, and long lifespan, thus holding immense promise. Because MRAM's resistance is variable, it can store data information through different resistance states.

[0003] MRAM contains a magnetic tunnel junction (MTJ). MTJ data is rewritten by changing the direction of the magnetic moment of the free layer through spin electron flow. Therefore, even a small current for a long time can rewrite the data. Thus, read disturbances can easily occur during read operations, leading to data rewriting. Summary of the Invention

[0004] The technical problem solved by this application is to avoid interference with MRAM during read operations.

[0005] To address the aforementioned technical problems, this application provides a read reference circuit, comprising: one or more reference modules connected in parallel; each reference module includes two first reference units and second reference units connected in series and having different data to be written; the first reference unit and the second reference unit have the same current direction during write and read operations, respectively.

[0006] In this embodiment of the application, the read reference circuit further includes: a first reference bit line connected to the first reference unit; a second reference bit line connected to the second reference unit; and a reference source line connected to the first reference unit and the second reference unit; wherein, one of the first reference bit line and the second reference bit line outputs a reference signal, the other is connected to a low level, and the reference source line is floating.

[0007] In this embodiment, the first reference unit is written with 0, the second reference unit is written with 1, the first reference bit line outputs a reference signal, and the second reference bit line is connected to a low level.

[0008] In this embodiment, the first reference unit includes: a first MTJ unit connected to the first reference bit line; and a first transistor, wherein a first electrode of the first transistor is connected to the first MTJ unit, and a second electrode of the first transistor is connected to the reference source line and the second reference unit.

[0009] In this embodiment, the second reference unit includes: a second MTJ unit connected to the second reference bit line; and a second transistor, wherein the first electrode of the second transistor is connected to the second MTJ unit, and the second electrode of the second transistor is connected to the reference source line and the second electrode of the first transistor.

[0010] This application also provides a read operation circuit, comprising: a read reference circuit for providing a reference signal, including one or more parallel reference modules, wherein the reference modules include two first reference units and second reference units connected in series and having different written data, wherein the first reference units and the second reference units have the same current direction when performing write and read operations, respectively; a data path for providing data to be read and outputting a data signal; and an amplifier circuit connected to the reference circuit and the data path for comparing the data signal and the reference signal to obtain a read result.

[0011] In this embodiment of the application, the reference circuit further includes: a first reference bit line connected to the first reference unit; a second reference bit line connected to the second reference unit; and a reference source line connected to the first reference unit and the second reference unit; one of the first reference bit line and the second reference bit line is connected to the amplifier circuit, the other is connected to a low level, and the reference source line is floating.

[0012] In this embodiment, the first reference unit is written with 0, the second reference unit is written with 1, the first reference bit line is connected to the amplifier circuit, and the second reference bit line is connected to a low level.

[0013] In this embodiment, the first reference unit includes: a first MTJ unit connected to the first reference bit line; and a first transistor, wherein a first electrode of the first transistor is connected to the first MTJ unit, and a second electrode of the first transistor is connected to the reference source line and the second reference unit.

[0014] In this embodiment, the second reference unit includes: a second MTJ unit connected to the second reference bit line; and a second transistor, wherein the first electrode of the second transistor is connected to the second MTJ unit, and the second electrode of the second transistor is connected to the reference source line and the second electrode of the first transistor.

[0015] In this embodiment of the application, the data path includes a data storage unit, one end of which is connected to a bit line and the other end is connected to a source line, which is connected to the amplifier circuit.

[0016] In this embodiment, the data signal is the output current of the data path, and the reference signal is the output current of the reference circuit.

[0017] In this embodiment of the application, the amplification circuit includes a sensitive amplifier.

[0018] This application also provides a storage unit including the read operation circuit described above.

[0019] The read reference circuit of this application includes one or more parallel reference modules, and each reference module includes two series-connected first reference units and second reference units with different written data. The read operation current and write operation current of the first reference unit and the second reference unit are aligned in direction, which effectively solves the problem of read disturb that is easy to occur when writing "1" reference units, significantly improves data storage performance, and ensures the consistency of the improved reference circuit and the overall array. It breaks the conventional understanding that the reference bit line is connected to a high level and the reference source line is connected to a low level during the read operation in the existing read reference circuit. Attached Figure Description

[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0021] Figure 1 This is a schematic diagram of a reference circuit.

[0022] Figure 2 This is a schematic diagram of the read reference circuit according to an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the read operation circuit according to an embodiment of this application. Detailed Implementation

[0024] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0025] refer to Figure 1A reference circuit includes a reference cell for writing "0" (0 cell) and a reference cell for writing "1" (1 cell), wherein the reference cell for writing "0" includes MTJ0 and transistor M0, and one end of MTJ0 is connected to the reference bit line BL_REF. <1> The other end is connected to the transistor M0, and one end of the transistor M0 is connected to the source line SL. The reference cell (1 cell) for writing "1" includes MTJ1 and transistor M1, and one end of MTJ1 is connected to the reference bit line BL_REF. <0> The other end is connected to the transistor M1, and one end of the transistor M1 is connected to the source line SL.

[0026] The reference cell for writing "0" and the reference cell for writing "1" are connected in parallel. During a read operation, the bit line BL_REF... <1> and the bit line BL_REF <0> When connected to a high level, the source line SL is grounded, and the reference current I of the reference cell for writing "0" is... P The current flows from FL (free layer) to PL (fixed layer), with a reference current I. P The size is V0 / (R) P +r0), V0 is the voltage across the reference cell where "0" is written, R P r0 is the resistance of MTJ0, and r0 is the resistance of transistor M0. Similarly, the reference current I of the reference cell for writing "1" is... AP The current flows from FL (free layer) to PL (fixed layer), with a reference current I. AP The size is V1 / (R) AP +r1), V1 is the voltage across the reference cell where "0" is written, R AP R1 is the resistor of MTJ1, and R2 is the resistor of transistor M1. The reference current I after the parallel connection of the reference cell for writing "0" and the reference cell for writing "1" is 0.5 (I P +I AP ).

[0027] Typically, a set of reference circuits provides references for devices on multiple bit lines BL. Assuming there are 2x bit lines BL, the total charge flowing through the reference device is 2x times that of a typical device. This results in the total charge in the reference device being 2x times that of a typical device. This is due to the write current of the reference cell for writing "1" and the reference current I. AP The inconsistent flow direction greatly increases the probability of read disturbance in cell 1 of the reference device, which will significantly limit the data retention of the entire MRAM.

[0028] This application provides a read reference circuit that breaks through the conventional understanding that the reference bit line is connected to a high level and the reference source line is connected to a low level during the read operation. By changing the implementation of the reference circuit, reliability is improved. It uses 0 cell and 1 cell in series to ensure that the reference current flow is consistent with the data written by MTJ, which solves the problem of readdisturbance that is prone to occur in MRAM, effectively improves the data storage performance, and at the same time ensures the consistency of the improved reference circuit and the overall array.

[0029] The technical solution of this application will be described in detail below with reference to the embodiments and accompanying drawings.

[0030] refer to Figure 2 The read reference circuit of this application embodiment includes a reference module 11. The number of reference modules 11 can be one or more, and the reference modules 11 are connected in parallel. This application embodiment uses two parallel reference modules as an example for illustration.

[0031] The reference module 11 includes a first reference unit 111 and a second reference unit 112 connected in series. The data written to the first reference unit 111 and the second reference unit 112 are different. For example, the first reference unit 111 can be written with "0" and the second reference unit 112 with "1", or the first reference unit 111 can be written with "1" and the second reference unit 112 with "0". In this embodiment, it is specified that when writing "0", the current flows from the free layer to the fixed layer of the MTJ unit, and when writing "1", the current flows from the fixed layer to the free layer of the MTJ unit. In other embodiments, it can also be specified that when writing "0", the current flows from the fixed layer to the free layer of the MTJ unit, and when writing "1", the current flows from the free layer to the fixed layer of the MTJ unit, depending on the actual situation.

[0032] In this embodiment, the first reference unit 111 and the second reference unit 112 have the same current flow direction during write and read operations. Since the first reference unit 111 and the second reference unit 112 are connected in series, the direction and magnitude of the current flowing through them are the same. Because the current direction is the same in both the first reference unit 111 and the second reference unit 112 during write and read operations, read disturbance can be avoided.

[0033] The read reference circuit also includes a first reference bit line BL_REF. <1> Second reference bit line BL_REF <2> and reference source line SL_REF, first reference bit line BL_REF <1> Connect the first reference unit 111, that is, the first reference bit line BL_REF <1> One end of the reference module 11 is connected, and the second reference bit line BL_REF <2> Connect the second reference unit 112, that is, the second reference bit line BL_REF <2> The other end of the reference module 11 is connected. The reference source line SL_REF connects the first reference unit 111 and the second reference unit 112 of each reference module 11, that is, all reference units share a single reference source line SL_REF.

[0034] Among them, the first reference bit line BL_REF <1> and the second reference bit line BL_REF <2> One of the reference bits is used to output a reference signal, and the other is connected to a low level. The reference source line SL_REF is floating. In this embodiment, the reference bit line connected to the reference unit that writes "0" is used to output a reference signal, and the reference bit line connected to the reference unit that writes "1" is connected to a low level. In this embodiment, the first reference unit 111 writes "0", and the first reference bit line BL_REF connected to the first reference unit 111... <1> Used to output a reference signal, the second reference unit 112 is written with "1", and the second reference bit line BL_REF connected to the second reference unit 112... <2> Connect to a low level. In other embodiments, the first reference unit 111 may also be specified to be written with "1", and the first reference bit line BL_REF connected to the first reference unit 111 may be specified to be low. <1> When connected to a low level, the second reference unit 112 is written with "0", and the second reference bit line BL_REF connected to the second reference unit 112 is... <2> Used to output a reference signal, the reference source line SL REF is floating.

[0035] This application embodiment designs a first reference bit line BL_REF. <1> Second reference bit line BL_REF <2> The connection method of the reference source line SL_REF is such that the current direction of the first reference unit 111 is the same during write and read operations, and the current direction of the second reference unit 112 is also the same during write and read operations. This avoids the phenomenon of read disturb caused by the inconsistent flow direction of the write current and the reference current of the reference unit writing "1".

[0036] Continue to refer to Figure 2 The first reference unit 111 includes a first MTJ cell (0 cell) and a first transistor M1, and the first MTJ cell (0 cell) is connected to the first reference bit line BL_REF. <1> And the write current and the reference current I REFAll flows from FL (free layer) to PL (fixed layer). The first electrode of the first transistor M1 is connected to the first MTJ cell (0 cell), and the second electrode of the first transistor M1 is connected to the reference source line SL_REF and the second reference cell 112. In this embodiment, the first transistor M1 may be a PMOS transistor, the first electrode of the first transistor M1 may be the source, and the second electrode of the first transistor M1 may be the drain.

[0037] The second reference cell 112 includes a second MTJ cell (1 cell) and a second transistor M2, wherein the second MTJ cell (1 cell) is connected to the second reference bit line BL_REF. <2> The write current and reference current flowing through the second MTJ cell (1 cell) both flow from PL to FL. The first electrode of the second transistor M2 is connected to the second MTJ cell (1 cell), and the second electrode of the second transistor M2 is connected to the reference source line SL_REF and the second electrode of the first transistor M1. In this embodiment, the second transistor M2 can be a PMOS transistor, the first electrode of the second transistor M2 can be the drain, and the second electrode of the second transistor M2 can be the source.

[0038] The read reference circuit in this embodiment uses a shared reference source line SL_REF for connection. Two reference units are connected in series to form a reference module, and multiple reference modules are then connected in parallel to form a reference module. When writing data, it is connected to the first reference bit line BL_REF. <1> The data written to the connected reference cell is "0", which is consistent with the second reference bit line BL_REF. <2> The data written to the connected reference cell is "1"; during the read operation, the first reference bit line BL_REF is... <1> Connected to an amplification module (e.g., a sensitive amplifier), the second reference bit line BL_REF <2> With the reference source line SL_REF grounded and floating, when the number of parallel groups is 2, the obtained reference current I... REF for:

[0039] I REF =2V / (R) P +R AP +2×r);

[0040] Where V is the total voltage of the first reference unit 111 and the second reference unit 112, RP is the resistance of the first MTJ unit (0 cell), and R AP r is the resistance value of the second MTJ unit (1 cell), and r is the resistance value of the first transistor M1 and the second transistor M2. The I REF Size in Figure 1 The I shown P and IAP between.

[0041] For the first reference bit line BL_REF <1> For the first MTJ cell (0 cell), the current direction is from FL to PL, which is the same as the current direction for writing data "0"; for the second reference bit line BL_REF <2> For the second MTJ cell (1 cell), the current direction is from PL to FL, which is the same as the current direction when writing data "1". This avoids the possibility of read disturbing the reference cell.

[0042] refer to Figure 3 This application also provides a read operation circuit, including a reference circuit 1, a data path 2, and an amplifier circuit 3. The reference circuit 1 provides a reference signal, the data path 2 provides the data to be read and outputs a data signal, and the amplifier circuit 3 compares the data signal and the reference signal to obtain a read result.

[0043] The reference circuit 1 includes one or more parallel reference modules 11. Each reference module 11 includes two first reference units 111 and second reference units 112 connected in series and with different data to be written. The first reference unit 111 and the second reference unit 112 have the same current direction when performing write and read operations, which can avoid the possibility of read disturb in each reference unit and effectively improve the data storage performance of MRAM.

[0044] The reference circuit 1 also includes a first reference bit line BL_REF <1> Second reference bit line BL_REF <2> and reference source line SL_REF, first reference bit line BL_REF <1> Connect the first reference unit 111, and the second reference bit line BL_REF <2> The second reference unit 112 is connected, and the reference source line SL_REF connects the first reference unit 111 and the second reference unit 112. The first reference bit line BL_REF... <1> and the second reference bit line BL_REF <2> One of the reference bits is connected to the amplifier circuit 3, and the other is connected to a low level, while the reference source line SL_REF is floating. In this embodiment, the reference bit line connected to the reference cell that writes "0" is connected to the amplifier circuit 3, and the reference bit line connected to the reference cell that writes "1" is connected to a low level, that is, the first reference bit line BL_REF. <1> The amplifier circuit 3 is connected to output a reference signal, the second reference bit line BL_REF. <2> A low-level connection is provided to supply a low potential, and since no current flows through the reference source line SL_REF, the read reference circuit is a series circuit to ensure that the reference current flows from the first reference unit 111 to the second reference unit 112.

[0045] Continue to refer to Figure 3 The first reference cell 111 includes a first MTJ cell (0 cell) and a first transistor M1, the first MTJ cell being connected to the first reference bit line BL_REF. <1> The connection stores data "0". The first electrode of the first transistor M1 is connected to the first MTJ cell (0 cell), and the second electrode of the first transistor M1 is connected to the reference source line SL_REF and the second reference cell 112. The first transistor M1 can be a PMOS transistor, its first electrode can be the source, and its second electrode can be the drain.

[0046] The second reference cell 112 includes a second MTJ cell (1 cell) and a second transistor M2, the second MTJ cell (1 cell) and the second reference bit line BL_REF <2> Connected to store data "1", the second electrode of the second transistor M2 is connected to the reference source line SL_REF and the second electrode of the first transistor M1. The second transistor M2 can be a PMOS transistor, its first electrode can be the drain, and its second electrode can be the source.

[0047] The data path 2 includes a data storage unit 21. The number of data storage units 21 can be multiple, used to store the same or different data. One end of the data storage unit 21 is connected to the bit line BL, and the other end is connected to the source line SL. The source line SL is connected to the amplifier circuit 3.

[0048] The data storage unit 21 includes an MTJ cell and a transistor M0. The free layer (FL) of the MTJ cell is connected to the bit line BL, the fixed layer (PL) of the MTJ cell is connected to the first electrode of the transistor M0, and the second electrode of the transistor M0 is connected to the source line SL. The transistor M0 can be a PMOS, the first electrode of the transistor M0 can be the source, and the second electrode of the transistor M0 can be the drain.

[0049] The amplifier circuit 3 is connected to the reference circuit 1 and the data path 2. Specifically, the amplifier circuit 3 is connected to the first reference bit line BL_REF of the reference circuit 1. <1> The bit line BL of the data path 2 is used to compare the data signal of the data path 2 with the reference signal of the reference circuit 1 to obtain a read result. In some embodiments, the data signal is the output current I of the data path 2. cell The reference signal is the output current I of the reference circuit 1. REF If the output current Icell Greater than the output current I REF If the output current I is 1, then the result read is "1"; cell Less than the output current I REF If so, the result read will be "0".

[0050] This embodiment of the application outputs a reference signal from the reference bit line connected to the reference unit for writing "0" in the read reference circuit, while the reference bit line connected to the reference unit for writing "1" is connected to a low level, and the source line shared by the two reference units is made to float, thus connecting the reference units in series. At the same time, the write operation current and read operation current of each reference unit are in the same direction, which solves the read disturb problem caused by the inconsistent flow direction of the write current and reference current of the reference unit for writing "1", and greatly improves the read performance of the read reference circuit.

[0051] This application embodiment also provides a storage unit, including the read operation circuit described above.

[0052] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0053] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0054] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0055] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0056] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A reference reading circuit, characterized in that, include: One or more reference modules connected in parallel; The reference module includes two series-connected first reference units and second reference units with different data to be written. The first reference unit includes: a first MTJ unit connected to a first reference bit line; and a first transistor, the first electrode of which is connected to the first MTJ unit, and the second electrode of which is connected to the reference source line and the second reference unit. The first reference unit and the second reference unit have the same current direction during write and read operations, respectively. The first reference bit line is connected to the first reference cell; The second reference bit line is connected to the second reference cell; The reference source line is shared by the first reference unit and the second reference unit. One of the first reference bit line and the second reference bit line outputs a reference signal, while the other is connected to a low level. The reference source line is floating.

2. The reference reading circuit according to claim 1, characterized in that, The first reference cell is written with 0, the second reference cell is written with 1, the first reference bit line outputs a reference signal, and the second reference bit line is connected to a low level.

3. The read reference circuit according to claim 2, characterized in that, The second reference unit includes: a second MTJ unit, connected to the second reference bit line; The second transistor has a first electrode connected to the second MTJ cell and a second electrode connected to the reference source line and the second electrode of the first transistor.

4. A read operation circuit, characterized in that, include: A read reference circuit is used to provide a reference signal, including one or more parallel reference modules. The reference modules include two first reference units and second reference units connected in series and having different data written to them. The first reference unit and the second reference unit have the same current direction when performing write and read operations, respectively. The read reference circuit also includes a first reference bit line connected to the first reference unit. A second reference bit line is connected to the second reference unit; a reference source line is shared by the first reference unit and the second reference unit, wherein one of the first reference bit line and the second reference bit line outputs a reference signal, and the other is connected to a low level, and the reference source line is floating; wherein the first reference unit includes: a first MTJ unit connected to the first reference bit line; a first transistor, the first electrode of the first transistor is connected to the first MTJ unit, and the second electrode of the first transistor is connected to the reference source line and the second reference unit; The data path provides the data to be read and outputs data signals. An amplifier circuit, connected to the read reference circuit and the data path, is used to compare the data signal and the reference signal to obtain the read result.

5. The read operation circuit according to claim 4, characterized in that, The first reference cell is written with 0, the second reference cell is written with 1, the first reference bit line is connected to the amplifier circuit, and the second reference bit line is connected to a low level.

6. The read operation circuit according to claim 5, characterized in that, The second reference unit includes: a second MTJ unit, connected to the second reference bit line; The second transistor has a first electrode connected to the second MTJ cell and a second electrode connected to the reference source line and the second electrode of the first transistor.

7. The read operation circuit according to claim 4, characterized in that, The data path includes a data storage unit, one end of which is connected to a bit line and the other end of which is connected to a source line, which is connected to the amplifier circuit.

8. The read operation circuit according to claim 4, characterized in that, The data signal is the output current of the data path, and the reference signal is the output current of the read reference circuit.

9. The read operation circuit according to claim 4, characterized in that, The amplifier circuit includes a sensitive amplifier.

10. A storage unit, characterized in that, Includes the read operation circuit as described in any one of claims 4 to 9.

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