Flash control method and Flash controller

Abstract

The present disclosure provides a Flash control method and a Flash controller, the method comprising: obtaining a first bus address from a received first control instruction, the first control instruction being a read instruction; determining a Flash memory address corresponding to the first bus address according to a preset address mapping relationship; and obtaining data from a corresponding position in the Flash memory according to the Flash memory address. The embodiment of the present disclosure utilizes the mapping relationship between the first bus address and the Flash memory address to determine the Flash memory address, and can directly read data from the corresponding position of the Flash memory, avoiding the operation of the register, thereby improving the efficiency of reading data from the Flash memory.

Description

Technical Field

[0001] The present disclosure relates to the technical field of Flash control, and in particular to a Flash control method and a Flash controller. Background Art

[0002] Flash (FLASH flash memory) is a non-volatile memory and is widely used in various portable digital devices. Flash-based SSD (Solid State Disk) includes Flash controller and Flash memory (i.e. Flash chip). Most Flash controllers support reading, checking, and programming control of Flash memory, and support ECC (Error Correcting Code) verification.

[0003] In the related art, the Flash controller usually uses registers to access the Flash memory, and generally sets the transmission mode, address length, address, data and data length according to the command, and then reads and writes the data stored in the Flash memory according to the command timing, and caches the read data in the register for the read instruction. This Flash control solution that relies on registers has low transmission efficiency. Summary of the invention

[0004] The present disclosure provides a Flash control method and a Flash controller.

[0005] In a first aspect, an embodiment of the present disclosure provides a Flash control method, including:

[0006] Acquire a first bus address from a received first control instruction, where the first control instruction is a read instruction;

[0007] Determine the Flash memory address corresponding to the first bus address according to a preset address mapping relationship;

[0008] Data is acquired from a corresponding position in the Flash memory according to the Flash memory address.

[0009] In some embodiments, the Flash memory address includes a NOR Flash memory address and a NAND Flash memory address.

[0010] In some embodiments, the method further comprises:

[0011] Acquire a second bus address from a received second control instruction, where the second control instruction is a read instruction or a write instruction;

[0012] According to the second bus address, a data processing operation corresponding to the second control instruction is performed in a corresponding register.

[0013] In some embodiments, the Flash controller includes a first control module and a second control module. Before receiving the first control instruction and the second control instruction, the method further includes:

[0014] Receive the control instruction sent by the central processing unit CPU and obtain the bus address carried therein;

[0015] In response to the bus address being a first bus address, sending a first control instruction carrying the first bus address to the first control module;

[0016] In response to the bus address being a second bus address, a second control instruction carrying the second bus address is sent to the second control module.

[0017] In some embodiments, the obtaining the first bus address from the received first control instruction includes: in response to receiving the first control instruction during the Flash memory reset process, caching the first control instruction, and obtaining the first bus address from the first control instruction after the Flash memory reset is completed; and / or,

[0018] The acquiring the second bus address from the received second control instruction comprises: in response to receiving the second control instruction during the Flash memory reset process, caching the second control instruction, and acquiring the second bus address from the second control instruction after the Flash memory reset is completed.

[0019] In some embodiments, the Flash memory is a NOR Flash memory, and the Flash memory reset is completed, including: the NOR Flash memory power-on reset is completed;

[0020] The Flash memory is a NAND Flash memory, and the Flash memory is reset, which includes: the NAND Flash memory is powered on and reset and the software is reset.

[0021] In yet another aspect, an embodiment of the present disclosure further provides a Flash controller, comprising a first control module, a command control module and a sending module, wherein the command control module is connected to the first control module and the sending module respectively;

[0022] The first control module is used to obtain a first bus address from a received first control instruction, where the first control instruction is a read instruction; and determine a Flash memory address corresponding to the first bus address according to a preset address mapping relationship;

[0023] The command control module is used to generate a data query instruction according to the Flash memory address;

[0024] The sending module is used to send the data query instruction to the Flash memory, and after receiving the data sent by the Flash memory, send the data to the first control module, where the data is the data obtained by the Flash memory according to the Flash memory address.

[0025] In some embodiments, the Flash controller also includes a second control module, which is connected to the command control module and is used to obtain a second bus address from a received second control instruction, where the second control instruction is a read instruction or a write instruction; according to the second bus address, a data processing operation corresponding to the second control instruction is executed in a corresponding register.

[0026] In some embodiments, the Flash controller also includes an instruction distribution module, which is connected to the first control module and the second control module, and is used to receive control instructions sent by the central processing unit CPU and obtain the bus address carried therein; in response to the bus address being a first bus address, sending a first control instruction carrying the first bus address to the first control module; in response to the bus address being a second bus address, sending a second control instruction carrying the second bus address to the second control module.

[0027] In some embodiments, the first control module and the second control module are connected to the instruction distribution module via an AHB bus.

[0028] In some embodiments, the Flash controller further includes a reset control module, and the reset control module is connected to the first control module and the second control module;

[0029] The first control module is used for caching the first control instruction in response to receiving the first control instruction during the resetting process of the Flash memory;

[0030] The second control module is used for caching the second control instruction in response to receiving the second control instruction during the resetting process of the Flash memory;

[0031] The reset control module is used to, after the Flash memory is reset, instruct the first control module to obtain the first bus address from the first control instruction; and / or, after the Flash memory is reset, to obtain the second bus address from the second control instruction.

[0032] In some embodiments, the first control module includes a cache unit, the bit width of the cache unit is 8-64 bits, and the cache unit is used to cache the data.

[0033] The Flash control method provided by the embodiment of the present disclosure is applied to the Flash controller, and the method includes: obtaining a first bus address from a received first control instruction, the first control instruction being a read instruction; determining a Flash memory address corresponding to the first bus address according to a preset address mapping relationship; and obtaining data from a corresponding position in the Flash memory according to the Flash memory address. The embodiment of the present disclosure determines the Flash memory address by using the mapping relationship between the first bus address and the Flash memory address, and can directly read data from the corresponding position of the Flash memory, avoiding the operation of the register, thereby improving the efficiency of reading data from the Flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the Flash control method provided in the embodiment of the present disclosure Figure 1 ;

[0035] Figure 2 Schematic diagram of the Flash control method provided in the embodiment of the present disclosure Figure 2 ;

[0036] Figure 3 A flowchart of instruction distribution provided by an embodiment of the present disclosure;

[0037] Figure 4 A schematic diagram of the structure of the Flash controller provided in the embodiment of the present disclosure Figure 1 ;

[0038] Figure 5 A schematic diagram of the structure of the Flash controller provided in the embodiment of the present disclosure Figure 2 ;

[0039] Figure 6 A schematic diagram of the structure of the Flash controller provided in the embodiment of the present disclosure Figure 3 ;

[0040] Figure 7 A schematic diagram of the structure of the Flash controller provided in the embodiment of the present disclosure Figure 4 ;

[0041] Figure 8 A schematic diagram of the structure of the Flash controller provided in the embodiment of the present disclosure Figure 5 . DETAILED DESCRIPTION

[0042] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0043] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0045] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of idealized schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0047] The present disclosure provides a Flash control method. Figure 1 As shown, the Flash control method is applied to a Flash controller, the Flash controller at least includes a first control module, and the Flash control method includes the following steps:

[0048] Step 11, obtaining a first bus address from a received first control instruction, where the first control instruction is a read instruction.

[0049] In this step, after receiving the read instruction, the first control module obtains the first bus address carried therein. The first control module may be an Advanced High Performance Bus (AHB) slave (AHB SLV), and a mapping relationship between the first bus address and the Flash memory address is preset in the first control module.

[0050] Step 12: Determine the Flash memory address corresponding to the first bus address according to a preset address mapping relationship.

[0051] In this step, the first control module queries the address mapping relationship according to the first bus address, and determines the Flash memory address corresponding to the first bus address, where the Flash memory address is the storage address of the data in the Flash memory.

[0052] Step 13, obtaining data from a corresponding position in the Flash memory according to the Flash memory address.

[0053] In this step, the Flash controller encapsulates the Flash memory address in a data read command and sends the data read command to the Flash memory to query data at the corresponding position of the Flash memory. After receiving the data returned by the Flash memory, the data is cached in the first control module and sent to the CPU (central processing unit).

[0054] The Flash control method provided by the embodiment of the present disclosure is applied to the Flash controller, and the method includes: obtaining a first bus address from a received first control instruction, the first control instruction being a read instruction; determining a Flash memory address corresponding to the first bus address according to a preset address mapping relationship; and obtaining data from a corresponding position in the Flash memory according to the Flash memory address. The embodiment of the present disclosure determines the Flash memory address by using the mapping relationship between the first bus address and the Flash memory address, and can directly read data from the corresponding position of the Flash memory, avoiding the operation of the register, thereby improving the efficiency of reading data from the Flash memory.

[0055] In the related art, a Flash controller can only access a single type of Flash memory. When a system mounts multiple types of Flash memories, multiple Flash controllers are required to match them, resulting in a complex system hardware structure and high cost.

[0056] In order to solve the above problem, in some embodiments of the present disclosure, the Flash controller supports two types of Flash memories. Accordingly, the Flash memory address includes the NOR Flash memory address and the NAND Flash memory address, so that only one Flash controller can be set to match the NOR Flash memory and the NAND Flash memory, thereby simplifying the hardware structure and reducing the cost.

[0057] In some embodiments, the Flash controller further includes a second control module, such as Figure 2 As shown, the Flash control method also includes the following steps:

[0058] Step 21, obtaining a second bus address from a received second control instruction, where the second control instruction is a read instruction or a write instruction.

[0059] In this step, after receiving the read instruction or write instruction, the second control module obtains the second bus address carried therein. The second control module may be an AHB register slave (AHB reg SLV), and the second control module can read and write data in the Flash memory.

[0060] Step 22: Execute a data processing operation corresponding to the second control instruction in a corresponding register according to the second bus address.

[0061] In this step, for read instructions, the second control module reads data from the corresponding position in the register according to the second bus address, and the data is obtained from the Flash memory and cached in the register; for write instructions, the second control module writes the data to be written into the corresponding register according to the second bus address, and then writes the data to be written into the Flash memory.

[0062] In some embodiments, the Flash controller includes a first control module, a second control module and an instruction distribution module. Figure 3 As shown, before receiving the first control instruction and the second control instruction (ie, step 11 and step 21), the Flash control method further includes the following steps:

[0063] Step 31, receiving the control instruction sent by the CPU, and obtaining the bus address carried therein.

[0064] In this step, the instruction distribution module receives the control instruction sent by the CPU and obtains the bus address carried in the control instruction. It should be noted that the instruction distribution module and the CPU can be connected via an AHB bus.

[0065] Step 32, if the bus address is the first bus address, execute step 33; if the bus address is the second bus address, execute step 34.

[0066] In this step, the instruction distribution module determines which control module will process the control instruction based on the bus address. Exemplarily, the instruction distribution is performed based on the address segment of the bus address. If the bus address belongs to the address segment of the first bus address, the control instruction is processed by the first control module, that is, step 33 is executed; if the bus address belongs to the address segment of the second bus, the control instruction is processed by the second control module, that is, step 34 is executed.

[0067] Step 33: Send a first control instruction carrying a first bus address to the first control module.

[0068] In this step, the instruction distribution module encapsulates the first bus address, generates a first control instruction, and sends the first control instruction to the first control module.

[0069] Step 34: Send a second control instruction carrying a second bus address to the second control module.

[0070] In this step, the instruction distribution module encapsulates the second bus address, generates a second control instruction, and sends the second control instruction to the second control module.

[0071] The disclosed embodiment takes into account two Flash control schemes. Not only can the first control module be used to implement data reading, but the second control module can also be used to implement data reading and writing. Users can choose two Flash control schemes, which is more flexible to use.

[0072] In some embodiments, the first control module receives the first control instruction via the AHB bus, and the second control module receives the second control instruction via the AHB bus, so that only one bus is used, saving bus resources.

[0073] In the related art, if a control instruction is received during the Flash memory reset process, the Flash controller will discard the control instruction, resulting in the loss of data processing instructions within the reset time period. To solve the above problem, the embodiment of the present disclosure caches the control instruction received during the Flash memory reset process, and processes the control instruction after the Flash memory reset is completed, thereby avoiding the loss of the control instruction.

[0074] Accordingly, in some embodiments, the step of obtaining the first bus address from the received first control instruction (i.e., step 11) includes the following steps: in response to receiving the first control instruction during the Flash memory reset process, caching the first control instruction, and obtaining the first bus address from the first control instruction after the Flash memory reset is completed.

[0075] In some embodiments, the step of obtaining the second bus address from the received second control instruction (i.e., step 21) includes the following steps: in response to receiving the second control instruction during the Flash memory reset process, caching the second control instruction, and obtaining the second bus address from the second control instruction after the Flash memory reset is completed.

[0076] In some embodiments, the Flash memory is a NOR Flash memory, and the Flash memory reset is completed, including: the NOR Flash memory power-on reset is completed.

[0077] In some embodiments, the Flash memory is a NAND Flash memory, and the Flash memory reset is completed, including: the NAND Flash memory power-on reset is completed and the software reset is completed.

[0078] In some embodiments, the Flash control method may further include the following steps: receiving a clock frequency configuration instruction, and configuring the clock frequency according to the clock frequency configuration instruction. Since different Flash memories have different clock frequencies, the clock frequency can be configured according to the received clock frequency configuration instruction, and the clock division can be adjusted, so that it can be applicable to Flash memories with different clock frequencies.

[0079] In the related art, the Flash controller only supports the operation of one type of Flash memory, and the transmission efficiency is relatively low. For power-on waiting and reset waiting, other power-on reset waiting modules are required to implement. In addition, most Flash controllers only support the operation of Flash memory through registers. The embodiments of the present disclosure have made targeted designs for these problems and completely solved the above problems, providing a more convenient user experience and greatly improving the transmission efficiency.

[0080] Based on the same technical concept, the embodiment of the present disclosure also provides a Flash controller, such as Figure 4 As shown, it includes a first control module 101, a command control module 102 and a sending module 103, and the command control module 102 is connected to the first control module 101 and the sending module 103 respectively.

[0081] The first control module 101 is used to obtain a first bus address from a received first control instruction, where the first control instruction is a read instruction; and determine a Flash memory address corresponding to the first bus address according to a preset address mapping relationship.

[0082] The command control module 102 is used to generate a data query instruction according to the Flash memory address.

[0083] The sending module 103 is used to send the data query instruction to the Flash memory, and after receiving the data sent by the Flash memory, send the data to the first control module, where the data is the data obtained by the Flash memory according to the Flash memory address.

[0084] In some embodiments, the Flash memory address includes a NOR Flash memory address and a NAND Flash memory address.

[0085] In some embodiments, Figure 5 As shown, the Flash controller also includes a second control module 104, which is connected to the command control module 102 and is used to obtain a second bus address from a received second control instruction, where the second control instruction is a read instruction or a write instruction; according to the second bus address, a data processing operation corresponding to the second control instruction is executed in a corresponding register.

[0086] In some embodiments, Figure 6 As shown, the Flash controller also includes an instruction distribution module 105, which is connected to the first control module 101 and the second control module 104, and is used to receive control instructions sent by the central processing unit CPU and obtain the bus address carried therein; in response to the bus address being a first bus address, sending a first control instruction carrying the first bus address to the first control module; in response to the bus address being a second bus address, sending a second control instruction carrying the second bus address to the second control module.

[0087] In some embodiments, the first control module 101 and the second control module 104 are connected to the instruction distribution module 105 via an AHB bus.

[0088] In some embodiments, Figure 7 As shown, the Flash controller further includes a reset control module 106 , which is connected to the first control module 101 and the second control module 104 .

[0089] The first control module is further configured to cache the first control instruction in response to receiving the first control instruction during the resetting process of the Flash memory.

[0090] The second control module is further configured to cache the second control instruction in response to receiving the second control instruction during the resetting process of the Flash memory.

[0091] The reset control module 106 is used to, after the reset of the Flash memory is completed, instruct the first control module to obtain the first bus address from the first control instruction; and / or, after the reset of the Flash memory is completed, to obtain the second bus address from the second control instruction.

[0092] In some embodiments, the first control module 101 includes a cache unit, the bit width of the cache unit is 8-64 bits, and the cache unit is used to cache the data. By increasing the bit width of the cache in the first control module 101, the efficiency of data reading can be improved.

[0093] In some embodiments, the second control module 104 is further configured to receive a clock frequency configuration instruction, and configure the clock frequency according to the clock frequency configuration instruction.

[0094] The Flash controller of the embodiment of the present disclosure is described in detail below with reference to a specific example. Figure 8 As shown, the Flash controller includes: a command distribution module, an AHB register control slave (AHB reg SLV, i.e., a second control module), an AHB slave (AHB SLV, i.e., a first control module), a command control module (Flash cmd exe), an SPI (Serial Peripheral Interface, serial peripheral interface) txrx sending module (i.e., a sending module), and a reset control module (FLASH POWER UP CTRL). Among them, the command distribution module is used to distribute the control commands issued by the CPU to the AHB register control slave or the AHB slave, and the AHB reg SLV module can configure the relevant registers, and after the configuration is successful, send the corresponding data to the Flash memory. The AHB SLV module directly reads the Flash memory through the AHB bus, and directly uses the AHB bus address as the read address of the Flash memory. The FLASH POWER UP CTRL module performs power-on waiting and reset waiting on the Flash memory. The Flash cmd exe module reassembles the received commands into the command format required by the Flash memory. The SPI data sending module interacts with the Flash memory to complete the data reading operation.

[0095] The Flash controller provided in the disclosed embodiment is a fully hardware-implemented SPI Flash controller that supports control of NAND Flash memory and NOR Flash memory, and specifically controls which Flash memory can be directly selected through I / O. The disclosed embodiment supports directly mapping the Flash space to the system space through the AHB protocol, and can also perform various operations on the Flash memory directly through registers. At the same time, this controller supports 1-line, 2-line and 4-line operations on Flash, and the Flash memory can be read directly through the AHB bus after the system is powered on successfully. At the same time, when reading data directly through AHB, it supports 8 DW (Data Warehouse) deep caches, which can greatly improve the efficiency of reading Flash memory.

[0096] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, the functional modules / units in the device may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0097] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A Flash control method, applied to a Flash controller, wherein the Flash controller comprises a first control module, characterized in that: The method comprises: The first control module obtains a first bus address from a received first control instruction, where the first control instruction is a read instruction; Determine the Flash memory address corresponding to the first bus address according to a preset address mapping relationship; According to the Flash memory address, data is acquired from a corresponding position in the Flash memory, the data is cached, and sent to a central processing unit CPU.

2. The method according to claim 1, characterized in that The Flash memory address includes a NOR Flash memory address and a NAND Flash memory address.

3. The method according to claim 1, characterized in that The Flash controller further includes a second control module, and the method further includes: The second control module obtains a second bus address from a received second control instruction, where the second control instruction is a read instruction or a write instruction; According to the second bus address, a data processing operation corresponding to the second control instruction is performed in a corresponding register.

4. The method according to claim 3, characterized in that The Flash controller further includes an instruction distribution module. Before receiving the first control instruction and the second control instruction, the method further includes: The instruction distribution module receives the control instruction sent by the CPU and obtains the bus address carried therein; In response to the bus address being a first bus address, sending a first control instruction carrying the first bus address to the first control module; In response to the bus address being a second bus address, a second control instruction carrying the second bus address is sent to the second control module.

5. The method according to claim 3, characterized in that The Flash controller further includes a reset control module, and the first control module obtains a first bus address from a received first control instruction, including: in response to receiving the first control instruction during the reset process of the Flash memory, the first control module caches the first control instruction, and after the reset of the Flash memory is completed, obtains the first bus address from the first control instruction based on an instruction of the reset control module; and / or, The second control module obtains the second bus address from the received second control instruction, including: in response to receiving the second control instruction during the Flash memory reset process, the second control module caches the second control instruction, and after the Flash memory reset is completed, obtains the second bus address from the second control instruction based on the instruction of the reset control module.

6. The method according to claim 5, characterized in that The Flash memory is a NOR Flash memory, and the Flash memory is reset, comprising: the NOR Flash memory is powered on and reset is completed; The Flash memory is a NAND Flash memory, and the Flash memory is reset, which includes: the NAND Flash memory is powered on and reset and the software is reset.

7. A Flash controller, characterized in that: It includes a first control module, a command control module and a sending module, wherein the command control module is connected to the first control module and the sending module respectively; The first control module is used to obtain a first bus address from a received first control instruction, where the first control instruction is a read instruction; Determine the Flash memory address corresponding to the first bus address according to a preset address mapping relationship; The command control module is used to generate a data query instruction according to the Flash memory address; The sending module is used to send the data query instruction to the Flash memory, and after receiving the data sent by the Flash memory, send the data to the first control module, where the data is the data obtained by the Flash memory according to the Flash memory address; The first control module is further used to cache the data and send it to a central processing unit CPU.

8. The Flash controller according to claim 7, characterized in that: It also includes a second control module, which is connected to the command control module and is used to obtain a second bus address from a received second control instruction, where the second control instruction is a read instruction or a write instruction; According to the second bus address, a data processing operation corresponding to the second control instruction is performed in a corresponding register.

9. The Flash controller according to claim 8, characterized in that: The system further comprises an instruction distribution module, the instruction distribution module being connected to the first control module and the second control module and configured to receive a control instruction sent by the CPU and obtain a bus address carried therein; in response to the bus address being a first bus address, send a first control instruction carrying the first bus address to the first control module; In response to the bus address being a second bus address, a second control instruction carrying the second bus address is sent to the second control module.

10. The Flash controller according to claim 9, characterized in that: The first control module and the second control module are connected to the instruction distribution module via an AHB bus.

11. The Flash controller according to claim 8, characterized in that: It also includes a reset control module, which is connected to the first control module and the second control module; The first control module is used for caching the first control instruction in response to receiving the first control instruction during the resetting process of the Flash memory; The second control module is used for caching the second control instruction in response to receiving the second control instruction during the resetting process of the Flash memory; The reset control module is used to, after the Flash memory is reset, instruct the first control module to obtain the first bus address from the first control instruction; and / or, after the Flash memory is reset, to obtain the second bus address from the second control instruction.

12. The Flash controller according to any one of claims 7 to 11, characterized in that: The first control module includes a cache unit, the bit width of the cache unit is 8-64 bits, and the cache unit is used to cache the data.

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