A deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles

Abstract

The present invention provides a deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles. In addition to controlling the flow rate of the adhesive by temperature control and applying a reasonable amount of adhesive to control the generation of pad bubbles, the wafer is particularly repeatedly pre-vacuumed in a bonding chamber to complete the wafer bubble removal process. At the same time, a low-temperature preheating method is combined to slow down the flow rate of the bonding adhesive under low viscosity conditions to reduce the risk of residual adhesive overflow. In addition, a low-rate step-by-step heating is used to change the traditional one-step heating bonding mode, and the bubble defect rate is basically controlled to be about 0.5%.

Description

Technical Field

[0001] The invention relates to the technical field of advanced electronic packaging, and in particular to a deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles. Background Art

[0002] Integrated circuit technology and the miniaturization and multifunctional integration of electronic devices have promoted the development of micro-electromechanical system technology. Micro-electromechanical systems use advanced semiconductor processes and technologies to integrate machinery, electronics and even systems into a single chip, and have great application prospects in aerospace, information communication, biomedicine and other fields. Stereo integration technology based on through-silicon vias can greatly reduce chip size by making vertical three-dimensional integration, while improving interconnection density and electrical performance. It has broad application prospects, especially in the fields of network big data and memory manufacturing, as well as MEMS systems. It has now become the fourth-generation advanced packaging technology with the most development potential. Among them, permanent wafer bonding is a key technology for realizing three-dimensional stacking and interconnection in three-dimensional electronic packaging. In radio frequency (RF), MEMS, and especially CMOS image sensors, permanent bonding technology reduces the occupied area and greatly improves product performance. Wafer-level adhesive bonding is a type of wafer bonding with an intermediate layer. The quality of the intermediate layer directly determines whether there will be erosion and over-etching in the subsequent process. Existing wafer-level adhesive bonding is mainly based on the traditional technology of preheating the product, then evacuating the vacuum, then increasing the temperature and pressure, then maintaining the temperature and pressure, and finally reducing the temperature and pressure. For products with a wafer Pad depth of less than 1μm, this technology rarely or almost never causes voids and bubbles in the middle layer of permanent bonding adhesive. However, when the wafer Pad is greater than 1μm, the depth of the bonding adhesive flowing into the cavity is increased, which greatly increases the difficulty of controlling the number of bubbles in the Pad, resulting in abnormal product quality and appearance, seriously affecting the product yield.

[0003] The camera module manufactured by wafer-level packaging and integration technology has achieved low-cost integration of small and medium-sized cameras in various handheld devices. However, there are difficulties and challenges in the bonding process between wafer-level packaging glass and CIS wafers. The wafer-level CIS adhesive bonding process is facing the challenges brought by the CIS front-end manufacturing process. In the CIS wafer, the logic chip circuit and the storage circuit are prepared next to and below the photosensitive area, and are led out to the metal pad next to the photosensitive area through metal interconnection lines. The depth of the pad manufactured by different front-end manufacturing processes is also different. According to relevant industry experience, the depth of the pad is generally between 0.5μm and 1μm. Pad wafers with a depth of more than 1μm are usually called deep Pad wafers. The challenge that deep Pad wafers bring to the adhesive bonding process is that the bonding glue cannot be fully filled into the pit where the Pad is located within the limited bonding time before the glue is cured. After the bonding glue around the Pad is cured, a cavity is generated near the Pad area, which is the so-called glue bubble. These bubbles will affect the subsequent process, that is, cause the solution to penetrate into the pad through the cavity bubbles, causing pad corrosion, thus affecting the device characteristics. Currently, there is no good solution for the bubble control of such deep pads in the industry.

[0004] The existing technology aims to solve the problem of Pad bubbles generated in the WLCSP adhesive bonding process without causing yield loss, and improve the bonding quality and reliability. The process optimization is mainly carried out from three aspects: the viscosity of the bonding glue, the bonding temperature and the time. Generally, the bonding glue is a resin compound. This bonding glue is divided into two parts, A and B. When used, A and B are vacuum mixed to form a gel polymer with a certain viscosity. The viscosity of this glue is affected by both the standing waiting time and the temperature. The viscosity of this mixed polymer can be reflected by its flow rate. The greater the flow rate, the lower the viscosity, and vice versa. In general, the flow rate of the glue decreases with the extension of the standing time, reflecting that the viscosity decreases with the extension of the standing time. At the same time, the viscosity of this glue is also affected by temperature. It is determined that the viscosity of this glue increases with the increase of temperature. When it reaches 70°C, the fluidity and activity reach the highest, and it gradually begins to solidify at 70°C-80°C. At 90°C, it completely loses its fluidity and achieves preliminary solidification. This solidification is an irreversible chemical change and is completely solidified when it reaches 150°C. During the bonding process, the cofferdam glass 12 coated with the bonding adhesive layer 11 is at the bottom, and the CIS wafer layer 1 is at the top. During the bonding process, the bonding adhesive on the cofferdam glass is mainly affected by the temperature of the lower plate of the bonding machine. Figure 1As shown; Generally speaking, by regulating the fluidity of the bonding glue, the bonding glue layer 11 can flow into the pit where the CIS wafer layer 1Pad is located, fully filling the pit where the CIS wafer 1Pad is located, and the generation of Pad bubbles can be avoided after curing; however, if the flow rate of the glue is too high, the glue on the entire cofferdam will flow into the photosensitive area of ​​the CIS wafer layer 1 (this defect is called overflow glue, and it will be replaced by overflow glue below), as shown Figure 2 This abnormality affects the imaging of the CIS chip and causes yield loss. Therefore, the generation of Pad bubbles cannot be reduced by simply increasing the glue flow rate. The adverse losses caused by excessive glue flow rate can be suppressed by reducing the amount of glue, but too little glue can easily lead to the generation of cavities with or without glue after wafer glass bonding, which can easily cause cracks in the glass or wafer during subsequent processing and also cause yield loss. At the same time, due to the deeper Pad, the flow rate of the glue is difficult to control, resulting in more bubbles and difficult to control. Tracking the bubble defect rate of 200 traditional glue-bonded products, it is about 20%-40%. Summary of the invention

[0005] In view of the problem in the prior art that when the wafer Pad is larger than 1μm, the difficulty in controlling the number of Pad bubbles increases due to the increased depth of the bonding glue flowing into the cavity. The present invention provides a deep pad wafer-level preparation method for eliminating wafer-level adhesive bonding bubbles, which effectively reduces the bubbles in the deep pad wafer and ensures the product yield.

[0006] The present invention is achieved through the following technical solutions:

[0007] A deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles comprises the following steps:

[0008] Step 1, placing a substrate on the CIS wafer layer, and aligning the two sides of the substrate with the metal pad layer of the cutting path on both sides of the CIS wafer layer, and forming a cofferdam layer with a height and a bonding adhesive layer on the substrate in sequence along the direction from the substrate to the CIS wafer layer to obtain a CIS wafer chip; wherein the bonding adhesive layer is aligned with the metal pad layer to form a bonding chamber;

[0009] Step 2, evacuate the bonding chamber for the first time, so that the bonding chamber is in a high vacuum state, and at the same time, the bubbles in the CIS wafer chip are extracted, and the CIS wafer chip is in a vacuum state; after the vacuum is broken, the inside of the bonding chamber is under atmospheric pressure, and after the CIS wafer chip is in a vacuum state, the pressure difference between the inside and outside squeezes out the residual bubbles in the CIS wafer core;

[0010] Step 3, vacuuming the bonding chamber for the second time to remove the residual bubbles squeezed out from the inside of the CIS wafer core, thus completing the bubble removal process;

[0011] Step 4, combined with low-temperature preheating, makes the glue of the bonding layer flow slower into the metal Pad layer under low viscosity conditions to offset the residual glue caused by the pressure difference after breaking the vacuum, and cooperates with low-rate step-by-step heating to achieve solidification; at the same time, while low-temperature preheating is performed in the metal Pad layer to reduce residual glue, overflow glue, and low-rate step-by-step heating is performed, vacuuming is continued until the bubbles in the metal Pad layer are extracted by vacuum to obtain a CIS wafer chip with a wafer-level adhesive bonding structure.

[0012] Preferably, in step 1, the surface of the CIS wafer layer uses several materials to form a composite structure surface, including the surface of an integrated circuit chip, a silicon substrate surface, a ceramic substrate surface and a glass substrate surface, wherein the middle portion of the CIS wafer layer is a photosensitive area for placing logic chip circuits and storage circuits, wherein the logic chip circuits and storage circuits are led out to the metal Pad layer on both sides of the photosensitive area through metal interconnection lines, and the outer side of the metal Pad layer is a cutting path.

[0013] Preferably, the material of the metal Pad layer is gold, copper, aluminum, nickel or a metal alloy material.

[0014] Preferably, the depth of the metal Pad layer is greater than 1 μm.

[0015] Preferably, the material of the substrate is a carrier glass sheet or a transparent glass-like sheet, wherein the size and shape of the substrate corresponds to the size and shape of the CIS wafer layer.

[0016] Preferably, the substrate is patterned using photolithography technology and photoresist to produce a dam layer of sufficient height, and then a bonding glue is printed on the dam layer by manual glue rolling technology or screen printing glue technology, i.e., a bonding glue layer.

[0017] Preferably, in step 4, the low temperature ranges from 15 to 35°C.

[0018] Preferably, in step 4, the low-rate step range is: the first step temperature rise rate is 20°C / min; the second step temperature rise rate is 45°C / min.

[0019] Compared with the prior art, the present invention has the following beneficial technical effects:

[0020] The present invention provides a deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles. In addition to controlling the generation of pad bubbles by controlling the flow rate of the adhesive through temperature control and applying a reasonable amount of adhesive, in particular, the wafer is repeatedly pre-vacuumed in a bonding chamber to complete the wafer bubble removal process. At the same time, a low-temperature preheating method is combined to slow down the flow rate of the bonding adhesive under low viscosity conditions to reduce the risk of residual adhesive overflow. In addition, a low-rate step-by-step heating is used to change the traditional one-step heating bonding mode, and the bubble defect rate is basically controlled to be about 5%.

[0021] Furthermore, the present invention effectively solves the problems of high defect rate of bubbles and poor process stability. It reduces the difficulty of process control and improves the process yield. This method is more effective for deep pad products (≥1um) and provides a new solution for subsequent bonding bubbles of deeper pad products. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the depth structure of CIS wafer Pad in the prior art;

[0023] Figure 2 It is a schematic diagram of a wafer-level adhesive bonding pre-alignment structure in the prior art;

[0024] Figure 3 It is a schematic diagram of the wafer-level adhesive bonding pre-alignment structure in the present invention.

[0025] In the figure: 1-CIS wafer layer; 11-metal pad layer; 12-cutting road; 13-photosensitive area; 2-substrate; 21-dam layer; 22-bonding adhesive layer. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0029] In one embodiment of the present invention, a deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles is provided, which effectively reduces bubbles in the deep pad wafer and ensures the yield of the product.

[0030] Specifically, the deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles comprises the following steps:

[0031] Step 1, placing a substrate 2 on a CIS wafer layer 1, and aligning the two sides of the substrate 2 with the metal pad layer 11 of the cutting path 12 on both sides of the CIS wafer layer 1, and sequentially forming a cofferdam layer 21 with a height and a bonding adhesive layer 22 on the substrate 2 in the direction from the substrate 2 to the CIS wafer layer 1, to obtain a CIS wafer chip; wherein the bonding adhesive layer 22 is aligned with the metal pad layer to form a bonding chamber;

[0032] Step 2, evacuate the bonding chamber for the first time, so that the bonding chamber is in a high vacuum state, and at the same time, the bubbles in the CIS wafer chip are extracted, and the CIS wafer chip is in a vacuum state; after the vacuum is broken, the inside of the bonding chamber is under atmospheric pressure, and after the CIS wafer chip is in a vacuum state, the pressure difference between the inside and outside squeezes out the residual bubbles in the CIS wafer core;

[0033] Step 3, vacuuming the bonding chamber for the second time to remove the residual bubbles squeezed out from the inside of the CIS wafer core, thus completing the bubble removal process;

[0034] Step 4, combined with low-temperature preheating, makes the glue of the bonding adhesive layer 22 flow slowly into the metal Pad layer 11 under low viscosity conditions to offset the residual glue caused by the pressure difference after breaking the vacuum, wherein the low temperature temperature range is 15-35°C; and cooperates with low-rate step-by-step heating to achieve solidification, wherein the low-rate step-by-step range is: the first step temperature rise rate is 20°C / min; the second step temperature rise rate is 45°C / min; at the same time, low-temperature preheating is performed in the metal Pad layer 11 to reduce residual glue, overflow glue, and low-rate step-by-step heating is performed while continuing to evacuate the metal Pad layer 11 until the bubbles in the metal Pad layer 11 are extracted by vacuum to obtain a CIS wafer chip with a wafer-level adhesive bonding structure.

[0035] Specifically, in step 1, the surface of the CIS wafer layer 1 is composed of several materials to form a composite structure surface, including the surface of an integrated circuit chip, a silicon substrate surface, a ceramic substrate surface and a glass substrate surface. The surface of the CIS wafer layer 1 is preferably a flat surface, and the tolerance of the surface unevenness is the surface unevenness allowed by the wafer process. The middle part of the CIS wafer layer 1 is a photosensitive area 13 for placing logic chip circuits and storage circuits, wherein the logic chip circuits and storage circuits are led out to the metal Pad layer 11 on both sides of the photosensitive area 13 through metal interconnect lines, and the outer side of the metal Pad layer 11 is a cutting path 12, such as Figure 1As shown, the shape of the CIS wafer layer 1 can be a round piece, a square piece or a rectangular piece.

[0036] Specifically, the material of the metal Pad layer 11 is a metal or metal alloy material such as gold, copper, aluminum, nickel, etc., wherein the depth of the metal Pad layer 11 is greater than 1 μm.

[0037] Specifically, the material of the substrate 2 is a carrier glass sheet or a transparent glass-like sheet, and its thickness is not limited, and can be 300 μm, 400 μm, 700 μm, etc.; wherein the size and shape of the substrate 2 corresponds to the size and shape of the CIS wafer layer.

[0038] After the substrate 2 is cleaned, in order to prevent the exposed surface from being scratched or contaminated, a protective film can be applied to the back. The protective film used can be a blue film or a yellow film, but is not limited thereto. As long as it is corrosion-resistant, high-temperature-resistant, and not prone to wrinkling, it can be used. Then, according to the size of the corresponding photosensitive area 13 of the CIS wafer layer 1, the substrate 2 is patterned using photolithography technology and photoresist to produce a cofferdam layer 21 of sufficient height; then, the bonding glue is printed on the cofferdam layer 21 using manual glue rolling technology or screen printing glue technology, i.e., the bonding glue layer 22, such as Figure 2 As shown, the main component of the bonding adhesive layer 22 is an epoxy resin compound. The epoxy resin compound can be cured into a rubber-like solid at room temperature or higher, which can provide a bond with excellent flexibility and chemical resistance. These adhesives can be well bonded to many substrates, have strong peel resistance, high shear strength and excellent low-temperature performance, and can work for a long time under certain temperature and humidity conditions. The WLCSP packaging structure stacks a substrate 2 with a cofferdam pattern cavity wall onto the device wafer 1. The covered substrate 2 has two main functions: ① as a window for image processing, ② to protect the image sensing area from particles during the back TSV and WLCSP process.

[0039] Specifically, in order to stack the substrate 2 onto the CIS wafer layer 1, a thermosetting polymer is generally used to bond the CIS wafer layer 1 and the substrate 2 with the dam layer 22, wherein the dam layer 22 on the surface of the substrate 2 may or may not be composed of the same material as the adhesive material for achieving bonding.

[0040] The bonding process needs to be completed in a high vacuum environment. The high vacuum environment can not only promote the discharge of bubbles in the pits of the metal pad layer 11, but also prevent the occurrence of other additional chemical reactions during the bonding process. For the CIS wafer layer 1, a single vacuum pumping cannot completely remove the pad bubbles. Therefore, multiple vacuum pumping is particularly important in the deep pad bonding process. Figure 3 shown.

[0041] The present invention makes a breakthrough in deep pad wafer bonding process from two aspects: bonding adhesive viscosity and vacuum conditions. The invention seeks a suitable adhesive volume window, a static time window, and a temperature window to assist in completing the deep pad wafer bonding process breakthrough under multiple high vacuum conditions, reduces and eliminates the generation of pad bubbles without affecting the yield after bonding, and improves the bonding quality and reliability.

[0042] Before the silicon wafer is thinned to an appropriate thickness, the front side of the CIS wafer layer 1 must be bonded to the dam layer 22 of the carrier glass 2 to provide sufficient mechanical strength during and after the back side thinning. WLCSP wafer bonding can provide a suitable controlled bubble bonding process, flipping the CIS wafer layer 1 upside down and bonding it to the transparent optical glass 1 with the dam layer 22, thinning the bonded CIS wafer layer 1 and preparing TSV interconnection holes on the back side, coating a photosensitive organic insulating layer to replace the silicon oxide layer before copper plating, preparing a copper interconnection line photolithography pattern on the insulating layer, and then preparing copper interconnection wires and flip-chip solder balls to complete the WLCSP packaging of the CIS wafer layer 1, and subsequently completing the preparation of a single CIS wafer chip through dicing and sorting.

[0043] In summary, the present invention provides a deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles. In addition to controlling the generation of Pad bubbles by controlling the flow rate of the glue through temperature control and applying a reasonable amount of glue, the wafer is particularly repeatedly pre-vacuumed in a bonding chamber to complete the wafer bubble removal process. At the same time, the low-temperature preheating method is combined to slow down the flow rate of the bonding glue under low viscosity conditions to reduce the risk of residual glue overflow, and the low-rate step-by-step heating is used to change the traditional one-step heating bonding mode, and the bubble defect rate is basically controlled, which is basically 0.5%. The present invention effectively solves the problems of high defect rate of bubbles and poor process stability. It reduces the difficulty of process control and improves the process yield. Especially for deep Pad products (≥1um), this method is more effective and provides a new solution for subsequent deeper pad product bonding bubbles.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles, characterized in that: The steps include: Step 1, placing a substrate (2) on a CIS wafer layer (1) in correspondence, with both sides of the substrate (2) respectively aligned with the metal pad layer (11) of the cutting paths (12) on both sides of the CIS wafer layer (1), and sequentially forming a dam layer (21) with a height and a bonding adhesive layer (22) on the substrate (2) in a direction from the substrate (2) to the CIS wafer layer (1), to obtain a CIS wafer chip; wherein the bonding adhesive layer (22) is aligned with the metal pad layer to form a bonding chamber; Step 2, evacuate the bonding chamber for the first time, so that the bonding chamber is in a high vacuum state, and at the same time, the bubbles in the CIS wafer chip are extracted, and the CIS wafer chip is in a vacuum state; after the vacuum is broken, the inside of the bonding chamber is under atmospheric pressure, and after the CIS wafer chip is in a vacuum state, the pressure difference between the inside and outside squeezes out the residual bubbles in the CIS wafer core; Step 3, vacuuming the bonding chamber for the second time to remove the residual bubbles squeezed out from the inside of the CIS wafer core, thus completing the bubble removal process; Step 4, combining low-temperature preheating to slow down the flow rate of the glue of the bonding adhesive layer (22) into the metal pad layer (11) under low viscosity conditions, so as to offset the residual glue caused by the pressure difference after breaking the vacuum, and to achieve solidification by low-speed step-by-step heating; while low-temperature preheating is performed in the metal pad layer (11) to reduce residual glue and overflow glue, and low-speed step-by-step heating is performed, vacuuming is continued until the bubbles in the metal pad layer (11) are vacuumed out to obtain a CIS wafer chip with a wafer-level adhesive bonding structure; The temperature range of low temperature is 15-35℃; The low-rate step range is: the first step temperature rise rate is 20°C / min; the second step temperature rise rate is 45°C / min.

2. A deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles according to claim 1, characterized in that: In step 1, the surface of the CIS wafer layer (1) is formed of a composite structure surface using a plurality of materials, including an integrated circuit chip surface, a silicon substrate surface, a ceramic substrate surface, and a glass substrate surface, wherein the middle portion of the CIS wafer layer (1) is a photosensitive area (13) for placing a logic chip circuit and a storage circuit, wherein the logic chip circuit and the storage circuit are led out to the metal pad layer (11) on both sides of the photosensitive area (13) through metal interconnection lines, and the outer side of the metal pad layer (11) is a cutting path (12).

3. A deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles according to claim 1, characterized in that: The material of the metal Pad layer (11) is gold, copper, aluminum, nickel or a metal alloy material.

4. A deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles according to claim 1, characterized in that: The depth of the metal pad layer (11) is greater than 1 μm.

5. The deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles according to claim 1, characterized in that: The material of the substrate (2) is a carrier glass sheet or a transparent glass-like sheet, wherein the size and shape of the substrate (2) corresponds to the size and shape of the CIS wafer layer.

6. A deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles according to claim 1, characterized in that: The substrate (2) is patterned using photolithography technology and photoresist to produce a dam layer (21) of a desired height, and then a bonding adhesive is printed on the dam layer (21) using a manual adhesive rolling technique or a screen printing technique, i.e. a bonding adhesive layer (22).

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