Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region extending along a first lateral direction and including a plurality of first epitaxial structures. The semiconductor device includes an interconnect structure extending along the first lateral direction and disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion offset relative to the first active region along a second lateral direction perpendicular to the first lateral direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. In semiconductor IC design, the standard cell approach is typically used to design semiconductor devices on a single chip. The standard cell approach uses standard cells as abstract representations of certain functions to integrate millions or billions of devices onto a single chip. As ICs continue to shrink, more and more devices are integrated onto a single chip. This shrinkage process typically provides benefits by increasing production efficiency and reducing associated costs. Summary of the Invention

[0003] A first aspect of this disclosure relates to a semiconductor device comprising: a first active region extending along a first lateral direction and including a plurality of first epitaxial structures; and an interconnect structure extending along the first lateral direction and disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure; wherein the interconnect structure includes at least a first portion offset relative to the first active region along a second lateral direction perpendicular to the first lateral direction.

[0004] A second aspect of this disclosure relates to a semiconductor device comprising: a plurality of first source / drain structures laterally disposed along a first lateral direction, wherein the plurality of first source / drain structures are separated from each other by a plurality of first gate structures, the plurality of first gate structures extending along a second lateral direction perpendicular to the first lateral direction; and an interconnect structure extending along the first lateral direction and disposed below the plurality of first source / drain structures; wherein at least one of the plurality of first source / drain structures extends beyond a first sidewall of the interconnect structure along the second lateral direction.

[0005] A third aspect of this disclosure relates to a method for testing a semiconductor device, comprising: forming a plurality of transistors on a first side of a semiconductor substrate, wherein the plurality of transistors includes a plurality of source / drain structures; electrically coupling the plurality of transistors to each other by forming a plurality of first interconnect structures on the first side; and forming a second interconnect structure on a second side of the semiconductor substrate opposite to the first side, wherein the second interconnect structure includes portions exposing at least some of the source / drain structures, and no metal structure is disposed between the source / drain structures. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 Semiconductor devices being tested under a tester according to some embodiments are shown.

[0008] Figure 2A The illustration includes, according to some embodiments Figure 1 Example layout design of semiconductor devices.

[0009] Figure 2B Illustrations are shown according to some embodiments Figure 2A A cross-sectional view at line A-A'.

[0010] Figure 3A The illustration includes, according to some embodiments Figure 1 Example layout design of semiconductor devices.

[0011] Figure 3B Illustrations are shown according to some embodiments Figure 3A A cross-sectional view at line A-A'.

[0012] Figure 4A The illustration includes, according to some embodiments Figure 1 Another example of a layout design for semiconductor devices.

[0013] Figure 4B and Figure 4C Each illustrates a particular embodiment. Figure 4A A cross-sectional view at line A-A'.

[0014] Figure 5 A perspective view of a gate-all-around (GAA) field-effect transistor (FET) device according to some embodiments is shown.

[0015] Figure 6 A flowchart illustrating an example method for fabricating a nonplanar transistor device including an interconnect structure, according to some embodiments, is shown.

[0016] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 20E and Figure 20F The passage according to some embodiments is shown. Figure 6 Cross-sectional views of example semiconductor devices manufactured using this method during various manufacturing stages.

[0017] Figure 21 The use of a tester to inspect according to some embodiments is illustrated. Figure 6 A flowchart of an example method for semiconductor devices. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0020] This disclosure provides various embodiments of semiconductor structures and methods of fabrication thereof. The semiconductor structures include gate-all-around (GAA) field-effect transistor (FET) structures that allow a back power rail to be electrically coupled to its source and / or drain. Typically, the back power rail is formed on the back side of the wafer to reduce the standard cell height of the semiconductor device. However, this presents problems when performing fault analysis on the semiconductor device. This is because the metal layer of the back power rail may absorb signals (e.g., electrons, light, etc.) present at the source and / or drain of the GAA FET. These signals are typically used to detect defects in the GAA FET and various interconnect structures formed on the front side of the wafer, such as electrical short circuits / open circuits. In this disclosure, the back metal of the back power rail is at least partially offset relative to the active regions (e.g., source, drain) of one or more GAA transistors. In other words, the back power rail does not overlap with the active regions, such that signals present on the active regions are not absorbed by any of the back metal. This provides an advantage in fault analysis using testers that detect signals present on (e.g., emanating from) the active regions.

[0021] Figure 1 A semiconductor device 100 is shown being tested under a tester 102 according to some embodiments. The semiconductor device 100 includes multiple layers that are formed and / or deposited to form devices such as transistors, capacitors, wires, coils, etc. In the development of the semiconductor device, there is a front-end-of-line (FEOL) process, in which semiconductor devices such as transistors, capacitors, etc., are formed on a first side (e.g., commonly referred to as the front side) of the semiconductor device 100. There is a first back-end-of-line (BEOL) process, in which a plurality of metal interconnect structures are formed on the front side over transistors. Furthermore, there is a second BEOL process, in which a plurality of metal interconnect structures are formed on a second side (e.g., commonly referred to as the back side) of the semiconductor device 100. This provides a reduction in standard cell height and continuous scaling in accordance with Moore's Law.

[0022] For example, in Figure 1 In the semiconductor device 100, a plurality of GAA transistors 104 are formed on the front side, each GAA transistor 104 including a plurality of channel layers, the ends of which are coupled to a source / drain structure. Details of the GAA transistors will be discussed in more detail below (e.g., Figures 5 to 20FOn the front side, the semiconductor device 100 also includes a plurality of interconnect structures 106 coupled (e.g., electrically and physically coupled) to one or more GAA transistors 104. The interconnect structures 106 are typically formed of metal and are therefore sometimes referred to as front-side metal. Furthermore, the semiconductor device 100 includes a plurality of interconnect structures 108 formed on the back side, which are coupled (e.g., electrically and physically coupled) to one or more GAA transistors 104. The interconnect structures 108 are typically formed of metal and are therefore sometimes referred to as back-side metal. Such interconnect structures 108 include structures that carry a supply voltage (e.g., V). DD V SS One or more rear power rails, which will be discussed below.

[0023] The use of test apparatus 102 may involve positioning test apparatus 112 facing the back side of semiconductor device 100. Test apparatus 112 may be, for example, a microscope, such as a photon microscope (e.g., emission microscopy (EMMI)), an electron beam microscope (e.g., electron beam irradiation microscopy (EBI)), or a laser scanning microscope (e.g., a scanning microscope using beam-induced resistance change (OBIRCH)). Testing may include applying an electrical signal through the topmost front interconnect layer and detecting a signal using test apparatus 112, which may include, for example, photons and / or electrons passing through semiconductor device 100, such as secondary electrons. If no undesired events or problems are observed (e.g., unwanted electrical open circuits and / or short circuits) or if some undesired events or problems are within a predefined threshold, then semiconductor device 100 (or any component thereof, such as transistors, wires, interconnect structures, etc.) passes the test.

[0024] In some embodiments, the test apparatus 112 may be an EMMI (Emission Microscope). An EMMI microscope can perform emission microscopy analysis, which can be a highly efficient optical analysis technique for detecting and locating certain integrated circuit (IC) faults. Emission microscopy is non-invasive and can be operated from either the front or back of a semiconductor device. For example, many defects in an IC can cause weak light emission in the visible and near-infrared (IR) spectra. An EMMI microscope may include a sensitive camera to view and capture these light emissions, allowing the apparatus to detect and locate certain IC defects. Since the emission can be detected from the back, the EMMI microscope may also include a laser (e.g., an IR laser) to create a superimposed image of the circuit. This allows faults to be directly correlated with circuit features, accelerating fault resolution. A typical EMMI photograph may include a superimposed image of two images: the circuit and the emission point. For clarity, each image may be arbitrarily colored in a different manner.

[0025] Although not in Figure 1As shown in the cross-sectional view, the transistor 104 in the semiconductor device 100 includes an active region with channels that become conductive when the transistor is turned on. In the prior art, this active region overlaps with the back power rails of the interconnect structure 108, which can lead to various analytical problems as described above. In this disclosure, the back power rails are formed (e.g., patterned) so as not to overlap with the active region, i.e., exposing the main portion of the active region. Therefore, when the tester 102 is used to test for defects in the transistor, the back power rails do not absorb any signals emitted or generated by the active region during the test. As will be discussed in further detail below, when the semiconductor device 100 is tested, the test apparatus 112 can collect signals 110 (e.g., light, electrons, etc.) so that the user can accurately assess whether any defects (e.g., electrical open circuits or short circuits) are present in the semiconductor device 100.

[0026] refer to Figure 2A According to some embodiments, an example layout layer 200 for forming a semiconductor device is shown. Such a semiconductor device can be part of a semiconductor device 100 that can be tested without the aforementioned analytical problems, such as Figure 1 As shown. For simplicity, various layout layers have been omitted. Figure 2A The layout can correspond to a scan D flip-flop circuit, or a D flip-flop circuit with a scan input (hereinafter referred to as an "SDF" circuit). For example, in Figure 2A In this example, layout layer 200 includes multiple patterns of active regions, gates, and interconnect structures to form an SDF circuit. Example layout layer 200 includes top row transistors 250 and bottom row transistors 260, which are electrically connected to each other and formed on a V... DD and V SS Between. The semiconductor device corresponding to layout layer 200 can be formed by GAA transistors, but the disclosed technology is not limited thereto. For example, the disclosed technology can be applied to planar transistors and other three-dimensional devices such as FinFET devices, while still within the scope of this disclosure.

[0027] Example layout layer 200 includes an active region 202, a back via 204, a back metal 206, and a gate 208. In various embodiments, the active region 202 and the gate 208 are formed on the front side of the substrate, while the back via 204 and the back metal 206 are formed on the back side opposite to the front side.

[0028] Active region 202 is where a conductive channel overlapping with gate 208, as well as source and drain structures, are formed. Active region 202 includes source / drain region 220A of top row transistor 250 and source / drain region 220B of bottom row transistor 260. Source / drain regions 220A and 220B are electrically connected to each other via intermediate interconnect structure 230.

[0029] The back metal 206 extends in the x-direction. In some embodiments, the back metal 206 is configured to carry a power supply voltage, such as V. DD or V SS Therefore, the back metal 206 is sometimes referred to as the back power rail. The back metal 206 is patterned so that it does not overlap with portions of the active region 202. For example, referring to example layout layer 200, the back metal 206 includes a plurality of protrusions extending in the y-direction and overlapping the active region 202. For example, the back metal 206 overlaps with the active region 202 where a back via 204 is also present. Referring to example layout layer 200, the back metal 206 includes protrusions 210A and 210B formed at opposite ends. Protrusions 210A and 210B allow the back metal 206 to have a bone-shaped profile. The back metal 206 may include other protrusions, such as protrusions 210C and 210D. Thus, as... Figure 2A As shown, the protrusions do not necessarily form a bone-like profile, and the back metal 206 may have protrusions on only one side and / or protrusions of different lengths.

[0030] Furthermore, although the back metal 206 is shown to overlap (e.g., the center) with some portions of the source / drain regions 220A and 220B (source / drain structures 212 and 222) in the z-direction, the embodiment is not limited to this. For example, depending on the embodiment and design, the back metal 206 may not overlap with the center portion of one or both of the source / drain regions 220A and 220B (source / drain structures 212 and 222). In this example, the source / drain regions 220A and 220B on both sides, as well as the source / drain structures 212 and 222, are n-doped. However, the embodiment is not limited to this, and both sides may be p-doped or have different doping. In other words, one side may be n-doped while the other side may be p-doped.

[0031] refer to Figure 2B According to some embodiments, line A-A' is shown. Figure 2A The example layout layer 200 is shown in the cross-sectional view at (). For simplicity, the individual layers are omitted. See the reference above. Figure 2A The cross-section under discussion includes source / drain regions from two different transistors (e.g., source / drain region 220A and source / drain region 220B). An n-type source / drain structure 212 corresponds to source / drain region 220A, and an n-type source / drain structure 222 corresponds to source / drain region 220B.

[0032] Spacers 218 are formed around the back via 214 except where the back metal 206 contacts the back via 214. Therefore, the n-type source / drain structures 212 and 222, the back via 214, and the back metal 206 are all electrically coupled to each other. Since the back metal 206 is still electrically coupled to the n-type source / drain structures 212 and 222, the back power rail can still power semiconductor devices (e.g., transistors including the n-type source / drain structures 212 and 222) through the back via 214. In this way, the SDF circuit formed using the example layout layer 200 can be tested for fault analysis with greater accuracy using the tester 102 because no unwanted signals are absorbed by the back metal 206, and the back metal 206 does not overlap with the active region 202 in the portion of the active region 202 without the back vias 204 / 214.

[0033] refer to Figure 3A According to some embodiments, an example layout layer 300 of a semiconductor device is shown. Such a semiconductor device can be part of a semiconductor device 100 that can be tested without the aforementioned analytical problems, such as Figure 1 As shown. For simplicity, various layout layers have been omitted. Figure 3A Layout layer 300 can correspond to an SDF circuit. For example, in Figure 3A In the example layout layer 300, multiple patterns of active regions, gates, and interconnect structures are included to form an SDF circuit. The example layout layer 300 includes top row transistors 350 and bottom row transistors 360, which are electrically connected to each other and formed on a V... DD and V SS Between. The semiconductor device corresponding to layout layer 300 can be formed by GAA transistors, but the disclosed technology is not limited thereto. For example, the disclosed technology can be applied to planar transistors and other three-dimensional devices such as FinFET devices, while still within the scope of this disclosure.

[0034] Example layout layer 300 includes an active region 302, a back via 304, a back metal 306, and a gate 308. The active region 302 is where a conductive channel overlapping the gate 308 is formed, as well as source and drain structures. Furthermore, dashed line 340 shows that spacers are opened to allow the back via 304 to connect to the back metal 306 (see [link]). Figure 3B The location of the active region 302 and the gate 308 is shown in various embodiments. The active region 302 and the gate 308 are formed on the front side of the substrate, while the back via 304 and the back metal 306 are formed on the back side opposite to the front side.

[0035] The active region 302 includes the source / drain region 320A of the top row transistor 350 and the source / drain region 320B of the bottom row transistor 360. The source / drain regions 320A and 320B are electrically connected to each other through an intermediate interconnect structure 330.

[0036] The back metal 306 extends in the x-direction. In some embodiments, the back metal 306 is configured to carry a power supply voltage, such as V. DD or V SS Therefore, the back metal 306 can sometimes be referred to as the back power rail. The back metal 306 is patterned so that it does not overlap with the active region 302 and does not form protrusions that overlap with the back via 304. Therefore, unlike the back metal 206 of layer 200, the back metal 306 is substantially rectangular. However, embodiments are not limited to this, and the back metal 306 can have protrusions of different shapes and sizes that overlap with the back via 304. Thus, the back metal 304 can have a bone-like profile.

[0037] refer to Figure 3B According to some embodiments, line A-A' is shown. Figure 3A The example layout layer 300 is shown in the cross-sectional view at (). For simplicity, the individual layers are omitted. See the reference above. Figure 3A The cross-section under discussion includes source / drain regions from two different transistors (e.g., source / drain region 320A and source / drain region 320B). n-type source / drain structure 312 corresponds to source / drain region 320A, and n-type source / drain structure 322 corresponds to source / drain region 320B.

[0038] Spacers 318 are formed around the back via 314 except where the back metal 306 contacts the back via 314. Therefore, the p-type source / drain structures 312 and 322, the back via 314, and the back metal 306 are all electrically coupled to each other. Since the back metal 306 is still electrically coupled to the p-type source / drain structures 312 and 322, the user can still power semiconductor devices (e.g., transistors including p-type source / drain structures 312 and 322) using the back power rails via the back via 314. Therefore, the user can use the tester 102 to perform fault analysis on the SDF circuit formed using the example layout layer 300 with greater accuracy because no unwanted signals are absorbed by the back metal 306, and the back metal 306 does not overlap with the active region 302 in the portion of the active region 302 without the back vias 304 / 314.

[0039] Furthermore, although it is shown that the back metal 306 does not overlap with the central portions of the source / drain regions 320A and 320B (source / drain structures 312 and 322) in the z-direction, the embodiment is not limited to this. For example, depending on the embodiment and design, the back metal 306 may overlap with the central portions of one or both of the source / drain regions 320A and 320B (source / drain structures 312 and 322). In such an embodiment, the spacer 318 will be formed so as not to overlap with the central portions of the source / drain regions 320A and 320B (source / drain structures 312 and 322) in the z-direction. In this example, the source / drain regions 320A and 320B on both sides, as well as the source / drain structures 312 and 322, are p-doped. However, the embodiment is not limited to this, and the two sides may be n-doped or have different doping. In other words, one side may be n-doped and the other side may be p-doped.

[0040] refer to Figure 4A According to some embodiments, an example layout layer 400 for forming a semiconductor device is shown. Such a semiconductor device can be part of a semiconductor device 100 that can be tested without the aforementioned analytical problems, such as Figure 1 As shown. For simplicity, various layout layers have been omitted. Figure 4A The layout can correspond to an AND-OR-Invert circuit (hereinafter referred to as an "AOI" circuit). For example, in Figure 4A In this example, layout layer 400 includes multiple patterns of active regions, gates, and interconnect structures to form an AOI circuit. Example layout layer 400 includes elements electrically connected to each other and formed on a V... DD and V SS A row of transistors between the layers. The semiconductor device corresponding to layout layer 400 can be formed by GAA transistors, but the disclosed technology is not limited thereto. For example, the disclosed technology can be applied to planar transistors as well as other three-dimensional devices such as FinFET devices, while still within the scope of this disclosure.

[0041] Example layout layer 400 includes an active region 402, a back via 404, a back metal 406, and a gate 408. The active region 402 is where a conductive channel overlapping the gate 408 is formed, as well as source and drain structures. Furthermore, dashed line 440 shows that spacers are opened to allow the back via 404 to connect to the back metal 406 (see [link]). Figure 4B and Figure 4C The location of the active region 402 and the gate 408 is shown in various embodiments. The active region 402 and the gate 408 are formed on the front side of the substrate, while the back via 404 and the back metal 406 are formed on the back side opposite to the front side.

[0042] The active region 402 includes source / drain regions 420A and 420B, and source / drain regions 422A and 422B. Source / drain regions 420A and 420B include the source and drain of a p-type transistor, and source / drain regions 422A and 422B include the source and drain of an n-type transistor.

[0043] The back metal 406 extends in the x-direction. In some embodiments, the back metal 306 is configured to carry a power supply voltage, such as V. DD or V SS Therefore, the back metal 306 can sometimes be referred to as the back power rail. The back metal 406 is patterned so that it does not overlap with the active region 402 and does not form protrusions that overlap with the back via 404. Therefore, unlike the back metal 206 of layer 200, the back metal 406 is substantially rectangular. However, embodiments are not limited to this, and the back metal 406 can have protrusions of different shapes and sizes that overlap with the back via 404. Thus, the back metal 404 can have a bone-shaped profile.

[0044] Figure 4B and Figure 4C Cross-sectional views at points A-A' and B-B' are shown respectively. (Reference) Figure 4B According to some embodiments, line A-A' is shown. Figure 4A The example layout layer 400 is shown in the cross-sectional view at (). For simplicity, the individual layers are omitted. See the reference above. Figure 4A The discussed cross-section includes source / drain regions from two different transistors (e.g., source / drain region 420A and source / drain region 422A). A p-type source / drain structure 412A corresponds to source / drain region 420A, and an n-type source / drain structure 424A corresponds to source / drain region 422A. The back metal 406 includes back metal 416A (…). Figure 4B (It is the portion of the cross-section of the back metal 406 at A-A') and the back metal 416B ( Figure 4C (It is the section of the back metal 406 at B-B').

[0045] Spacer 418A is formed around the back via 414A except where the back metal 416A contacts the back via 414A. Furthermore, an interlayer dielectric (ILD) 450A is formed beneath the p-type source / drain structure 412A, and spacer 418A is formed around the ILD 450A. Therefore, the p-type source / drain structure 412A is electrically isolated from the back metal 416A, the back via 414A, and the n-type source / drain structure 424A. On the other hand, the n-type source / drain structure 424A, the back via 414A, and the back metal 416A are all electrically coupled to each other. Since the back metal 416A is still electrically coupled to the n-type source / drain structure 424A, the user can still power semiconductor devices (e.g., transistors including the n-type source / drain structure 424A) using the back power rail. Therefore, the user can use the tester 102 to perform fault analysis on the AOI circuit formed using the example layout layer 400 with higher accuracy, because no unwanted signals are absorbed by the back metal 416A, and the back metal 416A does not overlap with the active region 402 in the portion of the active region 402 without the back vias 404 / 414A.

[0046] Furthermore, although it is shown that the back metal 416A does not overlap with the central portions of the source / drain regions 420A and 422A (source / drain structures 412A and 424A) in the z-direction, the embodiment is not limited to this. For example, depending on the embodiment and design, the back metal 416A may overlap with the central portions of one or both of the source / drain regions 420A and 422A (source / drain structures 412A and 424A). In such an embodiment, the spacer 418A will be formed to overlap with the central portions of one or both of the source / drain regions 420A and 422A (source / drain structures 412A and 424A) in the z-direction. In this example, the source / drain regions 420A and source / drain structure 412A are p-doped, and the source / drain regions 422A and source / drain structure 424A are n-doped. However, the embodiment is not limited to this, and depending on the layout and circuitry, the two sides may be doped in opposite directions. In other embodiments, both sides can be n-doped or p-doped.

[0047] refer to Figure 4C According to some embodiments, line B-B' is shown. Figure 4A The example layout layer 400 is shown in the cross-sectional view at (). For simplicity, the individual layers are omitted. See the reference above. Figure 4A The cross-section under discussion includes source / drain regions from two different transistors (e.g., source / drain region 420B and source / drain region 422B). The p-type source / drain structure 412B corresponds to the source / drain region 420B, and the n-type source / drain structure 424B corresponds to the source / drain region 422B.

[0048] Spacer 418B is formed around the back via 414B except where the back metal 416B contacts the back via 414B. Furthermore, an interlayer dielectric (ILD) 450B is formed beneath the n-type source / drain structure 424B, and spacer 418B is formed around the ILD 450B. Therefore, the n-type source / drain structure 424B is electrically isolated from the back metal 416B, the back via 414B, and the p-type source / drain structure 412B. On the other hand, the p-type source / drain structure 412B, the back via 414B, and the back metal 416B are all electrically coupled to each other. Since the back metal 416B is still electrically coupled to the p-type source / drain structure 412B, the user can still power semiconductor devices (e.g., transistors including the p-type source / drain structure 412B) using the back power rail. Therefore, the user can use the tester 102 to perform fault analysis on the AOI circuit formed using the example layout layer 400 with higher accuracy, because no unwanted signals are absorbed by the back metal 416B, and the back metal 416B does not overlap with the active region 402 in the portion of the active region 402 without the back vias 404 / 414B.

[0049] Although the back metal 416B is shown not to overlap with the central portions of the source / drain regions 420B and 422B (source / drain structures 412B and 424B) in the z-direction, the embodiment is not limited to this. For example, depending on the embodiment and design, the back metal 416B may overlap with the central portions of one or both of the source / drain regions 420A and 422B (source / drain structures 412B and 424B). In such an embodiment, the spacer 418B will be formed to overlap with the central portions of one or both of the source / drain regions 420B and 422B (source / drain structures 412B and 424B) in the z-direction. In this example, the source / drain regions 420B and source / drain structure 412B are p-doped, and the source / drain regions 422B and source / drain structure 424B are n-doped. However, the embodiment is not limited to this, and depending on the layout and circuitry, the two sides may be doped in opposite directions. In other embodiments, both sides can be n-doped or p-doped. Furthermore, refer to... Figure 4B and Figure 4C Both, the back vias 414A and 414B can be formed to connect to another source / drain structure (p-type source / drain structure 412A and n-type source / drain structure 424B), and ILDs 450A and 450B can be formed on another source / drain structure (n-type source / drain structure 424A and p-type source / drain structure 412B).

[0050] Depending on the needs of the circuit design, various shapes of back metal can be used. For example, when an open spacer pattern is not used (e.g., Figure 2AIn the example layout layer 200), the back metal can have a bone-shaped design including one or more protruding portions. In such an embodiment, the back metal can extend in a direction substantially parallel to the active region and have protrusions extending substantially perpendicularly in both directions, such that the back metal overlaps with and is electrically coupled to the selected source / drain region via a back via. As mentioned above, the protrusions can have various widths and lengths, and the protrusions can extend in only one direction without necessarily extending in the opposite direction. In another example, when using an open spacer pattern (e.g., Figure 3A Example layout layer 300 and Figure 4A In an example layout layer 400, the back metal may have a linear design and no protruding portions. In such an embodiment, the back metal extends in the direction of the active region and is electrically coupled to selected source / drain regions via back vias where no spacers are formed. In some embodiments, bone-shaped designs may be combined with linear designs in different parts of the layout.

[0051] Figure 5 A perspective view of an example gate-all-around (GAA) field-effect transistor (FET) device 500 according to some embodiments is shown. It can be constructed... Figures 2A-4C The aforementioned GAA FET circuit can be substantially similar to GAA FET device 500. GAA FET device 500 includes a substrate 502 and a plurality of semiconductor layers (e.g., nanosheets, nanowires, or other nanostructures) 504 above the substrate 502. The semiconductor layers 504 are vertically separated from each other and can collectively serve as a (conductive) channel for GAA FET device 500. An isolation region / structure 506 is formed on the opposite side of a raised portion of the substrate 502, and the semiconductor layers 504 are disposed above the raised portion. A gate structure 508 surrounds each semiconductor layer 504 (e.g., the entire periphery of each semiconductor layer 504). A spacer 509 extends along each sidewall of the gate structure 508. A source / drain structure is disposed on the opposite side of the gate structure 508, and the spacer 509 is disposed between the source / drain structure and the gate structure 508, for example, Figure 5 The source / drain structure 510 is shown. An interlayer dielectric (ILD) 512 is disposed on the source / drain structure 510.

[0052] Figure 5 The GAA FET device shown is simplified; therefore, it should be understood that one or more features of a complete GAA FET device may not be present. Figure 5 As shown in the image. For example, Figure 5 Another source / drain structure on the other side of the gate structure 508 relative to the source / drain structure 510, and an ILD disposed on such a source / drain structure, are not shown. Furthermore, [the following is provided] Figure 5 For reference, several cross-sections in the following figures are shown. As illustrated, cross-section AA is cut along the longitudinal axis of semiconductor layer 504 and in the current direction between the source / drain structures; cross-section BB is cut along the longitudinal axis of gate structure 508. These reference cross-sections are used in the following figures for clarity.

[0053] Figure 6 The following are examples of methods for fabricating GAA FET devices (e.g., according to some embodiments). Figure 5 The flowchart illustrates an example method for a 500-type GAA FET device, which also includes one or more disclosed back-side interconnect structures (e.g., 500). Figures 2A-2B 206 Figures 3A-3B 306 Figures 4A-4C (Referring to 406 / 416A / 416B). Please note that process 600 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that... Figure 6 Additional steps / operations are provided before, during, and after process 600, and some other operations may only be briefly described herein. The operation of process 600 can be combined with, for example... Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B , Figures 13A-13B , Figures 14A-14B , Figures 15A-15B , Figures 16A-16B , Figures 17A-17B , Figures 18A-18B , Figures 19A-19B and Figures 20A-20F The cross-sectional views of the example semiconductor device 100 shown at various manufacturing stages are associated and will be discussed in further detail below.

[0054] In short, process 600 begins at operation 602, providing a substrate. Process 600 can then proceed to operation 604, forming a buried oxide layer. Alternatively, the buried oxide layer can be formed later (see operation 614). Process 600 then proceeds to operation 606, forming a channel layer and a sacrificial layer alternately stacked on top of each other. Process 600 proceeds to operation 608, defining a semiconductor fin. Process 600 proceeds to operation 610, forming a dummy gate structure over the semiconductor fin. Process 600 proceeds to operation 612, forming source and / or drain recesses. If the buried oxide layer is not formed in operation 604 (see operation 604), process 600 can proceed to operation 614, forming the buried oxide layer. Process 600 proceeds to operation 616, growing a source / drain structure. Process 600 proceeds to operation 618, replacing the dummy gate structure with an active structure. Process 600 proceeds to operation 620, forming a front-side interconnect structure. Process 600 proceeds to operation 622, thinning the substrate until the bottom oxide layer is exposed. Process 600 proceeds to operation 624, replacing selected portions of the bottom oxide layer with back-side vias. Then, process 600 proceeds to operation 626, forming spacers. Process 600 proceeds to operation 628, selectively opening the spacers. Process 600 proceeds to operation 630, forming the back-side interconnect structure.

[0055] As mentioned above, Figures 7-20F Cross-sectional views of an example semiconductor device manufactured according to some embodiments via process 600 are shown during various manufacturing stages. For example, Figures 7-8 and Figures 10-20F It is along Figure 5 Cross-sectional views of semiconductor devices taken at various manufacturing stages by wire AA cutting, and Figure 9 It is along Figure 5 A cross-sectional view of a semiconductor device taken during the manufacturing stage by wire-cutting (BB). Furthermore, in some embodiments, the semiconductor device may be n-type or p-type. Although Figures 7-20F The semiconductor device shown includes a GAA transistor; however, it should be understood that a GAA transistor can include a number of other devices, such as inductors, fuses, capacitors, coils, etc., for clarity. Figures 7-20F Not shown in the image.

[0056] For simplicity, Figures 8-11 And from Figures 12A to 20A The accompanying diagram, with numbers ending in "A", illustrates the semiconductor device 600A at various manufacturing stages during operation 604. If operation 604 is not performed, operation 614 is performed to form a semiconductor device 600A as shown in the diagram. Figure 12B The buried oxide layer is shown. Therefore, Figures 12B to 20BThe accompanying drawings, which contain numbers ending in "B", illustrate the semiconductor device 600B at various manufacturing stages during operation 614. Therefore, those skilled in the art will recognize that... Figures 8-11 The buried oxide layer shown will be omitted from transistor device 600B.

[0057] Corresponding to operation 602, Figure 7 This is a cross-sectional view of a semiconductor device 600A, including a semiconductor substrate 702, at one of the various manufacturing stages. Figure 7 The cross-sectional view is along the longitudinal direction of the active / dummy gate structure of semiconductor device 600A (e.g., Figure 5 The section shown is AA).

[0058] Substrate 702 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., having p-type or n-type dopants) or undoped. Substrate 702 may be a wafer, such as a silicon wafer. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of substrate 702 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0059] Corresponding to operation 604, Figure 8 This is a cross-sectional view of a semiconductor device 600A, including a buried oxide layer 802, at one of the various manufacturing stages. The semiconductor device 600A includes a silicon-on-insulator (SOI) device, which includes a semiconductor material layer 804 formed on the buried oxide layer 802. This cross-sectional view is along... Figure 5 The AA cut is shown.

[0060] As described above, semiconductor device 600A includes a type of transistor in which a buried oxide layer 802 is formed over the entire substrate 702. In another embodiment, the buried oxide layer 802 may be formed later in a manufacturing process (see operation 614).

[0061] Corresponding to operation 606, Figure 9 This is a cross-sectional view of a semiconductor device 600A comprising multiple sacrificial layers 902 and channel layers 904 at one of the various manufacturing stages. The cross-sectional view is along... Figure 5 The AA cut is shown.

[0062] Multiple sacrificial layers 902 and multiple channel layers 904 are alternately disposed on top of each other to form a stack. For example, one of the channel layers 904 is disposed on top of one of the sacrificial layers 902, then another of the sacrificial layers 902 is disposed on top of the channel layer 904, and so on. The stack can include any number of alternately disposed sacrificial layers 902 and channel layers 904. For example, in Figure 9 In the embodiment shown (and following figures), the stack may include four sacrificial layers 902, with four channel layers 904 alternately disposed therebetween, and one of the channel layers 904 is the topmost semiconductor layer. It should be understood that the semiconductor device 600A may include any number of sacrificial layers and any number of channel layers, wherein the topmost layer may be either a sacrificial layer or a channel layer, and is still within the scope of this disclosure.

[0063] Layers 902 and 904 can each have different thicknesses. Furthermore, the individual layers of sacrificial layer 902 can have different thicknesses. The individual layers of channel layer 904 can have different thicknesses. The thickness of each of layers 902 and 904 can range from a few nanometers to tens of nanometers. The first layer of the stack can be thicker than the other semiconductor layers 902 and 904. In one embodiment, each sacrificial layer 902 has a thickness ranging from about 5 nanometers (nm) to about 20 nm, and each channel layer 904 has a thickness ranging from about 5 nm to about 20 nm.

[0064] The two layers 902 and 904 can have different compositions. In various embodiments, the two layers 902 and 904 have compositions that provide different oxidation rates and / or different etch selectivity between the layers. In one embodiment, the sacrificial layer 902 may each comprise silicon germanium (Si... 1-x Ge x The channel layers may each comprise silicon (Si). In one embodiment, each channel layer 904 may be undoped or substantially dopant-free silicon (i.e., having approximately 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 (foreign dopant concentration), wherein, for example, intentional doping (e.g., silicon) was not performed when forming the channel layer 904.

[0065] In various embodiments, the semiconductor layer 904 may be intentionally doped. For example, when the semiconductor device 600A is configured as an n-type transistor (and operates in enhancement mode), each channel layer 904 may be silicon doped with a p-type dopant (e.g., boron (B), aluminum (Al), indium (In), and gallium (Ga)); and when the semiconductor device 600A is configured as a p-type transistor (and operates in enhancement mode), each channel layer 904 may be silicon doped with an n-type dopant (e.g., phosphorus (P), arsenic (As), and antimony (Sb)). In another example, when the semiconductor device 600A is configured as an n-type transistor (and operates in depletion mode), each channel layer 904 may alternatively be silicon doped with an n-type dopant; and when the semiconductor device 600A is configured as a p-type transistor (and operates in depletion mode), each channel layer 904 may alternatively be silicon doped with a p-type dopant.

[0066] In some embodiments, each sacrificial layer 902 is a Si 1-x Ge x In molar proportions, it includes less than 50% (x < 0.5) of Ge. For example, in molar proportions, Ge can constitute Si. 1-x Ge x The sacrificial layer 902 comprises approximately 15% to 35%. Furthermore, different compositions may be included between the sacrificial layers 902, and different compositions may be included between the channel layers 904. Either layer 902 or 904 may include other materials, such as compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. The materials of layers 902 and 904 may be selected based on providing different oxidation rates and / or etch selectivity.

[0067] Layers 902 and 904 can be epitaxially grown from semiconductor substrate 702. For example, each of layers 902 and 904 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (e.g., metal-organic CVD (MOCVD) processes), and / or other suitable epitaxial growth processes. During epitaxial growth, the crystal structure of semiconductor substrate 702 extends upward, such that layers 902 and 904 have the same crystal orientation as semiconductor substrate 702.

[0068] Corresponding to operation 608, Figure 10 This is a cross-sectional view of the semiconductor device 600A, including the semiconductor fin 1002, at one of the various manufacturing stages. This cross-sectional view is along... Figure 6The BB cut is shown. After growing layers 902 and 904 (as a stack) on the semiconductor substrate 702, the stack can be patterned to form the fin structure 1002, as shown. Figure 10 As shown. The fin structure extends laterally and includes a stack of patterned sacrificial layers 902 and channel layers 904 that are staggered with each other. The fin structure 1002 is formed by patterning the stack of layers 902 and 904 and the semiconductor substrate 702 using techniques such as photolithography and etching.

[0069] For example, in the topmost semiconductor layer of the stack (e.g., Figure 10 A mask layer (which may include multiple layers, such as a pad oxide layer and an overlying hard mask layer) is formed on top of layer 904. The pad oxide layer may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer may serve as an adhesion layer between the topmost channel layer 904 and the hard mask layer. In some embodiments, the hard mask layer may include silicon nitride, silicon oxynitride, silicon carbonitride, etc., or combinations thereof. In some other embodiments, the hard mask layer may include a material similar to that of layers 902 / 904, such as Si. 1-y Ge y The molar ratio (y) of the mask layer (x) can be different from or similar to that of the sacrificial layer 902. The hard mask layer can be formed on the stack (i.e., before patterning the stack) using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0070] Photolithography can be used to pattern mask layers. Typically, photolithography utilizes a photoresist material (not shown), which is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). For example, photoresist material is used to pattern pad oxide layers and pad nitride layers to form a patterned mask.

[0071] A patterned mask can then be used to pattern the exposed portions of layers 902 and 904 and substrate 702 to form fin structures 1002, thereby defining trenches (or openings) between adjacent fin structures. When multiple fin structures are formed, such trenches can be provided between any adjacent fin structures. In some embodiments, fin structures 1002 are formed by etching trenches in layers 902-904 and substrate 702 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. In some embodiments, the trenches can be stripes that are parallel to each other and closely spaced from each other (when viewed from above). In some embodiments, the trenches can be continuous and surround the respective fin structure.

[0072] Corresponding to operation 610, Figure 11 This is a cross-sectional view of a semiconductor device 600A, which includes a dummy gate structure 1102, at one of the various stages of manufacturing. Figure 11 The cross-sectional view is along Figure 5 The AA-cut structure is shown. A dummy gate structure 1102 is formed on the fin structure 1002.

[0073] The dummy gate structure 1102 may include a dummy gate dielectric and a dummy gate, which are not shown separately for clarity. To form the dummy gate structure 1102, a dielectric layer may be formed on the fin structure 1002. The dielectric layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or multiple layers thereof, and may be deposited or thermally grown.

[0074] A gate layer is formed on top of a dielectric layer, and a mask layer is formed on top of the gate layer. The gate layer can be deposited on top of the dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited on top of the gate layer. The gate layer can be formed of, for example, polysilicon, but other materials can also be used. The mask layer can be formed of, for example, silicon nitride.

[0075] After forming the layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer can be patterned using appropriate photolithography and etching techniques. Next, the pattern of the mask layer can be transferred to the gate layer and dielectric layer using appropriate etching techniques to form the dummy gate structure 1102.

[0076] After forming the dummy gate structure 1102, a gate spacer 1104 can be formed on the opposite sidewall of the dummy gate structure 1102, such as... Figure 11 As shown. The gate spacer 1104 can be a low-k spacer and can be formed from a suitable dielectric material, such as silicon oxide, silicon carbonitride, etc. Any suitable deposition method (e.g., thermal oxidation, chemical vapor deposition (CVD), etc.) can be used to form the gate spacer 1104. Figure 11 The shape and formation method of the gate spacer 1104 shown are merely non-limiting examples, and other shapes and formation methods are also possible. These and other variations are intended to be included within the scope of this disclosure.

[0077] Corresponding to operation 612, Figure 12A This is a cross-sectional view of a semiconductor device 600A, including the source / drain (SD) recess 1202, at one of the various manufacturing stages. This cross-sectional view is along... Figure 5 The AA cut is shown.

[0078] The dummy gate structure 1102 (together with the gate spacer 1104) can be used as a mask to recess (e.g., etch) the non-overlapping portions of the fin structure 1002, such that the remaining fin structure 1002 has the respective remaining portions of the sacrificial layer 902 and the channel layer 904 alternately stacked on top of each other. As a result, a recess 1202 can be formed on the opposite side of the remaining fin structure 1002.

[0079] The recessing step forming the recess 1202 can be configured to have at least some anisotropic etching characteristics. For example, the recessing step may include a plasma etching process, which may have a certain amount of anisotropic characteristics. In such plasma etching processes (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources (e.g., chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), and other suitable gas sources and combinations thereof) can be used with passivation gases (e.g., nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof). Furthermore, for the recessing step, the gas source and / or passivation gas can be diluted with gases (e.g., argon (Ar), helium (He), neon (Ne) and other suitable diluting gases and combinations thereof) to control the etching rate described above.

[0080] Corresponding to operation 614, Figure 12B This is a cross-sectional view of a semiconductor device 600B, including a dummy gate structure 1102, gate spacer 1104, SD recess 1202, fin structure 1216, and bottom oxide layer 1218, at one of the various manufacturing stages. The dummy gate structure 1102, gate spacer 1104, SD recess 1202, and fin structure 1216 can be formed using processes and materials similar to those described above. The bottom oxide layer 1218 is formed after the SD recess 1202 is formed. As described above, unlike semiconductor device 600A, semiconductor device 600B does not have a buried oxide layer formed between the fin structure and the substrate. This cross-sectional view is along... Figure 5 The AA cut is shown.

[0081] Corresponding to operation 616, Figure 13A This is a cross-sectional view of a semiconductor device 600A, including the source / drain structure 1302 and the interlayer dielectric (ILD) 1306, at one of the various manufacturing stages. Figure 13BThis is a cross-sectional view of a semiconductor device 600B, including the source / drain structure 1302, at one of the various manufacturing stages. This cross-sectional view is along... Figure 5 The AA cut is shown.

[0082] A source / drain structure 1302 is disposed in the recess 1202. Therefore, the lower portion of the source / drain structure 1302 can inherit the dimensions and contours of the recess 1202 (e.g., extending into the substrate 702). The source / drain structure 1302 is formed by epitaxially growing a semiconductor material in the recess 1202 using a suitable method, such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or combinations thereof.

[0083] Before forming the source / drain structure 1302, a "pull-back" process can be used to remove (e.g., etch) the ends of the semiconductor layer to pull the semiconductor layer 902 of the fin structure 1002 back a pull-back distance. In an example where the channel layer 904 comprises Si and the sacrificial layer 902 comprises SiGe, the pull-back process can include an isotropic etching process using hydrogen chloride (HCl) gas, which etches SiGe without eroding Si. Therefore, the Si layer (nanostructure) 904 can remain intact in this process. Thus, a pair of recesses can be formed at the ends of each sacrificial layer 902 relative to adjacent channel layers 904. These recesses along the ends of each sacrificial layer 902 can then be filled with a dielectric material to form internal spacers 1304, such as... Figure 13A and Figure 13B As shown. The dielectric material used for the internal spacers may include silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxycarbon, or any other type of dielectric material suitable for forming the insulating gate sidewalls of transistors (e.g., a dielectric material with a dielectric constant k less than about 5).

[0084] like Figure 13A and Figure 13B As further shown, the source / drain structure 1302 is disposed on the opposite side of the fin structure 1002 to couple to the channel layer 904 of the fin structure 1002, and is separated from the sacrificial layer 902 of the fin structure 1002 by an internal spacer 1304 disposed therebetween. Furthermore, the source / drain structure 1302 is separated from the dummy gate structure 1102 by a gate spacer 1104 (at least its lower portion).

[0085] According to various embodiments of this disclosure, the channel layer 904 in each fin structure 1216 can collectively serve as the conductive channel of the completed transistor. The sacrificial layer 902 in each fin structure can later be configured as part of an active gate structure surrounding the respective channel layer.

[0086] In some embodiments, an ILD 1306 may be formed simultaneously to correspondingly cover the source / drain structure 1302. The ILD 1306 is formed of a dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and can be deposited by any suitable method, such as CVD, PECVD, or FCVD. After the ILD is formed, an optional dielectric layer (not shown) is formed on top of the ILD. The dielectric layer can serve as a protective layer to prevent or reduce ILD loss during subsequent etching processes. The dielectric layer can be formed from a suitable material such as silicon nitride, silicon carbonitride, etc., using suitable methods such as CVD, PECVD, or FCVD. After the dielectric layer is formed, a planarization process (e.g., CMP process) may be performed to obtain a flat top surface of the dielectric layer. In some embodiments, after the planarization process, the top surface of the dielectric layer is flush with the top surface of the dummy gate structure 1102.

[0087] Corresponding to operation 618, Figure 14A This is a cross-sectional view of a semiconductor device 600A, including the active metal gate 1402, at one of the various stages of manufacturing. Figure 14B These are cross-sectional views of a semiconductor device 600B, including the active metal gate 1402, manufactured at various stages. These cross-sectional views are along... Figure 5 The AA cut shown. (Reference) Figure 14A The semiconductor device 600A includes GAA transistor 1404 and GAA transistor 1406. (Reference) Figure 14B The semiconductor device 600B includes GAA transistor 1408 and GAA transistor 1410.

[0088] After forming ILD 1306, the dummy gate structure 1102 and the (remaining) sacrificial layer 902 can be removed simultaneously. In various embodiments, the dummy gate structure 1102 and the sacrificial layer 902 can be removed by applying selective etching (e.g., hydrochloric acid (HCl)) while keeping the channel layer 904 substantially intact. After removing the dummy gate structure 1102, gate trenches can be formed to expose the corresponding sidewalls of each channel layer 904. After removing the sacrificial layer 902 to further extend the gate trenches, the corresponding bottom and / or top surfaces of each channel layer 904 can be exposed. Thus, the entire periphery of each channel layer 904 can be exposed. Next, an active gate structure 1402 is formed to surround each channel layer 904 of the fin (or stack) structure 1216.

[0089] In some embodiments, each active gate structure 1402 includes a gate dielectric and a gate metal. The gate dielectric may surround each channel layer 904, for example, a top surface, a bottom surface, and sidewalls. The gate dielectric may be formed of different high-k dielectric materials or similar high-k dielectric materials. Example high-k dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric may comprise a stack of multiple high-k dielectric materials. The gate dielectric may be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In some embodiments, the gate dielectric may optionally comprise a substantially thin oxide (e.g., SiO2). x The layer can be a natural oxide layer formed on the surface of each channel layer 904.

[0090] The gate metal may comprise a stack of multiple metal materials. For example, the gate metal may be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. The work function layer may also be referred to as the work function metal. Examples of p-type work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Examples of n-type work function metals may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer; therefore, the material of the work function layer is selected to adjust its work function value so as to achieve a target threshold voltage V in the device to be formed. t One or more work function layers can be deposited by CVD, physical vapor deposition (PVD), ALD and / or other suitable processes.

[0091] After the active gate structure 1402 is formed, multiple transistors can be defined (or otherwise formed). For example, transistors can be formed that use the active gate structure 1402 and the source / drain structure 1302 as their gate, drain, and source, respectively.

[0092] Corresponding to operation 620, Figure 15A This is a cross-sectional view of a semiconductor device 600A, including the front-side interconnect structure 1502, at one of the various stages of manufacturing. Figure 15B These are cross-sectional views of a semiconductor device 600B, including the front-side interconnect structure 1502, at one of the various stages of manufacturing. These cross-sectional views are along... Figure 5 The AA cut is shown.

[0093] In both semiconductor devices 600A and 600B, the front-side interconnect structure 1502 includes multiple metal layers, including a first interconnect structure 1504 and an nth interconnect structure 1506. The front-side interconnect structure 1502 can connect one or more of the active metal gate 1402 and / or source / drain structures 1302 of transistors 600A or 600B together. For example, in Figure 15A In the first interconnect structure 1504, the active metal gates 1402 of GAA transistor 1404 and GAA transistor 1406 are connected together through a gate via VG formed on the active metal gate 1402; for example, in Figure 15B In the diagram, the first interconnect structure 1504 connects the gate structures 1402 of GAA transistor 1408 and GAA transistor 1410 together via a gate via VG formed on the active metal gate 1402. Although not shown, those skilled in the art will recognize that the front interconnect structure 1502 can couple the gate and / or source and / or drain of the GAA transistor by forming vias and interconnect structures on the GAA transistor.

[0094] Corresponding to operation 622, Figure 16A This is a cross-sectional view of a semiconductor device 600A, including the bottom oxide layer 1602, at one of the various manufacturing stages, and Figure 16B These are cross-sectional views of a semiconductor device 600B, including the bottom oxide layer 1604, at one of the various manufacturing stages. These cross-sectional views are along... Figure 5 The AA cut is shown.

[0095] refer to Figure 16A The buried oxide layer 802 formed in operation 604 is exposed by thinning the substrate 702 to expose the bottom oxide layer 1602. (See reference) Figure 16B The buried oxide layer 1218 formed in operation 614 is exposed by thinning the substrate 702 to expose the bottom oxide layer 1604. The substrate 702 can be thinned, for example, by CMP.

[0096] Corresponding to operation 624, Figure 17A This is a cross-sectional view of semiconductor device 600A, including the back via 1702, at one of the various manufacturing stages, and Figure 17B These are cross-sectional views of semiconductor device 600B, including the back via 1702, at one of the various manufacturing stages. These cross-sectional views are along... Figure 5 The diagram shows an AA cut. A portion of the bottom oxide layer 1602 is etched away and replaced by a back-side via 1702. These back-side vias are formed to deliver power from the back-side metal to the source / drain structure 1302 (see [reference]). Figures 20A-20F ).

[0097] Corresponding to operation 626, Figure 18A This is a cross-sectional view of a semiconductor device 600A, including spacer 1802, at one of the various manufacturing stages, and Figure 18B These are cross-sectional views of the semiconductor device 600B, including spacer 1804, at one of the various manufacturing stages. These cross-sectional views are along... Figure 5 The AA cut is shown.

[0098] refer to Figure 18A Spacers 1802 are formed on the bottom oxide layer 1602 and the back via 1702. (Reference) Figure 18B Spacers 1804 are formed on the bottom oxide layer 1604 and the back via 1702.

[0099] Spacers 1802 and 1804 can be low-k spacers and can be formed from suitable dielectric materials, such as silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride oxycarbonate, etc. Spacers 1802 and 1804 can be formed using any suitable deposition method (e.g., thermal oxidation, chemical vapor deposition (CVD), etc.). Figure 18A and Figure 18B The shapes and forming methods of the spacers 1802 and 1804 shown are merely non-limiting examples, and other shapes and forming methods are also possible. These and other variations are intended to be included within the scope of this disclosure.

[0100] Corresponding to operation 628, Figure 19A This is a cross-sectional view of semiconductor device 600A, including opening 1902, at one of the various manufacturing stages, and Figure 19B This is a cross-sectional view of semiconductor device 600B, including opening 1904, at one of the various manufacturing stages. These cross-sectional views are along... Figure 5 As shown, it is cut by AA. (As shown in the image) Figure 19A and Figure 19B The shapes and forming methods of the spacers 1802 and 1804 shown are merely non-limiting examples, and other shapes and forming methods are also possible. These and other variations are intended to be included within the scope of this disclosure.

[0101] Spacers 1802 and 1804 are etched to form openings 1902 and 1904, respectively. Openings 1902 and 1904 expose the ILD 1306 of semiconductor devices 600A and 600B, respectively. (As will be...) Figures 20A-20F As can be seen, openings 1902 and 1904 can have various shapes and are not limited to those shown in the figure.

[0102] Corresponding to operation 630, Figures 20A-20FThese are cross-sectional views of semiconductor devices 2000A, 2000B, 2000C, 2000D, 2000E, and 2000F, including the back-side interconnect structure 2002, at one of the various manufacturing stages. These cross-sectional views are along... Figure 5 The diagram shows AA-cut semiconductor devices. Semiconductor devices 2000A-2000E are similar to semiconductor devices 600A and 600B, but semiconductor devices 2000A-2000F also include a back metal interconnect structure. For simplicity, from... Figures 20A-20F The front interconnect structure and various layers of semiconductor devices 2000A-2000F are omitted.

[0103] refer to Figure 20A Semiconductor device 2000A includes a back interconnect structure 2002A, a GAA transistor 2004A, a back via 2014A, a GAA transistor 2006A, and a back via 2016A. Semiconductor device 2000A utilizes a buried oxide layer formed in operation 604. Figure 8 The back interconnect structure 2002A is coupled to the back via 2014A, which in turn couples to the source / drain structure of the GAA transistor 2004A. The back interconnect structure 2002A is also coupled to the back via 2016A, which in turn couples to the source / drain structure of the GAA transistor 2006A. The back interconnect structure 2002A does not overlap with the channel regions of both the GAA transistor 2004A and the GAA transistor 2006A.

[0104] refer to Figure 20B Semiconductor device 2000B includes a back interconnect structure 2002B, a GAA transistor 2004B, a back via 2014B, a GAA transistor 2006B, and a back via 2016B. Semiconductor device 2000B utilizes a buried oxide layer formed in operation 614. Figure 12B The back interconnect structure 2002B is coupled to the back via 2014B, which in turn couples to the source / drain structure of the GAA transistor 2004B. The back interconnect structure 2002B is also coupled to the back via 2016B, which in turn couples to the source / drain structure of the GAA transistor 2006B. The back interconnect structure 2002B does not overlap with the channel regions of both the GAA transistor 2004B and the GAA transistor 2006B.

[0105] refer to Figure 20C Semiconductor device 2000C includes a back interconnect structure 2002C, a GAA transistor 2004C, a back via 2014C, a GAA transistor 2006C, and a back via 2016C. Semiconductor device 2000C utilizes a buried oxide layer formed in operation 604. Figure 8The back interconnect structure 2002C is coupled to the back via 2014C, and the back via 2014C is coupled to the source / drain structure 2008C of the GAA transistor 2004C. However, with Figure 20A and Figure 20B Unlike the previous embodiment, the back interconnect structure 2002C is not coupled to the back via 2016C. In this embodiment, the back interconnect structure 2002C supplies power to the source / drain structure 2008C of the GAA transistor 2004C through the back via 2014C, but not to the GAA transistor 2006C. Similarly, the back interconnect structure 2002C does not overlap with the channel regions of both the GAA transistor 2004C and the GAA transistor 2006C.

[0106] refer to Figure 20D Semiconductor device 2000D includes a back interconnect structure 2002D, a GAA transistor 2004D, a back via 2014D, a GAA transistor 2006D, and a back via 2016C. Semiconductor device 2000D utilizes a buried oxide layer formed in operation 614. Figure 12B The back-side interconnect structure 2002D is coupled to the back-side via 2014D, and the back-side via 2014D is coupled to the source / drain structure 2008D of the GAA transistor 2004D. However, with Figure 20A and Figure 20B Unlike the previous embodiment, the back interconnect structure 2002D is not coupled to the back via 2016D. In this embodiment, the back interconnect structure 2002D supplies power to the source / drain structure 2008D of the GAA transistor 2004D through the back via 2014D, but does not supply power to the GAA transistor 2006D. Similarly, the back interconnect structure 2002D does not overlap with the channel regions of both the GAA transistor 2004D and the GAA transistor 2006D.

[0107] refer to Figure 20E Semiconductor device 2000E includes a back interconnect structure 2002E, a GAA transistor 2004E, a back via 2014E, and a GAA transistor 2006E. Semiconductor device 2000E utilizes a buried oxide layer formed in operation 614. Figure 12B The back-side interconnect structure 2002E is coupled to the back-side via 2014E, and the back-side via 2014E is coupled to the source / drain structure 2008E of the GAA transistor 2004E. However, with Figures 20A-20DUnlike other GAA transistors, GAA transistor 2006E does not have a back-side via attached to its source / drain structure 2008E. In this embodiment, the back-side interconnect structure 2002E supplies power to the source / drain structure 2008E of GAA transistor 2004E via a back-side via 2014E. Similarly, the back-side interconnect structure 2002E does not overlap with the channel regions of both GAA transistor 2004E and GAA transistor 2006E.

[0108] refer to Figure 20F Semiconductor device 2000F includes a back interconnect structure 2002F, a GAA transistor 2004F, a back via 2014F, a GAA transistor 2006F, and a back via 2016F. Semiconductor device 2000F utilizes a buried oxide layer formed in operation 604. Figure 8 The back interconnect structure 2002F is coupled to the back via 2014F, which in turn couples to the source / drain structure of the GAA transistor 2004F. The back interconnect structure 2002F is also coupled to the back via 2016F, which in turn couples to the source / drain structure of the GAA transistor 2006F. Therefore, the back interconnect structure 2002F overlaps with the back vias 2014F and 2016F to form a bone-like shape. The back interconnect structure 2002F does not overlap with the channel regions of both the GAA transistors 2004F and 2006F.

[0109] In addition, Figures 20A-20F In either of these, although not shown, the back-side interconnect structures 2002A-2002F may extend to overlap with the back-side vias 2014A-2014F and / or 2016A-2016F.

[0110] Figure 21 The use of a tester according to some embodiments is shown. Figures 20A-20E A flowchart illustrating an example method for testing semiconductor devices 2000A-2000E is provided. It should be noted that process 2100 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that... Figure 21 Additional steps / operations are provided before, during, and after the process 2100, and some other operations may only be briefly described in this document.

[0111] In short, process 2100 begins with operation 2102, manufacturing a semiconductor device. Process 2100 can then proceed to operation 2104, placing the wafer containing the semiconductor device onto a testing system. Process 2100 can then proceed to operation 2106, inspecting the wafer.

[0112] Corresponding to operation 2102, semiconductor devices can be fabricated on the wafer according to process 600. Those skilled in the art will recognize that the wafer does not necessarily have to go through the entire semiconductor device fabrication process 600 before being tested in a tester. In other words, the user can place the wafer in the tester at any stage of the fabrication process 600.

[0113] Corresponding to operation 2104, the wafer is positioned in the test system, where the user can test the desired locations on the wafer. This process can be automated or manual, depending on the test system and user preference.

[0114] Corresponding to operation 2106, the semiconductor device is tested on a tester. As described above, any suitable test system can be used, such as EMMI, EBI, or OBIRCH. When using this tester, signals (electrons, light, etc.) generated or transmitted by the tester through the channel region are not absorbed by the back-side interconnect structure. Therefore, the user can accurately detect any defects in the semiconductor device.

[0115] In one aspect of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first active region extending along a first lateral direction and including a plurality of first epitaxial structures. The semiconductor device includes an interconnect structure extending along the first lateral direction and disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion offset relative to the first active region along a second lateral direction perpendicular to the first lateral direction.

[0116] In another aspect of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of first source / drain structures laterally disposed along a first lateral direction, wherein the plurality of first source / drain structures are separated from each other by a plurality of first gate structures, the plurality of first gate structures extending along a second lateral direction perpendicular to the first lateral direction. The semiconductor device also includes an interconnect structure extending along the first lateral direction and disposed below the plurality of first source / drain structures. At least one of the plurality of first source / drain structures extends beyond a first sidewall of the interconnect structure along the second lateral direction.

[0117] In another aspect of this disclosure, a method for testing a semiconductor device is disclosed. The method includes forming a plurality of transistors on a first side of a semiconductor substrate, wherein the plurality of transistors include a plurality of source / drain structures. The method further includes forming a plurality of first interconnect structures on the first side to electrically couple the plurality of transistors to each other. The method further includes forming a second interconnect structure on a second side of the semiconductor substrate opposite to the first side, wherein the second interconnect structure includes portions exposing at least some of the source / drain structures, without any metal structure disposed between the at least some source / drain structures.

[0118] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0119] Example 1. A semiconductor device, comprising:

[0120] A first active region, the first active region extending along a first lateral direction and including a plurality of first epitaxial structures; and

[0121] An interconnect structure extending along the first lateral direction and disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure;

[0122] The interconnect structure includes at least a first portion offset relative to the first active region along a second lateral direction, the second lateral direction being perpendicular to the first lateral direction.

[0123] Example 2. The semiconductor device according to Example 1, wherein the interconnect structure includes power rails configured to carry power supply voltages.

[0124] Example 3. The semiconductor device according to Example 1 further includes a plurality of metal gate structures that extend along the second lateral direction and are disposed on corresponding portions of the first active region.

[0125] Example 4. The semiconductor device according to Example 3, wherein the at least first portion of the interconnect structure extends across at least some of the plurality of metal gate structures.

[0126] Example 5. The semiconductor device according to Example 3, wherein the portions of the first active region respectively covered by the plurality of metal gate structures each include a plurality of nanostructures that are separated from each other in the vertical direction.

[0127] Example 6. The semiconductor device according to Example 1, wherein the interconnect structure includes at least a second portion that protrudes relative to the first portion along the second lateral direction and overlaps with the at least one first epitaxial structure.

[0128] Example 7. The semiconductor device according to Example 6 further includes a via structure disposed below the at least one first epitaxial structure and electrically connecting the interconnect structure to the at least one first epitaxial structure.

[0129] Example 8. The semiconductor device according to Example 1 further includes:

[0130] The second active region also extends along the first lateral direction and includes a plurality of second extensional structures;

[0131] Wherein, at least one of the plurality of second epitaxial structures is electrically coupled to the interconnect structure located below the second active region; and

[0132] Wherein, the at least first portion of the interconnect structure is laterally offset relative to the second active region along the second lateral direction.

[0133] Example 9. The semiconductor device according to Example 8, wherein the interconnect structure includes at least a pair of second portions that protrude relative to the first portion along the second lateral direction and overlap with the at least one first epitaxial structure and the at least one second epitaxial structure, respectively.

[0134] Example 10. The semiconductor device according to Example 9 further includes:

[0135] A first via structure is disposed below the at least one first epitaxial structure and electrically connects the interconnect structure to the at least one first epitaxial structure; and

[0136] A second via structure is disposed below the at least one second epitaxial structure and electrically connects the interconnect structure to the at least one second epitaxial structure;

[0137] The first epitaxial structure has a first conductivity type, and the second epitaxial structure has a second conductivity type, wherein the first conductivity type is the same as or opposite to the second conductivity type.

[0138] Example 11. A semiconductor device, comprising:

[0139] A plurality of first source / drain structures are laterally arranged along a first lateral direction, wherein the plurality of first source / drain structures are separated from each other by a plurality of first gate structures, and the plurality of first gate structures extend along a second lateral direction perpendicular to the first lateral direction; and

[0140] An interconnect structure that extends along the first lateral direction and is disposed below the plurality of first source / drain structures;

[0141] Wherein, at least one of the plurality of first source / drain structures extends beyond the first sidewall of the interconnect structure along the second lateral direction.

[0142] Example 12. The semiconductor device according to Example 11 further includes:

[0143] Multiple second source / drain structures are laterally arranged along the first lateral direction, wherein the multiple second source / drain structures are separated from each other by multiple second gate structures extending along the second lateral direction;

[0144] Wherein, at least one of the plurality of second source / drain structures extends beyond the second sidewall of the interconnect structure along the second lateral direction.

[0145] Example 13. The semiconductor device according to Example 12, wherein the interconnect structure is configured to provide a power supply voltage to one or more of the plurality of first source / drain structures and one or more of the plurality of second source / drain structures.

[0146] Example 14. The semiconductor device according to Example 12, wherein the first source / drain structure has a first conductivity type and the second source / drain structure has a second conductivity type, and wherein the first conductivity type and the second conductivity type are the same as or opposite to each other.

[0147] Example 15. The semiconductor device according to Example 11 further includes: a metal via structure disposed below the at least one first source / drain structure and electrically coupling the interconnect structure to the at least one first source / drain structure.

[0148] Example 16. The semiconductor device according to Example 11 further includes: a dielectric structure disposed below the at least one first source / drain structure and electrically decoupling the interconnect structure from the at least one first source / drain structure.

[0149] Example 17. The semiconductor device according to Example 11 further includes a channel disposed between adjacent first source / drain structures in the plurality of first source / drain structures, wherein the channel includes a plurality of nanostructures extending along the first lateral direction and separated from each other in the vertical direction.

[0150] Example 18. A method for testing a semiconductor device, comprising:

[0151] A plurality of transistors are formed on a first side of a semiconductor substrate, wherein the plurality of transistors include a plurality of source / drain structures;

[0152] The plurality of transistors are electrically coupled to each other by forming a plurality of first interconnect structures on the first side; and

[0153] A second interconnect structure is formed on a second side of the semiconductor substrate opposite to the first side, wherein the second interconnect structure includes portions that expose at least some of the source / drain structures, and no metal structure is disposed between these source / drain structures.

[0154] Example 19. The method according to Example 18 further includes:

[0155] A test signal is applied through the first interconnect structure;

[0156] A microscope is placed on the second side of the semiconductor substrate to detect the signal present on the source / drain structure;

[0157] Based on the detected signals, it is determined whether there is an electrical connection problem in the transistor, the first interconnect structure, and the second interconnect structure.

[0158] Example 20. The method according to Example 18, wherein each of the transistors includes a gate-all-around (GAA) transistor.

Claims

1. A semiconductor device, comprising: A first active region extends along a first lateral direction and includes a plurality of first epitaxial structures; as well as An interconnect structure extending along the first lateral direction and disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure; The interconnect structure includes at least a first portion offset relative to the first active region along a second lateral direction, the second lateral direction being perpendicular to the first lateral direction; and The interconnect structure includes power rails configured to carry power supply voltages.

2. The semiconductor device according to claim 1 further includes a plurality of metal gate structures, the plurality of metal gate structures extending along the second lateral direction and disposed on corresponding portions of the first active region.

3. The semiconductor device according to claim 2, wherein, The at least first portion of the interconnect structure extends across at least some of the plurality of metal gate structures.

4. The semiconductor device according to claim 2, wherein, Each portion of the first active region covered by the plurality of metal gate structures includes a plurality of nanostructures that are separated from each other in the vertical direction.

5. The semiconductor device according to claim 1, wherein, The interconnect structure includes at least a second portion that protrudes relative to the first portion along the second lateral direction and overlaps with the at least one first extensional structure.

6. The semiconductor device of claim 5 further includes a via structure disposed below the at least one first epitaxial structure and electrically connecting the interconnect structure to the at least one first epitaxial structure.

7. The semiconductor device according to claim 1, further comprising: The second active region also extends along the first lateral direction and includes a plurality of second extensional structures; Wherein, at least one of the plurality of second epitaxial structures is electrically coupled to the interconnect structure located below the second active region; and Wherein, the at least first portion of the interconnect structure is laterally offset relative to the second active region along the second lateral direction.

8. The semiconductor device according to claim 7, wherein, The interconnect structure includes at least one pair of second portions that protrude relative to the first portion along the second lateral direction and overlap with the at least one first epitaxial structure and the at least one second epitaxial structure, respectively.

9. The semiconductor device according to claim 8, further comprising: A first via structure is disposed below the at least one first epitaxial structure and electrically connects the interconnect structure to the at least one first epitaxial structure; as well as A second via structure is disposed below the at least one second epitaxial structure and electrically connects the interconnect structure to the at least one second epitaxial structure; The first epitaxial structure has a first conductivity type, and the second epitaxial structure has a second conductivity type, wherein the first conductivity type is the same as or opposite to the second conductivity type.

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