Driving substrate, manufacturing method thereof and display panel

Abstract

The application discloses a driving substrate, a manufacturing method thereof and a display panel. The driving substrate comprises a display area and a non-display area, and the non-display area is located at least one side of the display area. The driving substrate comprises a substrate, a first thin film transistor structure and a second thin film transistor structure. The first thin film transistor structure is arranged on the substrate and corresponds to the non-display area. The first thin film transistor structure comprises a first light shielding layer, a first active layer, a first gate, a first source and a first drain. The first light shielding layer is multiplexed as a second gate. The first light shielding layer is electrically connected with the first gate. The second thin film transistor structure is located on the substrate and corresponds to the display area. The second thin film transistor structure comprises a second light shielding layer, a second active layer, a third gate, a second source and a second drain. The second light shielding layer is electrically connected with the second source.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving substrate and its manufacturing method, and a display panel. Background Technology

[0002] With the development of display technology, the demand for large-size, high-quality display devices is increasing. Among them, oxide semiconductors are often used in large-size, high-quality OLED (Organic Light-Emitting Diode) display applications due to their excellent characteristics and manufacturing process advantages. Gate Driver on Array (GOA) technology integrates the gate driving circuit on the array substrate of the display panel to achieve a line-by-line scanning driving method, thereby eliminating the need for the gate driving circuit. This has the advantages of reducing production costs and enabling narrow bezel designs, and is used in various displays. As a mainstream display technology, GOA technology has significant advantages in achieving low cost and reducing bezel size in high-quality display devices. As is well known, the GOA region requires high current driving. Therefore, if conventional device structures are used, the size of the TFT (Thin Film Transistor) needs to be increased to increase the current. The size of the TFT limits the size of the GOA circuit and the bezel to a certain extent. Therefore, improving the carrier mobility of the TFT in the GOA region can reduce the size of the driving substrate, thereby achieving a narrow bezel design.

[0003] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0004] This application provides a driving substrate and its manufacturing method, as well as a display panel, for reducing the size of the driving substrate, thereby achieving a narrow bezel design.

[0005] This application provides a driving substrate, including a display area and a non-display area, wherein the non-display area is located on at least one side of the display area, and the driving substrate includes:

[0006] Substrate;

[0007] A first thin-film transistor structure is disposed on the substrate and corresponds to the non-display area. The first thin-film transistor structure includes a first light-shielding layer, a first active layer, a first gate, a first source, and a first drain. The first light-shielding layer is multiplexed as a second gate, and the first light-shielding layer is electrically connected to the first gate.

[0008] A second thin-film transistor structure is located on the substrate and corresponds to the display area. The second thin-film transistor structure includes a second light-shielding layer, a second active layer, a third gate, a second source, and a second drain. The second light-shielding layer and the second source are electrically connected.

[0009] In the driving substrate provided in this application embodiment, the first light-shielding layer is located on the substrate, and the driving substrate further includes:

[0010] A buffer layer is located on the side of the first light-shielding layer that is away from the substrate;

[0011] A gate insulating layer is located on the side of the first active layer away from the buffer layer and covers the first active layer. The gate insulating layer includes a first via that penetrates the gate insulating layer and the buffer layer.

[0012] A connecting electrode is disposed within the first via.

[0013] An interlayer dielectric layer is located on the side of the first gate away from the gate insulating layer, and the interlayer dielectric layer includes a second via and a third via;

[0014] Wherein, the second via and the third via penetrate the interlayer dielectric layer, and the first source and the first drain are electrically connected to the first active layer through the second via and the third via, respectively;

[0015] A passivation layer is located on the side of the interlayer dielectric layer away from the first gate.

[0016] In the driving substrate provided in the embodiments of this application, the driving substrate further includes:

[0017] A buffer layer is located on the side of the first light-shielding layer that is away from the substrate;

[0018] A gate insulating layer is located on the side of the first active layer away from the buffer layer;

[0019] An interlayer dielectric layer is located on the side of the first gate away from the gate insulating layer, and the interlayer dielectric layer includes a first via, a second via, a third via, and a fourth via;

[0020] The first via, the second via, and the third via penetrate the interlayer dielectric layer, the fourth via penetrates the interlayer dielectric layer and the buffer layer, and the first source and the first drain are electrically connected to the first active layer through the second via and the third via, respectively.

[0021] A connecting electrode is provided, comprising a first connecting electrode, a second connecting electrode, and a connecting portion. The first connecting electrode and the second connecting electrode are connected through the connecting portion, which is located on the interlayer dielectric layer. The first connecting electrode is disposed in the first via, and the second connecting electrode is disposed in the fourth via.

[0022] A passivation layer is located on the side of the interlayer dielectric layer away from the first gate and covers the first source, the first drain and the connection electrode.

[0023] In the driving substrate provided in this application embodiment, the connecting electrode is disposed on the same layer as the first source electrode.

[0024] In the driving substrate provided in the embodiments of this application, the driving substrate further includes:

[0025] A third thin-film transistor structure is located on the substrate and corresponds to the display area. The third thin-film transistor structure includes a third active layer, a fourth gate, a third source, and a third drain.

[0026] In the driving substrate provided in the embodiments of this application, the first light-shielding layer and the second light-shielding layer are disposed in the same layer;

[0027] The first active layer, the second active layer, and the third active layer are disposed on the same layer;

[0028] The first gate, the third gate, and the fourth gate are disposed in the same layer;

[0029] The first source, the first drain, the second source, the second drain, the third source, and the third drain are disposed on the same layer.

[0030] In the driving substrate provided in the embodiments of this application, the driving substrate further includes:

[0031] A fourth thin-film transistor structure is located on the substrate and corresponds to the display area. The fourth thin-film transistor structure includes a fourth active layer, a fifth gate, a fourth source, and a fourth drain.

[0032] The fourth active layer and the third active layer are disposed on the same layer;

[0033] The fifth gate and the fourth gate are disposed in the same layer;

[0034] The fourth source, the fourth drain, the third source, and the third drain are disposed in the same layer.

[0035] In the driving substrate provided in the embodiments of this application, the orthogonal projection of the first light-shielding layer on the substrate covers the orthogonal projection of the first active layer on the substrate.

[0036] In the driving substrate provided in the embodiments of this application, the first active layer is an amorphous silicon active layer or a metal oxide active layer, and the second and third active layers are metal oxide active layers.

[0037] Accordingly, this application embodiment also provides a display panel, the display panel including the above-mentioned driving substrate and light-emitting functional layer, the light-emitting functional layer being disposed on the driving substrate and located in the display area.

[0038] Accordingly, this application also provides a method for manufacturing a driving substrate, the method comprising the following steps:

[0039] Provide a substrate;

[0040] A first thin-film transistor structure and a second thin-film transistor structure are formed on the substrate. The first thin-film transistor structure includes a first light-shielding layer, a first active layer, a first gate, a first source, and a first drain. The first light-shielding layer is multiplexed as a second gate, and the first light-shielding layer and the first gate are electrically connected. The second thin-film transistor structure includes a second light-shielding layer, a second active layer, a third gate, a second source, and a second drain. The second light-shielding layer and the second source are electrically connected.

[0041] In the method for fabricating a driving substrate provided in this application embodiment, the step of forming a first thin-film transistor structure and a second thin-film transistor structure on the substrate further includes:

[0042] A light-shielding material layer is formed on the substrate, and the light-shielding material layer is patterned to form the first light-shielding layer and the second light-shielding layer;

[0043] A buffer layer is formed on the first light-shielding layer and the second light-shielding layer;

[0044] A semiconductor material layer is formed on the buffer layer, and the semiconductor material layer is patterned to form the first active layer and the second active layer;

[0045] A gate insulating layer is formed on the buffer layer, and the gate insulating layer is processed using a photolithography process to form a first via.

[0046] A first metal layer is formed on the gate insulating layer, and the first metal layer is patterned to form the first gate, the third gate, and the connection electrode. The connection electrode is disposed in the first via, and the first gate and the first light-shielding layer are electrically connected through the connection electrode.

[0047] An interlayer dielectric layer is formed on the first gate, and the interlayer dielectric layer is processed using a photolithography process to form a second via, a third via, a first contact hole, a second contact hole, and a third contact hole.

[0048] A second metal layer is formed on the interlayer dielectric layer, and the second metal layer is patterned to form a first source, a first drain, a second source, a second drain, and an auxiliary electrode. The first source and the first drain are electrically connected to the first active layer through the second via and the third via, respectively. The auxiliary electrode is disposed in the first contact hole. The second source and the second drain are electrically connected to the second active layer through the second contact hole and the third contact hole, respectively.

[0049] A passivation layer is formed on the interlayer dielectric layer.

[0050] In the method for fabricating a driving substrate provided in this application embodiment, the step of forming a first thin-film transistor structure and a second thin-film transistor structure on the substrate further includes:

[0051] A light-shielding material layer is formed on the substrate, and the light-shielding material layer is patterned to form the first light-shielding layer and the second light-shielding layer;

[0052] A buffer layer is formed on the first light-shielding layer and the second light-shielding layer;

[0053] A semiconductor material layer is formed on the buffer layer, and the semiconductor material layer is patterned to form the first active layer and the second active layer;

[0054] An insulating material layer is formed on the first active layer and the second active layer;

[0055] A first metal layer is formed on the insulating material layer, and the first metal layer is patterned to form the first gate and the third gate;

[0056] Using the first gate and the third gate as self-alignment, the insulating material layer is patterned to form a gate insulating layer;

[0057] An interlayer dielectric layer is formed on the first gate, and the interlayer dielectric layer is processed using a photolithography process to form a first via, a second via, a third via, a fourth via, a first contact hole, a second contact hole, and a third contact hole.

[0058] A second metal layer is formed on the interlayer dielectric layer and patterned to form a first source, a first drain, a connection electrode, a second source, a second drain, and an auxiliary electrode. The connection electrode includes a first connection electrode, a second connection electrode, and a connection portion. The first connection electrode and the second connection electrode are connected through the connection portion. The first connection electrode is disposed within a first via, and the second connection electrode is disposed within a fourth via. The first source and the first drain are electrically connected through the second via and the third via, respectively. The auxiliary electrode is disposed within a first contact hole, and the second source and the second drain are electrically connected to the active layer through the second contact hole and the third contact hole, respectively.

[0059] A passivation layer is formed on the interlayer dielectric layer.

[0060] This application provides a driving substrate and its fabrication method, as well as a display panel. The driving substrate includes a display area and a non-display area, with the non-display area located on at least one side of the display area. The driving substrate includes a substrate, a first thin-film transistor (TFT) structure, and a second TFT structure. The first TFT structure is disposed on the substrate and corresponds to the non-display area. The first TFT structure includes a first light-shielding layer, a first active layer, a first gate, a first source, and a first drain. The first light-shielding layer is multiplexed as a second gate. The first light-shielding layer is electrically connected to the first gate. The second TFT structure is located on the substrate and corresponds to the display area. The second TFT structure includes a second light-shielding layer, a second active layer, a third gate, a second source, and a second drain. The second light-shielding layer and the second source are electrically connected. In this embodiment, the first light-shielding layer not only shields the first active layer from light to prevent light from affecting its stability, but also, since the first light-shielding layer is reused as the second gate and is electrically connected to the first gate, two conductive channels are formed, increasing the on-state current and effectively suppressing the negative drift of the threshold voltage, thus improving carrier mobility and facilitating narrow bezel design. Furthermore, the second light-shielding layer not only shields the second active layer from light to prevent light from affecting its stability, but is also electrically connected to the second source. Since the second light-shielding layer overlaps with both the second active layer and the third gate, parasitic capacitances are formed between them. When the driving substrate is operating, the voltage on the second drain changes with the voltage applied to the data signal line, causing the voltage on the second light-shielding layer to also change, thus affecting the electrical performance of the second active layer. By connecting the second light-shielding electrode to the second source to form an equipotential connection, the voltage change on the second light-shielding layer can be prevented from affecting the electrical performance of the second active layer. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 A schematic plan view of a driving substrate provided in an embodiment of this application;

[0063] Figure 2 This is a schematic diagram of a first structure of the driving substrate provided in an embodiment of this application;

[0064] Figure 3 This is a schematic diagram of a second structure of the driving substrate provided in an embodiment of this application;

[0065] Figure 4 A flowchart illustrating the steps of a method for fabricating a driving substrate according to an embodiment of this application;

[0066] Figure 5 This is a first schematic diagram illustrating a method for fabricating a driving substrate according to an embodiment of this application;

[0067] Figure 6 A second schematic diagram illustrating a method for fabricating a driving substrate according to an embodiment of this application;

[0068] Figure 7 A schematic diagram of the display panel structure is provided for an embodiment of this application. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Please refer to the figures in the drawings, where the same component symbols represent the same components. The following description is based on the specific embodiments of this application shown, and should not be considered as limiting other specific embodiments not detailed herein. The term "embodiment" as used in this specification means example, illustration, or illustration.

[0070] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0071] This application provides a driving substrate, a method for manufacturing the same, and a display panel. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0072] This application provides a driving substrate, which includes a display area and a non-display area, with the non-display area located on at least one side of the display area. The driving substrate includes a substrate, a first thin-film transistor (TFT) structure, and a second TFT structure. The first TFT structure is disposed on the substrate and corresponds to the non-display area. The first TFT structure includes a first light-shielding layer, a first active layer, a first gate, a first source, and a first drain. The first light-shielding layer is reused as a second gate. The first light-shielding layer is electrically connected to the first gate. The second TFT structure is located on the substrate and corresponds to the display area. The second TFT structure includes a second light-shielding layer, a second active layer, a third gate, a second source, and a second drain. The second light-shielding layer and the second source are electrically connected. In this application embodiment, the first light-shielding layer not only blocks light from the first active layer to prevent light from affecting the stability of the first active layer, but also, since the first light-shielding layer is reused as a second gate and the first light-shielding layer and the first gate are electrically connected, two conductive channels are formed, increasing the on-state current, thereby effectively suppressing the negative drift of the threshold voltage and improving the carrier mobility, thus facilitating narrow bezel design. Furthermore, the second light-shielding layer not only serves to shield the second active layer from light, preventing illumination from affecting its stability, but also, being electrically connected to the second source electrode, creates parasitic capacitances between the second light-shielding layer, the second active layer, and the third gate electrode due to overlapping regions. During substrate operation, the voltage on the second drain electrode changes with varying voltages applied to the data signal lines, consequently altering the voltage on the second light-shielding layer and affecting the electrical performance of the second active layer. By connecting the second light-shielding layer to the second source electrode to achieve equipotentiality, the voltage variation on the second light-shielding layer can be prevented from affecting the electrical performance of the second active layer.

[0073] It should be noted that, in the embodiments of this application, the non-display area may include the gate driving area.

[0074] The driving substrate provided in this application will be described in detail below through specific embodiments.

[0075] Please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a planar structure of a driving substrate provided in an embodiment of this application. Figure 2 This is a schematic diagram of a first structure of a driving substrate provided in an embodiment of this application. The driving substrate 10 includes a display area AA and a non-display area NA, with the non-display area NA located on at least one side of the display area AA. The non-display area NA includes a gate driving area GOA.

[0076] The driving substrate 10 includes a substrate 11, a first thin-film transistor (TFT) structure T1, and a second TFT structure T2. The first TFT structure T1 is disposed on the substrate 11 and corresponds to the non-display area NA. The first TFT structure T1 includes a first light-shielding layer LS1, a first active layer 12a, a first gate 12b, a first source 12c, and a first drain 12d. The first light-shielding layer LS1 is multiplexed as a second gate 12e. The first light-shielding layer LS1 is electrically connected to the first gate 12b. The second TFT structure T2 is located on the substrate 11 and corresponds to the display area AA. The second TFT structure T2 includes a second light-shielding layer LS2, a second active layer 13a, a third gate 13b, a second source 13c, and a second drain 13d. The second light-shielding layer LS2 and the second source 13c are electrically connected. In this embodiment, the first light-shielding layer LS1 not only shields the first active layer 12a from light to prevent light from affecting its stability, but also, since the first light-shielding layer LS1 is reused as the second gate 12e and the first light-shielding layer LS1 and the first gate 12b are electrically connected, two conductive channels are formed, increasing the on-state current and effectively suppressing the negative drift of the threshold voltage, thus improving the carrier mobility and facilitating narrow bezel design. Furthermore, the second light-shielding layer LS2 not only shields the second active layer 13a from light to prevent light from affecting its stability, but also, since the second light-shielding layer LS2 is electrically connected to the second source 13c, parasitic capacitances are formed between the second light-shielding layer LS2 and both the second active layer 13a and the third gate 13b due to overlapping regions. When the driving substrate is working, the voltage on the second drain 13d changes with the voltage applied to the data signal line, which in turn changes the voltage on the second light-shielding layer LS2, thus affecting the electrical performance of the second active layer 13a. By connecting the second light-shielding layer LS2 and the second source 13c to form an equipotential connection, the voltage variation on the second light-shielding layer LS2 can be prevented from affecting the electrical performance of the second active layer 13a.

[0077] Furthermore, the first light-shielding layer LS1 and the second light-shielding layer LS2 are located on the substrate 11. The driving substrate 10 also includes a buffer layer 16, a gate insulating layer 17, a connection electrode 12f, an interlayer dielectric layer 18, and a passivation layer 19. The buffer layer 16 is located on the side of the first light-shielding layer LS1 away from the substrate 11. The gate insulating layer 17 is located on the side of the first active layer 12a away from the buffer layer 16 and covers the first active layer 12a and the second active layer 13a. The gate insulating layer 17 includes a first via h1, which penetrates the gate insulating layer 17 and the buffer layer 16. The connection electrode 12f is disposed within the first via h1. The interlayer dielectric layer 18 is located on the side of the first gate 12b away from the gate insulating layer 17. The interlayer dielectric layer 18 includes a second via h2 and a third via h3. The second via h2 and the third via h3 penetrate the interlayer dielectric layer 18. The first source electrode 12c is electrically connected to the first active layer 12a through the second via h2. The first drain 12d is electrically connected to the first active layer 12a through the third via h3. The passivation layer 19 is located on the side of the interlayer dielectric layer 18 away from the first gate 12b.

[0078] In some embodiments, the orthographic projection of the first light-shielding layer LS1 onto the substrate 11 covers the orthographic projection of the first active layer 12a onto the substrate 11. In this embodiment, since the orthographic projection of the first light-shielding layer LS1 onto the substrate 11 covers the orthographic projection of the first active layer 12a onto the substrate 11, when light shines onto the first active layer 12a, the light can be completely blocked by the first light-shielding layer LS1, thereby improving the stability of the driving substrate 10.

[0079] Optionally, in some embodiments, the driving substrate 10 may further include a third thin-film transistor structure T3, which is disposed on the substrate 11 and corresponds to the display area AA. The third thin-film transistor structure T3 includes a third active layer 14a, a fourth gate 14b, a third source 14c, and a third drain 14d. In the embodiments of this application, the first light-shielding layer LS1 and the second light-shielding layer LS2 are disposed on the same layer. The first active layer 12a, the second active layer 13a, and the third active layer 14a are disposed on the same layer. The first gate 12b, the third gate 13b, and the fourth gate 14b are disposed on the same layer. The first source 12c, the first drain 12d, the second source 13c, the second drain 13d, the third source 14c, and the third drain 14d are disposed on the same layer.

[0080] It should be understood that the second thin-film transistor structure T2 in the embodiments of this application can be a driving thin-film transistor, and the third thin-film transistor structure T3 can be a switching thin-film transistor.

[0081] In this embodiment, the driving circuit architecture located in the display area AA is 2T1C (i.e., two thin film transistors and one capacitor). The 2T1C driving circuit architecture has a simple fabrication process, and since it uses two thin film transistors to drive one sub-pixel unit, it is conducive to miniaturization.

[0082] In some embodiments, the first active layer 12a is an amorphous silicon active layer, and the second active layer 13a and the third active layer 14a are metal oxide active layers. In this embodiment, the active layers of the thin-film transistors in the display area AA and the non-display area NA of the driving substrate 10 are made of different materials. The active layer of the thin-film transistors in the display area AA of the driving substrate 10 is made of a metal oxide semiconductor material. This allows the high mobility of the metal oxide semiconductor material to meet the charging rate requirements of high-resolution display products when the display product has a high resolution. The active layer of the thin-film transistors in the non-display area NA of the driving substrate 10 is made of a non-metal oxide semiconductor material. This prevents the threshold voltage V of the thin-film transistor from escalating under long-term bias. th Drift ensures that the characteristics of the thin-film transistor do not change, thus ensuring the normal scanning function of the circuit in the non-display area (NA).

[0083] In some embodiments, the first active layer 12a may be a metal oxide active layer, and the second active layer 13a and the third active layer 14a may also be metal oxide active layers. In the embodiments of this application, both the display area AA and the non-display area NA of the driving substrate 10 are made of metal oxide semiconductor material. Therefore, the first active layer 12a, the second active layer 13a, and the third active layer 14a can be fabricated simultaneously in a single mask process, simplifying the process of the driving substrate 10.

[0084] In some embodiments, the first active layer 12a may include a first sub-active layer, a second sub-active layer, and a third sub-active layer stacked sequentially, wherein the number of gallium atoms in the first and third sub-active layers is greater than the number of gallium atoms in the second sub-active layer. Because gallium has a strong affinity for oxygen atoms, it can effectively suppress the generation of deep-level defects, thereby improving the stability of the device and thus enhancing the reliability of the display panel. The ratio of indium atoms, gallium atoms, and zinc atoms in the second sub-active layer is indium:gallium:zinc = 1:1:1, ensuring the conductivity and mobility of the driving substrate 10.

[0085] In some embodiments, the material of the first sub-active layer includes indium gallium zinc oxide, wherein the ratio of the number of indium atoms, gallium atoms, and zinc atoms in the first sub-active layer is indium:gallium:zinc = M:1:N, where 0 < M < 1 and 0 < N < 1. For example, in one embodiment, the ratio of the number of indium atoms, gallium atoms, and zinc atoms in the first sub-active layer is any one of indium:gallium:zinc = 0.1:1:0.2, 0.4:1:0.2, 0.3:1:0.3, or 0.1:1:0.8.

[0086] The material of the third sub-active layer includes indium gallium zinc oxide, and the ratio of the number of indium atoms, gallium atoms, and zinc atoms in the third sub-active layer is indium:gallium:zinc = X:1:Y, 0 < X ​​< 1, 0 < Y < 1. For example, in one embodiment, the ratio of the number of indium atoms, gallium atoms, and zinc atoms in the first sub-active layer is any one of indium:gallium:zinc = 0.3:1:0.2, 0.4:1:0.2, 0.3:1:0.3, or 0.6:1:0.8.

[0087] It should be noted that the number of gallium atoms in the first and third sub-active layers can be the same or different.

[0088] The material of the second active layer includes indium gallium zinc oxide, wherein the ratio of the number of indium atoms, gallium atoms, and zinc atoms in the second active layer is indium:gallium:zinc = 1:1:1.

[0089] In some embodiments, the first sub-active layer includes a nitrogen-doped indium gallium zinc oxide active layer, and the third sub-active layer includes a nitrogen-doped indium gallium zinc oxide active layer. Since nitrogen atoms have a strong binding affinity to oxygen vacancies, the introduction of nitrogen can occupy oxygen vacancies, effectively controlling the carrier concentration and defect concentration in the active layer, thereby improving the mobility of the display panel and enhancing the reliability of the driving substrate.

[0090] In some embodiments, at least one of phosphorus, fluorine, selenium, or tellurium may be doped into the first sub-active layer and / or the third sub-active layer.

[0091] In some embodiments, the driving substrate 10 may further include a fourth thin-film transistor structure T4, which is disposed on the substrate 11 and corresponds to the display area AA. The fourth thin-film transistor structure T4 includes a fourth active layer 15a, a fifth gate 15b, a fourth source 15c, and a fourth drain 15d. The fourth active layer 15a and the third active layer 14a are disposed on the same layer. The fifth gate 15b and the fourth gate 14b are disposed on the same layer. The fourth source 15c, the fourth drain 15d, the third source 14c, and the third drain 14d are disposed on the same layer.

[0092] It should be understood that the second thin-film transistor structure T2 in the embodiments of this application can be a driving thin-film transistor, the third thin-film transistor structure T3 can be a switching thin-film transistor, and the fourth thin-film transistor structure T4 can be a sensing thin-film transistor.

[0093] In this embodiment, the driving circuit architecture located in the display area AA is 3T1C (i.e., three thin-film transistors and one capacitor). Under the 2T driving architecture, for a single sub-pixel, there is only one gate line to control the data voltage (V). data The write of ) and the write of V data It will be transmitted to the gate of the driving TFT and stored in the storage capacitor C. st In the 2T driving architecture, the source electrode of the driving TFT is in a floating state with an uncertain initial potential, resulting in significant flicker in the display. In contrast, the 3T driving architecture allows for control of the driving TFT source voltage via an additional gate line, effectively providing two gate lines and significantly improving display quality. Furthermore, the 3T architecture enables accurate TFT mobility detection, further enhancing display quality. Currently, most large-size OLED displays utilize the 3T driving architecture.

[0094] It should be understood that, in the embodiments of this application, the gate insulating layer 17 can be a structure formed over the entire surface, and the first gate 12b can extend inward into the surface. It can be understood that the width of the first active layer 12a in the surface is smaller than the width of the first gate 12b in the surface, and the width of the first light-shielding layer LS1 in the surface is greater than the width of the first active layer 12a in the surface. Therefore, the first via h1 directly penetrates the gate insulating layer 17, thereby preventing the connecting electrode 12f from being short-circuited with the first active layer 12a.

[0095] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a second structure of the driving substrate provided in an embodiment of this application. The driving substrate 10 includes a display area AA and a non-display area NA, with the non-display area NA located on at least one side of the display area AA. The non-display area NA includes a gate driving area GOA.

[0096] The driving substrate 10 includes a substrate 11, a first thin-film transistor (TFT) structure T1, and a second TFT structure T2. The first TFT structure T1 is disposed on the substrate 11 and corresponds to the non-display area NA. The first TFT structure T1 includes a first light-shielding layer LS1, a first active layer 12a, a first gate 12b, a first source 12c, and a first drain 12d. The first light-shielding layer LS1 is multiplexed as a second gate 12e. The first light-shielding layer LS1 is electrically connected to the first gate 12b. The second TFT structure T2 is located on the substrate 11 and corresponds to the display area AA. The second TFT structure T2 includes a second light-shielding layer LS2, a second active layer 13a, a third gate 13b, a second source 13c, and a second drain 13d. The second light-shielding layer LS2 and the second source 13c are electrically connected. In this embodiment, the first light-shielding layer LS1 not only shields the first active layer 12a from light to prevent light from affecting its stability, but also, since the first light-shielding layer LS1 is reused as the second gate 12e and the first light-shielding layer LS1 and the first gate 12b are electrically connected, two conductive channels are formed, increasing the on-state current and effectively suppressing the negative drift of the threshold voltage, thus improving the carrier mobility and facilitating narrow bezel design. Furthermore, the second light-shielding layer LS2 not only shields the second active layer 13a from light to prevent light from affecting its stability, but also, since the second light-shielding layer LS2 is electrically connected to the second source 13c, parasitic capacitances are formed between the second light-shielding layer LS2 and both the second active layer 13a and the third gate 13b due to overlapping regions. When the driving substrate is working, the voltage on the second drain 13d changes with the voltage applied to the data signal line, which in turn changes the voltage on the second light-shielding layer LS2, thus affecting the electrical performance of the second active layer 13a. By connecting the second light-shielding layer LS2 and the second source 13c to form an equipotential connection, the voltage variation on the second light-shielding layer LS2 can be prevented from affecting the electrical performance of the second active layer 13a.

[0097] Furthermore, the first light-shielding layer LS1 and the second light-shielding layer LS2 are located on the substrate 11. The driving substrate 10 also includes a buffer layer 16, a gate insulating layer 17, a connection electrode 12f, an interlayer dielectric layer 18, and a passivation layer 19. The connection electrode 12f includes a first connection electrode 12f1, a second connection electrode 12f2, and a connection portion 12f3. The first connection electrode 12f1 and the second connection electrode 12f2 are connected through the connection portion 12f3. The buffer layer 16 is located on the side of the first light-shielding layer LS1 away from the substrate 11. The gate insulating layer 17 is located on the side of the first active layer 12a away from the buffer layer 16. The interlayer dielectric layer 18 is located on the side of the first gate 12b away from the gate insulating layer 17. The connection portion 12f3 is located on the interlayer dielectric layer 18, which includes a first via h1, a second via h2, a third via h3, and a fourth via h4. The first via h1, the second via h2, and the third via h3 penetrate the interlayer dielectric layer 18. The fourth via h4 penetrates the interlayer dielectric layer 18 and the buffer layer 16. The first source 12c and the first drain 12d are electrically connected to the first active layer 12a through the second via h2 and the third via h3, respectively. The first connection electrode 12f1 is disposed in the first via h1, and the second connection electrode 12f2 is disposed in the fourth via h4. The passivation layer 19 is located on the side of the interlayer dielectric layer 18 away from the first gate 12b and covers the first source 12c, the first drain 12d, and the connection electrode 12f.

[0098] An auxiliary electrode 13e is disposed within the first contact hole cnt1. The second source electrode 13c and the second drain electrode 13d are electrically connected to the second active layer 13a through the second contact hole cnt2 and the third contact hole cnt3, respectively.

[0099] In this embodiment, the first light-shielding layer LS1 and the first gate 12b are electrically connected via a connecting electrode 12f. Since the connecting electrode 12f and the first source 12c are disposed on the same layer, they can be fabricated using the same mask process. Therefore, the driving substrate 10 in this embodiment further improves the carrier mobility of the non-display area NA without increasing process costs, thereby achieving a narrow bezel design.

[0100] It should be understood that, in the embodiments of this application, the gate insulating layer 17 is formed by self-alignment with the first gate 12b, the connecting electrode 12f is disposed in the same layer as the first source 12c, the first via h1 directly penetrates the interlayer dielectric layer 18, and the fourth via h4 directly penetrates the interlayer dielectric layer 18 and the buffer layer 16, so that the connecting electrode 12f will not be short-circuited with the first active layer 12a.

[0101] Optionally, in some embodiments, the substrate 11 includes a first flexible layer, a first barrier layer, a second flexible layer, and a second barrier layer stacked sequentially. The first barrier layer prevents water and oxygen from penetrating through one side of the first flexible layer to the structure above the first barrier layer, thus preventing damage to the driving substrate 10. In some embodiments, the materials of the first barrier layer, the second barrier layer, and the buffer layer 16 include, but are not limited to, silicon-containing oxides, nitrides, or oxynitrides. For example, the material of the first barrier layer is SiO2. x SiN x or SiO x N y At least one of the following. The material of the first flexible layer can be the same as that of the second flexible layer, which may include at least one of PI (polyimide), PET (polyethylene dicarboxylate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate), or PCO (polycyclic olefin). The buffer layer 16 may be a silicon nitride layer and a silicon oxide layer stacked together, wherein the silicon nitride layer is used to prevent water and oxygen from intruding from one side of the second flexible layer, thereby damaging the film layer above the driving substrate 10, and the silicon oxide layer is used to keep the thin-film transistor above it warm.

[0102] The first active layer 12a, the second active layer 13a, the third active layer 14a, and the fourth active layer 15a are disposed alternately on the buffer layer 16. The first active layer 12a, the second active layer 13a, the third active layer 14a, and the fourth active layer 15a can be made of indium gallium zinc oxide, indium zinc tin oxide, or indium gallium zinc tin oxide, or any combination thereof. Alternatively, the first active layer 12a, the second active layer 13a, the third active layer 14a, and the fourth active layer 15a can also be made of LTPO (Low Temperature Polycrystalline Oxide). The materials of the first light-shielding layer LS1, the second light-shielding layer LS2, the first gate 12b, the third gate 13b, the fourth gate 14b, the fifth gate 15b, the first source 12c, the first drain 12d, the second source 13c, the second drain 13d, the third source 14c, the third drain 14d, the fourth source 15c, the fourth drain 15d, the connecting electrode 12f, and the auxiliary electrode 13e include one or any combination of metals such as silver (Ag), magnesium (Mg), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), neodymium (Nd), or scandium (Sc), their alloys, their nitrides, etc.

[0103] The gate insulating layer 17, the interlayer dielectric layer 18, and the passivation layer 19 are made of silicon oxide, silicon nitride, or silicon oxynitride, or any combination thereof.

[0104] Accordingly, please refer to Figure 4 , Figure 4 This is a flowchart illustrating the first step of a method for fabricating a driving substrate according to an embodiment of this application. The method for fabricating the driving substrate includes the following steps:

[0105] Step B001: Provide a substrate 11.

[0106] Step B002: Form a first thin-film transistor structure T1 and a second thin-film transistor structure T2 on substrate 11. The first thin-film transistor structure T1 includes a first light-shielding layer LS1, a first active layer 12a, a first gate 12b, a first source 12c, and a first drain 12d. The first light-shielding layer LS1 is multiplexed as a second gate 12e. The first light-shielding layer LS1 and the first gate 12b are electrically connected. The second thin-film transistor structure T2 includes a second light-shielding layer LS2, a second active layer 13a, a third gate 13b, a second source 13c, and a second drain 13d. The second light-shielding layer LS2 and the second source 13c are electrically connected. Please refer to [reference needed]. Figure 5 .

[0107] Furthermore, step B002 also includes forming a third thin-film transistor structure T3 and a fourth thin-film transistor structure T4. The third thin-film transistor structure T3 includes a third active layer 14a, a fourth gate 14b, a third source 14c, and a third drain 14d. The fourth thin-film transistor structure T4 includes a fourth active layer 15a, a fifth gate 15b, a fourth source 15c, and a fourth drain 15d.

[0108] Step B002 may specifically include: first, forming a light-shielding material layer LS on the substrate 11, and patterning the light-shielding material layer LS to form a first light-shielding layer LS1 and a second light-shielding layer LS2.

[0109] Next, a buffer layer 16 is formed on the first light-shielding layer LS1 and the second light-shielding layer LS2.

[0110] Next, a semiconductor material layer 121 is formed on the buffer layer 16, and the semiconductor material layer 121 is patterned to form a first active layer 12a, a second active layer 13a, a third active layer 14a, and a fourth active layer 15a.

[0111] Then, a gate insulating layer 17 is formed on the buffer layer 16, and the gate insulating layer 17 is processed using a photolithography process to form a first via h1.

[0112] Subsequently, a first metal layer M1 is formed on the gate insulating layer 17, and the first metal layer M1 is patterned to form a first gate 12b, a third gate 13b, a fourth gate 14b, a fifth gate 15b, a connecting electrode 12f, and an auxiliary electrode 13e. The connecting electrode 12f is disposed in the first via h1, and the first gate 12b and the first light-shielding layer LS1 are electrically connected through the connecting electrode 12f.

[0113] Next, an interlayer dielectric layer 18 is formed on the first gate 12b, and the interlayer dielectric layer 18 is processed using a photolithography process to form a second via h2, a third via h3, a first contact hole cnt1, a second contact hole cnt2, a third contact hole cnt3, a fourth contact hole cnt4, a fifth contact hole cnt5, a sixth contact hole cnt6, and a seventh contact hole cnt7.

[0114] Next, a second metal layer M2 is formed on the interlayer dielectric layer 18, and the second metal layer M2 is patterned to form a first source 12c, a first drain 12d, a second source 13c, a second drain 13d, a third source 14c, a third drain 14d, a fourth source 15c, a fourth drain 15d, and an auxiliary electrode 13e. The first source 12c and the first drain 12d are electrically connected to the first active layer 12a through the second via h2 and the third via h3, respectively. The auxiliary electrode 13e is disposed in the first contact hole cnt1. The second source 13c and the second drain 13d are electrically connected to the second active layer 13a through the second contact hole cnt2 and the third contact hole cnt3, respectively. The third source 14c and the third drain 14d are electrically connected to the third active layer 14a through the fourth contact hole cnt4 and the fifth contact hole cnt5, respectively. The fourth source 15c and the fourth drain 15d are electrically connected to the fourth active layer 15a through the sixth contact hole cnt6 and the seventh contact hole cnt7, respectively.

[0115] Finally, a passivation layer 19 is formed on the interlayer dielectric layer 18, thereby forming the driving substrate 10.

[0116] In the method for fabricating the driving substrate provided in this application embodiment, the gate insulating layer 17 can be a structure formed over the entire surface, and the first gate 12b can extend inward. It can be understood that the width of the first active layer 12a in the surface is smaller than the width of the first gate 12b in the surface, and the width of the first light-shielding layer LS1 in the surface is greater than the width of the first active layer 12a in the surface. Therefore, the first via h1 directly penetrates the gate insulating layer 17, thus preventing the connection electrode 12f from short-circuiting with the first active layer 12a. In this application embodiment, the first light-shielding layer LS1 not only serves to shield the first active layer 12a from light, preventing light from affecting the stability of the first active layer 12a; but also, since the first light-shielding layer LS1 is reused as the second gate 12e, and the first light-shielding layer LS1 and the first gate 12b are electrically connected, two conductive channels are formed, increasing the on-state current, thereby effectively suppressing the negative drift of the threshold voltage and improving the carrier mobility, thus facilitating narrow bezel design. Furthermore, the second light-shielding layer LS2 not only serves to shield the second active layer 13a from light, preventing illumination from affecting its stability, but also, being electrically connected to the second source electrode 13c, overlaps with both the second light-shielding layer LS2, the second active layer 13a, and the third gate electrode 13b, resulting in parasitic capacitances between them. During substrate operation, the voltage on the second drain electrode 13d changes with the voltage applied to the data signal line, causing a corresponding change in the voltage on the second light-shielding layer LS2 and thus affecting the electrical performance of the second active layer 13a. By connecting the second light-shielding layer LS2 to the second source electrode 13c to achieve equipotentiality, the voltage variation on the second light-shielding layer LS2 can be prevented from affecting the electrical performance of the second active layer 13a.

[0117] In some embodiments, please refer to Figure 6 Step B002 may specifically include:

[0118] First, a light-shielding material layer LS is formed on the substrate 11, and the light-shielding material layer LS is patterned to form a first light-shielding layer LS1 and a second light-shielding layer LS2.

[0119] Next, a buffer layer 16 is formed on the first light-shielding layer LS1 and the second light-shielding layer LS2.

[0120] Next, a semiconductor material layer 121 is formed on the buffer layer 16, and the semiconductor material layer 121 is patterned to form a first active layer 12a, a second active layer 13a, a third active layer 14a, and a fourth active layer 15a.

[0121] Then, an insulating material layer 171 is formed on the first active layer 12a, the second active layer 13a, the third active layer 14a and the fourth active layer 15a.

[0122] Subsequently, a first metal layer M1 is formed on the gate insulating layer 17, and the first metal layer M1 is patterned to form a first gate 12b, a third gate 13b, a fourth gate 14b, and a fifth gate 15b.

[0123] Next, the insulating material layer 171 is patterned using the first gate 12b, the third gate 13b, the fourth gate 14b, and the fifth gate 15b as self-alignment to form the gate insulating layer 17.

[0124] Next, an interlayer dielectric layer 18 is formed on the first gate 12a, and the interlayer dielectric layer 18 is processed using a photolithography process to form a first via h1, a second via h2, a third via h3, a first contact hole cnt1, a second contact hole cnt2, a third contact hole cnt3, a fourth contact hole cnt4, a fifth contact hole cnt5, a sixth contact hole cnt6, and a seventh contact hole cnt7.

[0125] Next, a second metal layer M2 is formed on the interlayer dielectric layer 18, and the second metal layer M2 is patterned to form a first source 12c, a first drain 12d, a second source 13c, a second drain 13d, a third source 14c, a third drain 14d, a fourth source 15c, a fourth drain 15d, a connecting electrode 12f, and an auxiliary electrode 13e. The connecting electrode 12f includes a first connecting electrode 12f1, a second connecting electrode 12f2, and a connecting portion 12f3. The first connecting electrode 12f1 and the second connecting electrode 12f2 are connected through the connecting portion 12f3. The first connecting electrode 12f1 is disposed within a first via h1. The second connecting electrode 12f2 is disposed within a fourth via h4. The first source 12c and the first drain 12d are electrically connected to the first active layer 12a through the second via h2 and the third via h3, respectively. The auxiliary electrode 13e is disposed within a first contact hole cnt1. The second source electrode 13c and the second drain electrode 13d are electrically connected to the second active layer 13a through the second contact hole cnt2 and the third contact hole cnt3, respectively. The third source electrode 14c and the third drain electrode 14d are electrically connected to the third active layer 14a through the fourth contact hole cnt4 and the fifth contact hole cnt5, respectively. The fourth source electrode 15c and the fourth drain electrode 15d are electrically connected to the fourth active layer 15a through the sixth contact hole cnt6 and the seventh contact hole cnt7, respectively.

[0126] Finally, a passivation layer 19 is formed on the interlayer dielectric layer 18 to form the driving substrate 10.

[0127] In the method for fabricating the driving substrate provided in this application embodiment, the first light-shielding layer LS1 and the first gate 12b are electrically connected through a connecting electrode 12f. Since the connecting electrode 12f and the first source 12c are disposed in the same layer, the connecting electrode 12f and the first source 12c can be fabricated using the same mask process. Therefore, the driving substrate 10 of this application embodiment further improves the carrier mobility of the non-display area NA without increasing the process cost, thereby achieving a narrow bezel design.

[0128] Accordingly, please refer to Figure 7 This application also provides a display panel, the display panel 100 including the driving substrate 10 and the light-emitting functional layer 20 described in any of the above embodiments. The light-emitting functional layer 20 is disposed on the driving substrate 10 and corresponds to the display area AA.

[0129] Specifically, the light-emitting functional layer 20 includes an anode 20a, a light-emitting layer 20b, and a cathode 20c. The display panel 100 also includes a planarization layer 21 and a pixel definition layer 22. The planarization layer 21 is disposed on the passivation layer 19. The anode 20a is electrically connected to the second source electrode 13c through a via. The material of the anode 20a may include indium tin oxide, silver, and indium tin oxide stacked sequentially. The pixel definition layer 22 has an opening, and the light-emitting layer 20b is defined within the opening of the pixel definition layer 22. The cathode 20c covers the light-emitting layer 20b and a portion of the pixel definition layer 22.

[0130] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A driving substrate, characterized in that, The driving substrate includes a display area and a non-display area, wherein the non-display area is located on at least one side of the display area, and the driving substrate includes: Substrate; A first thin-film transistor structure is disposed on the substrate and corresponds to the non-display area. The first thin-film transistor structure includes a first light-shielding layer, a first active layer, a first gate, a first source, and a first drain. The first light-shielding layer is multiplexed as a second gate, and the first light-shielding layer is electrically connected to the first gate. A second thin-film transistor structure is located on the substrate and corresponds to the display area. The second thin-film transistor structure includes a second light-shielding layer, a second active layer, a third gate, a second source, and a second drain. The second light-shielding layer and the second source are electrically connected. The driving substrate further includes: A third thin-film transistor structure is located on the substrate and corresponds to the display area. The third thin-film transistor structure includes a third active layer, a fourth gate, a third source, and a third drain. The second thin-film transistor is a driving thin-film transistor, and the third thin-film transistor is a switching thin-film transistor; The driving substrate further includes: A buffer layer is located on the side of the first light-shielding layer that is away from the substrate; A gate insulating layer is located on the side of the first active layer away from the buffer layer; An interlayer dielectric layer is located on the side of the first gate away from the gate insulating layer, and the interlayer dielectric layer includes a first via, a second via, a third via, and a fourth via; The first via, the second via, and the third via penetrate the interlayer dielectric layer, the fourth via penetrates the interlayer dielectric layer and the buffer layer, and the first source and the first drain are electrically connected to the first active layer through the second via and the third via, respectively. A connecting electrode is provided, comprising a first connecting electrode, a second connecting electrode, and a connecting portion. The first connecting electrode and the second connecting electrode are connected through the connecting portion, which is located on the interlayer dielectric layer. The first connecting electrode is disposed in the first via, and the second connecting electrode is disposed in the fourth via. A passivation layer is located on the side of the interlayer dielectric layer away from the first gate, and covers the first source, the first drain and the connection electrode; The connecting electrode is disposed in the same layer as the first source electrode; The width of the first active layer in the plane is smaller than the width of the first gate in the plane, and the width of the first light-shielding layer in the plane is greater than the width of the first active layer in the plane. The first active layer includes a first sub-active layer, a second sub-active layer, and a third sub-active layer stacked sequentially, wherein the number of gallium atoms in the first sub-active layer and the third sub-active layer is greater than the number of gallium atoms in the second sub-active layer.

2. The driving substrate according to claim 1, characterized in that, The first light-shielding layer and the second light-shielding layer are disposed in the same layer; The first active layer, the second active layer, and the third active layer are disposed on the same layer; The first gate, the third gate, and the fourth gate are disposed in the same layer; The first source, the first drain, the second source, the second drain, the third source, and the third drain are disposed on the same layer.

3. The driving substrate according to claim 2, characterized in that, The driving substrate further includes: A fourth thin-film transistor structure is located on the substrate and corresponds to the display area. The fourth thin-film transistor structure includes a fourth active layer, a fifth gate, a fourth source, and a fourth drain. The fourth active layer and the third active layer are disposed on the same layer; The fifth gate and the fourth gate are disposed in the same layer; The fourth source, the fourth drain, the third source, and the third drain are disposed in the same layer.

4. The driving substrate according to claim 1, characterized in that, The orthogonal projection of the first light-shielding layer onto the substrate covers the orthogonal projection of the first active layer onto the substrate.

5. The driving substrate according to claim 1, characterized in that, The first active layer is an amorphous silicon active layer or a metal oxide active layer, and the second and third active layers are metal oxide active layers.

6. A display panel, characterized in that, The display panel includes a driving substrate and a light-emitting functional layer as described in any one of claims 1 to 5, wherein the light-emitting functional layer is disposed on the driving substrate and located in the display area.

7. A method for manufacturing a driving substrate, characterized in that, The method for manufacturing the driving substrate includes the following steps: Provide a substrate; A first thin-film transistor structure and a second thin-film transistor structure are formed on the substrate. The first thin-film transistor structure includes a first light-shielding layer, a first active layer, a first gate, a first source, and a first drain. The first light-shielding layer is multiplexed as a second gate, and the first light-shielding layer and the first gate are electrically connected. The second thin-film transistor structure includes a second light-shielding layer, a second active layer, a third gate, a second source, and a second drain. The second light-shielding layer and the second source are electrically connected. The first thin-film transistor structure and the second thin-film transistor structure are formed on the substrate. The first thin-film transistor structure includes a first light-shielding layer, a first active layer, a first gate, a first source, and a first drain. The first light-shielding layer is multiplexed as the second gate, and the first light-shielding layer and the first gate are electrically connected. The second thin-film transistor structure includes a second light-shielding layer, a second active layer, a third gate, a second source, and a second drain. The electrical connection between the second light-shielding layer and the second source further includes: A third thin-film transistor structure is formed on a substrate, wherein the third thin-film transistor structure includes a third active layer, a fourth gate, a third source, and a third drain; The step of forming the first thin-film transistor structure and the second thin-film transistor structure on the substrate further includes: A light-shielding material layer is formed on the substrate, and the light-shielding material layer is patterned to form the first light-shielding layer and the second light-shielding layer; A buffer layer is formed on the first light-shielding layer and the second light-shielding layer; A semiconductor material layer is formed on the buffer layer, and the semiconductor material layer is patterned to form the first active layer and the second active layer; An insulating material layer is formed on the first active layer and the second active layer; A first metal layer is formed on the insulating material layer, and the first metal layer is patterned to form the first gate and the third gate; Using the first gate and the third gate as self-alignment, the insulating material layer is patterned to form a gate insulating layer; An interlayer dielectric layer is formed on the first gate, and the interlayer dielectric layer is processed using a photolithography process to form a first via, a second via, a third via, a fourth via, a first contact hole, a second contact hole, and a third contact hole. A second metal layer is formed on the interlayer dielectric layer and patterned to form a first source, a first drain, a connection electrode, a second source, a second drain, and an auxiliary electrode. The connection electrode includes a first connection electrode, a second connection electrode, and a connection portion. The first connection electrode and the second connection electrode are connected through the connection portion. The first connection electrode is disposed within a first via, and the second connection electrode is disposed within a fourth via. The first source and the first drain are electrically connected through the second via and the third via, respectively. The auxiliary electrode is disposed within a first contact hole, and the second source and the second drain are electrically connected to the second active layer through the second contact hole and the third contact hole, respectively. A passivation layer is formed on the interlayer dielectric layer; The connecting electrode is disposed in the same layer as the first source electrode; The width of the first active layer in the plane is smaller than the width of the first gate in the plane, and the width of the first light-shielding layer in the plane is greater than the width of the first active layer in the plane. The first active layer includes a first sub-active layer, a second sub-active layer, and a third sub-active layer stacked sequentially, wherein the number of gallium atoms in the first sub-active layer and the third sub-active layer is greater than the number of gallium atoms in the second sub-active layer.

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