Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a first display area and a second display area. The first display area comprises a first sub-pixel circuit and a first light-emitting unit connected thereto, and the second display area comprises a second sub-pixel circuit and a second light-emitting unit connected thereto. The display substrate further comprises a pixel circuit column group comprising a first pixel circuit column, a second pixel circuit column, a third pixel circuit column and a fourth pixel circuit column connected to a first data line, a second data line, a third data line and a fourth data line respectively. The second data line, the third data line and the fourth data line connected to the pixel circuit column group are disconnected to form a first disconnection, the data lines on both sides of the first disconnection are connected to the first sub-pixel circuit and the second sub-pixel circuit respectively, and the second data line is connected to the third data line or the fourth data line through a data line connection part. By arranging the data line connection part, the matching of the data signals transmitted to the first display area and the second display area can be ensured.

Description

TECHNICAL FIELD

[0001] The present disclosure at least one embodiment relates to a display substrate and a display device. BACKGROUND

[0002] With the continuous pursuit of the visual effect of display products, narrow frame or even full screen display has become a new trend of current organic light emitting diode (OLED) display product development. With the gradual improvement of the screen ratio of many mobile phones, the full screen has become the current trend. The front camera is the key to the design of the full screen. In order to achieve a higher screen ratio, display products with notch screen, water drop screen, and hole screen have appeared. These three kinds of full screen forms improve the screen ratio by sacrificing the appearance of the mobile phone. Therefore, the design of the under-screen camera can ensure the appearance of the mobile phone and improve the screen ratio. The under-screen camera refers to the front camera located under the screen without affecting the screen display function. When the front camera is not used, the screen above the camera can still display images normally. From the appearance, the under-screen camera will not have any camera hole, and truly achieves the full screen display effect. SUMMARY

[0003] The present disclosure at least one embodiment provides a display substrate and a display device.

[0004] At least one embodiment of the present disclosure provides a display substrate, comprising: a substrate substrate comprising a first display area and a second display area, the first display area and the second display area comprising a plurality of pixel circuits arranged along a first direction and a second direction to form a plurality of pixel circuit columns and a plurality of pixel circuit rows, the first direction and the second direction intersecting, a plurality of data lines extending along the second direction and located on the substrate substrate, and respectively connected with the plurality of pixel circuit columns. The plurality of pixel circuits located in the first display area comprise a plurality of first sub-pixel circuits, the plurality of pixel circuits located in the second display area comprise a plurality of second sub-pixel circuits, the first display area further comprises a plurality of first light emitting units, the plurality of first light emitting units are connected with the plurality of first sub-pixel circuits one by one, the second display area further comprises a plurality of second light emitting units, and each of the second light emitting units is connected with at least two second sub-pixel circuits; each of the pixel circuit columns comprises a pixel circuit column group composed of four adjacent columns, each pixel circuit column group comprises a first pixel circuit column, a second pixel circuit column, a third pixel circuit column and a fourth pixel circuit column arranged in sequence along the first direction, the first pixel circuit column, the second pixel circuit column, the third pixel circuit column and the fourth pixel circuit column in the first display area are connected with a first data line, a second data line, a third data line and a fourth data line arranged in sequence along the first direction respectively, at least part of the pixel circuits of the first pixel circuit column, at least part of the pixel circuits of the second pixel circuit column, at least part of the pixel circuits of the third pixel circuit column and at least part of the pixel circuits of the fourth pixel circuit column in the second display area are connected with a first data line, a second data line, a third data line and a fourth data line arranged in sequence along the first direction respectively, the second data line, the third data line and the fourth data line connected with at least one pixel circuit column group are disconnected to form a first disconnection, the data line on one side of the first disconnection is connected with the first sub-pixel circuit, the data line on the other side of the first disconnection is connected with the second sub-pixel circuit, and the end point of the second data line at the first disconnection is connected to the end point of the third data line or the fourth data line at the first disconnection through a data line connection part.

[0005] For example, in an embodiment of the present disclosure, the end point of the second data line at the first disconnection is connected to the end point of the fourth data line at the first disconnection through a data line connection part, and the data line connection part passes through the first disconnection of the third data line.

[0006] For example, in the embodiment of the present disclosure, the second data line connected with the first sub-pixel circuit and the second data line connected with the second sub-pixel circuit are configured to transmit different signals; the third data line connected with the first sub-pixel circuit and the third data line connected with the second sub-pixel circuit are configured to transmit different signals; and the fourth data line connected with the first sub-pixel circuit and the fourth data line connected with the second sub-pixel circuit are configured to transmit different signals.

[0007] For example, in the embodiment of the present disclosure, in the second display area, in at least one pixel circuit column group, the data input terminals of two pixel circuits located in the same pixel circuit row and respectively located in the first pixel circuit column and the second pixel circuit column are electrically connected to form a first pixel circuit pair, and the data input terminals of two pixel circuits located in the same pixel circuit row and respectively located in the third pixel circuit column and the fourth pixel circuit column are electrically connected to form a second pixel circuit pair.

[0008] For example, in the embodiment of the present disclosure, the substrate substrate further comprises a third display area; the plurality of pixel circuits of the second display area further comprises a plurality of third sub-pixel circuits, and the third display area comprises a plurality of third light emitting units, each of which is connected with at least two third sub-pixel circuits.

[0009] For example, in the embodiment of the present disclosure, in the second display area and the third display area, the plurality of light emitting units are respectively connected with a plurality of first pixel circuit pairs and a plurality of second pixel circuit pairs of the second display area; the first pixel circuit pair connected with the light emitting unit of the second display area is connected with the first data line located in the second display area, the second pixel circuit pair connected with the light emitting unit of the second display area is connected with the fourth data line located in the second display area, the first pixel circuit pair connected with the light emitting unit of the third display area is connected with the second data line located in the second display area, and the second pixel circuit pair connected with the light emitting unit of the third display area is connected with the third data line located in the second display area.

[0010] For example, in the embodiment of the present disclosure, the data line connection part and the plurality of data lines are located in different layers.

[0011] For example, in the embodiment of the present disclosure, the display substrate further comprises a plurality of power signal lines, which are arranged in the same layer as the plurality of data lines and extend along the second direction. Along a third direction perpendicular to the substrate substrate, the data line connection part and the power signal line overlap.

[0012] For example, in the embodiment of the present disclosure, the display substrate further comprises a plurality of reset power supply signal lines located between the plurality of data lines and the substrate and extending along the first direction. Each of the pixel circuits comprises a drive transistor, a threshold compensation transistor, and a first reset control transistor, the first electrode of the threshold compensation transistor is connected to the first electrode of the drive transistor, the second electrode of the threshold compensation transistor is connected to the gate electrode of the drive transistor, the first electrode of the first reset control transistor is connected to the reset power supply signal line, the second electrode of the first reset control transistor is connected to the second electrode, and the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in the pixel circuit row adjacent to the second sub-pixel circuit in the first sub-pixel circuit are provided with the data line connection part.

[0013] For example, in the embodiment of the present disclosure, the distance between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in the pixel circuit row adjacent to the second sub-pixel circuit in the first sub-pixel circuit in the first direction is 7-12 microns to provide the data line connection part between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor.

[0014] For example, in the embodiment of the present disclosure, the data line connection part and the reset power supply signal line are located in the same layer.

[0015] For example, in the embodiment of the present disclosure, the third display area comprises a center area and an edge area surrounding the center area, the edge area comprises a plurality of dummy pixel circuits arranged along the first direction and the second direction to form at least one dummy pixel circuit column and at least one dummy pixel circuit row; the at least one dummy pixel circuit column in the third display area comprises a dummy pixel circuit column group composed of four adjacent columns, each dummy pixel circuit column group comprises a first dummy pixel circuit column, a second dummy pixel circuit column, a third dummy pixel circuit column, and a fourth dummy pixel circuit column arranged in sequence along the first direction, at least part of the dummy pixel circuits in the first dummy pixel circuit column, at least part of the dummy pixel circuits in the second dummy pixel circuit column, at least part of the dummy pixel circuits in the third dummy pixel circuit column, and at least part of the dummy pixel circuits in the fourth dummy pixel circuit column are connected to a first data line, a second data line, a third data line, and a fourth data line arranged in sequence along the first direction respectively, the third data line and the fourth data line are disconnected to form a second disconnection, the data line on one side of the second disconnection is connected to the dummy pixel circuit, and the data line on the other side of the second disconnection is connected to the first sub-pixel circuit.

[0016] For example, in the embodiments of the present disclosure, the display substrate further comprises a peripheral area located on a side of the third display area away from the first display area, a portion of the first data line located in the edge area of the third display area bypasses the center area to connect to one of the second data line and the third data line of the second display area in the peripheral area, and a portion of the second data line located in the edge area of the third display area bypasses the center area to connect to the other of the second data line and the third data line of the second display area in the peripheral area.

[0017] For example, in the embodiments of the present disclosure, the first pixel circuit pair is arranged along the second direction, and four first pixel circuit pairs arranged adjacently in the second direction are respectively connected with a first color light emitting unit, a third color light emitting unit of the second display area, and two second color light emitting units of the third display area.

[0018] For example, in the embodiments of the present disclosure, the display substrate further comprises: a scan signal line extending along the first direction and located between the reset power supply signal line and the substrate substrate; a reset control signal line extending along the first direction and arranged in the same layer as the scan signal line; and a light emitting control signal line extending along the first direction and arranged in the same layer as the scan signal line. The pixel circuit of each of the sub-pixels further comprises a data writing transistor, a storage capacitor, a first light emitting control transistor, a second light emitting control transistor and a second reset transistor, the first electrode of the data writing transistor is connected with the second electrode of the driving transistor, the second electrode of the data writing transistor is connected with the data line, and the gate electrode of the data writing transistor is electrically connected with the scan signal line; the first electrode of the storage capacitor is electrically connected with the power supply signal line, and the second electrode of the storage capacitor is electrically connected with the gate electrode of the driving transistor; the gate electrode of the threshold value compensation transistor is electrically connected with the scan signal line; the gate electrode of the first reset transistor is electrically connected with the reset control signal line; the first electrode of the second reset transistor is electrically connected with the reset power supply signal line, the second electrode of the second reset transistor is electrically connected with the gate electrode of the driving transistor, and the gate electrode of the second reset transistor is electrically connected with the reset control signal line; the first electrode of the first light emitting control transistor is electrically connected with the first electrode of the driving transistor, the second electrode of the first light emitting control transistor is electrically connected with the light emitting unit, and the gate electrode of the first light emitting control transistor is electrically connected with the light emitting control signal line; the first electrode of the second light emitting control transistor is electrically connected with the power supply signal line, the second electrode of the second light emitting control transistor is electrically connected with the second electrode of the driving transistor, and the gate electrode of the second light emitting control transistor is electrically connected with the light emitting control signal line.

[0019] Another embodiment of the present disclosure provides a display device comprising the above display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure, but not limit the present disclosure.

[0021] FIG. 1 A partial planar structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown in the figure.

[0022] FIG. 2 A partial planar structure schematic diagram of a display substrate according to an embodiment of the present disclosure is shown in the figure. FIG. 1 An equivalent diagram of a pixel circuit of at least one of the second pixel circuit group and the third pixel circuit group shown in the figure.

[0023] FIG. 3AA partial plan view of an active semiconductor layer of a pixel circuit in a second display area according to an embodiment of the present disclosure is shown in FIG. 6A;

[0024] FIG. 3B A partial plan view of a first conductive layer and an active semiconductor layer in a second display area according to an embodiment of the present disclosure is shown in FIG. 6B;

[0025] FIG. 3C A partial plan view of a second conductive layer in a second display area according to an embodiment of the present disclosure is shown in FIG. 6C;

[0026] FIG. 3D A partial plan view of a second conductive layer and an active semiconductor layer in a second display area according to an embodiment of the present disclosure is shown in FIG. 6D;

[0027] FIG. 3E A partial plan view of a source-drain metal layer of a second display area according to an embodiment of the present disclosure is shown in FIG. 6E;

[0028] FIG. 3F A partial plan view of a source-drain metal layer and a second conductive layer in a second display area according to an embodiment of the present disclosure is shown in FIG. 6F;

[0029] FIG. 4A A connection relationship between a second light emitting unit group and a second pixel circuit group of a second display area according to an embodiment of the present disclosure is shown in FIG. 6G;

[0030] FIG. 4B A schematic layer structure of a light emitting unit is shown in FIG. 6H; FIG. 4A

[0031] A schematic layer structure of a light emitting unit is shown in FIG. 6I; FIG. 4C FIG. 4A A schematic position relationship between a second light emitting unit group and a via hole of a second display area is shown in FIG. 6J;

[0032] FIG. 5A A partial pixel circuit structure at a junction between a first display area and a second display area according to an embodiment of the present disclosure is shown in FIG. 6K;

[0033] FIG. 5B A film layer structure at a data line connection portion of a position shown in FIG. 6L is shown in FIG. 6M; FIG. 5A

[0034] A film layer structure of a data line at a position shown in FIG. 6N is shown in FIG. 6O; FIG. 5C FIG. 5A A partial plan view of a first display area and a second display area in a display substrate is shown in FIG. 6P;

[0035] FIG. 5D FIG. 1 A partial plan view of a first display area and a second display area in a display substrate is shown in FIG. 6Q;

[0036] ​​​FIG. 5E A partial plan view of a first display area and a second display area in a display substrate according to another example of embodiments of the present disclosure is provided;

[0037] FIG. 6 A partial pixel circuit structure schematic view at an edge area intersection of the first display area and a third display area according to embodiments of the present disclosure is provided;

[0038] FIG. 7 A schematic view of a second electrode of a light emitting unit group located in the first display area according to embodiments of the present disclosure is provided;

[0039] FIG. 8 A schematic view of a second electrode of a light emitting unit group located in a non-edge of the second display area according to embodiments of the present disclosure is provided;

[0040] FIG. 9 A schematic view of a second electrode of a light emitting unit group located in the third display area according to embodiments of the present disclosure is provided;

[0041] FIG. 10 A schematic view of a second electrode of each light emitting unit in two rows of light emitting unit groups of the second display area intersecting with the first display area according to embodiments of the present disclosure is provided; and

[0042] FIG. 11 A schematic view of a second electrode of each light emitting unit in two columns of light emitting unit groups of the second display area intersecting with the first display area according to embodiments of the present disclosure is provided. DETAILED DESCRIPTION

[0043] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0044] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects.

[0045] In the research, the inventors of the present application found that in the organic light-emitting diode display device with an under-screen camera design, the display brightness and current of a low-density display area (L area) are at least one time lower than those of a high-density display area (H area), which affects the display effect.

[0046] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a substrate, a first display area and a second display area, the first display area and the second display area include a plurality of pixel circuits arranged along a first direction and a second direction to form a plurality of pixel circuit columns and a plurality of pixel circuit rows, the first direction and the second direction intersect, a plurality of data lines extending along the second direction are located on the substrate and are connected to the plurality of pixel circuit columns respectively. The plurality of pixel circuits located in the first display area include a plurality of first sub-pixel circuits, the plurality of pixel circuits located in the second display area include a plurality of second sub-pixel circuits, the first display area further includes a plurality of first light emitting units, the plurality of first light emitting units are connected to the plurality of first sub-pixel circuits one by one, the second display area further includes a plurality of second light emitting units, each second light emitting unit is connected to at least two second sub-pixel circuits; each pixel circuit column includes a pixel circuit column group composed of four adjacent columns, each pixel circuit column group includes a first pixel circuit column, a second pixel circuit column, a third pixel circuit column and a fourth pixel circuit column arranged along the first direction in sequence, the first pixel circuit column, the second pixel circuit column, the third pixel circuit column and the fourth pixel circuit column in the first display area are connected to a first data line, a second data line, a third data line and a fourth data line arranged along the first direction in sequence respectively, at least part of the pixel circuits of the first pixel circuit column, at least part of the pixel circuits of the second pixel circuit column, at least part of the pixel circuits of the third pixel circuit column and at least part of the pixel circuits of the fourth pixel circuit column in the second display area are connected to the first data line, the second data line, the third data line and the fourth data line arranged along the first direction in sequence respectively, the second data line, the third data line and the fourth data line connected to at least one pixel circuit column group are disconnected to form a first disconnection, the data line on one side of the first disconnection is connected to the first sub-pixel circuit, the data line on the other side of the first disconnection is connected to the second sub-pixel circuit, and the end point of the second data line at the first disconnection is connected to the end point of the third data line or the fourth data line at the first disconnection through a data line connection part. In the display substrate provided by the embodiments of the present disclosure, the second data line, the third data line and the fourth data line are disconnected at the position where the pixel circuits in the first display area and the pixel circuits in the second display area meet, and the end point of the second data line located in the first display area close to the second display area is connected to the end point of the fourth data line located in the second display area close to the first display area through the data line connection part, so that the matching of the data signals transmitted from the data line to the light emitting units in the first display area and the data signals transmitted from the data line to the light emitting units in the second display area can be ensured.

[0047] The display substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0048] FIG. 1 This is a schematic diagram of a partial planar structure of a display substrate according to an embodiment of the present disclosure. FIG. 1 As shown, the display substrate includes a substrate 10. The display substrate includes a first display area 100 and a second display area 200. For example, the display substrate also includes a third display area 300. For example, the second display area 200 is located around the third display area 300, for example, on both sides of the third display area 300 along the X direction, and the first display area 100 is located around the second display area 200 and the third display area 300. For example, the second display area 200 and the third display area 300 are located at the edges of the display areas, that is, the display substrate includes the display areas and the peripheral areas surrounding the display areas, and the edges of the second display area 200 and the third display area 300 away from the first display area 100 are connected to the peripheral areas. That is, the first display area 100 is only located on one side of the third display area 300 along the Y direction. For example, the third display area 300 can be rectangular, with two edges extending along the Y direction respectively connecting to the second display areas 200 located on both sides thereon, one edge extending along the X direction connecting to the peripheral area, and the other edge connecting to the first display area 100. For example, the second display area 200 is located between the first display area 100 and the third display area 300 arranged along the X direction, and one of the two edges of the second display area 200 extending along the X direction is connected to the peripheral area, and the other edge is connected to the first display area 100.

[0049] like FIG. 1 As shown, the first display area 100 includes a plurality of first light-emitting unit groups 110 and a plurality of first pixel circuit groups 120 respectively connected to the plurality of first light-emitting unit groups 110. For example, a first light-emitting unit group 110 can be connected to a first pixel circuit group 120 to drive the first light-emitting unit group 110 to emit light. The first light-emitting unit groups 110 and the first pixel circuit groups 120 that drive the first light-emitting unit groups 110 to emit light are both located in the first display area 100.

[0050] like FIG. 1As shown, the second display area 200 includes multiple second light-emitting unit groups 210 and multiple second pixel circuit groups 220, with each of the multiple second light-emitting unit groups 210 connected to the multiple second pixel circuit groups 220. For example, the second display area 200 also includes multiple third pixel circuit groups 230. For example, one second light-emitting unit group 210 can be connected to one second pixel circuit group 220 to drive the second light-emitting unit group 210 to emit light. Both the second light-emitting unit group 210 and the second pixel circuit group 220 that drives the second light-emitting unit group 210 to emit light are located in the second display area 200. For example, the third display area 300 includes multiple third light-emitting unit groups 310, with each of the multiple third light-emitting unit groups 310 connected to the multiple third pixel circuit groups 230. That is, the third light-emitting unit groups 310 located in the third display area 300 and the third pixel circuit groups 230 located in the second display area 200 are connected, and the third light-emitting unit groups 310 and the third pixel circuit groups 230 that drive the third light-emitting unit groups 310 to emit light are located in different display areas. For example, as... FIG. 1 As shown, the central area 301 of the third display area 300 is only provided with a transparent third light-emitting unit group 310, and no non-transparent pixel circuit group is provided. This central area 301 can be used as an under-screen camera area, which can have a high light transmittance to realize the camera function, and can also realize light emission by connecting with the pixel circuit group of other areas without affecting the display function of the screen.

[0051] like FIG. 1 As shown, the density of the multiple second light-emitting unit groups 210 is less than the density of the multiple first light-emitting unit groups 110. For example, the density of the multiple third light-emitting unit groups 310 is less than the density of the multiple first light-emitting unit groups 110. Since the density (i.e., pixel density) of the light-emitting unit groups in the under-display camera area (the central area of ​​the third display area) is lower than the density of the light-emitting unit groups in the normal display area (the first display area), the camera can be positioned below a low-pixel-density area that allows more light to pass through. The statement "the density of both the multiple second light-emitting unit groups 210 and the multiple third light-emitting unit groups 310 is less than the density of the multiple first light-emitting unit groups 110" means that the number of second light-emitting unit groups is less than the number of first light-emitting unit groups in the same area.

[0052] For example, the first display area 100 is a main display area, and has a high resolution (PPI, Pixel Per Inch), i.e. the first display area 100 is arranged with a high density of sub-pixels for display. Each sub-pixel includes a light emitting unit and a pixel circuit for driving the light emitting unit. The third display area 300 can allow light incident from the display substrate display side to pass through the display substrate to the back side of the display substrate, so as to enable normal operation of components such as sensors located on the back side of the display substrate. The embodiments of the present disclosure are not limited thereto, for example, the third display area 300 can also allow light emitted from the back side of the display substrate to pass through the display substrate to the display side of the display substrate. The third display area 300 and the second display area 200 also include a plurality of sub-pixels for display. However, since the pixel circuit of the sub-pixel is generally not transparent to light, in order to improve the light transmittance of the central area 301 of the third display area 300, the light emitting unit of the sub-pixel of the third display area 300 and the pixel circuit for driving the light emitting unit can be separated in physical position. For example, the pixel circuit connected with the light emitting unit group (for example FIG. 1 in the third display area 300, as shown by the block in the third display area 300) can be arranged in the second display area 200, thus occupying part of the space of the second display area 200; and the remaining space of the second display area 200 is used to arrange the pixels of the second display area 200 (including the second pixel circuit group 220 and the second light emitting unit group 210), for example, each dot filling block in the second display area 200 represents a pixel. At this time, the pixels in the second display area 200 and the third pixel circuit group 230 connected with the third light emitting unit group 310 in the third display area 300 are arranged in an array in the second display area 200. Thus, the resolutions of the third display area 300 and the second display area 200 are lower than the resolution of the first display area 100, i.e. the density of the pixels for display arranged in the third display area 300 and the second display area 200 is lower than the pixel density of the first display area 100.

[0053] FIG. 2 For FIG. 1 the equivalent diagram of the pixel circuit pair in the second pixel circuit group and the third pixel circuit group. As FIG. 2As shown, each pixel circuit group includes a plurality of pixel circuits 600. The second pixel circuit group 220 includes a plurality of first pixel circuit units 610, and each first pixel circuit unit 610 includes at least a first pixel circuit 611 and a second pixel circuit 612. For example, the first pixel circuit unit 610 can include two pixel circuits, and the first pixel circuit unit 610 can be referred to as a pixel circuit pair 610. The embodiments of the present disclosure schematically show that the first pixel circuit unit includes two pixel circuits, but are not limited thereto, and can also include three pixel circuits or more pixel circuits. For example, each light emitting unit group includes a plurality of light emitting units, the first pixel circuit group 210 includes a plurality of pixel circuits, and each pixel circuit is configured to be connected with one light emitting unit to drive the light emitting unit to emit light; the second pixel circuit group 220 includes a plurality of pixel circuit pairs 610, and each pixel circuit pair 610 of the second pixel circuit group 220 is configured to be connected with one light emitting unit to drive the light emitting unit to emit light.

[0054] For example, the third pixel circuit group 230 includes a plurality of second pixel circuit units, each second pixel circuit unit includes at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit are configured to be connected with the same light emitting unit to drive the light emitting unit to emit light. For example, the second pixel circuit unit can include two pixel circuits, and the second pixel circuit unit can also be referred to as a pixel circuit pair 610. The embodiments of the present disclosure schematically show that the second pixel circuit unit includes two pixel circuits, but are not limited thereto, and can also include three pixel circuits or more pixel circuits.

[0055] For example, the display substrate further includes a reset power supply signal line, a data line, a scanning signal line, a power supply signal line, a reset control signal line, and a light emitting control signal line on the substrate. As shown in FIG. 1, the display substrate further includes a reset power supply signal line 101, a data line 102, a scanning signal line 103, a power supply signal line 104, a reset control signal line 105, and a light emitting control signal line 106 on the substrate. FIG. 2 As shown, each pixel circuit 600 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7, a first electrode of the threshold compensation transistor T2 is connected with a first electrode of the driving transistor T3, a second electrode of the threshold compensation transistor T2 is connected with a gate electrode of the driving transistor T3, a first electrode of the first reset control transistor T7 is connected with the reset power supply signal line to receive a reset signal Vinit, a second electrode of the first reset control transistor T7 is connected with the light emitting unit, and a first electrode of the data writing transistor T4 is connected with a second electrode of the driving transistor T3. For example, as shown in FIG. 1, the first electrode of the data writing transistor T4 is connected with the data line 102, the first electrode of the driving transistor T3 is connected with the power supply signal line 104, the second electrode of the driving transistor T3 is connected with the light emitting unit, and the second electrode of the threshold compensation transistor T2 is connected with the scanning signal line 103. FIG. 2As shown, the pixel circuit of each sub-pixel further comprises a storage capacitor C, a first light emitting control transistor T6, a second light emitting control transistor T5 and a second reset transistor T1. The gate of the data writing transistor T4 is electrically connected to a scanning signal line to receive a scanning signal Gate; the first pole of the storage capacitor C is electrically connected to a power signal line, and the second pole of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the gate of the threshold value compensation transistor T2 is electrically connected to a scanning signal line to receive a compensation control signal; the gate of the first reset transistor T7 is electrically connected to a reset control signal line to receive a reset control signal Reset; the first pole of the second reset transistor T1 is electrically connected to a reset power signal line to receive a reset signal Vinit, the second pole of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the second reset transistor T1 is electrically connected to a reset control signal line to receive a reset control signal Reset; the gate of the first light emitting control transistor T6 is electrically connected to a light emitting control signal line to receive a light emitting control signal EM; the first pole of the second light emitting control transistor T5 is electrically connected to a power signal line, the second pole of the second light emitting control transistor T5 is electrically connected to the second pole of the driving transistor T3, and the gate of the second light emitting control transistor T5 is electrically connected to a light emitting control signal line to receive a light emitting control signal EM. The above-mentioned power signal line refers to a signal line outputting a voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, for example, a positive voltage signal.

[0056] For example, the scanning signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold value compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate of the data writing transistor T3 and the gate of the threshold value compensation transistor T2 can also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T3 is electrically connected to a first scanning signal line, and the gate of the threshold value compensation transistor T2 is electrically connected to a second scanning signal line, and the signals transmitted by the first scanning signal line and the second scanning signal line can be the same or different, so that the gate of the data writing transistor T3 and the gate of the threshold value compensation transistor T2 can be controlled separately, increasing the flexibility of controlling the pixel circuit.

[0057] For example, the light emitting control signals inputted by the first light emitting control transistor T6 and the second light emitting control transistor T5 can be the same, that is, the gate of the first light emitting control transistor T6 and the gate of the second light emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate of the first light emitting control transistor T6 and the gate of the second light emitting control transistor T5 can also be electrically connected to different light emitting control signal lines respectively, and the signals transmitted by different light emitting control signal lines can be the same or different.

[0058] For example, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 can be the same; that is, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to different reset control signal lines, in which case the signals on the different reset control signal lines can be the same or different.

[0059] For example, such as FIG. 2 As shown, when the display substrate is working, in the first stage of image display, the second reset transistor T1 is turned on to initialize the voltage of node N1. In the second stage, the same data signal Data is stored in the two N1 nodes of the two pixel circuits 600 through two connected data writing transistors T4, and two driving transistors T3 and two threshold compensation transistors T2 respectively connected to the two connected data writing transistors T4. In the third light-emitting stage, the second light-emitting control transistor T5, driving transistor T3 and first light-emitting control transistor T6 in the two pixel circuits 600 (i.e., the pixel circuit pair 610 composed of the first pixel circuit 611 and the second pixel circuit 612) are all turned on to transmit the same data signal to the two N4 nodes. At this time, the N4 nodes of the two pixel circuits 600 are connected and jointly drive the same light-emitting unit 20 to emit light, which can achieve the purpose of increasing current and brightness.

[0060] It should be noted that, in the embodiments of this disclosure, the pixel circuit of the sub-pixel can be, in addition to being, FIG. 2 Besides the 7T1C (seven transistors and one capacitor) structure shown, other structures with different numbers of transistors can also be used, such as 7T2C, 6T1C, 6T2C, or 9T2C structures. This disclosure does not limit the specific implementation of these structures. The goal is simply to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to enable them to jointly drive the same light-emitting unit to emit light.

[0061] FIG. 3A This is a partial planar structure diagram of the active semiconductor layer of the pixel circuit in the second display area provided according to an embodiment of this disclosure. (See diagram below.) FIG. 3AAs shown, the active semiconductor layer 3100 can be formed by patterning a semiconductor material. The active semiconductor layer 3100 can be used to form the active layers of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, and the first reset control transistor T7 described above. The active semiconductor layer 3100 includes the active layer pattern (channel region) and the doped region pattern (source / drain doped region) of each transistor of each sub-pixel, and the active layer pattern and the doped region pattern of each transistor in the same pixel circuit are integrally arranged.

[0062] It should be noted that the active layer can include an integrally formed low-temperature polysilicon layer, and the source region and the drain region can be conductorized by doping to realize electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., a source region and a drain region) and an active layer pattern, and the active layers of different transistors are separated by a doped structure.

[0063] For example, the active semiconductor layer 3100 can be made of amorphous silicon, polysilicon, oxide semiconductor material, etc. It should be noted that the source region and the drain region described above can be regions doped with n-type impurities or p-type impurities.

[0064] FIG. 3B A schematic view of the active semiconductor layer and the first conductive layer in the second display area according to an embodiment of the present disclosure is shown. The display substrate includes a gate insulating layer on the side of the active semiconductor layer away from the substrate, for insulating the active semiconductor layer 3100 described above from the first conductive layer 3200 (i.e., the gate metal layer) formed subsequently. FIG. 3B The first conductive layer 3200 included in the display substrate is shown, which is disposed on the gate insulating layer, thereby being insulated from the active semiconductor layer 3100. The first conductive layer 320 can include the second pole CC2 of the capacitor C, a plurality of scanning signal lines 430 extending in the first direction (X direction in the figure), a plurality of reset control signal lines 440, a plurality of light-emitting control signal lines 450, and the gates of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, and the first reset control transistor T7.

[0065] For example, as shown in FIG. 4, the first conductive layer 3200 includes the second pole CC2 of the capacitor C, the plurality of scanning signal lines 430, the plurality of reset control signal lines 440, the plurality of light-emitting control signal lines 450, and the gates of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, and the first reset control transistor T7. FIG. 3BAs shown, the gate of the data writing transistor T3 can be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100; the gate of the first light-emitting control transistor T6 can be the first portion where the light-emitting control signal line 450 overlaps with the active semiconductor layer 3100, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line 450 overlaps with the active semiconductor layer 3100. The gate of the second reset transistor T1 is the first portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100, and the gate of the first reset control transistor T7 is the second portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100. The threshold compensation transistor T2 can be a dual-gate thin-film transistor. The first gate of the threshold compensation transistor T2 can be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100, and the second gate of the threshold compensation transistor T2 can be the portion where the protruding structure P protruding from the scan signal line 430 overlaps with the active semiconductor layer 3100. FIG. 3B As shown, the gate of the driving transistor T1 can be the second terminal CC2 of the capacitor C.

[0066] It should be noted that, FIG. 3B The dashed rectangles in the diagram illustrate the overlapping portions of the first conductive layer 3200 and the active semiconductor layer 3100. As the channel regions of each transistor, the active semiconductor layers on both sides of each channel region are conductiveized through processes such as ion doping, serving as the first and second electrodes of each transistor. The source and drain of a transistor can be structurally symmetrical, so their physical structures can be indistinguishable. In embodiments of this disclosure, to distinguish transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode, and the other as the second electrode. Therefore, in embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0067] For example, such as FIG. 3B As shown, the scan signal line 430, reset control signal line 440, and light emission control signal line 450 are arranged along the second direction (Y direction). The scan signal line 430 is located between the reset control signal line 440 and the light emission control signal line 450. In this embodiment, the first direction and the second direction are intersecting directions, for example, the first direction is perpendicular to the second direction. In this embodiment, the first direction and the second direction can be interchanged.

[0068] For example, in the second direction, the second terminal CC2 of capacitor C (i.e., the gate of driving transistor T1) is located between scan signal line 430 and light emission control signal line 450. The protruding structure P protruding from scan signal line 430 is located on the side of scan signal line 430 away from light emission control signal line 450.

[0069] For example, a first insulating layer is formed on the first conductive layer 3200 described above, so as to insulate the first conductive layer 3200 described above from a second conductive layer 3300 to be formed subsequently.

[0070] FIG. 3C A partial planar structure schematic diagram of a second conductive layer in a second display area according to an embodiment of the present disclosure is provided as follows, FIG. 3D A schematic diagram of an active semiconductor layer, a first conductive layer and a second conductive layer in a second display area according to an embodiment of the present disclosure is provided as follows. As FIG. 3C to FIG. 3D The second conductive layer 330 includes a first pole CC1 of a capacitor C and a plurality of reset power signal lines 410 extending in a first direction. The first pole CC1 of the capacitor C at least partially overlaps with a second pole CC2 of the capacitor C to form the capacitor C.

[0071] As FIG. 3C to FIG. 3D The display substrate provided by the embodiment of the present disclosure further includes a plurality of first connection portions 510. A first end of at least part of the first connection portions 510 is connected to a second pole of a data writing transistor T4 of a first pixel circuit 611 in a first pixel circuit unit, a second end of the first connection portion 510 is connected to a second pole of a data writing transistor T4 of a second pixel circuit 612 in the first pixel circuit unit, so that at least two data writing transistors T4 of the first pixel circuit unit are connected to the same data line, and in the second direction, the first connection portion 510 is located between the second pole of the data writing transistor T2 in the first pixel circuit 611 and the first pole of the first reset control transistor T7.

[0072] In the embodiment of the present disclosure, the second poles of the data writing transistors of the at least two pixel circuits in the second display area are connected through the first connection portion to drive one light emitting unit to emit light, which can increase the current and brightness of the light emitting unit of the second display area, for example, the current and brightness of the light emitting unit of the second display area can be increased to 1.8 to 2 times of the case of being driven by one pixel circuit, thereby solving the problem of small current and brightness in the second display area and realizing more uniform visual display effect of the full-screen.

[0073] For example, the first end of the first connection part 510 is connected to the second electrode of the data write transistor T4 of the third pixel circuit in the second pixel circuit unit, and the second end of the first connection part 510 is connected to the second electrode of the data write transistor T4 of the fourth pixel circuit in the second pixel circuit unit, so that at least two data write transistors T4 of the second pixel circuit unit are connected to the same data line, and along the second direction, the first connection part 510 is located between the second electrode of the data write transistor T2 and the first electrode of the first reset control transistor T7 in the third pixel circuit. For the convenience of subsequent description, the first pixel circuit unit and the second pixel circuit unit in the present disclosure are collectively referred to as a pixel circuit pair, and the two pixel circuits included in each pixel circuit unit are collectively referred to as a first pixel circuit and a second pixel circuit, that is, the third pixel circuit in the second pixel circuit unit can be referred to as the first pixel circuit, and the fourth pixel circuit in the second pixel circuit unit can be referred to as the second pixel circuit.

[0074] For example, along the second direction, the first connection part 510 is located between the second electrode of the threshold compensation transistor T3 and the first electrode of the first reset control transistor T7 in the first pixel circuit 611.

[0075] For example, the first connection part 510 is arranged on the same layer as the reset power supply signal line 410.

[0076] For example, a second insulating layer is formed on the second conductive layer 3300 described above, for insulating the second conductive layer 3300 described above from the source-drain metal layer 3400 to be formed subsequently.

[0077] For example, FIG. 3E A partial planar structure schematic diagram of the source-drain metal layer of the second display area according to an embodiment of the present disclosure is shown in FIG. 7. FIG. 3F A schematic diagram of the active semiconductor layer, the first conductive layer, the second conductive layer, and the source-drain metal layer in the second display area according to an embodiment of the present disclosure is shown in FIG. 8. As shown in FIG. 8, the source-drain metal layer 3400 includes a data line 420 and a power supply signal line 460 extending along the second direction. The data line 420 is electrically connected to the second electrode of the data write transistor T2 through a via hole penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer. The power supply signal line 460 is electrically connected to the first electrode of the second light-emitting control transistor T5 through a via hole penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer. The power supply signal line 460 and the data line 420 are arranged alternately along the first direction. The power supply signal line 460 is electrically connected to the first electrode CC1 of the capacitor C through a via hole penetrating through the second insulating layer. FIG. 3E to FIG. 3F For example, a passivation layer and a planarization layer can be arranged on the side of the source-drain metal layer 3400 away from the substrate, for protecting the source-drain metal layer 3400.

[0078] For example, a passivation layer and a planarization layer can be arranged on the side of the source-drain metal layer 3400 away from the substrate, for protecting the source-drain metal layer 3400.

[0079] For example, FIG. 3D to FIG. 3F The second pixel circuit group 220 and the third pixel circuit group 230 are schematically shown as including pixel circuit pairs each including a first pixel circuit 611 and a second pixel circuit 612 arranged along the first direction, and the second electrodes of the data write transistors T4 of the two pixel circuits in each pixel circuit pair are connected by the first connection part 510 to drive the same light emitting unit to emit light. The present embodiment is not limited thereto, and for example, only the second pixel circuit group can include the pixel circuit pairs, or only the third pixel circuit group can include the pixel circuit pairs.

[0080] For example, as shown in FIG. 6, the second pixel circuit group 220 and the third pixel circuit group 230 can include eight pixel circuits arranged in two rows, i.e., four pixel circuit pairs arranged in a two-dimensional array. The first pixel circuit group does not include the pixel circuit pairs (not shown) and only includes four pixel circuits arranged in a two-dimensional array, and each of the two adjacent pixel circuits in the first pixel circuit group along the first direction drives one light emitting unit to emit light, and the two data write transistors in the two adjacent pixel circuits are independent of each other and connected to different data lines. The main difference between the layout of the first pixel circuit group and the layout of the second pixel circuit group in the present embodiment is whether the first connection part is provided and the position of the second electrode of the data write transistor connected to the first connection part. FIG. 3D to FIG. 3F

[0081] For example, as shown in FIG. 6, the second pixel circuit group 220 and the third pixel circuit group 230 can include eight pixel circuits arranged in two rows, i.e., four pixel circuit pairs arranged in a two-dimensional array. The first pixel circuit group does not include the pixel circuit pairs (not shown) and only includes four pixel circuits arranged in a two-dimensional array, and each of the two adjacent pixel circuits in the first pixel circuit group along the first direction drives one light emitting unit to emit light, and the two data write transistors in the two adjacent pixel circuits are independent of each other and connected to different data lines. The main difference between the layout of the first pixel circuit group and the layout of the second pixel circuit group in the present embodiment is whether the first connection part is provided and the position of the second electrode of the data write transistor connected to the first connection part. FIG. 3D to FIG. 3F ​As shown, the display substrate provided in this embodiment can adopt a quarter-high resolution (QHD). However, since the distance along the second direction between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in each pixel circuit designed with this resolution is very small, for example, less than 2 micrometers, or for example, 1.4 to 1.8 micrometers, it is difficult to set the first connection portion between the second electrode of the two data write transistors (data input nodes) of the pixel circuit pair and the first electrode of the threshold compensation transistor and the first electrode of the first reset control transistor. Since the pixel size in QHD resolution products is generally smaller than the pixel size in full-screen resolution (FHD) products, in this embodiment, the pixel circuit with QHD resolution is designed into the pixel pitch with FHD resolution, thereby increasing the distance along the second direction between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 in each pixel circuit, so as to ensure that the data input nodes of the two pixel circuits of the pixel circuit pair are connected by a hole through the first connection portion.

[0082] For example, such as FIG. 3A to FIG. 3F As shown, relative to a display substrate, its second display area includes multiple light-emitting units and multiple pixel circuits connected one-to-one with the multiple light-emitting units. In the case where dummy pixel circuits that are not connected to any light-emitting units are set between adjacent pixel circuits, in this embodiment of the present disclosure, a first connecting part is used to connect the dummy pixel circuits and the pixel circuits that connect the light-emitting units in the second display area. This can effectively utilize the dummy pixel circuits while minimizing changes to the overall structure of the pixel circuits, thereby increasing the current and brightness of the light-emitting units in the second display area (and at least one of the third display areas), and achieving a more uniform full-screen visual display effect.

[0083] For example, the distance between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 along the second direction is 7 to 12 micrometers so that a first connection portion 510 is provided between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7.

[0084] For example, such as FIG. 3A to FIG. 3FAs shown, each pixel circuit further includes a second connection portion 520 and a third connection portion 530 disposed on the same layer as the data line 420. The second connection portion 520 is configured to connect the second terminal of the threshold compensation transistor T2 and the gate of the driving transistor T3. The third connection portion 530 is configured to connect the first terminal of the first reset control transistor T7 and the reset power supply signal line 410. For example, one end of the second connection portion 520 is electrically connected to the second terminal of the threshold compensation transistor T2 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of the second connection portion 520 is electrically connected to the gate of the driving transistor T3 (i.e., the second terminal CC2 of capacitor C) through a via penetrating the first insulating layer and the second insulating layer. One end of the third connection portion 530 is electrically connected to the reset power supply signal line 410 through a via penetrating the second insulating layer. The other end of the third connection portion 530 is electrically connected to the first terminal of the first reset control transistor T7 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer.

[0085] For example, such as FIG. 3A to FIG. 3F As shown, in the first pixel circuit 611, the distance in the second direction between the adjacent edges of the second connecting portion 520 and the third connecting portion 530 is 7 to 12 micrometers so that the first connecting portion 510 is disposed between the second connecting portion 520 and the third connecting portion 530. For example, in the first pixel circuit 611, the distance in the second direction between the adjacent edges of the second connecting portion 520 and the third connecting portion 530 can be 8 to 11 micrometers.

[0086] For example, such as FIG. 3A to FIG. 3F As shown, the first connection portion 510 and the data line 420 are located on different layers and are perpendicular to the substrate in a third direction. Each first connection portion 510 overlaps with the data line 420 and the power signal line 460. For example, a data line 410 and a power signal line 460 are provided between the two data writing transistors T4 included in the pixel circuit pair 610, and the first connection portion 510 connecting the two data writing transistors T4 overlaps with both the data line 410 and the power signal line 460.

[0087] For example, such as FIG. 1As shown, each pixel circuit further comprises a fourth connecting part 540 disposed in the same layer as the data line 420, the fourth connecting part 540 is configured to connect the first connecting part 510 and the second electrode of the data writing transistor T4, the fourth connecting part 540 of one of the pair of pixel circuits 610 (for example, the second pixel circuit 612) has a spacing with the adjacent data line 420, the fourth connecting part 540 of the other of the pair of pixel circuits 610 (for example, the first pixel circuit 611) is integrated with the data line 420 to realize that the pair of pixel circuits 610 is connected with only one data line 420. In the above-mentioned “the fourth connecting part 540 has a spacing with the adjacent data line 420”, the “adjacent data line” means that there is no other data line between the fourth connecting part 540 and the data line 420.

[0088] For example, as shown in FIG. 6, the first connecting part 510 of the pair of pixel circuits 610 is connected with the data line 420. FIG. 3A to FIG. 3F 、 FIG. 3E As shown, the plurality of first pixel circuit groups 210 are arranged in an array along the first direction and the second direction. Along the first direction, the plurality of second pixel circuit groups 220 and the plurality of third pixel circuit groups 230 are arranged alternately, along the second direction, the plurality of second pixel circuit groups 220 and the plurality of third pixel circuit groups 230 are arranged alternately, and the second pixel circuit groups 220 and the third pixel circuit groups 230 are connected with different data lines 420.

[0089] For example, a straight line extending along the first direction passes through the second electrodes of the two data writing transistors in the pair of pixel circuits, and the whole of the first connecting part extends along the first direction. For example, different pixel circuit groups are connected with different data lines, so the length of the first connecting part along the first direction in different pixel circuit groups can be different. For example, in the same pixel circuit group, the length of the first connecting part along the first direction in different pairs of pixel circuits can also be different.

[0090] For example, as shown in FIG. 6, the first connecting part 510 of the pair of pixel circuits 610 is connected with the data line 420. FIG. 3A to FIG. 3FAs shown, the fourth connecting portion 540 integrated with the data line 420 is designated as the first sub-part 541, and the fourth connecting portion 540 spaced from the adjacent data line 420 is designated as the second sub-part 542. Taking a second pixel circuit group comprising eight pixel circuits arranged in an array (four pixel circuits arranged along the row direction and two pixel circuits arranged along the column direction) as an example, in the second pixel circuit group, two first sub-parts 541 are arranged along the second direction (e.g., in one column), and two second sub-parts 542 are arranged along the second direction (e.g., in one column), with the first sub-parts 541 and second sub-parts 542 alternating in the first direction (e.g., in the row direction). Similarly, the arrangement of the first and second sub-parts in the third pixel circuit group is the same as that in the second pixel circuit group. For the second and third pixel circuit groups that alternate along the second direction, the first sub-parts in the second pixel circuit group and the second sub-parts in the third pixel circuit group are located in different columns so that the second pixel circuit group and the third pixel circuit group are connected to different data lines.

[0091] Since there are no pixel circuit pairs in the first pixel circuit group, the fourth connection part of each of the two adjacent pixel circuits arranged along the first or second direction in the first pixel circuit group is integrated with the data line to realize the electrical connection between each pixel circuit and the corresponding data line.

[0092] For example, such as FIG. 3A to FIG. 3F As shown, the display substrate also includes a plurality of cover portions S disposed on the same layer as the first connection portion 510. Each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2 and an active semiconductor layer 3100 located between the two gates. Along the third direction, the cover portions S overlap with the active semiconductor layer 3100 between the two gates, the data line 420, and the power signal line 460.

[0093] For example, the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is off. This makes it susceptible to voltage fluctuations due to surrounding lines, which can affect the leakage current of the threshold compensation transistor T2 and consequently its luminous brightness. To maintain a stable voltage in the active semiconductor layer between the two channels of the threshold compensation transistor T2, a capacitor is formed between the cover portion S and the active semiconductor layer between the two channels of the threshold compensation transistor T2. The cover portion S can be connected to the power signal line 460 to obtain a constant voltage, thus ensuring a stable voltage for the floating active semiconductor layer. The overlap between the cover portion S and the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 also prevents the active semiconductor layer between the two gates from being illuminated and altering its characteristics, such as preventing voltage changes in this portion of the active semiconductor layer to prevent crosstalk. For example, the power signal line 460 can be electrically connected to the cover portion S through a via penetrating the second insulating layer to provide a constant voltage to the cover portion S.

[0094] For example, the orthographic projection of the cover portion S overlapping with the active semiconductor layer on a first straight line extending in the first direction overlaps with the orthographic projection of the first connecting portion 510 on the first straight line, and the orthographic projection of the fourth connecting portion 540 on a second straight line extending in the second direction overlaps with the orthographic projection of the cover portion S on the second straight line. Thus, in order to maintain a distance from the cover portion S disposed in the same layer, the first connecting portion 510 is configured as a non-linear type, such as a broken line type.

[0095] For example, such as FIG. 4A As shown, the first connecting portion 510 includes a main connecting portion 511 extending along a first direction and two end portions 512 located at both ends of the main connecting portion 511 and extending along a second direction. The two end portions 512 are respectively connected to the two fourth connecting portions 540 of the pixel circuit pair 610. The orthographic projections of the two end portions 512 on the second straight line overlap with the orthographic projections of the cover portion S on the second straight line. Thus, the main connecting portion and the two end portions form a zigzag shape to maintain a distance from the cover portion.

[0096] For example, in the second direction, the distance between the cover portion S and the second electrode of the threshold compensation transistor T2 is less than the distance between the cover portion S and the first electrode of the first reset control transistor T7, that is, the cover portion S is closer to the threshold compensation transistor T2. Therefore, for ease of design and to maintain a certain distance between the first connection portion 510 and the cover portion S, the first connection portion 510 is set to be closer to the first electrode of the first reset transistor T7, that is, in the Y direction, the distance between the main body connection portion 511 and the second electrode of the threshold compensation transistor T2 in the first pixel circuit 611 is greater than the distance between the main body connection portion 511 and the first electrode of the first reset control transistor T7 in the first pixel circuit 611.

[0097] For example, FIG. 4B This is a schematic diagram showing the connection relationship between the second light-emitting unit group and the second pixel circuit group in the second display area according to an embodiment of this disclosure. FIG. 4A for FIG. 1 to FIG. 4B A schematic layer structure diagram of one light-emitting unit. (See diagram below.) FIG. 1 to FIG. 4B As shown, each light-emitting unit group includes multiple light-emitting units 20. For example, each light-emitting unit group includes a first-color light-emitting unit 201, a second-color light-emitting unit pair 202, and a third-color light-emitting unit 203. The first-color light-emitting unit 201 and the third-color light-emitting unit 203 are arranged along a second direction. The second-color light-emitting unit pair 202 includes two second-color light-emitting units arranged along the second direction. There are also first light-emitting unit blocks 202-1 and second light-emitting unit blocks 202-2. The first-color light-emitting unit 201 and the second-color light-emitting unit pair 202 are arranged along a first direction. For example, the orthographic projection of the second electrode of the first-color light-emitting unit 201 onto a straight line extending along the Y direction overlaps with the orthographic projection of the second electrode of the first light-emitting unit block 202-1 onto that straight line; the orthographic projection of the second electrode of the third-color light-emitting unit 203 onto that straight line overlaps with the orthographic projection of the interval between the second electrodes of the two second-color light-emitting units onto that straight line. For example, the orthographic projection of the main electrode of the third color light-emitting unit 203 (described later) onto a straight line extending in that direction does not overlap with the orthographic projection of the main electrodes of the two second color light-emitting units onto the same straight line.

[0098] For example, each light emitting unit 20 includes a first electrode 21, a light emitting layer 23, and a second electrode 22 arranged in this order in a direction perpendicular to the substrate base plate 10, and the second electrode 12 is located on the side of the light emitting layer 13 facing the substrate base plate 10. The display substrate further includes a pixel defining layer 24 including an opening for defining a light emitting region of a sub-pixel, the opening exposing the second electrode 22 of the light emitting unit 20, and when the light emitting layer 23 of a subsequent light emitting unit 20 is formed in the opening of the pixel defining layer 24, the light emitting layer 23 is in contact with the second electrode 22, so that this part can drive the light emitting layer 23 to emit light to form an effective light emitting region. The "effective light emitting region" here can refer to a two-dimensional planar region parallel to the substrate base plate. It should be noted that due to process reasons, the size of the opening of the pixel defining layer away from the substrate base plate is slightly larger than that close to the substrate base plate, or gradually increases from the side close to the substrate base plate to the side away from the substrate base plate, so the size of the effective light emitting region may be slightly different from the size of the opening of the pixel defining layer at different positions, but the overall area shape and size are basically equivalent. For example, the orthographic projection of the effective light emitting region on the substrate base plate substantially coincides with the orthographic projection of the opening of the corresponding pixel defining layer on the substrate base plate. For example, the orthographic projection of the effective light emitting region on the substrate base plate is completely within the orthographic projection of the opening of the corresponding pixel defining layer on the substrate base plate, and the shapes are similar, and the projection area of the effective light emitting region on the substrate base plate is slightly smaller than the projection area of the opening of the corresponding pixel defining layer on the substrate base plate.

[0099] For example, the first color light emitting unit can be one of a red light emitting unit and a blue light emitting unit, the third color light emitting unit is the other of the red light emitting unit and the blue light emitting unit, and the second color light emitting unit is a pair of green light emitting units. The present disclosure schematically shows that the first color light emitting unit is a red light emitting unit and the second color light emitting unit is a green light emitting unit.

[0100] For example, as FIG. 1 to FIG. 4BAs shown, each pixel circuit further includes a fifth connection part 550 disposed in the same layer as the data line 420, and the second electrode 22 of the light emitting unit 20 in the first display area 100 and the second display area 200 can be directly electrically connected to the second electrode of the first light emitting control transistor T6 through the fifth connection part 550. For example, in the first display area 100, the second electrode of each light emitting unit 20 in the first light emitting unit group 110 can be directly electrically connected to the second electrode of the first light emitting control transistor T6 through the fifth connection part 550 of the corresponding pixel circuit 600 in the first pixel circuit group 120. In the second display area 200, the second electrode of each light emitting unit 20 in the second light emitting unit group 210 can be directly electrically connected to the second electrode of the first light emitting control transistor T6 through the fifth connection part 550 of the corresponding pixel circuit 600 in the second pixel circuit group 220. For example, in the second display area 200, the second electrode of each light emitting unit 20 in the second light emitting unit group 210 can be connected to the fifth connection part 550 through the first via hole 561 in the passivation layer and the planarization layer.

[0101] For example, as shown in FIG. 6, the display substrate further includes a plurality of transparent wires 700 between the second electrode 22 and the film layer in which the data line 420 is disposed, and each transparent wire 700 extends in the first direction. For example, the third pixel circuit group 230 includes a plurality of pixel circuit pairs 610, and the transparent wire 700 is configured to connect the second electrode 22 of the light emitting unit 20 in the third light emitting unit group 310 and the fifth connection part 550 to electrically connect the second electrode 22 of each light emitting unit 20 in the third light emitting unit group 310 to the second electrodes of the two first light emitting control transistors T6 in the pixel circuit pair 610 of the third pixel circuit group 230. FIG. 1 to FIG. 4B For example, as shown in FIG. 6, the display substrate further includes a plurality of transparent wires 700 between the second electrode 22 and the film layer in which the data line 420 is disposed, and each transparent wire 700 extends in the first direction. For example, the third pixel circuit group 230 includes a plurality of pixel circuit pairs 610, and the transparent wire 700 is configured to connect the second electrode 22 of the light emitting unit 20 in the third light emitting unit group 310 and the fifth connection part 550 to electrically connect the second electrode 22 of each light emitting unit 20 in the third light emitting unit group 310 to the second electrodes of the two first light emitting control transistors T6 in the pixel circuit pair 610 of the third pixel circuit group 230.

[0102] FIG. 4C For example, as shown in FIG. 6, the display substrate further includes a plurality of transparent wires 700 between the second electrode 22 and the film layer in which the data line 420 is disposed, and each transparent wire 700 extends in the first direction. For example, the third pixel circuit group 230 includes a plurality of pixel circuit pairs 610, and the transparent wire 700 is configured to connect the second electrode 22 of the light emitting unit 20 in the third light emitting unit group 310 and the fifth connection part 550 to electrically connect the second electrode 22 of each light emitting unit 20 in the third light emitting unit group 310 to the second electrodes of the two first light emitting control transistors T6 in the pixel circuit pair 610 of the third pixel circuit group 230.

[0103] For example, in the second display area 200, the transparent wire 700 is electrically connected to the fifth connection part 550 in the third pixel circuit group 310 through the second via hole 562 in the passivation layer and the planarization layer; and in the third display area 300, the second electrode 22 of the light emitting unit 20 is connected to the transparent wire 700 through the third insulating layer between the transparent wire 700 and the second electrode 22, thereby realizing the connection with the pixel circuit 600 in the second display area 200.

[0104] For example, as shown in FIG. 6, the display substrate further includes a plurality of transparent wires 700 between the second electrode 22 and the film layer in which the data line 420 is disposed, and each transparent wire 700 extends in the first direction. For example, the third pixel circuit group 230 includes a plurality of pixel circuit pairs 610, and the transparent wire 700 is configured to connect the second electrode 22 of the light emitting unit 20 in the third light emitting unit group 310 and the fifth connection part 550 to electrically connect the second electrode 22 of each light emitting unit 20 in the third light emitting unit group 310 to the second electrodes of the two first light emitting control transistors T6 in the pixel circuit pair 610 of the third pixel circuit group 230. FIG. 4A For​FIG. 4A A schematic view of the positional relationship between the second light emitting unit group of the second display area and the via. FIG. 4C And FIG. 5D As shown, a plurality of first vias 561 connecting one second light emitting unit group 210 and one second pixel circuit group 220 form a first via group 5610, and a plurality of second vias 562 connecting one third light emitting unit group 310 and one third pixel circuit group 230 form a second via group 5620. Along the first direction, the plurality of first via groups 5610 and the plurality of second via groups 5620 are arranged alternately; along the second direction, the plurality of first via groups 5610 and the plurality of second via groups 5620 are arranged alternately. In the embodiment of the present disclosure, the second electrode of the light emitting unit of the second light emitting unit group is directly connected to the fifth connection part, and the second electrode of the light emitting unit of the third light emitting unit group is connected to the fifth connection part through the transparent trace, compared with the case that the second light emitting unit group and the third light emitting unit group are both connected to the fifth connection part through the transparent trace on the film layer where the transparent trace is located, which can leave more space for the transparent trace and prevent signal crosstalk.

[0105] For example, FIG. 1 As shown in the partial plan view of the first display area and the second display area in the display substrate, FIG. 1 As shown, FIG. 5D And FIG. 1 As shown in the embodiment of the present disclosure, the first display area 100 and the second display area 200 in the display substrate include a plurality of pixel circuits 030 arranged along the first direction and the second direction to form a plurality of pixel circuit columns 32 and a plurality of pixel circuit rows 31. The plurality of pixel circuits 030 located in the first display area 100 include a plurality of first sub-pixel circuits 031, and the plurality of pixel circuits 030 located in the second display area 200 include a plurality of second sub-pixel circuits 032. The plurality of first light emitting units (i.e. the three color light emitting units included in the first light emitting unit group 110, such as R, G1, G2, B shown in the figure) of the first display area 100 are connected to the plurality of first sub-pixel circuits 031 one by one, and each second light emitting unit (i.e. the three color light emitting units included in the second light emitting unit group 210, such as R, G1, G2, B shown in the figure) of the second display area 200 is connected to at least two second sub-pixel circuits 032.

[0106] For example, as shown in the partial plan view of the first display area 100 and the second display area 200, FIG. 1 The third display area 300 includes a center area 301 and an edge area 302 surrounding the center area 301, and the edge area 302 of the third display area 300 is connected to the first display area 100 in the Y direction. For example, FIG. 1The diagram schematically shows that the third display area 300 is rectangular in shape, and the central area 301 of the third display area 300 is circular in shape. The edge area 302 is the area located within the rectangle excluding the central circular area. This embodiment is not limited to this; the shapes of the central and edge areas of the third display area can be set according to actual product requirements.

[0107] For example, such as FIG. 1 As shown, both the central area 301 and the edge area 302 of the third display area 300 are provided with third light-emitting unit groups 310. Multiple third light-emitting unit groups 310 located in the third display area 300 are electrically connected to multiple third pixel circuit groups 230 in the second display area 200 via transparent traces 700 to drive the third light-emitting unit groups 310 to emit light. The central area 301 of the third display area 300 only has light-emitting unit groups and no pixel circuit groups, thereby reducing the metal coverage area and achieving higher light transmittance. The edge area 302 of the third display area 300, in addition to having light-emitting unit groups, also has a light-blocking structure so that the third display area 300 forms a light-transmitting area (i.e., the central area 301) with a preset shape. For example, in this embodiment, the light-blocking structure disposed in the peripheral area 302 of the third display area 300 can be multiple dummy pixel circuit groups 320. Each dummy pixel circuit group 320 includes a portion located between the third light-emitting unit group 310 and the substrate, and a portion spaced between adjacent third light-emitting unit groups 310. Each dummy pixel circuit group 320 is not connected to any light-emitting unit group and is merely a suspended pixel circuit. For example, the edge area 302 is a ring-shaped trace area. For example, data lines, scan signal lines, power signal lines, reset control lines, light-emitting control signal lines, and reset power signal lines connecting the third pixel circuit groups are all located in the ring-shaped trace area.

[0108] For example, such as FIG. 1 As shown, the third light-emitting unit group 310 in the third display area 300 can be controlled in a left-right half-control manner, with the third pixel circuit groups 230 in the two second display areas 200 that are symmetrical about the center line extending along the Y direction of the third display area 300 being controlled separately. For example, the third light-emitting unit group 310 located to the left of the center line is controlled by the third pixel circuit group 230 in the second display area 200 located to the left of the center line, and the third light-emitting unit group 310 located to the right of the center line is controlled by the third pixel circuit group 230 in the second display area 200 located to the right of the center line. The traces used to drive the light-emitting units in the circular central area 301 are arranged in a dense manner in the edge area 302, so that the circular central area 301, which serves as the under-screen display area, can have a maximum area.

[0109] For example, such as FIG. 1 to FIG. 4AAs shown, the first display area 100 and the second display area 200 include a plurality of pixel circuits arranged along a first direction and a second direction to form a plurality of pixel circuit columns 32 and a plurality of pixel circuit rows 31. For example, the edge area 302 of the third display area 300 includes a plurality of dummy pixel circuits 034 arranged along a first direction and a second direction to form a plurality of dummy pixel circuit columns and a plurality of dummy pixel circuit rows. Here, the dummy pixel circuits in the third display area 300 are also referred to as pixel circuits. Although the dummy pixel circuits are not connected to any light-emitting unit, their structure can be roughly the same as the pixel circuit structure of other areas, for example, all including a 7T1C (i.e., seven transistors and one capacitor) structure. For example, multiple data lines 420 extending along the Y direction are respectively connected to the plurality of pixel circuit columns 32.

[0110] For example, such as FIG. 1 to FIG. 4A As shown, each pixel circuit column 32 includes a pixel circuit column group consisting of four adjacent columns. Each pixel circuit column group includes a first pixel circuit column 321, a second pixel circuit column 322, a third pixel circuit column 323, and a fourth pixel circuit column 324 arranged sequentially along the X direction (i.e., the direction intersecting with the extension direction of the data line 420). The first pixel circuit column 321, the second pixel circuit column 322, the third pixel circuit column 323, and the fourth pixel circuit column 324 within the first display area 100 are respectively connected to the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 arranged sequentially along the X direction. At least some of the pixel circuits in the first pixel circuit column 321, at least some of the pixel circuits in the second pixel circuit column 322, at least some of the pixel circuits in the third pixel circuit column 323, and at least some of the pixel circuits in the fourth pixel circuit column 324 in the second display area 200 are respectively connected to the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 arranged sequentially along the X direction.

[0111] For example, such as FIG. 1 to FIG. 4A As shown, within the second display area 200, in at least one pixel circuit column group, the data output terminals (i.e., the fourth connection portion 540) of two pixel circuits located in the same pixel circuit row 31 and located in the first pixel circuit column 321 and the second pixel circuit column 322 are electrically connected to form a first pixel circuit pair 601, and the data output terminals (i.e., the fourth connection portion 540) of two pixel circuits 600 located in the same pixel circuit row 31 and located in the third pixel circuit column 323 and the fourth pixel circuit column 324 are electrically connected to form a second pixel circuit pair 602. This embodiment of the present disclosure is illustrated by example where each pixel circuit column group in the second display area includes a first pixel circuit pair and a second pixel circuit pair, but it is not limited to this and can be configured according to actual product requirements.

[0112] For example, such as FIG. 1 to FIG. 4AThe first display area 100, the second display area 200, and the third display area 300 each include a plurality of light emitting units 20. The plurality of light emitting units 20 in the first display area 100 are respectively connected to the plurality of pixel circuits 600 of the first display area 100. The plurality of light emitting units 20 of the second display area 200 are respectively connected to a part of the pixel circuits 600 of the second display area 200, and the plurality of light emitting units 20 of the third display area 300 are respectively connected to another part of the pixel circuits 600 of the second display area 200. That is, in the second display area 200, the light emitting units 20 in the second light emitting unit group 210 are connected to the pixel circuits 600 in the second pixel circuit group 220; the light emitting units 20 in the third light emitting unit group 310 in the third display area 300 are connected to the pixel circuits 600 in the third pixel circuit group 230 in the second display area 200. The embodiments of the present disclosure schematically show that the second display area includes only the second pixel circuit group and the third pixel circuit group, but are not limited thereto. According to factors such as space design requirements in the product, the second display area can also include other pixel circuit groups, for example, a dummy pixel circuit group (not connected to the light emitting unit) and the like.

[0113] For example, as shown in FIG. 2, the second pixel circuit group 220 and the third pixel circuit group 230 in the second display area 200 each include a first pixel circuit pair 601 and a second pixel circuit pair 602. Therefore, in the second display area 200 and the third display area 300, the plurality of light emitting units 20 are respectively connected to the plurality of first pixel circuit pairs 601 and the plurality of second pixel circuit pairs 602 in the second display area 200. FIG. 1 to FIG. 4A

[0114] For example, the light emitting units provided in the first display area in the embodiments of the present disclosure can be referred to as first light emitting units, the light emitting units provided in the second display area can be referred to as second light emitting units, and the light emitting units provided in the third display area can be referred to as third light emitting units.

[0115] ​Because the second pixel circuit group 220 and the third pixel circuit group 230 are arranged alternately in both the X and Y directions, and the second pixel circuit group 220 and the third pixel circuit group 230 arranged in the same column along the Y direction are connected to different data lines 420, some pixel circuits in the first pixel circuit column 321 located in the second display area 200 are connected to the first data line 421. For example, the pixel circuits in the second pixel circuit group 220 located in the first pixel circuit column 321 are connected to the first data line 421, while the pixel circuits in the third pixel circuit group 230 located in the first pixel circuit column 321 are not connected to the first data line 421. Similarly, some pixel circuits in the second pixel circuit column 322 located in the second display area 200 are connected to the second data line 422. For example, the pixel circuits in the third pixel circuit group 230 located in the second pixel circuit column 322 are connected to the second data line 422, while the pixel circuits in the second pixel circuit group 220 located in the second pixel circuit column 322 are not connected to the second data line 422. Some pixel circuits in the third pixel circuit column 323 located within the second display area 200 are connected to the third data line 423. For example, the pixel circuits in the third pixel circuit group 230 within the third pixel circuit column 323 are connected to the third data line 423, while the pixel circuits in the second pixel circuit group 220 within the third pixel circuit column 323 are not connected to the third data line 423. Some pixel circuits in the fourth pixel circuit column 324 located within the second display area 200 are connected to the fourth data line 424. For example, the pixel circuits in the second pixel circuit group 220 within the fourth pixel circuit column 324 are connected to the fourth data line 422, while the pixel circuits in the third pixel circuit group 230 within the fourth pixel circuit column 324 are not connected to the fourth data line 424.

[0116] For example, such as FIG. 1 to FIG. 4A As shown, multiple first pixel circuit pairs 601 connected to multiple light-emitting units 20 of the second display area 200 are connected to the first data line 421, multiple second pixel circuit pairs 602 connected to multiple light-emitting units 20 of the second display area 200 are connected to the fourth data line 424, multiple first pixel circuit pairs 601 connected to multiple light-emitting units 20 of the third display area 300 are connected to the second data line 422, and multiple second pixel circuit pairs 601 connected to multiple light-emitting units 20 of the third display area 300 are connected to the third data line 423.

[0117] For example, in the second pixel circuit group 220, the two pixel circuits in the first pixel circuit pair 601 are connected with the first data line 421, and the two pixel circuits in the second pixel circuit pair 602 are connected with the fourth data line 424. In the third pixel circuit group 230, the two pixel circuits in the first pixel circuit pair 601 are connected with the second data line 422, and the two pixel circuits in the second pixel circuit pair 602 are connected with the third data line 423.

[0118] For example, as shown in FIG. 6, the first pixel circuit pair 601 connected with the first color light emitting unit 201 and the third color light emitting unit 203 in the second light emitting unit group 210 is connected with the first data line 421, and the second pixel circuit pair 602 connected with the second color light emitting unit pair 202 in the second light emitting unit group 210 is connected with the fourth data line 424. FIG. 5A

[0119] FIG. 5B A schematic diagram of the film layer structure of the data line connection part at the position shown in FIG. 8 is shown in FIG. 9. FIG. 5A A schematic diagram of the film layer structure of the data line at the position shown in FIG. 8 is shown in FIG. 10. FIG. 5C A schematic diagram of the film layer structure of the data line at the position shown in FIG. 8 is shown in FIG. 10. FIG. 5A A schematic diagram of the film layer structure of the data line at the position shown in FIG. 8 is shown in FIG. 10. FIG. 1 to FIG. 5D A schematic diagram of the film layer structure of the data line at the position shown in FIG. 8 is shown in FIG. 10. FIG. 5A ​As shown, at the junction of the first display area 100 and the second display area 200, i.e. at the interval between the first sub-pixel circuit 031 and the second sub-pixel circuit 032, the second data line 422, the third data line 423 and the fourth data line 424 connected with the at least one pixel circuit column group are disconnected to form a first disconnection 4201, and the first data line 421 remains continuous without disconnection. That is, the part of the second data line 422 located in the second display area 200 is not connected with the part located in the first display area 100 at the junction of the first display area 100 and the second display area 200. Similarly, the part of the third data line 423 located in the second display area 200 is not connected with the part located in the first display area 100 at the junction of the first display area 100 and the second display area 200; the part of the fourth data line 424 located in the second display area 200 is not connected with the part located in the first display area 100 at the junction of the first display area 100 and the second display area 200. The part of the second data line 422 located in the first display area 100 is connected to the part of the fourth data line 424 located in the second display area 200 near the end point 4240 of the first display area 100 through a data line connection part 560, and the data line connection part 560 passes through the first disconnection 4201 of the third data line 423. Here, the first data line 421, the second data line 422, the third data line 423 and the fourth data line 424 can refer to a continuous data line, such as the first data line 421 being a continuous data line; or can refer to data lines connected with the same column of pixel circuits and discontinuous, such as the second data line 422, the third data line 423 and the fourth data line 424, whereby the second data line 422 connected with the first sub-pixel circuit and the second data line 422 connected with the second sub-pixel circuit are configured to transmit different signals; the third data line 423 connected with the first sub-pixel circuit and the third data line 423 connected with the second sub-pixel circuit are configured to transmit different signals; and the fourth data line 424 connected with the first sub-pixel circuit and the fourth data line 424 connected with the second sub-pixel circuit are configured to transmit different signals.

[0120] For example, the second data line 422 connected with the first sub-pixel circuit 031 and the second data line 422 connected with the second sub-pixel circuit 032 are configured to transmit different signals; the third data line 423 connected with the first sub-pixel circuit 031 and the third data line 423 connected with the second sub-pixel circuit 032 are configured to transmit different signals; and the fourth data line 424 connected with the first sub-pixel circuit 031 and the fourth data line 424 connected with the second sub-pixel circuit 032 are configured to transmit different signals. Although the data lines located on the same straight line in the first display area and the second display area are all referred to as the second data line, the third data line or the fourth data line in the present application, the second data line (the third data line or the fourth data line) located in different display areas is configured to transmit different signals.

[0121] For example, the second data line in the first display area is schematically shown as being connected with the fourth data line in the second display area through the data line connection part in the end point of the second display area, but is not limited thereto, and the second data line in the first display area can also be connected with the third data line in the second display area through the data line connection part in the end point of the first display area.

[0122] In the present embodiment of the present disclosure, the pixel circuit located in the first display area is referred to as the first sub-pixel circuit, the pixel circuit connected with the light emitting unit located in the second display area is referred to as the second sub-pixel circuit, and the pixel circuit connected with the light emitting unit located in the third display area is referred to as the third sub-pixel circuit.

[0123] For example, as shown in FIG. 3, the present embodiment of the present disclosure takes the first pixel circuit column 321 in the first display area 100 as an example, and the multiple light emitting units 20 connected with the first pixel circuit column 321 include the first color light emitting unit and the third color light emitting unit. FIG. 1 to FIG. 5A For example, as shown in FIG. 3, the present embodiment of the present disclosure takes the first pixel circuit column 321 in the first display area 100 as an example, and the multiple light emitting units 20 connected with the first pixel circuit column 321 include the first color light emitting unit and the third color light emitting unit.

[0124] In the embodiment of the present disclosure, the data signal is transmitted from the source driving integrated circuit located at the side of the first display area away from the second display area to the pixel circuit in the first display area and the second display area through the data line. The data signal transmitted to the pixel circuit connected with the light emitting unit of one color in the second display area should be the same as the data signal transmitted to the pixel circuit connected with the light emitting unit of the same color in the first display area. Thus, the same pixel circuit column in the first display area is connected to the same data line, and the pixel circuit in the second display area is connected to the same data line. The problem that the data signal transmitted to the pixel circuit connected with the first color light emitting unit in the first display area is the same as the data signal transmitted to the pixel circuit connected with the second color light emitting unit pair in the second display area is prone to occur, resulting in the mismatch of the data signal of the first display area and the second display area.

[0125] For example, in the first display area 100, each first light emitting unit group 110 includes one first color light emitting unit, one second color light emitting unit pair, and one third color light emitting unit. Each second color light emitting unit pair includes a first light emitting unit block and a second light emitting unit block. The first color light emitting unit and the third color light emitting unit are arranged along the direction (Y direction) parallel to the extension direction of the data line, the first light emitting unit block and the second light emitting unit block are arranged along the Y direction, the first color light emitting unit and the second color light emitting unit pair are arranged along the X direction intersecting the Y direction, and the directions in which the first color light emitting units of the two adjacent first light emitting unit groups point to the third color light emitting unit are opposite. That is, the light emitting units connected with the four pixel circuits in the pixel circuit column group in the row of pixel circuits close to the second display area in the first display area are the first color light emitting unit, the first light emitting unit block, the third color light emitting unit, and the second light emitting unit block in sequence. And the four light emitting units connected with the pixel circuits in the second row of pixel circuits close to the second display area in the first display area in the above-mentioned pixel circuit column group are the third color light emitting unit, the second light emitting unit block, the first color light emitting unit, and the first light emitting unit block in sequence. Thus, the arrangement modes of the first color light emitting unit and the third color light emitting unit connected with the pixel circuits in the first pixel circuit column and the third pixel circuit column are different, and the arrangement modes of the first light emitting unit block and the second light emitting unit block connected with the pixel circuits in the second pixel circuit column and the fourth pixel circuit column are different. The data signal transmitted by the data line is related to the arrangement of the corresponding color light emitting unit, and the first display area and the second display area should both transmit the matching data signal according to the above-mentioned arrangement mode of the light emitting unit.

[0126] For example, as shown in FIG. 1, the first display area 100 includes a first pixel circuit column 101, a second pixel circuit column 102, a third pixel circuit column 103, and a fourth pixel circuit column 104. The first display area 100 includes a first light emitting unit group 110, a second light emitting unit group 120, and a third light emitting unit group 130. The first light emitting unit group 110 includes a first color light emitting unit 111, a first light emitting unit block 112, a third color light emitting unit 113, and a second light emitting unit block 114. The second light emitting unit group 120 includes a second color light emitting unit pair 121 and a fourth color light emitting unit 122. The third light emitting unit group 130 includes a fifth color light emitting unit 131 and a sixth color light emitting unit 132. FIG. 1 to FIG. 5AAs shown, the plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the second display area 200 include alternating first-color light-emitting units 201 and third-color light-emitting units 203. The light-emitting unit connected to the pixel circuit of the first pixel circuit column 321 located in the second display area 200 near the first display area 100 is, for example, the third-color light-emitting unit 203. The plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 include alternating first-color light-emitting units and third-color light-emitting units. The light-emitting unit connected to the pixel circuit of the first pixel circuit column 321 located in the first display area 100 near the second display area 200 is the first-color light-emitting unit. Therefore, the pixel circuit in the row of pixel circuits closest to the second display area in the first display area and connected to the first data line is connected to the first color light-emitting unit, and the pixel circuit in the row of pixel circuits closest to the first display area in the second display area and connected to the same first data line is connected to the third color light-emitting unit. The arrangement of the light-emitting units matches the data signal transmitted by the first data line, so the first data line can remain connected at the junction of the first display area and the second display area without needing to be disconnected at the junction of the two display areas.

[0127] For example, such as FIG. 1 to FIG. 5A As shown, the plurality of second-color light-emitting unit pairs 202 connected to the fourth pixel circuit column 324 in the second display area 200 include alternating first light-emitting unit blocks 202-1 and second light-emitting unit blocks 202-2. For example, the light-emitting unit connected to the pixel circuit of the fourth pixel circuit column 324 located in the second display area 200 near the first display area 100 is the second light-emitting unit block 202-2. Similarly, the plurality of second-color light-emitting unit pairs connected to the fourth pixel circuit column 324 in the first display area 100 include alternating first light-emitting unit blocks and second light-emitting unit blocks. The light-emitting unit connected to the pixel circuit of the fourth pixel circuit column 324 located in the first display area 100 near the second display area 200 is also a second light-emitting unit block. Therefore, if the light-emitting unit connected to the pixel circuit of the row of pixel circuits near the second display area in the first display area and the light-emitting unit connected to the pixel circuit of the row of pixel circuits near the first display area in the second display area and the light-emitting unit of the same type are the same light-emitting unit, then the data signal of the fourth data line connected to the fourth pixel circuit column in the first display area and the data signal of the fourth data line connected to the fourth pixel circuit column in the second display area do not match. Therefore, the fourth data line should be disconnected at the junction of the first display area and the second display area.

[0128] For example, such as FIG. 5A to FIG. 5CAs shown, the multiple second color light emitting units pairs connected with the second pixel circuit column 322 in the first display area 100 include first light emitting unit blocks and second light emitting unit blocks arranged alternately, and the light emitting units connected with the pixel circuit in the first display area 100 close to the second display area 200 and belonging to the second pixel circuit column 322 are the first light emitting unit blocks. Thus, the data signal of the fourth data line connected with the fourth pixel circuit column of the second display area matches the data signal of the second data line connected with the second pixel circuit column of the first display area, the part of the second data line in the first display area is disconnected with the part of the second data line in the second display area at the position where the two display areas meet, and the second data line in the first display area is connected with the fourth data line in the second display area through the data line connection part, so as to meet the algorithm processing of the integrated circuit (IC) in the first display area and the second display area.

[0129] In the embodiment of the present disclosure, the second data line, the third data line and the fourth data line are disconnected at the position where the first display area and the second display area meet, and the end point of the part of the second data line in the first display area close to the second display area is connected with the end point of the part of the fourth data line in the second display area close to the first display area through the data line connection part, so as to ensure the matching of the data signal transmitted from the data line to the light emitting unit in the first display area and the data signal transmitted from the data line to the light emitting unit in the second display area.

[0130] For example, as shown in FIG. 5, the data line connection part 560 is arranged on the same layer as the second data line 420. FIG. 5A to FIG. 5C For example, as shown in FIG. 5, the data line connection part 560 is arranged on the same layer as the second data line 420.

[0131] For example, as shown in FIG. 5, the data line connection part 560 is arranged on the same layer as the reset power signal line 410. FIG. 5A to FIG. 5C

[0132] For example, as shown in FIG. 5, the data line connection part 560 is arranged on the same layer as the reset power signal line 410. FIG. 6 For example, as shown in FIG. 5, the data line connection part 560 is arranged between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 in the two pixel circuits of the third pixel circuit column 323 and the fourth pixel circuit column 324 in the first row of the first pixel circuit row 31 adjacent to the second display area 200 in the first display area 100.

[0133] ​In the embodiment of the present disclosure, the junction of the first display area 100 and the second display area 200 refers to the interval between the first electrode of the first reset transistor of the pixel circuit in the row 31 of the pixel circuit adjacent to the second display area 200 and the second electrode of the data writing transistor of the pixel circuit in the row 31 of the pixel circuit adjacent to the first display area 100.

[0134] For example, in the row 31 of the pixel circuit adjacent to the second display area 200 in the first display area 100, the distance between the second electrode of the threshold compensation transistor T2 and the second electrode of the first reset control transistor T7 in the second direction is 7-12 microns to set the data line connection part 560 between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7.

[0135] For example, in the pixel circuit in the first display area 100, the distance between the edges of the second connection part 520 and the third connection part 530 close to each other in the second direction is 7-12 microns to set the data line connection part 560 between the second connection part 520 and the third connection part 530. In the embodiment of the present disclosure, the first connection part and the data line connection part are respectively arranged at the junction of the second display area and the first display area and the second display area, but by adjusting the distance of the space between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor of the pixel circuit, the first connection part and the data line connection part can be arranged in the larger space reserved between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor of the pixel circuit to prevent interference with other signals.

[0136] For example, FIG. 6 A schematic diagram of the structure of the part of the pixel circuit at the junction of the edge area of the first display area and the third display area provided according to the embodiment of the present disclosure is provided. For example, as shown in FIG. 6, the first display area 100 and the third display area 300 are arranged in the same way as the first display area 100 and the second display area 200, and the first display area 100 and the third display area 300 are arranged in the same way as the first display area 100 and the second display area 200. FIG. 1 to FIG. 6As shown, the plurality of dummy pixel circuit columns in the third display area includes a dummy pixel circuit column group composed of four adjacent columns, each dummy pixel circuit column group includes a first dummy pixel circuit column 0341, a second dummy pixel circuit column 0342, a third dummy pixel circuit column 0343 and a fourth dummy pixel circuit column 0344 arranged in the second direction in sequence, at least part of the dummy pixel circuits 034 in the first dummy pixel circuit column 0341, at least part of the dummy pixel circuits 034 in the second dummy pixel circuit column 0342, at least part of the dummy pixel circuits 034 in the third dummy pixel circuit column 0343 and at least part of the dummy pixel circuits 034 in the fourth dummy pixel circuit column 0344 are connected with a first data line 421, a second data line 422, a third data line 423 and a fourth data line 424 arranged in the second direction in sequence respectively, the third data line 423 and the fourth data line 424 are disconnected to form a second break 4202 at the interval between the dummy pixel circuits 034 and the first pixel circuit 031 (for example, at the boundary between the edge area 302 of the third display area 300 and the first display area 100).

[0137] For example, the first dummy pixel circuit column 0341, the second dummy pixel circuit column 0342, the third dummy pixel circuit column 0343 and the fourth dummy pixel circuit column 0344 described above can also be referred to as a first pixel circuit column, a second pixel circuit column, a third pixel circuit column and a fourth pixel circuit column respectively.

[0138] For example, as shown, FIG. 1 to FIG. 6 The pixel circuit pair connected with the first color light emitting unit and the third color light emitting unit in the third light emitting unit group 310 can be one of the first pixel circuit pair 601 and the second pixel circuit pair 602, and the pixel circuit pair connected with the second color light emitting unit pair in the third light emitting unit group 310 can be the other one of the first pixel circuit pair 601 and the second pixel circuit pair 602.

[0139] For example, the pixel circuit pair connected with the first color light emitting unit and the third color light emitting unit of the third light emitting unit group 310 can be connected with one of the second data line 422 and the third data line 423, and the pixel circuit pair connected with the first light emitting unit block and the second light emitting unit block of the third light emitting unit group 310 can be connected with the other of the second data line 422 and the third data line 423. For example, the pixel circuit pair connected with the first color light emitting unit and the third color light emitting unit of the third light emitting unit group 310 can be connected with the third data line 423, and the pixel circuit pair connected with the first light emitting unit block and the second light emitting unit block of the third light emitting unit group 310 can be connected with the second data line 422. Since the second data line and the third data line are both disconnected at the boundary of the first display area and the second display area, the pixel circuit connected with the third light emitting unit group cannot be inputted with the matching data signal by the data line in the first display area connected with the second display area. Therefore, the first data line and the second data line connected in succession at the boundary of the third display area and the first display area in the embodiment of the present disclosure are respectively connected with the pixel circuit pair connected with the first light emitting unit block and the second light emitting unit block of the third light emitting unit group 310 and the pixel circuit pair connected with the first color light emitting unit and the third light emitting unit of the third light emitting unit group 310, so as to realize inputting the matching data signal to the pixel circuit connected with the third light emitting unit group, and satisfy the algorithm processing of the integrated circuit in the first display area and the third display area.

[0140] For example, the multiple light emitting units connected with the third pixel circuit column 323 of the second display area 200 in the third display area 300 include the first color light emitting unit and the third color light emitting unit arranged alternately, and the light emitting unit connected with the pixel circuit located in the first row of the second display area 200 away from the first display area 100 and the third pixel circuit column 323 is the third color light emitting unit. The multiple light emitting units 20 connected with the first pixel circuit column 321 in the first display area 100 include the first color light emitting unit and the third color light emitting unit arranged alternately, and the data line connected with the pixel circuit located in the first row of the first display area 100 close to the third display area 300 and connected with the first color light emitting unit is the first data line.

[0141] For example, the plurality of light-emitting units connected to the second pixel circuit column 322 of the second display area 200 in the third display area 300 include alternating first light-emitting unit blocks and second light-emitting unit blocks, and the light-emitting unit connected to the pixel circuit in the first row of the second display area 200 away from the first display area 100 and in the second pixel circuit column 322 is the second light-emitting unit block. The plurality of light-emitting units 20 connected to the second pixel circuit column 322 in the first display area 100 include alternating first light-emitting unit blocks and second light-emitting unit blocks, and the data line connected to the pixel circuit of the first light-emitting unit block in the row of the third display area 300 close to the first display area 100 is the second data line. Therefore, the data signals on the first and second data lines in the area where the edge areas of the first and third display areas meet are matched with the data signals on the third and second data lines in the second display area, respectively. However, the data signals transmitted by the third and fourth data lines in the area where the edge areas of the first and third display areas meet do not match the data signals on the third and second data lines in the second display area. Thus, at the boundary between the edge area of ​​the third display area and the first display area, the first and second data lines remain connected, while the third and fourth data lines are disconnected.

[0142] For example, such as FIG. 1-FIG. 6 As shown, the display substrate also includes a peripheral region 303 located on the side of the third display area 300 away from the first display area 100, a first data line 421 located in the edge region 302 of the third display area 300 bypasses the central region 301 to connect to one of the second data line 422 and the third data line 423 of the second display area 200 in the peripheral region 303, and the second data line 422 located in the edge region 302 of the third display area 300 bypasses the central region 301 to connect to the other of the second data line 422 and the third data line 423 of the second display area 200 in the peripheral region 303.

[0143] For example, an embodiment of this disclosure schematically shows that a first data line 421 located in the edge area 302 of the third display area 300 bypasses the center area 301 to connect to a third data line 423 in the peripheral area 303 of the second display area 200, and a second data line 422 located in the edge area 302 of the third display area 300 bypasses the center area 301 to connect to a second data line 422 in the peripheral area 303 of the second display area 200, thereby facilitating the routing of data lines in the third and second display areas.

[0144] For example, such as FIG. 1-FIG. 6As shown, another embodiment of this disclosure provides a display substrate including a first display area 100 and a second display area 200. The first display area 100 includes a plurality of first light-emitting units 110-1 and a plurality of first sub-pixel circuits 031. The plurality of first light-emitting units 110-1 includes adjacent rows of first light-emitting units 110-11 and second light-emitting units 110-12. Each row of light-emitting units is connected to a corresponding row of first sub-pixel circuits 031. The second display area 120 includes a plurality of second light-emitting units 120-1 and a plurality of second sub-pixel circuits 032. The plurality of second light-emitting units 120-1 includes adjacent rows of third light-emitting units 120-11 and fourth light-emitting units 120-12. Each row of light-emitting units in the second display area 200 is connected to a row of first sub-pixel circuit pairs 032-1. Each row of first sub-pixel circuit pairs 032-1 includes two adjacent rows of second sub-pixel circuits 032.

[0145] For example, such as FIG. 1-FIG. 6 As shown, the display substrate also includes multiple first sub-data lines 4210, multiple second sub-data lines 4220, multiple third sub-data lines 4230, and multiple fourth sub-data lines 4240 extending along the second direction. Each first sub-data line 4210 is connected to each first light-emitting unit column 110-11, each second sub-data line 4220 is connected to each second light-emitting unit column 110-12, each third sub-data line 4230 is connected to each third light-emitting unit column 120-11, and each fourth sub-data line 4240 is connected to each fourth light-emitting unit column 120-12. The second direction intersects with the first direction.

[0146] For example, such as FIG. 1-FIG. 6 As shown, the arrangement direction of the first light-emitting unit column 110-11 and the second light-emitting unit column 110-12 is the same as that of the third light-emitting unit column 120-11 and the fourth light-emitting unit column 120-12. A column of first sub-pixel circuits 031 connected to the first light-emitting unit column 110-11 and a column of second sub-pixel circuits 032 connected to the third light-emitting unit column 120-11 are located in the same column. The first sub-data line 4210 and the third sub-data line 4230 are a continuous data line extending along the second direction. The two columns of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 and the column of first sub-pixel circuits 031 connected to the second light-emitting unit column 110-12 are located in different columns. The second sub-data line 4220 and the fourth sub-data line 4240 are connected through a data line connection part 560, and the extension direction of the data line connection part 560 intersects with the second direction.

[0147] The first sub-data line 4210, the second sub-data line 4220, the third sub-data line 4230, and the fourth sub-data line 4240 here have different meanings from the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 in the above embodiments. Here, the first sub-data line 4210 refers only to the data line in the first data line 421 in the above embodiments that connects to the pixel circuit in the first display area. Here, the second sub-data line 4220 refers only to the data line in the second data line 422 in the above embodiments that connects to the pixel circuit in the first display area. Here, the third sub-data line 4230 refers only to the data line in the first data line 421 in the above embodiments that connects to the pixel circuit in the second display area. Here, the fourth sub-data line 4240 refers only to the data line in the fourth data line 424 in the above embodiments that connects to the pixel circuit in the second display area.

[0148] At the junction of the pixel circuits in the first display area and the second display area, the second sub-data line and the fourth sub-data line are disconnected, and the second sub-data line and the fourth sub-data line are connected through the data line connector, thereby ensuring the matching of the data signal transmitted from the data line to the light-emitting unit in the first display area and the data signal transmitted from the data line to the light-emitting unit in the second display area.

[0149] For example, such as FIG. 1-FIG. 6 As shown, a column of first sub-pixel circuits 031 connected to the second light-emitting unit column 110-12 and another column of second sub-pixel circuits 032 connected to the third light-emitting unit column 120-11 are located in the same column.

[0150] For example, such as FIG. 1-FIG. 6 As shown, the first display area 100 also includes a fifth light-emitting unit column 110-13 and a sixth light-emitting unit column 110-14 arranged adjacent to each other. The first light-emitting unit column 110-11, the second light-emitting unit column 110-12, the fifth light-emitting unit column 110-13 and the sixth light-emitting unit column 110-14 are arranged repeatedly along the first direction, and the third light-emitting unit column 120-11 and the fourth light-emitting unit column 120-12 are arranged alternately along the first direction.

[0151] For example, such as FIG. 5D As shown, the display substrate also includes multiple fifth sub-data lines 4250 and multiple sixth sub-data lines 4260 extending along the second direction. Each fifth sub-data line 4250 is connected to each fifth light-emitting unit column 110-13, and each sixth sub-data line 4260 is connected to each sixth light-emitting unit column 110-14.

[0152] For example, such as FIG. 5EAs shown, the first sub-pixel circuit 031 connected with the fifth light emitting unit column 110-13 and the second sub-pixel circuit 032 connected with the fourth light emitting unit column 120-12 are located in the same column, the first sub-pixel circuit 031 connected with the sixth light emitting unit column 110-14 and the second sub-pixel circuit 032 connected with the fourth light emitting unit column 120-12 are located in the same column, and a gap is provided between the sixth sub-data line 4260 or the fifth sub-data line 4250 and the fourth sub-data line 4240. FIG. 5E As shown, the first sub-pixel circuit 031 connected with the fifth light emitting unit column 110-13 and the second sub-pixel circuit 032 connected with the fourth light emitting unit column 120-12 are located in the same column, the first sub-pixel circuit 031 connected with the sixth light emitting unit column 110-14 and the second sub-pixel circuit 032 connected with the fourth light emitting unit column 120-12 are located in the same column, and a gap is provided between the sixth sub-data line 4260 or the fifth sub-data line 4250 and the fourth sub-data line 4240.

[0153] For example, FIG. 5D A partial plan view of the first display area and the second display area in a display substrate according to another example of the embodiments of the present disclosure is shown. FIG. 5D The example shown is different from the example shown in FIG. 5E The difference between the example shown and the example shown in FIG. 5E In the example shown, the pixels are arranged in a GGRB arrangement, FIG. 1-FIG. 6 In the example shown, the pixels are arranged in a realRGB arrangement. As FIG. 1-FIG. 6As shown, every six RGB light-emitting units in the first display area 100 constitute one repeating cycle. The data line 420 connecting to the first column of R light-emitting units in the first display area 100 and the data line 420 connecting to the first column of R light-emitting units in the second display area 100 are the same continuous data line; there is a gap between the data line 420 connecting to the second column of G light-emitting units in the first display area 100 and the data line 420 connecting to the second column of R light-emitting units in the second display area 100, and the data line 420 connecting to the second column of G light-emitting units in the first display area 100 is connected to the data line 420 connecting to the third column of G (or fourth column of G) light-emitting units in the second display area 100 via a data line connector 560; there is a gap between the data line 420 connecting to the third column of B light-emitting units in the first display area 100 and the data line 420 connecting to the third column of G light-emitting units in the second display area 100. The data lines 420 connected to the third column B light-emitting units of the first display area 100 are connected to the data lines 420 connected to the fifth column B (or sixth column B) light-emitting units of the second display area 100 via the data line connection part 560; there is a gap between the data lines 420 connected to the fourth column G light-emitting units of the first display area 100 and the data lines 420 connected to the fourth column G light-emitting units of the second display area 100; there is a gap between the data lines 420 connected to the fifth column R light-emitting units of the first display area 100 and the data lines 420 connected to the fifth column B light-emitting units of the second display area 100; there is a gap between the data lines 420 connected to the sixth column G light-emitting units of the first display area 100 and the data lines 420 connected to the sixth column B light-emitting units of the second display area 100. The embodiments disclosed herein are not limited to the above-described connections. As long as one R light-emitting unit in the first display area and one R light-emitting unit in the second display area are connected to the same data line, one B light-emitting unit in the first display area and one B light-emitting unit in the second display area are connected to the same data line, and one G light-emitting unit in the first display area and one G light-emitting unit in the second display area are connected to the same data line, it is acceptable.

[0154] For example, such as FIG. 1-FIG. 6 As shown, the first display area 100 includes a plurality of first sub-light-emitting unit groups 1-1 and a plurality of second sub-light-emitting unit groups 1-2 arranged alternately along a first direction and a second direction. The first sub-light-emitting unit group 1-1 includes light-emitting units in the first light-emitting unit column 110-11 and the second light-emitting unit column 110-12. The second sub-light-emitting unit group 1-2 includes light-emitting units in the fifth light-emitting unit column 110-13 and the sixth light-emitting unit column 110-14. The second display area 200 includes a plurality of third sub-light-emitting unit groups 1-3.

[0155] For example, such as FIG. 1-FIG. 6As shown in FIG. 1, each of the sub-emitting unit groups includes one first-color emitting unit R, one second-color emitting unit pair G1 and G2, and one third-color emitting unit B, the first-color emitting unit R and the third-color emitting unit B are arranged along the second direction, the second-color emitting unit pair G1 and G2 includes two second-color emitting units arranged along the second direction, the first-color emitting unit R and the second-color emitting unit pair G1 and G2 are arranged along the first direction, and the arrangement direction of the first-color emitting unit R and the third-color emitting unit B in the first sub-emitting unit group 1-1 is opposite to that in the second sub-emitting unit group 1-2, and the relative position distribution of each emitting unit in the first sub-emitting unit group 1-1 is the same as that in the third sub-emitting unit group 1-3. The first-color emitting unit in the embodiments of the present disclosure is exemplarily taken as a red emitting unit, the second-color emitting unit pair is exemplarily taken as a green emitting unit pair, and the third-color emitting unit is exemplarily taken as a blue emitting unit, but the present disclosure is not limited thereto. For example, the first-color emitting unit can be a blue emitting unit, the second-color emitting unit pair can be a green emitting unit pair, and the third-color emitting unit can be a red emitting unit. For example, the first-color emitting unit can be a green emitting unit, the second-color emitting unit pair can be a red emitting unit pair, and the third-color emitting unit can be a blue emitting unit.

[0156] For example, as shown in FIG. 1, the display substrate further includes a third display area 300, the second display area 200 further includes a plurality of third sub-pixel circuits 033, the third display area 300 includes a plurality of third emitting units 130-1, the plurality of third emitting units 130-1 include a seventh emitting unit column 130-11 and an eighth emitting unit column 130-12 arranged adjacently, the arrangement direction of the first emitting unit column 110-11 and the second emitting unit column 110-12 is the same as that of the seventh emitting unit column 130-11 and the eighth emitting unit column 130-12, each emitting unit column in the third display area 300 is connected with a column of second sub-pixel circuit pairs 033-1, and each column of second sub-pixel circuit pairs 033-1 includes two columns of third sub-pixel circuits 033. FIG. 1-FIG. 6 For example, as shown in FIG. 1, the display substrate further includes a third display area 300, the second display area 200 further includes a plurality of third sub-pixel circuits 033, the third display area 300 includes a plurality of third emitting units 130-1, the plurality of third emitting units 130-1 include a seventh emitting unit column 130-11 and an eighth emitting unit column 130-12 arranged adjacently, the arrangement direction of the first emitting unit column 110-11 and the second emitting unit column 110-12 is the same as that of the seventh emitting unit column 130-11 and the eighth emitting unit column 130-12, each emitting unit column in the third display area 300 is connected with a column of second sub-pixel circuit pairs 033-1, and each column of second sub-pixel circuit pairs 033-1 includes two columns of third sub-pixel circuits 033.

[0157] FIG. 1-FIG. 6 For example, as shown in FIG. 1, the display substrate further includes a third display area 300, the second display area 200 further includes a plurality of third sub-pixel circuits 033, the third display area 300 includes a plurality of third emitting units 130-1, the plurality of third emitting units 130-1 include a seventh emitting unit column 130-11 and an eighth emitting unit column 130-12 arranged adjacently, the arrangement direction of the first emitting unit column 110-11 and the second emitting unit column 110-12 is the same as that of the seventh emitting unit column 130-11 and the eighth emitting unit column 130-12, each emitting unit column in the third display area 300 is connected with a column of second sub-pixel circuit pairs 033-1, and each column of second sub-pixel circuit pairs 033-1 includes two columns of third sub-pixel circuits 033.

[0158] For example, as shown in FIG. 1, the display substrate further includes a third display area 300, the second display area 200 further includes a plurality of third sub-pixel circuits 033, the third display area 300 includes a plurality of third emitting units 130-1, the plurality of third emitting units 130-1 include a seventh emitting unit column 130-11 and an eighth emitting unit column 130-12 arranged adjacently, the arrangement direction of the first emitting unit column 110-11 and the second emitting unit column 110-12 is the same as that of the seventh emitting unit column 130-11 and the eighth emitting unit column 130-12, each emitting unit column in the third display area 300 is connected with a column of second sub-pixel circuit pairs 033-1, and each column of second sub-pixel circuit pairs 033-1 includes two columns of third sub-pixel circuits 033. FIG. 1-FIG. 6 ​As shown, at least one of the seventh sub-data line 4270 and the eighth sub-data line 4280 is arranged between the third sub-data line 4230 and the fourth sub-data line 4240. The seventh sub-data line 4270 here refers to the data line in the second data line 422 in the above embodiment that connects the pixel circuits in the second display area, and the eighth sub-data line 4280 here refers to the data line in the third data line 423 in the above embodiment that connects the pixel circuits in the second display area.

[0159] For example, as shown in FIG. 5A, the seventh sub-data line 4270 and the eighth sub-data line 4280 are arranged between the third sub-data line 4230 and the fourth sub-data line 4240. FIG. 1-FIG. 6

[0160] For example, the eighth sub-data line 4280 and the fifth sub-data line 4250 are broken at a position between the pixel circuits in the first display area and the pixel circuits in the second display area, and the connection part 560 is arranged at the broken position.

[0161] For example, as shown in FIG. 5A, the seventh sub-data line 4270 and the eighth sub-data line 4280 are arranged between the third sub-data line 4230 and the fourth sub-data line 4240. FIG. 1-FIG. 6 For example, as shown in FIG. 6A, the third display area 300 includes a center area 301 and an edge area 302 surrounding the center area 301, and the edge area 302 includes a plurality of dummy pixel circuit columns arranged along the first direction and the second direction to form a plurality of dummy pixel circuit column groups 3201.

[0162] For example, as shown in FIG. 6A, the third display area 300 includes a center area 301 and an edge area 302 surrounding the center area 301, and the edge area 302 includes a plurality of dummy pixel circuit columns arranged along the first direction and the second direction to form a plurality of dummy pixel circuit column groups 3201. FIG. 1-FIG. 6 For example, as shown in FIG. 6A, the third display area 300 includes a center area 301 and an edge area 302 surrounding the center area 301, and the edge area 302 includes a plurality of dummy pixel circuit columns arranged along the first direction and the second direction to form a plurality of dummy pixel circuit column groups 3201.

[0163] FIG. 6 For example, as shown in FIG. 6A, the third display area 300 includes a center area 301 and an edge area 302 surrounding the center area 301, and the edge area 302 includes a plurality of dummy pixel circuit columns arranged along the first direction and the second direction to form a plurality of dummy pixel circuit column groups 3201.

[0164] For example, as shown in FIG. 6A, the third display area 300 includes a center area 301 and an edge area 302 surrounding the center area 301, and the edge area 302 includes a plurality of dummy pixel circuit columns arranged along the first direction and the second direction to form a plurality of dummy pixel circuit column groups 3201. FIG. 1-FIG. 6 ​​As shown, the display substrate also includes a first dummy data line 431, a second dummy data line 432, a third dummy data line 433, and a fourth dummy data line 434. The first dummy data line 431 is connected to the first dummy pixel circuit column 0341, the second dummy data line 432 is connected to the second dummy pixel circuit column 0342, the third dummy data line 433 is connected to the third dummy pixel circuit column 0343, and the fourth dummy data line 434 is connected to the fourth dummy pixel circuit column 0344.

[0165] For example, such as FIG. 1-FIG. 6 As shown, a column of first sub-pixel circuits 031 and a column of first dummy pixel circuits 0341 connected to the first light-emitting unit column 110-11 are located in the same column; a column of first sub-pixel circuits 031 and a column of second dummy pixel circuits 0342 connected to the second light-emitting unit column 110-12 are located in the same column; a column of first sub-pixel circuits 031 connected to the fifth light-emitting unit column 110-13 and a column of third dummy pixel circuits 0343 are located in the same column; and a column of first sub-pixel circuits 031 connected to the sixth light-emitting unit column 110-14 and a column of fourth dummy pixel circuits 0344 are located in the same column. The two data lines connected to the first light-emitting unit group 1-1 and the corresponding two dummy data lines are consecutive data lines, or the two data lines connected to the second light-emitting unit group 1-2 and the corresponding two dummy data lines are consecutive data lines. FIG. 1-FIG. 6 The diagram schematically shows that the two data lines connected to the first light-emitting unit group 1-1 and the corresponding two dummy data lines are two continuous data lines.

[0166] For example, such as FIG. 7 As shown, the display substrate also includes a peripheral area 400 located on the side of the third display area 300 away from the first display area 100. Two dummy data lines connected to the first light-emitting unit group 1-1 or the second light-emitting unit group 1-2 bypass the central area 301 to connect the seventh sub-data line 4270 and the eighth sub-data line 4280 in the peripheral area 400, respectively.

[0167] For example, such as FIG. 8 As shown, the first dummy data line 431 and the first sub-data line 4210 are a continuous data line, the second dummy data line 432 and the second sub-data line 4220 are a continuous data line, there is a gap between the third dummy data line 433 and the fifth sub-data line 4250, and there is a gap between the fourth dummy data line 434 and the sixth sub-data line 4260.

[0168] For example, such as FIG. 9 As shown, the first dummy data line 431 bypasses the central area 301 to connect to the seventh sub-data line 4270 in the peripheral area 400, and the second dummy data line bypasses the central area to connect to the eighth data line in the peripheral area.

[0169] For example, FIG. 1 to FIG. 9 A schematic view of the second electrode of a group of light emitting units located in the first display area according to an embodiment of the present disclosure is provided, FIG. 1 to FIG. 9 A schematic view of the second electrode of a group of light emitting units located in the non-edge of the second display area according to an embodiment of the present disclosure is provided, FIG. 1 to FIG. 9 A schematic view of the second electrode of a group of light emitting units located in the third display area according to an embodiment of the present disclosure is provided. As FIG. 1 to FIG. 9 shown, the second electrode 22 of each light emitting unit 20 includes a main electrode 22-1 and a connecting electrode 22-2, the shape of the main electrode 22-1 is substantially the same as the shape of the effective light emitting area of each light emitting unit 20, and the connecting electrode 22-2 is configured to be electrically connected to the second electrode of the first light emitting control transistor T6 of the pixel circuit through the fifth connecting part 550. Each group of light emitting units located in the display area includes a plurality of light emitting units of different colors, for example, each group of light emitting units includes one first color light emitting unit 201, a pair of second color light emitting units 202, and a third color light emitting unit 203.

[0170] For example, as FIG. 1 to FIG. 9 shown, the area of the main electrode 22-1 of a light emitting unit of a certain color located in at least one of the non-edge area of the second display area 200 and the third display area 300 is greater than the area of the main electrode 22-1 of a light emitting unit of the same color as the above-mentioned light emitting unit of the certain color located in the first display area 100. The area of the main electrode of each color light emitting unit is related to the area of its effective light emitting area, and in the present embodiment, by setting the area of the main electrode of a light emitting unit of a certain color located in at least one of the non-edge area of the second display area and the third display area to be greater than the area of the main electrode of a light emitting unit of the same color as the above-mentioned light emitting unit of the certain color located in the first display area, the area of the effective light emitting area of a light emitting unit of a certain color located in at least one of the non-edge area of the second display area and the third display area can be designed to be greater than the area of the effective light emitting area of a light emitting unit of the same color as the above-mentioned light emitting unit of the certain color located in the first display area.

[0171] In the embodiments of the present disclosure, since the densities of the groups of light emitting units in the second display area and the third display area are both less than the density of the group of light emitting units in the first display area, by setting the area of the body electrode in the light emitting unit in at least one of the second display area and the third display area to be greater than the area of the body electrode in the light emitting unit in the first display area, so that the area of the effective light emitting area of a light emitting unit of one color located in the non-edge area of the second display area and at least one of the third display area is designed to be greater than the area of the effective light emitting area of a light emitting unit of the same color as the light emitting unit of the one color located in the first display area, the brightness of at least one of the second display area and the third display area can be increased on the basis of ensuring the service life of the light emitting unit, and a more uniform full-screen visual display effect can be achieved.

[0172] For example, the embodiments of the present disclosure schematically show that the area of the body electrode 22-1 of a light emitting unit of one color located in the non-edge area of the second display area 200 and the third display area 300 is greater than the area of the body electrode 22-1 of a light emitting unit of the same color as the light emitting unit of the one color located in the first display area 100, so that the area of the effective light emitting area of the light emitting unit of the one color located in the non-edge area of the second display area and at least one of the third display area is designed to be greater than the area of the effective light emitting area of the light emitting unit of the same color as the light emitting unit of the one color located in the first display area, thereby the brightness of the second display area and the third display area can be increased on the basis of ensuring the service life of the light emitting unit, and a more uniform full-screen visual display effect can be achieved.

[0173] For example, in an example of the embodiments of the present disclosure, each light emitting unit in the first display area, the second display area and the third display area is connected with one pixel circuit, that is, each light emitting unit in the second display area and the third display area can not be connected with a pair of pixel circuits, but only connected with one pixel circuit. At this time, since the densities of the groups of light emitting units in the second display area and the third display area are both less than the density of the group of light emitting units in the first display area, by setting the area of the body electrode in the light emitting unit in at least one of the second display area and the third display area to be greater than the area of the body electrode in the light emitting unit in the first display area, so that the area of the effective light emitting area of a light emitting unit of one color located in the non-edge area of the second display area and at least one of the third display area is designed to be greater than the area of the effective light emitting area of a light emitting unit of the same color as the light emitting unit of the one color located in the first display area, the display effect of each display area can be as uniform as possible.

[0174] For example, in another example of the embodiments of the present disclosure, each pixel circuit group includes a plurality of pixel circuits, at least one of the second pixel circuit group and the third pixel circuit group in the second display area includes a plurality of pixel circuit pairs, and each pixel circuit pair includes two pixel circuits configured to be electrically connected with the second electrode of the same light emitting unit. For example, the second pixel circuit group and the third pixel circuit group in the second display area each include a plurality of pixel circuit pairs, each pixel circuit pair in the second pixel circuit group is connected with each light emitting unit in the second light emitting unit group, and each pixel circuit pair in the third pixel circuit group is connected with each light emitting unit in the third light emitting unit group. The density of the light emitting unit group of the second display area and the third display area is less than the density of the light emitting unit group of the first display area. The scheme of designing the pixel circuit connected with the light emitting unit of the second display area and the third display area as a pixel circuit pair is combined with the scheme of setting the area of the main electrode in the light emitting unit of the second display area and the third display area to be greater than the area of the main electrode in the light emitting unit of the first display area, so that the current and the brightness of the light emitting unit of the second display area and the third display area can be increased to 1.8 to 2 times of the case of driving by one pixel circuit on the basis of ensuring the service life of the light emitting material of the light emitting unit, the problem of small current and brightness in the second display area and the third display area is solved, and a more uniform visual display effect of the full-screen is achieved.

[0175] For example, as shown in FIG. 2, each light emitting unit group includes a first color light emitting unit 201, and the area of the main electrode 2011 of each first color light emitting unit 201 located in at least one of the non-edge region of the second display area 200 and the third display area 300 is 1.5-2.5 times, for example, 1.9-2.1 times, of the area of the main electrode 2011 of each first color light emitting unit 201 located in the first display area 100. FIG. 1 to FIG. 9

[0176] For example, the area of the effective light emitting region of each first color light emitting unit 201 located in at least one of the non-edge region of the second display area 200 and the third display area 300 is 2 times of the area of the effective light emitting region of each first color light emitting unit 201 located in the first display area 100.

[0177] For example, as shown in FIG. 2, the shape of the main electrode 2011 and the effective light emitting region of each first color light emitting unit 201 located in each display area is a hexagon, and the area of the connecting electrode 2012 of the first color light emitting unit 201 located in the non-edge region of the second display area 200 can be greater than the area of the connecting electrode 2012 of the first color light emitting unit 201 located in the first display area 100 to realize the connection with the pixel circuit pair. FIG. 8 For example, as shown in FIG. 2, the shape of the main electrode 2011 and the effective light emitting region of each first color light emitting unit 201 located in each display area is a hexagon, and the area of the connecting electrode 2012 of the first color light emitting unit 201 located in the non-edge region of the second display area 200 can be greater than the area of the connecting electrode 2012 of the first color light emitting unit 201 located in the first display area 100 to realize the connection with the pixel circuit pair.

[0178] FIG. 9 ​​As shown, the area of ​​the main electrode 2021 of each second color light-emitting unit pair 202 located in the non-edge area of ​​the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5, for example, 1.9 to 2.1.

[0179] For example, the area of ​​the effective light-emitting area of ​​each second color light-emitting unit pair 202 in the non-edge area of ​​the second display area 200 and the third display area 300 is 2 times the area of ​​the effective light-emitting area of ​​each second color light-emitting unit pair 202 in the first display area 100.

[0180] For example, such as FIG. 10 As shown, the area of ​​the main electrode 2021-1 of each first light-emitting unit block 202-1 located in the non-edge region of the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5, for example, 1.9 to 2.1. Similarly, the area of ​​the main electrode 2021-2 of each second light-emitting unit block 202-2 located in the non-edge region of the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5, for example, 1.9 to 2.1.

[0181] For example, the area of ​​the connection electrode 2022-1 of each first light-emitting unit block 202-1 located in the non-edge region of the second display area 200 is larger than the area of ​​the connection electrode 2022-1 of each first light-emitting unit block 202-1 located in the first display area 100. Similarly, the area of ​​the connection electrode 2022-2 of each second light-emitting unit block 202-2 located in the non-edge region of the second display area 200 is larger than the area of ​​the connection electrode 2022-2 of each second light-emitting unit block 202-2 located in the first display area 100 to facilitate connection with the pixel circuit.

[0182] For example, the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5, for example, 1.9 to 2.1.

[0183] For example, the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 and the third display area 300 is 2 times the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the first display area 100. For example, the area of ​​the effective light-emitting area of ​​each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 and the third display area 300 is 2 times the area of ​​the effective light-emitting area of ​​each third color light-emitting unit 203 located in the first display area 100.

[0184] For example, the area of ​​the connection electrode 2032 of each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 is larger than the area of ​​the connection electrode 2032 of each third color light-emitting unit 203 located in the first display area 100 to achieve connection with the pixel circuit pair.

[0185] For example, the main electrode and the effective light-emitting area of ​​the third color light-emitting unit in each display area are both hexagonal in shape.

[0186] For example, such as FIG. 1 to FIG. 10 and FIG. 1 to FIG. 10 As shown, the second electrode of the light-emitting unit in the second display area is directly connected to the pixel circuit, so the area of ​​the connecting electrode of the light-emitting unit in the second display area is relatively large. However, the second electrode of the light-emitting unit in the third display area is connected to the pixel circuit of the second display area through a transparent trace, so the area of ​​the connecting electrode of the light-emitting unit in the third display area can be set to be relatively small.

[0187] For example, FIG. 1 to FIG. 10 This is a schematic diagram of the second electrode of each light-emitting unit in two rows of light-emitting unit groups at the boundary of the second display area and the first display area according to an embodiment of this disclosure. FIG. 1 to FIG. 10 As shown, the shape and area of ​​the main electrode 2011 of each first color light-emitting unit 201 in the row of light-emitting units adjacent to the first display area 100 in the Y direction of the second display area 200 are approximately the same as the shape and area of ​​the main electrode 2011 of each first color light-emitting unit 201 in the first display area 100. In this embodiment, the shape and area of ​​the main electrode of each first color light-emitting unit in the two rows of light-emitting units adjacent to each other in the Y direction of the second display area are set to be approximately the same. That is, the area of ​​the main electrode of the first color light-emitting unit located at the edge of the second display area is designed to be different from the area of ​​the main electrode of the first color light-emitting unit located in the non-edge area of ​​the second display area. This can increase the brightness of most of the first color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting units.

[0188] For example, such as FIG. 7 to FIG. 10As shown in FIG. 1, the area of the body electrode 2021 of each second-color light emitting unit pair 202 in the row of light emitting unit groups adjacent to the first display area 100 in the first direction of the second display area 200 is 0.9-1.1 times the area of the body electrode 2021 of each second-color light emitting unit pair 202 in the first display area 100. In the embodiment of the present disclosure, the area of the body electrode of each second-color light emitting unit in the two rows of light emitting unit groups adjacent to each other in the Y direction of the first display area in the second display area is designed to be substantially the same, that is, the area of the body electrode of the second-color light emitting unit located at the edge of the second display area is designed to be different from the area of the body electrode of the second-color light emitting unit located in the non-edge area of the second display area, which can increase the brightness of most of the second-color light emitting units in the second display area to achieve a uniform full-screen display effect while preventing the body electrodes of the two rows of light emitting units from colliding in space.

[0189] For example, as shown in FIG. 1, the shape of the body electrode 2021 of each second-color sub-pixel pair 202 in the first display area 100 is different from the shape of the two body electrodes 2021 of each second-color light emitting unit pair 202 in the row of light emitting unit groups adjacent to the first display area 100 in the first direction of the second display area 200. FIG. 7 to FIG. 10

[0190] In the embodiment of the present disclosure, the size of the pixel definition layer gap (PDL gap) between the two adjacent light emitting units located in the non-edge area of the second display area is substantially the same as the size of the PDL gap between the two adjacent light emitting units located in the edge area of the second display area, so as to make the uniformity of the display image light of the second display area.

[0191] For example, as shown in FIG. 1, the shape of the body electrode 2021 of each second-color sub-pixel pair 202 in the first display area 100 is different from the shape of the two body electrodes 2021 of each second-color light emitting unit pair 202 in the row of light emitting unit groups adjacent to the first display area 100 in the first direction of the second display area 200. FIG. 1 to FIG. 10

[0192] For example, as shown in FIG. 1, the shape of the body electrode 2021 of each second-color sub-pixel pair 202 in the first display area 100 is different from the shape of the two body electrodes 2021 of each second-color light emitting unit pair 202 in the row of light emitting unit groups adjacent to the first display area 100 in the first direction of the second display area 200. FIG. 11 ​​As shown, the length of the second side 2 of the main electrode 2021 of the second color light-emitting unit in the first display area 100 is less than the length of the fifth side 5 of the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200, so as to ensure that the area of ​​the main electrode of the second color light-emitting unit in the first display area is approximately equal to the area of ​​the main electrode of the second color light-emitting unit at the edge of the second display area.

[0193] For example, such as FIG. 11 As shown, when the area of ​​the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200 is set to be the same as the area of ​​the main electrode 2021 of the second color light-emitting unit in the first display area 100, in order to ensure that the PDL gap between the second color light-emitting unit at the edge of the second display area 200 and the first color light-emitting unit (or the third color light-emitting unit) and the PDL gap between the second color light-emitting unit and the first color light-emitting unit (or the third color light-emitting unit) in the non-edge area of ​​the second display area 200 are not parallel to the center line connecting the two main electrodes of each pair of second color light-emitting units in the row of light-emitting units adjacent to the first display area 100 in the first direction.

[0194] When the area of ​​the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200 is set to be the same as the area of ​​the main electrode 2021 of the second color light-emitting unit in the first display area 100, in order to ensure that the PDL gap between the second color light-emitting unit at the edge of the second display area 200 and the first color light-emitting unit (or the third color light-emitting unit) is the same as the PDL gap between the second color light-emitting unit and the first color light-emitting unit (or the third color light-emitting unit) in the non-edge area of ​​the second display area 200, the shape of the main electrode of the second color light-emitting unit at the edge of the second display area 200 is a pentagon including sharp corners, which would spatially conflict with the connection electrode of the first color light-emitting unit (or the third color light-emitting unit). Therefore, the shape of the main electrode of the second color light-emitting unit at the edge of the second display area no longer includes sharp corners. At this point, in order to ensure that the area of ​​the main electrode of the second color light-emitting unit at the edge of the second display area is approximately the same as the area of ​​the main electrode of the second color light-emitting unit in the first display area, it is necessary to compensate for the shape of the main electrode of the second color light-emitting unit at the edge of the second display area, that is, to add two sixth sides 6 and a seventh side 7 connecting the two sixth sides 6, so as to achieve that the area of ​​the main electrode of the second color light-emitting unit at the edge of the second display area is equal to the area of ​​the second color light-emitting unit in the first display area without spatial conflict.

[0195] For example, such as FIG. 11As shown, the shape and area of the body electrode 2031 of each third color light emitting unit 203 in the row of light emitting unit groups adjacent to the first display area 100 in the Y direction of the second display area 200 are substantially the same as the shape and area of the body electrode 2031 of each third color light emitting unit 203 located in the first display area 100. The embodiment of the present disclosure sets the shape and area of the body electrode of each third color light emitting unit in the two rows of light emitting unit groups adjacent to each other in the Y direction of the first display area of the second display area to be substantially the same, that is, the area of the body electrode of the third color light emitting unit located at the edge of the second display area is designed to be different from the area of the body electrode of the third color light emitting unit located in the non-edge area of the second display area, which can increase the brightness of most of the third color light emitting units in the second display area while preventing the body electrodes of the two rows of light emitting units from colliding in space.

[0196] For example, FIG. 11 A schematic view of the second electrode of each light emitting unit in the two columns of light emitting unit groups of the second display area bordering the first display area according to the embodiment of the present disclosure is shown. As shown in FIG. 6, the second electrode of each light emitting unit in the two columns of light emitting unit groups adjacent to each other in the X direction of the first display area of the second display area is substantially the same, that is, the area of the second electrode of the light emitting unit located at the edge of the second display area is designed to be different from the area of the second electrode of the light emitting unit located in the non-edge area of the second display area, which can increase the brightness of most of the light emitting units in the second display area while preventing the second electrodes of the two columns of light emitting units from colliding in space. FIG. 11 As shown, in the column of light emitting unit groups adjacent to the first display area 100 in the X direction of the second display area 200, the second color light emitting unit pair 202 is located on the side close to the first display area 100 of the first color light emitting unit 201 and the third color light emitting unit 203, and the area and shape of the body electrode 2021 of each second color light emitting unit pair 202 in the column of light emitting unit groups are substantially the same as the area and shape of the body electrode 2021 of each second color light emitting unit pair 202 located in the first display area 100. The embodiment of the present disclosure sets the shape and area of the body electrode of each second color light emitting unit pair in the two columns of light emitting unit groups adjacent to each other in the X direction of the first display area of the second display area to be substantially the same, that is, the area of the body electrode of the second color light emitting unit pair located at the edge of the second display area is designed to be different from the area of the body electrode of the second color light emitting unit pair located in the non-edge area of the second display area, which can increase the brightness of most of the second color light emitting unit pairs in the second display area while preventing the body electrodes of the two columns of light emitting units from colliding in space.

[0197] For example, a third pixel circuit group is provided between two adjacent second light-emitting unit groups arranged along the Y direction, thus no light-emitting unit group is provided at the interval between two adjacent second light-emitting unit groups arranged along the Y direction. In the first display area 100, a gap is provided between two adjacent first light-emitting unit groups in a column of multiple first light-emitting unit groups close to the second display area 200 in the X direction. This gap includes a first pixel circuit group not connected to the light-emitting unit group, and along the X direction, this first pixel circuit group and the light-emitting unit group in a column of second light-emitting unit groups adjacent to the first display area 100 are located on the same straight line. Therefore, the brightness distribution of the first and second display areas in the X direction can be balanced.

[0198] For example, such as ​ As shown, in a row of light-emitting units adjacent to the first display area 100 in the X direction in the second display area 200, the ratio of the area of ​​the main electrode 2011 of each first color light-emitting unit 201 to the area of ​​the main electrode 2011 of each first color light-emitting unit 201 in the first display area 100 is 1.5 to 2.5, for example, 1.9 to 2.1. For example, in a row of light-emitting units adjacent to the first display area 100 in the X direction in the second display area 200, the ratio of the area of ​​the effective light-emitting area of ​​each first color light-emitting unit 201 to the area of ​​the effective light-emitting area of ​​each first color light-emitting unit 201 in the first display area 100 is 2. In this embodiment of the disclosure, while ensuring that the main electrodes of the light-emitting units in a row of light-emitting units adjacent to the first display area in the X direction do not conflict in space, the shape and area of ​​the main electrode of the first color light-emitting unit located at the edge of the second display area are approximately the same as the shape and area of ​​the main electrode of the first color light-emitting unit located in the non-edge area of ​​the second display area. This can increase the brightness of most of the first color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing the main electrodes of the two rows of light-emitting units from conflicting in space.

[0199] For example, such as ​As shown, in the column of light emitting unit groups adjacent to the first display area 100 in the X direction of the second display area 200, the area ratio of the body electrode 2031 of each third color light emitting unit 203 to the body electrode 2031 of each third color light emitting unit 203 located in the first display area 100 is 1.5-2.5, for example, 1.9-2.1. For example, in the column of light emitting unit groups adjacent to the first display area 100 in the X direction of the second display area 200, the area ratio of the effective light emitting area of each third color light emitting unit 203 to the effective light emitting area of each third color light emitting unit 203 located in the first display area 100 is 2. In the embodiment of the present disclosure, in the case of ensuring that the body electrodes of the light emitting units in the column of light emitting unit groups adjacent to the first display area in the X direction of the second display area do not conflict in space, the shape and area of the body electrode of the third color light emitting unit located at the edge of the second display area are substantially the same as the shape and area of the body electrode of the third color light emitting unit located in the non-edge area of the second display area, which can increase the brightness of most of the third color light emitting units in the second display area to achieve a uniform full-screen display effect while preventing the body electrodes of the two columns of light emitting units from conflicting in space.

[0200] Another embodiment of the present disclosure provides a display device, which includes any one of the display substrates.

[0201] In the display device provided by an example of the embodiment of the present disclosure, two pixel circuits in the second display area drive one light emitting unit to emit light, which can increase the current and brightness of the light emitting units in at least one of the second display area and the third display area, and achieve a more uniform full-screen visual display effect.

[0202] In the display device provided by an example of the embodiment of the present disclosure, by setting the area of the body electrode in the light emitting unit of at least one of the second display area and the third display area to be greater than the area of the body electrode in the light emitting unit of the first display area, the area of the effective light emitting area of a light emitting unit of one color located in the non-edge area of the second display area and at least one of the third display area is designed to be greater than the area of the effective light emitting area of a light emitting unit of the same color as the above-mentioned one color located in the first display area, which can increase the brightness of at least one of the second display area and the third display area on the basis of ensuring the service life of the light emitting material of the light emitting unit, and achieve a more uniform full-screen visual display effect.

[0203] In the display device provided by an example of the embodiment of the present disclosure, by designing the data lines at the junctions of the first display area and the second display area and the first display area and the third display area, the algorithm processing of the integrated circuit (IC) can be unified in the first display area and the second display area.

[0204] The following points need to be explained:

[0205] (1) In the drawings of the embodiments of the present disclosure, only structures related to the embodiments of the present disclosure are involved, and other structures can be referred to general designs.

[0206] (2) In the case of no conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0207] The above only describes exemplary embodiments of the present disclosure, and is not intended to limit the protection scope of the present disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: The substrate includes a first display area and a second display area, wherein the first display area and the second display area include a plurality of pixel circuits arranged along a first direction and a second direction to form a plurality of pixel circuit columns and a plurality of pixel circuit rows, wherein the first direction and the second direction intersect. Multiple data lines extending along the second direction are located on the substrate and are respectively connected to the multiple pixel circuit columns. The plurality of pixel circuits located in the first display area include a plurality of first sub-pixel circuits, the plurality of pixel circuits located in the second display area include a plurality of second sub-pixel circuits, the first display area also includes a plurality of first light-emitting units, the plurality of first light-emitting units being connected one-to-one with the plurality of first sub-pixel circuits, the second display area also includes a plurality of second light-emitting units, each of the second light-emitting units being connected to at least two second sub-pixel circuits; Each pixel circuit column includes a pixel circuit column group consisting of four adjacent columns. Each pixel circuit column group includes a first pixel circuit column, a second pixel circuit column, a third pixel circuit column, and a fourth pixel circuit column arranged sequentially along the first direction. The first pixel circuit column, the second pixel circuit column, the third pixel circuit column, and the fourth pixel circuit column in the first display area are respectively connected to the first data line, the second data line, the third data line, and the fourth data line arranged sequentially along the first direction. At least a portion of the pixel circuits of the first pixel circuit column, the second pixel circuit column, the third pixel circuit column, and the fourth pixel circuit column in the second display area are respectively connected to the first data line, the second data line, the third data line, and the fourth data line arranged sequentially along the first direction. The second data line, the third data line, and the fourth data line connected to at least one pixel circuit array are disconnected to form a first break. The data line on one side of the first break is connected to the first sub-pixel circuit, and the data line on the other side of the first break is connected to the second sub-pixel circuit. The endpoint of the second data line at the first break is connected to the endpoint of the third or fourth data line at the first break via a data line connector.

2. The display substrate according to claim 1, wherein, The endpoint of the second data line at the first break is connected to the endpoint of the fourth data line at the first break via a data line connector, and the data line connector passes through the first break of the third data line.

3. The display substrate according to claim 2, wherein, The second data line connected to the first sub-pixel circuit and the second data line connected to the second sub-pixel circuit are configured to transmit different signals; the third data line connected to the first sub-pixel circuit and the third data line connected to the second sub-pixel circuit are configured to transmit different signals; the fourth data line connected to the first sub-pixel circuit and the fourth data line connected to the second sub-pixel circuit are configured to transmit different signals.

4. The display substrate according to claim 3, wherein, Within the second display area, in at least one pixel circuit column group, the data input terminals of two pixel circuits located in the same pixel circuit row and respectively located in the first pixel circuit column and the second pixel circuit column are electrically connected to form a first pixel circuit pair, and the data input terminals of two pixel circuits located in the same pixel circuit row and respectively located in the third pixel circuit column and the fourth pixel circuit column are electrically connected to form a second pixel circuit pair.

5. The display substrate according to claim 4, wherein, The substrate further includes a third display area; The second display area includes multiple pixel circuits, which further include multiple third sub-pixel circuits. The third display area includes multiple third light-emitting units, and each third light-emitting unit is connected to at least two third sub-pixel circuits.

6. The display substrate according to claim 5, wherein, The first pixel circuit pair connected to the second light-emitting unit of the second display area is connected to the first data line located in the second display area; the second pixel circuit pair connected to the second light-emitting unit of the second display area is connected to the fourth data line located in the second display area; the first pixel circuit pair connected to the third light-emitting unit of the third display area is connected to the second data line located in the second display area; and the second pixel circuit pair connected to the third light-emitting unit of the third display area is connected to the third data line located in the second display area.

7. The display substrate according to claim 1, wherein, The data cable connector is located on a different layer from the multiple data cables.

8. The display substrate according to claim 7, further comprising: Multiple power signal lines are arranged on the same layer as the multiple data lines and extend along the second direction. In particular, along a third direction perpendicular to the substrate, the data line connection portion overlaps with the power signal line.

9. The display substrate according to claim 8, further comprising: Multiple reset power signal lines are located between the multiple data lines and the substrate, and extend along the first direction. Each pixel circuit includes a driving transistor, a threshold compensation transistor, and a first reset control transistor. The first terminal of the threshold compensation transistor is connected to the first terminal of the driving transistor, the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor, the first terminal of the first reset control transistor is connected to the reset power supply signal line, and the second terminal of the first reset control transistor is connected to the corresponding light-emitting unit. The data line connection portion is provided between the second terminal of the threshold compensation transistor and the first terminal of the first reset control transistor in the two pixel circuits located in the pixel circuit row adjacent to the second sub-pixel circuit in the first sub-pixel circuit and in the third pixel circuit column and the fourth pixel circuit column.

10. The display substrate according to claim 9, wherein, In the pixel circuit row adjacent to the second sub-pixel circuit in the first sub-pixel circuit, the distance between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in the first direction is 7~12 micrometers so that the data line connection portion is provided between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor.

11. The display substrate according to claim 9, wherein, The data line connector and the reset power signal line are located on the same layer.

12. The display substrate according to claim 5 or 6, wherein, The third display area includes a central area and an edge area surrounding the central area. The edge area includes a plurality of dummy pixel circuits arranged along the first direction and the second direction to form at least one dummy pixel circuit column and at least one dummy pixel circuit row. The at least one dummy pixel circuit column in the third display area includes a group of dummy pixel circuit columns consisting of four adjacent columns. Each group of dummy pixel circuit columns includes a first dummy pixel circuit column, a second dummy pixel circuit column, a third dummy pixel circuit column, and a fourth dummy pixel circuit column arranged sequentially along the first direction. At least a portion of the dummy pixel circuits of the first dummy pixel circuit column, the second dummy pixel circuit column, the third dummy pixel circuit column, and the fourth dummy pixel circuit column are respectively connected to a first data line, a second data line, a third data line, and a fourth data line arranged sequentially along the first direction. The third data line and the fourth data line are disconnected to form a second break. The data line on one side of the second break is connected to the dummy pixel circuit, and the data line on the other side of the second break is connected to the first sub-pixel circuit.

13. The display substrate according to claim 12, wherein, The display substrate further includes a peripheral area located on the side of the third display area away from the first display area, wherein a portion of the first data line located in the edge area of ​​the third display area bypasses the central area to connect to one of the second data line and the third data line of the second display area in the peripheral area, and a portion of the second data line located in the edge area of ​​the third display area bypasses the central area to connect to the other of the second data line and the third data line of the second display area in the peripheral area.

14. The display substrate according to claim 5, wherein, The first pixel circuit pairs are arranged along the second direction, and the four first pixel circuit pairs arranged adjacently in the second direction are respectively connected to the first color light-emitting unit, the third color light-emitting unit, and the two second color light-emitting units of the third display area; the second pixel circuit pairs are arranged along the second direction, and the four second pixel circuit pairs arranged adjacently in the second direction are respectively connected to the two second color light-emitting units of the second display area and the first color light-emitting unit and the third color light-emitting unit of the third display area.

15. The display substrate according to any one of claims 9-11, further comprising: A scan signal line extends along the first direction and is located between the reset power signal line and the substrate. The reset control signal line extends along the first direction and is disposed on the same layer as the scan signal line; as well as The light emission control signal line extends along the first direction and is disposed on the same layer as the scanning signal line. Each pixel circuit further includes a data writing transistor, a storage capacitor, a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor. The first terminal of the data writing transistor is connected to the second terminal of the driving transistor, the second terminal of the data writing transistor is connected to the data line, and the gate of the data writing transistor is electrically connected to the scan signal line. The first terminal of the storage capacitor is electrically connected to the power signal line, and the second terminal of the storage capacitor is electrically connected to the gate of the driving transistor. The gate of the threshold compensation transistor is electrically connected to the scan signal line; The gate of the first reset control transistor is electrically connected to the reset control signal line; The first terminal of the second reset transistor is electrically connected to the reset power supply signal line, the second terminal of the second reset transistor is electrically connected to the gate of the driving transistor, and the gate of the second reset transistor is electrically connected to the reset control signal line. The first terminal of the first light-emitting control transistor is electrically connected to the first terminal of the driving transistor, the second terminal of the first light-emitting control transistor is electrically connected to the corresponding light-emitting unit, and the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line. The first terminal of the second light-emitting control transistor is electrically connected to the power signal line, the second terminal of the second light-emitting control transistor is electrically connected to the second terminal of the driving transistor, and the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line.

16. A display device comprising a display substrate according to any one of claims 1-15.

Images