An automatic testing method and device for a PCIe bus interface circuit

Abstract

The application discloses a kind of PCIe bus interface circuit's automatic testing method and device, through integrating high-speed relay on the carrier plate of automatic test equipment, PCIe root complex or / and endpoint device for testing, PCIe transceiving differential signal of measured circuit is connected with machine high-speed test channel using machine control signal control high-speed relay, and automatic test equipment is according to the relevant function and electrical parameter of the test excitation and response test circuit of measured circuit without PCIe interface work, PCIe transceiving differential signal of measured circuit is connected with the PCIe root complex or endpoint device for testing by the relay using machine control signal control, realize automatic testing, greatly improve the efficiency of automatic testing, reduce the labor cost, equipment cost and test time of circuit production test, the present application can realize multiple automatic testing in circuit production link, effectively reduce the probability of quality hidden danger such as appearance or shape damage caused by multiple plug-in of circuit in test fixture.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit testing, and specifically relates to an automatic testing method and apparatus for PCIe bus interface circuits. Background Technology

[0002] Testing is a necessary step to ensure the quality of integrated circuits. Generally, automated test equipment (ATE) is used to perform production and quality inspection tests on the electrical parameters and functions of the circuits. The automated test equipment places the circuit under test in a fixture on the test equipment's load board, applies test stimuli through the test machine, and performs output detection on the circuit.

[0003] The advantages of automated test equipment include high testing efficiency and accuracy, convenient high and low temperature control, and significantly reduced labor costs. However, for circuits with PCIe (Peripheral Component Interconnect Express) high-speed bus interfaces, test equipment cannot detect and analyze the real-time high-speed output signals of the circuit under test and provide corresponding high-speed excitation signals according to the bus protocol requirements. For example, the unidirectional data transfer rate of a single PCIe path can reach up to 2.5Gbps, 5Gbps, 8Gbps, 16Gbps, and 32Gbps. PCIe bus interface circuits can be divided into root complex (RC) device functional circuits, switch device functional circuits, and endpoint device functional circuits. For PCIe root complex functional circuits, the inability to perform functional testing of the PCIe interface will reduce test coverage; for PCIe switch and endpoint device circuits, if the functional testing of the PCIe interface cannot be performed, the core functions and dynamic power consumption parameters of the entire circuit cannot be tested. Therefore, to ensure test coverage, automated test equipment is generally used first to test electrical parameters and functions that do not require the PCIe interface to operate. Then, functional test fixtures specially developed for the circuit under test are used to supplement the functional tests and dynamic power consumption parameter tests.

[0004] However, the production process of circuits often requires multiple rounds of testing. Each round of testing is divided into two parts, which not only increases the labor cost, equipment cost and testing time, but also causes potential quality problems such as damage to appearance or shape due to repeated insertion and removal of the circuit in the test fixture. Summary of the Invention

[0005] The purpose of this invention is to provide an automatic testing method and apparatus for PCIe bus interface circuits to overcome the shortcomings of the prior art.

[0006] An automated testing method for PCIe bus interface circuits includes the following steps:

[0007] S1 integrates high-speed relays, test PCIe root complexes and / or endpoint devices on the carrier board of the automatic test equipment;

[0008] S2 controls the high-speed relay to connect the PCIe transmit / receive differential signal of the circuit under test to the high-speed test channel of the machine through the machine control signal. The automatic test equipment can test the relevant functions and electrical parameters of the circuit under test without the need for a PCIe interface by following the test excitation and response of the circuit under test.

[0009] S3, by controlling the relay through the machine control signal to connect the PCIe transmit / receive differential signal of the circuit under test to the PCIe root complex or endpoint device for testing, to achieve automatic testing.

[0010] Furthermore, the test channel of the test machine provides clock, reset, and control excitation signals to the circuit under test and the test PCIe root complex or / and endpoint device, and the test PCIe root complex or endpoint device automatically performs functional tests with the PCIe interface of the circuit under test.

[0011] Furthermore, the PCIe root complex or endpoint device used for testing provides debugging information interfaces based on the PCIe interface functional test status between the test and the circuit under test, allowing automated test equipment to determine whether the circuit function is normal.

[0012] Furthermore, the test equipment can test other functions of the circuit that can only be tested after the PCIe interface of the circuit under test is working, according to the test requirements of the circuit under test.

[0013] Furthermore, all PCIe interfaces between the test PCIe root complex or endpoint device and the circuit under test are automatically trained and established according to the PCIe protocol. If the circuit under test cannot successfully establish a link within a preset time, the circuit is judged to be functionally faulty.

[0014] Furthermore, after the PCIe interface between the test PCIe root complex or endpoint device and the circuit under test is successfully trained and established according to the PCIe protocol, the test PCIe root complex or endpoint device performs specific PCIe transaction transmissions and related functional tests based on the device function type, specific function, and the PCIe link interface between the circuit under test and the circuit under test.

[0015] Furthermore, when the circuit under test is a PCIe root complex device, the circuit under test initiates configuration 0 transactions and memory access transactions to perform PCIe interface functional tests with the test PCIe endpoint device.

[0016] When the circuit under test is a PCIe endpoint device, the test PCIe root complex initiates a configuration 0 transaction and performs tests on the PCIe interface and other functions of the circuit after the PCIe interface is working, based on the internal memory and / or I / O resources of the circuit under test.

[0017] Furthermore, when the circuit under test is a PCIe switching circuit, the test PCIe root complex performs enumeration and configuration tests on the circuit under test and the test PCIe endpoint devices connected thereto; the test PCIe root complex sends configuration 0 transactions, configuration 1 transactions, and memory access transactions to the upstream port of the circuit under test, and the test PCIe endpoint devices send memory transactions, message transactions, or response completion packets to the downstream port of the circuit under test.

[0018] An automatic test apparatus for a PCIe bus interface circuit includes a test root complex and / or endpoint device functions and multiple high-speed relays connected to the PCIe interface of the device under test.

[0019] The PCIe interface of the circuit under test transmits and receives signals through multiple high-speed relays under the control of the test machine and is connected to the test root complex and / or endpoint device functions, or to the high-speed electrical parameter test channel of the test machine.

[0020] The root complex or endpoint device used for testing and the circuit under test are independently powered by the power supply channel of the automatic test machine;

[0021] The PCIe root complex or endpoint device used for testing provides a debug information interface and connects to the test channel of the test machine.

[0022] Furthermore, when the circuit under test is a PCIe root complex device, only the test PCIe endpoint device function is integrated, and no other PCIe functional devices are integrated; when the circuit under test is a PCIe endpoint device, only the test PCIe root complex function is integrated, and no other PCIe functional devices are integrated; when the circuit under test is a PCIe switching circuit, one of the test PCIe root complex functional devices and one or more of the test PCIe endpoint devices are integrated.

[0023] Compared with the prior art, the present invention has the following beneficial technical effects:

[0024] This invention discloses an automatic testing method for PCIe bus interface circuits. By integrating a high-speed relay, a test PCIe root composite and / or endpoint device onto the carrier board of an automatic testing equipment, and using machine control signals to control the high-speed relay to connect the PCIe transmit / receive differential signals of the circuit under test to the high-speed test channel of the machine, the automatic testing equipment, according to the test excitation and response of the circuit under test, tests the relevant functions and electrical parameters of the circuit without requiring the PCIe interface to operate. The automatic testing equipment, through machine control signals, controls the relay to connect the PCIe transmit / receive differential signals of the circuit under test to the test PCIe root composite or endpoint device, thereby achieving automatic testing. This significantly improves the efficiency of automatic testing, reduces the labor costs, equipment costs, and testing time in circuit production testing, and enables multiple rounds of automatic testing in the circuit production process. This effectively reduces the probability of quality defects such as appearance or shape damage caused by repeated insertion and removal of the circuit in the test fixture.

[0025] This invention provides an automatic testing device for PCIe bus interface circuits. It uses general-purpose integrated circuit automatic testing equipment to automate the testing of root complex devices, PCIe switching switches, and endpoint device circuits. By combining automated testing equipment with dedicated functional testing fixtures to perform functional testing and dynamic power consumption parameter testing, the work of two tests is reduced to one. This reduces the labor costs, equipment costs, and testing time in circuit production testing, and effectively lowers the probability of quality defects such as appearance or shape damage caused by repeated insertion and removal of the circuit in the test fixture. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the automatic test board for the PCIe switching circuit in Embodiment 1 of the present invention.

[0027] Figure 2 This is a schematic diagram of the automatic test board principle of the PCIe to serial port circuit in Embodiment 2 of the present invention.

[0028] Figure 3 This is a schematic diagram of the automatic test carrier board for the PCIe root complex device functional circuit in Embodiment 3 of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] This invention provides an automatic testing method for PCIe bus interface circuits, comprising the following steps:

[0032] S1, integrates a high-speed relay, a test PCIe root complex and / or endpoint device on the carrier board of the automatic test equipment; the relay on the carrier board of the automatic test equipment controls the PCIe transmit / receive differential signal of the circuit under test to the high-speed test channel of the equipment or to the test PCIe root complex and / or endpoint device.

[0033] S2, the high-speed relay is controlled by the machine control signal to connect the PCIe transmit / receive differential signal of the circuit under test to the high-speed test channel of the machine. The automatic test equipment can test the relevant functions and electrical parameters of the circuit under test according to the test excitation and response of the circuit without the need for a PCIe interface.

[0034] For example: test the low-speed interface function of the circuit, static power supply current parameters, and control the receiver and transmitter electrical parameters of the PCIe interface of the circuit under test through the JTAG test pin of the circuit.

[0035] S3, the relay is controlled by the machine control signal to connect the PCIe transmit / receive differential signal of the circuit under test to the test PCIe root complex or endpoint device.

[0036] The test equipment provides the necessary clock, reset, and control excitation signals to the circuit under test and the test PCIe root complex or / and endpoint device through the test channel, and the test PCIe root complex or endpoint device automatically performs functional testing with the PCIe interface of the circuit under test.

[0037] The PCIe root complex or endpoint device used for testing provides debugging information interface based on the PCIe interface function test status between the test circuit and the circuit under test, allowing the automatic test machine to determine whether the circuit function is normal; the test machine tests other functions of the circuit that can only be tested after the PCIe interface of the circuit under test is working, according to the test requirements of the circuit under test.

[0038] Automatic functional testing via the PCIe root complex and / or endpoint devices and the PCIe interface of the circuit under test includes the following components:

[0039] All PCIe interfaces between the test PCIe root complex or endpoint device and the circuit under test are automatically trained and established according to the PCIe protocol.

[0040] If the circuit under test cannot successfully establish a link within the preset time, the circuit is judged to be faulty.

[0041] After the PCIe interface between the test PCIe root complex or endpoint device and the circuit under test is successfully trained and established according to the PCIe protocol, the test PCIe root complex or endpoint device performs specific PCIe transaction transmission and related functional tests based on the device function type, specific function, and the PCIe link interface between the circuit under test and the circuit under test.

[0042] When the circuit under test is a PCIe root complex device, the circuit under test initiates a configuration 0 transaction and a memory access transaction to perform a functional test of the PCIe interface with the PCIe endpoint device used for testing.

[0043] When the circuit under test is a PCIe endpoint device, the test PCIe root complex initiates a configuration 0 transaction and performs tests on the PCIe interface and other functions of the circuit after the PCIe interface is working, according to the internal memory and / or IO resources of the circuit under test.

[0044] When the circuit under test is a PCIe switching circuit, the test PCIe root complex performs enumeration and configuration tests on the circuit under test and the test PCIe endpoint devices connected to it; the test PCIe root complex sends configuration 0 transactions, configuration 1 transactions, and memory access transactions to the upstream port of the circuit under test, and the test PCIe endpoint devices send memory transactions, message transactions, or response completion packets to the downstream port of the circuit under test.

[0045] When the circuit under test is a PCIe switching circuit, the test PCIe root complex or endpoint device detects whether the circuit under test has correctly performed the transaction exchange between each port as expected; the test PCIe root complex also detects its own uncorrectable error status, detects the uncorrectable and correctable error status of each port of the circuit under test, detects the uncorrectable error status inside the test PCIe endpoint device, and outputs the detection results through the debug information interface;

[0046] When the circuit under test is a PCIe switching circuit, the test PCIe root complex or endpoint device can receive test commands output by the automatic test equipment and configure the link width of the test PCIe root complex and endpoint device to match the port link width of the PCIe switching circuit under test, so that the test circuit can be tested in different port modes.

[0047] When the circuit under test is a PCIe endpoint device, the test PCIe root complex detects whether the transactions received from the circuit under test are as expected and outputs the detection results through the debug information interface; the test PCIe root complex also detects its own uncorrectable fault register, the uncorrectable fault register and the correctable fault register of the circuit under test, and outputs the detection results through the debug information interface.

[0048] The automatic testing equipment selects a corresponding time period to perform dynamic power consumption testing on the circuit during the operation of the PCIe interface of the circuit under test, based on the dynamic power consumption test requirements of the circuit.

[0049] An automatic testing device for PCIe bus interface circuits includes a test root compound and / or endpoint device function and multiple high-speed relays, configured according to the device type of the PCIe interface of the device under test. The PCIe interface transmit / receive signals of the circuit under test are connected to the test root compound and / or endpoint device function via the multiple high-speed relays under the control of the testing machine, or connected to the high-speed electrical parameter testing channel of the testing machine. The test root compound or endpoint device and the circuit under test are independently powered by the power supply channel of the automatic testing machine. The test PCIe root compound or endpoint device provides a debugging information interface connected to the testing channel of the testing machine.

[0050] The PCIe root complex or endpoint device used for testing provides a command interface for connecting to the test channel of the test machine.

[0051] When the circuit under test is a PCIe root complex device, only the test PCIe endpoint device function is integrated, and no other PCIe functional devices are integrated; when the circuit under test is a PCIe endpoint device, only the test PCIe root complex function is integrated, and no other PCIe functional devices are integrated; when the circuit under test is a PCIe switching circuit, it integrates not only one of the test PCIe root complex functional devices, but also one or more of the test PCIe endpoint devices.

[0052] This invention utilizes general-purpose integrated circuit automatic test equipment to automate the testing of root complex devices, PCIe switching devices, and endpoint device circuits. It reduces the existing technical solution of first using automated test equipment and then using dedicated functional test fixtures to perform functional testing and dynamic power consumption parameter testing twice to a single test. This reduces the labor costs, equipment costs, and testing time in circuit production testing, and effectively lowers the probability of quality defects such as appearance or shape damage caused by repeated insertion and removal of circuits in test fixtures.

[0053] Example 1: Testing of a PCIe 2.0 Switching Circuit

[0054] Example 1 describes a fully automated test of an 8-channel, 8-port PCIe 2.0 switching circuit with a maximum link width of x4, based on the V93K integrated circuit automated test platform. The circuit under test in this example has 8 channels, including 8 pairs of PCIe transmit signals and 8 pairs of PCIe receive signals, totaling 32 high-speed signals with a maximum transmission rate of 5Gbps. Under current technological conditions, it is impossible to perform switching function and maximum dynamic power consumption tests on this circuit using an ATE automated test platform. Figure 1 This is a schematic diagram of an automatic test carrier board for a PCIe switching circuit according to an embodiment of the present invention. Using this carrier board and the automatic test method for the PCIe switching circuit described in this embodiment, comprehensive circuit tests such as electrical parameters, switching functions, and maximum dynamic power consumption of the PCIe switching circuit can be performed on an ATE automatic test platform.

[0055] This embodiment's carrier board design integrates two FPGAs and their associated loading PROMs. FPGA1 integrates a test root complex and up to three endpoint device functions, while FPGA2 integrates four test endpoint device functions. Both FPGAs have four PCIe 2.0 x1 paths. FPGA1 can function as either a test root complex and three endpoint device functions or as a root complex with four paths. This embodiment's carrier board also integrates 32 high-speed relays. Under the switching control signal of the high-speed relay group, the 32 high-speed PCIe signals of the circuit under test can be connected one-to-one with the 32 high-speed PCIe signals of the test PCIe root complex and up to seven PCIe endpoint device functions, or one-to-one with the 32 high-speed electrical parameter test channels of the test equipment. The FPGA and its associated loading PROM containing the test root complex or endpoint devices are connected to the circuit under test... Each path is independently powered by the power supply channel of the V93K test machine; the FPGA where the test root compound or endpoint device is located is provided with a shared reset signal and 8 pairs of 100MHz PCIe differential clock signals refclk0_100M_p / n~refclk7_100M_p / n by the low-speed channel of the V93K test machine; the test PCIe root compound or endpoint device provides a debug information interface fpga_out[15:0] which is connected to the low-speed test channel of the test machine; the test PCIe root compound and endpoint device in FPGA1 provide a command interface fpga_ctrl_in[1:0] which is connected to the test channel of the test machine.

[0056] The fpga_ctrl_in[1:0] signal is used to control whether FPGA1 works as a test root complex and 3-endpoint device or as an x4-channel root complex device; fpga_out[0] is the first information output signal indicating whether the circuit under test is functioning normally; fpga_out[8] is the second information output signal indicating whether the circuit under test is functioning normally; fpga_out[15:9,7:1] is the test program debugging signal.

[0057] The specific steps of an automatic testing method for a PCIe switching circuit according to Embodiment 1 of the present invention are as follows:

[0058] Step 1: Control the high-speed relay of the circuit under test to connect the PCIe transmit / receive differential signal of the circuit under test to the high-speed test channel of the machine through the machine control signal of the automatic test equipment. The automatic test equipment can test the relevant functions and electrical parameters of the circuit under test without the need for a PCIe interface according to the test excitation and response of the circuit under test.

[0059] Specific tests include: boundary scan test, scan chain test and memory built-in self-test of the circuit under test, SPI interface function test of the circuit under test, low-speed parameter test such as input and output level, input leakage current, tri-state leakage current and static power supply current of the circuit under test, and control the circuit under test to perform receiver and transmitter electrical parameter test of PCIe high-speed interface through the test pins such as JTAG.

[0060] Step 2: Control the high-speed relay to connect the PCIe transmit / receive differential signals of the circuit under test to the test PCIe root complex and endpoint devices through the machine control signal; provide the necessary clock, reset and control excitation signals to the circuit under test and the test PCIe root complex or endpoint devices through the test channel of the test machine; under the control of fpga_ctrl_in[1:0], make fpga1 function as a test x1 link root complex and three x1 link endpoint devices.

[0061] Step 3: After the reset signal is removed, all 8 PCIe links between the test PCIe root complex and endpoint devices and the circuit under test are automatically trained and established according to the PCIe protocol.

[0062] The FPGA hardware logic of the test PCIe root complex automatically enumerates and configures the circuit under test and its connected test PCIe endpoint devices 100ms after the reset ends. After the test root complex completes the enumeration and configuration of the switch circuit under test, it reads the link status registers of the 8 ports of the circuit under test through configuration transaction 0 or configuration transaction 1. If the root complex does not enumerate 8 port switches and 7 endpoint devices under test, it indicates that the link has not been established. Or, if any of the links of the 8 ports of the switch circuit under test is not at a rate of 5.0Gbps, the hardware in the FPGA will set the first information output signal fpga_out[0] to indicate that the circuit under test is malfunctioning.

[0063] Step 4: After all 8 ports of the switch circuit under test have successfully established a 5.0Gbps x1 link, the root complex and the 7 test endpoint devices automatically send switch test memory write transactions according to a 128-byte payload size; ports 0, 1, 2 and 3 of the switch under test exchange test memory write transactions bidirectionally with ports 4, 5, 6 and 7 respectively; at this time, the circuit is in maximum power consumption mode, and the automatic test equipment simultaneously tests the power supply current of the circuit under test and calculates the maximum dynamic power consumption of the circuit under test.

[0064] Step 5: The test PCIe root complex and 7 endpoint devices are automatically recorded by the hardware in the FPGA during the switching transaction test. The number of test memory write transactions from the switching circuit under test is recorded. After 100ms of testing, the transmission of test transactions is stopped and the number of received switching test memory transactions is checked. When the hardware in FPGA1 detects that the number of received switching test memory transactions does not meet the expectations, the first information output signal fpga_out[0] is set to indicate that the circuit under test is malfunctioning. When the hardware in FPGA2 detects that the number of received switching test memory transactions does not meet the expectations, the second information output signal fpga_out[8] is set to indicate that the circuit under test is malfunctioning.

[0065] Step 6: The test root complex device automatically reads the uncorrectable error status and correctable error status of each port of the PCIe switching circuit under test. It automatically reads the uncorrectable error status of the test endpoint device and determines whether the fault report bits such as Data Link Protocol Error Status, Poisoned TLP Status, Malformed TLP Status, and ECRC Error Status of each uncorrectable and correctable error status of the root complex itself and the read uncorrectable and correctable error status registers are set to determine whether the circuit under test is functioning normally. When the test root complex device determines that the circuit under test is malfunctioning based on the above fault registers, it sets the first information output signal fpga_out[0] to indicate that the circuit under test is malfunctioning.

[0066] Step 7: The high-speed relay connection state remains unchanged. The automatic test equipment resets FPGA1 and FPGA2. At the same time, by changing the value of the fpga_ctrl_in[1:0] signal, FPGA1 is configured to work as the root composite device mode of an x4 link. Subsequently, the circuit under test is tested in a working mode with one x4 upstream port and four x1 downstream ports, similar to the methods in steps 3 to 6. The first information output signal fpga_out[0] and the second information output signal fpga_out[8] indicate whether the circuit under test is functioning normally. The detailed steps will not be described here.

[0067] Example 2: Testing a PCIe interface to serial port circuit

[0068] Example 2 demonstrates the testing of a PCIe interface to serial port circuit using the V93K integrated circuit automated test platform. The host interface of the circuit under test is a 2.5Gbps PCIe 1.0x1 high-speed interface. The circuit integrates two completely independent full-duplex asynchronous serial ports with a maximum interface speed of 8Mbps. It also integrates independent asynchronous serial port data buffers for transmission and reception. The circuit's function is to convert data transmission between the PCIe interface connected to the CPU and an external serial port. This circuit under test is a PCIe endpoint device with four high-speed PCIe signals. Current technology does not allow for testing the data transmission conversion function and maximum dynamic power consumption of this circuit on the ATE automated test platform. Figure 2 This is a schematic diagram of the automatic test board principle of a PCIe interface to serial port circuit according to Embodiment 2 of the present invention.

[0069] The carrier board design of this embodiment integrates an FPGA and its associated program loading PROM, and integrates four high-speed relays. The FPGA integrates a test root composite device. Under the control of the switching control signals of the high-speed relay group, the four high-speed PCIe signals of the circuit under test can be connected one-to-one with the four high-speed PCIe signals of the test root composite device, or one-to-one with the four high-speed electrical parameter test channels of the test instrument. The FPGA and its associated loading PROM containing the test root composite device and the circuit under test are independently powered by the power supply channels of the test instrument. The FPGA is provided with a reset signal and a pair of 100MHz PCIe differential clock signals refclk0_100M_p / n by the low-speed channel of the test machine; the test PCIe root complex provides an information interface fpga_out[1:0] connected to the low-speed test channel of the test machine; the test PCIe root complex device provides a command interface fpga_ctrl_in[1:0] connected to the test channel of the test machine; fpga_out[0] is the first information output signal indicating whether the circuit under test is functioning normally, and fpga_out[1] is the second information output signal indicating whether the circuit under test is functioning normally.

[0070] Embodiment 2 of the present invention

[0071] The specific steps of an automated testing method for a PCIe interface to serial port circuit are as follows:

[0072] Step 1: Control the high-speed relay to connect the PCIe transmit / receive differential signal of the circuit under test to the high-speed test channel of the machine through the automatic test equipment's machine switching control channel. The automatic test equipment can test the relevant functions and electrical parameters of the circuit under test according to the test excitation and response of the circuit without the need for a PCIe interface.

[0073] Specific tests include: boundary scan test, scan chain test, and memory built-in self-test of the circuit under test, and the I / O of the circuit under test. 2 C interface function test, low-speed parameter test of the circuit under test such as input and output level, input leakage current, tri-state leakage current, static power supply current, etc., and control the circuit under test to perform PCIe high-speed interface receiver and transmitter electrical parameter test through the circuit's JTAG and other test pins.

[0074] Step 2: Control the relay to connect the PCIe transmit / receive differential signal of the circuit under test and the PCIe root complex device for testing through the machine switching control channel; provide the necessary clock, reset and control excitation signals to the circuit under test and the PCIe root complex device for testing through the test channel of the test machine.

[0075] Step 3: After the reset signal is removed, the PCIe link between the test PCIe root complex device and the circuit under test is automatically trained and established according to the PCIe protocol.

[0076] The FPGA internal hardware logic of the test PCIe root complex automatically enumerates and configures the circuit under test through configuration 0 transactions and memory transactions 100ms after the reset ends. Since the circuit under test is a 2.5Gbps PCIe interface with a link width of x1, the fact that the circuit under test can successfully respond to configuration 0 transactions and memory transactions during the enumeration and configuration tests proves that the link has been successfully established. If the circuit under test fails to respond to configuration 0 transactions and memory transactions during the enumeration and configuration tests, the test root complex hardware sets the first information output signal fpga_out[0] to indicate that the circuit under test has failed.

[0077] Step 4: After the circuit under test successfully establishes a link, the test root complex receives the command fpga_ctrl_in[1:0], writes transmission data to the transmit buffers of serial ports 1 and 2 through the PCIe interface, and starts serial port transmission; at the same time, the automatic test machine starts serial ports 1 and 2 to send data to the root complex of the PCIe interface. At this time, the circuit is in full-duplex transmission and data conversion between the dual serial ports and the PCIe interface, and is in the maximum power consumption mode. During this period, the automatic test equipment tests the power supply current of the circuit under test and calculates the maximum dynamic power consumption of the circuit under test.

[0078] Step 5: During the test, the tester detects the output of serial port 1 and serial port 2. When the tester detects that the output of serial port 1 and serial port 2 is inconsistent with the data sent by the PCIe root complex, the tester determines that the PCIe to serial port transmission conversion function of the circuit under test is invalid. During the test, the PCIe root complex automatically detects the PCIe data received by the circuit under test. When the data received by the PCIe interface is inconsistent with the data sent by serial port 1 and serial port 2, the hardware automatically sets the first information output signal fpga_out[0] to indicate that the serial port to PCIe interface transmission function of the circuit under test is invalid.

[0079] Step 6: When the set test time ends, the test root complex device automatically reads the uncorrectable fault register and correctable fault register of the PCIe circuit under test. It determines whether the circuit under test is functioning normally by combining the fault report bits such as DataLink Protocol Error Status, Poisoned TLP Status, Malformed TLP Status, and ECRCError Status of the uncorrectable fault register of the root complex itself. When the test root complex device determines that the circuit under test is malfunctioning based on the above fault registers, it sets the second information output signal fpga_out[1] to indicate that the circuit under test is malfunctioning.

[0080] Example 3: Automated Testing of Functional Circuitry for a PCIe Root Complex Device

[0081] Example 3 describes the testing of a processor circuit using the V93K integrated circuit automated test platform. The circuit under test integrates a processor core and multiple protocol bus interfaces, including a PCIe bus interface with a maximum speed of 5Gbps x2 interface, which functions as a root complex device. Figure 3 This is a schematic diagram of the automatic test carrier board for the functional circuit of a PCIe root complex device according to Embodiment 3 of the present invention.

[0082] The carrier board design of this embodiment integrates an FPGA and its associated program loading PROM, and integrates 8 high-speed relays. The FPGA integrates a test x2 endpoint device. Under the control of the switching control signal of the high-speed relay group, the 8 high-speed PCIe signals of the circuit under test can be connected one-to-one with the 4 high-speed PCIe signals of the test PCIe endpoint device, or one-to-one with the 8 high-speed electrical parameter test channels of the test machine. The FPGA and its associated loading PROM containing the test endpoint device are independently powered by the power supply channels of the test machine, as are the circuit under test. The FPGA containing the test endpoint device receives a reset signal and a pair of PCIe differential clock signals refclk0_100M_p / n from the low-speed channel of the test machine. The test PCIe endpoint provides an information interface ep_out connected to the low-speed test channel of the test machine. When a 5Gbps link with a width of x2 is successfully established between the circuit under test and the test endpoint device, the FPGA containing the test endpoint device automatically sets ep_out; otherwise, ep_out outputs a low level.

[0083] The specific test steps of the automatic test method for the functional circuit of a PCIe root complex device according to Embodiment 3 of the present invention are as follows:

[0084] Step 1: Control the relay to connect the PCIe transmit / receive differential signal of the circuit under test and the PCIe endpoint device for testing through the machine switching control channel; provide clock, reset and control excitation signals to the circuit under test and the PCIe endpoint device for testing through the test channel of the test machine.

[0085] Step 2: After the reset signal is removed, the PCIe link between the test PCIe endpoint device and the circuit under test will automatically be trained and established according to the PCIe protocol.

[0086] Step 3: The automatic test equipment tests the low-speed I / O functions such as serial ports and input / output levels, input leakage current, tri-state leakage current, and other electrical parameters of the circuit under test according to the test stimuli and response of the circuit under test.

[0087] Step 4: After completing the test in Step 3 above, the test machine determines whether a 5Gbps x2 link has been successfully established between the circuit under test and the test endpoint device by checking whether ep_out is set; if ep_out is low, it is determined that the PCIe interface function of the circuit under test is faulty.

[0088] Step 5: If a link is successfully established between the circuit under test and the test endpoint device, the root complex device circuit under test performs configuration and communication tests through configuration 0 transactions, memory read and write transactions and the test endpoint device. If the value read by the root complex circuit under test in a specific memory area of ​​the test endpoint device is different from the value written, the GPIO

[31] output of the circuit under test is set. When the test machine detects that GPIO

[31] is high, it determines that the PCIe interface function of the circuit under test is invalid. During this period, the automatic test equipment tests the power supply current of the PCIe interface of the circuit under test and calculates the maximum dynamic power consumption of the PCIe interface.

[0089] Step 6: After completing the set number of transaction tests, the PCIe circuit under test reads the fault report bits such as Data Link Protocol Error Status, Poisoned TLPStatus, Malformed TLP Status, and ECRC Error Status of its uncorrectable fault register and correctable fault register to determine whether the circuit under test is functioning normally; when the circuit under test is judged to be malfunctioning based on the above fault registers, the GPIO

[31] output of the circuit under test is set, and when the test machine detects that GPIO

[31] is high, it is judged that the PCIe interface function of the circuit under test is malfunctioning.

[0090] Step 7: After completing the PCIe interface function and dynamic power consumption test, the high-speed relay is controlled by the automatic test equipment's machine switching control channel to connect the PCIe transmit / receive differential signal of the circuit under test to the high-speed test channel of the machine. The automatic test equipment tests the electrical parameters of the PCIe transceiver terminal of the circuit that does not require the PCIe interface to work and the static power supply current parameters of the circuit according to the test excitation and response of the circuit under test.

Claims

1. An automatic testing method for PCIe bus interface circuits, characterized in that, Includes the following steps: S1 integrates high-speed relays, test PCIe root complexes and / or endpoint devices on the carrier board of the automatic test equipment; S2, through the control signal of the automatic test equipment, controls the high-speed relay to connect the PCIe transmit and receive differential signals of the circuit under test to the high-speed test channel of the automatic test equipment. The automatic test equipment can test the relevant functions and electrical parameters of the circuit under test without the need for a PCIe interface, according to the test excitation and response of the circuit under test. S3, the relay is controlled by the automatic test equipment control signal to connect the PCIe transmit / receive differential signal of the circuit under test to the test PCIe root complex and / or endpoint device to realize automatic testing; The test channel of the automatic test equipment provides clock, reset and control excitation signals to the circuit under test and the test PCIe root complex or / and endpoint device, and the test PCIe root complex or / and endpoint device automatically performs functional tests with the PCIe interface of the circuit under test. The test PCIe root complex and / or endpoint devices provide debugging information interfaces based on the PCIe interface function test status between the test PCIe and the circuit under test, allowing the automatic test equipment to determine whether the circuit function is normal. The automatic test equipment tests other circuit functions that can only be tested after the PCIe interface of the circuit under test is working, according to the test requirements of the circuit under test. The automatic functional testing of the PCIe interface between the test PCIe root complex and / or endpoint device and the circuit under test includes the following parts: all PCIe interfaces between the test PCIe root complex and / or endpoint device and the circuit under test are automatically trained and established according to the PCIe protocol. If the circuit under test cannot successfully establish a link within a preset time, the circuit is judged to be functionally faulty. After the PCIe interface between the test PCIe root complex and / or endpoint device and the circuit under test is successfully trained and established according to the PCIe protocol, the test PCIe root complex and / or endpoint device performs specific PCIe transaction transmission and related functional tests through the PCIe link interface based on the device function type and specific function of the circuit under test and the circuit under test. The automatic testing equipment selects a corresponding time period to perform dynamic power consumption testing of the circuit based on the dynamic power consumption test requirements of the circuit during the operation of the PCIe interface of the circuit under test. When the circuit under test is a PCIe root complex device, only the test PCIe endpoint device is integrated, and no other PCIe functional devices are integrated; when the circuit under test is a PCIe endpoint device, only the test PCIe root complex is integrated, and no other PCIe functional devices are integrated; when the circuit under test is a PCIe switching circuit, one of the test PCIe root complex functional devices and one or more of the test PCIe endpoint devices are integrated.

2. The automatic testing method for a PCIe bus interface circuit according to claim 1, characterized in that, When the circuit under test is a PCIe root complex device, the circuit under test initiates a configuration 0 transaction and a memory access transaction to perform a functional test of the PCIe interface with the PCIe endpoint device used for testing. When the circuit under test is a PCIe endpoint device, the test PCIe root complex initiates a configuration 0 transaction and performs tests on the PCIe interface and other functions of the circuit after the PCIe interface is working, based on the internal memory and / or I / O resources of the circuit under test.

3. The automatic testing method for a PCIe bus interface circuit according to claim 1, characterized in that, When the circuit under test is a PCIe switching circuit, the test PCIe root complex performs enumeration and configuration tests on the circuit under test and the test PCIe endpoint devices connected to it; the test PCIe root complex sends configuration 0 transactions, configuration 1 transactions, and memory access transactions to the upstream port of the circuit under test, and the test PCIe endpoint devices send memory transactions, message transactions, or response completion packets to the downstream port of the circuit under test.

4. An automatic testing device for a PCIe bus interface circuit used in the method of claim 1, characterized in that, Includes test PCIe root complex and / or endpoint device functions that connect to the PCIe interface of the device under test and multiple high-speed relays; The PCIe interface of the circuit under test transmits and receives signals through multiple high-speed relays under the control of the automatic test equipment and is connected to the test PCIe root complex and / or endpoint device functions, or to the high-speed test channel of the automatic test equipment. The PCIe root complex and / or endpoint devices used for testing are independently powered by the power channels of the automated test equipment, respectively, and the circuit under test. The PCIe root complex and / or endpoint devices used for testing provide a debug information interface and connect to the test channels of automated test equipment.

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