Memory controller and method of operation thereof

Abstract

Provided herein are a memory controller and an operating method thereof. The memory controller can include an SPO detector configured to output a detection signal upon detecting an SPO, a memory buffer configured to store host data, and a power loss controller configured to receive dump data corresponding to the host data based on the detection signal, store the dump data and a dump frequency corresponding to the dump data, and output the dump data and the dump frequency to a memory device, wherein the dump frequency indicates a number of times that different items of the host data have been dumped from the memory buffer to the power loss controller, and the power loss controller is configured to control a recovery operation corresponding to the SPO based on the dump frequency received from the memory device.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0166871, filed with the Korean Intellectual Property Office on December 2, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments described herein relate to a memory controller and a method of operating the memory controller. Background Technology

[0004] Storage devices store data under the control of a host device such as a computer, smartphone, or smartpad. Some storage devices (e.g., hard disk drives) store data on disks, while others (e.g., solid-state drives and memory cards) store data in semiconductor memory. Structurally, a storage device may include a controller that controls the data storage within the memory device. Memory devices can be volatile or non-volatile. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Summary of the Invention

[0005] One or more embodiments described herein relate to a memory controller that performs a recovery operation in the event of a sudden power outage.

[0006] These or other embodiments can perform recovery operations based on a comparison between the indexes of the recovery region and the meta region.

[0007] These or other embodiments relate to a method of operating a memory controller.

[0008] Embodiments of this disclosure may provide a memory controller for controlling a memory device. The memory controller may include: a sudden power outage (SPO) detector configured to output a detection signal upon detecting a sudden power outage; a memory buffer configured to store host data output from a host; and a power loss controller configured to receive dump data corresponding to the host data from the memory buffer based on the detection signal, store the dump data and a dump age corresponding to the dump data, and output the dump data and dump age to the memory device. The dump age may indicate the number of times different items of host data have been dumped from the memory buffer to the power loss controller. The power loss controller may be configured to receive the dump data and dump age from the memory device during a recovery operation corresponding to the sudden power outage, and control the recovery operation based on the dump age.

[0009] Embodiments of this disclosure may provide an apparatus. The apparatus may include a memory device and a memory controller configured to control the memory device to: store dump data and a dump frequency in a recovery area of ​​the memory device based on the detection of a sudden power failure, the dump data corresponding to data temporarily stored in a memory buffer of the memory controller; and perform a recovery operation based on the dump frequency stored in the memory device. The dump frequency may indicate the number of times different items of host data corresponding to the dump data have been dumped.

[0010] Embodiments of this disclosure may provide a method for operating a memory controller. The method may include: storing host data from a host in a memory buffer; upon detecting a sudden power failure, storing dump data and a corresponding dump frequency, the dump data corresponding to the host data stored in the memory buffer; determining whether the host data will be dumped to a memory device; outputting the dump data and dump frequency to the memory device; receiving the dump data and dump frequency from the memory device; and performing a recovery operation corresponding to the sudden power failure based on the dump frequency. The dump frequency may indicate the number of times different items of the host data have been dumped into dump data. Attached Figure Description

[0011] Figure 1 An embodiment of the storage device is shown.

[0012] Figure 2 An embodiment of the memory device is shown.

[0013] Figure 3 An embodiment of a memory cell array is shown.

[0014] Figure 4 An embodiment of the operation of the memory controller is shown.

[0015] Figure 5 An embodiment of the operation of the memory controller is shown.

[0016] Figure 6 An example of supplying auxiliary electricity is shown.

[0017] Figure 7 An example of the recovery operation is shown.

[0018] Figure 8 An example is shown where another sudden power outage occurs after the recovery operation corresponding to a sudden power outage (SPO) has been completed.

[0019] Figure 9 An example is shown where another sudden power outage occurs before the SPO recovery operation is complete.

[0020] Figure 10 An embodiment of a method for operating a memory controller is shown.

[0021] Figure 11 An embodiment of a method for operating a memory controller is shown.

[0022] Figure 12 An embodiment of a memory controller is shown.

[0023] Figure 13 An embodiment of a memory card system is shown.

[0024] Figure 14 An embodiment of a solid-state drive system is shown.

[0025] Figure 15 An example of a user system is shown. Detailed Implementation

[0026] The specific structural or functional descriptions of embodiments of this disclosure incorporated herein by reference are for the purpose of describing embodiments of this disclosure only. Such descriptions should not be construed as limiting the scope to the embodiments described herein.

[0027] Various embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown, enabling those skilled in the art to readily implement the technical ideas of the present disclosure.

[0028] Figure 1 An embodiment of storage device 50 is shown, which may include memory device 100 and memory controller 200. Storage device 50 may store data under the control of host 300. Examples of host 300 include mobile phones, smartphones, MP3 players, laptop computers, desktop computers, game consoles, televisions (TVs), tablet PCs, and in-vehicle infotainment systems.

[0029] Depending on the communication scheme of the interface of, for example, host 300, storage device 50 can be any of various types of storage devices. Examples of storage device 50 include solid-state drives (SSDs), multimedia cards such as MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC), or micro MMC, secure digital cards such as SD, mini SD, or micro SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0030] The storage device 50 can be any of various types of packages. Examples of packages include point-of-purchase (POP), system-in-package (SIP), system-on-a-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0031] The memory device 100 can store data in response to control by the memory controller 200. The memory device 100 may include a memory cell array comprising a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks, and each memory block may include a plurality of memory cells, which may constitute a plurality of pages. In embodiments, each page may be a unit for storing data in or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0032] Memory device 100 may include, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory Device, Resistive RAM (RRAM), Phase Change Random Access Memory (PRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). For ease of description, it may be assumed that memory device 100 is NAND Flash Memory.

[0033] The memory device 100 may have a two-dimensional (2D) array structure or a three-dimensional (3D) array structure. Although a 3D array structure is described below as an example, this disclosure is not limited to 3D array structures. This disclosure is applicable not only to flash memory devices in which the charge storage layer is formed by conductive floating gates (FGs), but also to charge-fetch flash memory (CTF) devices in which the charge storage layer is formed by an insulating layer.

[0034] In one embodiment, the memory device 100 may operate as a single-level cell (SLC) storing one data bit in one memory cell. In another embodiment, the memory device 100 may operate as a memory cell storing at least two data bits. For example, the memory device 100 may operate as a multi-level cell (MLC) storing two data bits in one memory cell, a three-level cell (TLC) storing three data bits in one memory cell, or a four-level cell (QLC) storing four data bits in one memory cell.

[0035] Memory device 100 can receive commands and addresses from memory controller 200 and can access a region in the memory cell array selected by the address. For example, memory device 100 can perform an operation corresponding to the command on the region selected by the address. In one embodiment, memory device 100 can perform a write operation (e.g., a programming operation), a read operation, or an erase operation in response to a received command. When a programming command is received, memory device 100 can program data into the region selected by the address. When a read command is received, memory device 100 can read data from the region selected by the address. When an erase command is received, memory device 100 can erase the data stored in the region selected by the address.

[0036] The memory controller 200 can control all operations of the storage device 50. When a power supply voltage is applied to the storage device 50, the memory controller 200 can execute instructions (e.g., firmware). When the storage device 100 is a flash memory device 100, the memory controller 200 can execute firmware such as a flash translation layer (FTL) to control communication between the host 300 and the storage device 100.

[0037] In one embodiment, the memory controller 200 may include firmware that receives data and logical block addresses (LBAs) from the host 300 and translates the LBAs into physical block addresses (PBAs), which indicate the addresses of memory cells in the memory device 100 where data is stored. Further, the memory controller 200 may store a logical-physical address mapping table configuring the mapping relationship between LBAs and PBAs in a buffer memory.

[0038] The memory controller 200 can control the memory device 100 in response to requests from the host 300, thereby performing programming, reading, or erasing operations. For example, when a programming request is received from the host 300, the memory controller 200 can translate the programming request into a programming command and provide the programming command, physical block address (PBA), and data to the memory device 100. When a read request and a logical block address are received together from the host 300, the memory controller 200 can translate the read request into a read command, select the physical block address corresponding to the logical block address, and then provide the read command and the physical block address (PBA) to the memory device 100. When an erase request and a logical block address are received together from the host 300, the memory controller 200 can translate the erase request into an erase command, select the physical block address corresponding to the logical block address, and then provide the erase command and the physical block address (PBA) to the memory device 100.

[0039] In this embodiment, the memory controller 200 can autonomously generate programming commands, addresses, and data without receiving a request from the host 300, and can transmit these programming commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0040] In an embodiment, the memory controller 200 may include a sudden power outage (SPO) detector 210. The SPO detector 210 can detect a sudden power outage (SPO), in which power to the memory device 100 is momentarily disconnected (or otherwise interrupted) during operation. When power is restored after an SPO, an SPO recovery operation can be performed. When a SPO occurs during programming operations of the memory device 100, data can be reprogrammed to a newly allocated memory block (rather than the memory block where the SPO occurred) via the SPO recovery operation.

[0041] The memory controller 200 may include, for example, a memory buffer 220, which may be, for example, dynamic random access memory (DRAM) and / or static random access memory (SRAM). The memory buffer 220 may temporarily store received data from the host 300 before it is programmed into the memory device 100. The data stored in the memory buffer 220 may be output and programmed into the memory device 100.

[0042] In the event of a sudden power outage (SPO) before the data stored in memory buffer 220 is programmed into memory device 100, the data stored in memory buffer 220 can be output to memory device 100 before the power is disconnected, and when the SPO recovery operation is performed, the data output to memory device 100 can be transferred back to memory buffer 220.

[0043] In one embodiment, the memory controller 200 may include a power loss controller 230. The power loss controller 230 can provide a stable power supply in the event of a sudden power outage (SPO) and can prevent data loss due to an SPO.

[0044] In one embodiment, the power loss controller 230 can prevent momentary power disconnection by supplying auxiliary power in the event of a sudden power outage (SPO). For example, the power loss controller 230 can gradually disconnect the power supply or disconnect the power supply at a predetermined rate or with a time delay. Furthermore, in the event of a sudden power outage (SPO), the power loss controller 230 can receive data stored in the memory buffer 220 and store the received data in the memory device 100.

[0045] In one embodiment, storage device 50 may include a buffer memory, and memory controller 200 may control data exchange between host 300 and the buffer memory. In one embodiment, memory controller 200 may temporarily store system data used to control storage device 100 in the buffer memory. For example, memory controller 200 may temporarily store data from host 300 in the buffer memory and then transfer the data temporarily stored in the buffer memory to storage device 100.

[0046] In various embodiments, the buffer memory can be used as the working memory or cache memory of the memory controller 200. The buffer memory can store code or commands executed by the memory controller 200. In one embodiment, the buffer memory can store data processed by the memory controller 200. The buffer memory can be implemented as, for example, DRAM, such as Double Data Rate SDRAM (DDR SDRAM), Generation 4 Double Data Rate (DDR4) SDRAM, Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, or Rambus DRAM (RDRAM), or can be implemented as static RAM (SRAM).

[0047] In various embodiments, the buffer memory may be external to and coupled to the storage device 50. In this case, one or more external volatile memory devices may be used as the buffer memory.

[0048] In one embodiment, the memory controller 200 can control at least two memory devices. In this case, the memory controller 200 can control the memory devices according to an interleaving scheme, thereby improving operational performance.

[0049] The host 300 can communicate with the storage device 50 using at least one of a variety of communication methods. Examples include Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Reduced Load DIMM (LRDIMM) communication methods.

[0050] Figure 2 An embodiment of a memory device 100 is shown, which may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0051] Reference Figure 2The memory cell array 110 includes multiple memory blocks BLK1 to BLKz connected to the row decoder 121 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. Each of the memory blocks BLK1 to BLKz may be connected to the page buffer group 123 via bit lines BL1 to BLn. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In this embodiment, the memory cells may be non-volatile memory cells. Memory cells connected to the same word line may correspond to a single page. Therefore, a single memory block may include multiple pages.

[0052] Each of the memory cells in the memory cell array 110 can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0053] The peripheral circuitry 120 can perform programming, reading, and / or erasing operations on selected regions of the memory cell array 110 under the control of the control logic 130. The peripheral circuitry 120 can also drive the memory cell array 110, for example, by applying various operating voltages to the row lines RL and bit lines BL1 to BLn, and / or discharge the applied voltages, under the control of the control logic 130.

[0054] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126. The row decoder 121 is connected to the memory cell array 110 via row lines RL, and the row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. In an embodiment, the word lines may include ordinary word lines and dummy word lines. In an embodiment, the row lines RL may further include pipe select lines.

[0055] The row decoder 121 can decode the row address RADD received from the control logic 130, and can select at least one of the memory blocks BLK1 to BLKz according to the decoded address. Further, the row decoder 121 can select at least one word line WL of the selected memory block according to the decoded address, thereby applying the voltage generated by the voltage generator 122 to the at least one word line WL.

[0056] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and can apply a programming pass voltage (e.g., a level lower than the programming voltage) to the unselected word line. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and apply a verification pass voltage (e.g., a level higher than the verification voltage) to the unselected word line. During a reading operation, the line decoder 121 can apply a read voltage to the selected word line and can apply a read pass voltage (e.g., a level higher than the read voltage) to the unselected word line.

[0057] In this embodiment, an erase operation of the memory device 100 is performed based on memory blocks. During the erase operation, the row decoder 121 can select a memory block based on the decoded address. During the erase operation, the row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0058] Voltage generator 122 can operate under the control of control logic 130. Voltage generator 122 can generate multiple voltages based on the external power supply voltage provided to memory device 100. For example, voltage generator 122 can generate various operating voltages Vop for programming, reading, and / or erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, and / or other voltages under the control of control logic 130.

[0059] In this embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the operating voltage of memory device 100.

[0060] In this embodiment, voltage generator 122 may generate multiple voltages based on an external power supply voltage or an internal power supply voltage. For example, voltage generator 122 may include multiple pumping capacitors for receiving the internal power supply voltage, and may generate multiple voltages by selectively activating the multiple pumping capacitors under the control of control logic 130. The generated voltages may be supplied to memory cell array 110 by line decoder 121.

[0061] Page buffer group 123 includes first to n page buffers PB1 to PBn connected to memory cell array 110 via first to nth bit lines BL1 to BLn. The first to nth page buffers PB1 to PBn can operate under the control of control logic 130. For example, the first to nth page buffers PB1 to PBn can operate in response to the page buffer control signal PBSIGNAL. Furthermore, for example, during read or verification operations, the first to nth page buffers PB1 to PBn can temporarily store data received via the first to nth bit lines BL1 to BLn, or can sense the voltage or current of the bit lines BL1 to BLn.

[0062] During programming operations, for example, when a programming voltage is applied to the selected word line, the first to nth page buffers PB1 to PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first to nth bit lines BL1 to BLn. The memory cell in the selected page is programmed based on the received data DATA.

[0063] During a programming verification operation, for example, the first to nth page buffers PB1 to PBn can read page data by sensing the voltage or current received from the selected memory cell through the first to nth bit lines BL1 to BLn.

[0064] During a read operation, for example, the first to nth page buffers PB1 to PBn can read data DATA from the memory cell in the selected page through the first to nth bit lines BL1 to BLn, and can output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0065] During an erase operation, for example, the first to nth page buffers PB1 to PBn may allow the first to nth bit lines BL1 to BLn to float, or an erase voltage may be applied to the first to nth bit lines BL1 to BLn.

[0066] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first to nth page buffers PB1 to PBn via the data lines DL, or it can exchange data with the input / output circuitry 125 via the column lines CL.

[0067] Input / output circuit 125 can transmit commands (CMD) and addresses (ADDR) to control logic 130, or exchange data (DATA) with column decoder 124. (See reference...) Figure 1 The memory controller described (e.g., Figure 1(200) Receive command CMD and address ADDR.

[0068] During a read or verification operation, sensing circuit 126 can generate a reference current in response to the enable bit VRYBIT, and can compare the sensed voltage VPB received from page buffer group 123 with the reference voltage generated by the reference current. Sensing circuit 126 can then output a pass signal PASS or a failure signal FAIL based on the comparison result.

[0069] Control logic 130 can respond to the corresponding command CMD and address ADDR by controlling peripheral circuitry 120 through outputting operation signal OPSIG, row address RADD, page buffer control signal PBSIGNAL, and one or more enable bits VRYBIT. For example, control logic 130 can control a read operation on a selected memory block in response to a sub-block read command and address. Control logic 130 can control an erase operation on a selected sub-block within a selected memory block in response to a sub-block erase command and address. Additionally, control logic 130 can determine whether a verification operation has passed or failed by using the PASS signal or the FAIL signal.

[0070] Figure 3 It is shown Figure 2 A diagram illustrating an embodiment of a memory cell array. (Refer to...) Figure 2 and Figure 3 , Figure 3 An embodiment of a circuit diagram of a memory block BLKa is shown, which can represent Figure 2 Storage blocks BLK1 to BLKz in the memory cell array 110.

[0071] The memory block BLKa can be connected to a first select line, a word line, and a second select line arranged in parallel to each other. For example, the word lines can be connected in parallel to each other between the first select line and the second select line. In one embodiment, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL).

[0072] For example, a memory block BLKa may include multiple strings connected between bit lines BL1 to BLn and source line SL. Bit lines BL1 to BLn may be individually connected to strings, and source line SL may be collectively connected to strings. The strings may be configured identically, and in this case, the string ST connected to the first bit line BL1 will be described by way of example.

[0073] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, multiple memory cells F1 to F16, and a drain selection transistor DST. A single string ST may include at least one source selection transistor SST and at least one drain selection transistor DST. A string ST may include more memory cells than memory cells F1 to F16.

[0074] The source of the source select transistor SST can be connected to the source line SL, while the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors in different strings of STs can be connected to the source select line SSL, the gates of the drain select transistors in different strings of STs can be connected to the drain select line DSL, and the gates of memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16 respectively. In one embodiment, among the memory cells in different strings of STs, a group of memory cells connected to the same word line can be referred to as a "physical page: PPG". Therefore, the memory block BLKa can include multiple physical pages PPGs corresponding to the number of word lines WL1 to WL16.

[0075] A memory cell can store one data bit. Such a cell can be designated as a "Single-Level Cell: SLC". A physical page (PPG) can store data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include the number of data bits corresponding to the number of memory cells in a physical page (PPG). In one embodiment, a memory cell can store two or more data bits. Such a cell can be designated as a "Multi-Level Cell: MLC". Here, a physical page (PPG) can store data corresponding to two or more logical page (LPG) cells.

[0076] A memory cell that stores two or more data bits can be referred to as a multi-level cell (MLC). In some cases, a multi-level cell (MLC) can refer to a memory cell that stores two data bits. A memory cell that stores three data bits can be referred to as a three-level cell (TLC). A memory cell that stores four or more data bits can be referred to as a four-level cell (QLC). Additionally, one or more embodiments can be applied to memory cell schemes that store multiple data bits. In one embodiment, memory device 100 may have memory cells that store two or more data bits.

[0077] In this embodiment, each of the memory blocks may have a three-dimensional (3D) structure. Each of the memory blocks may include a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged along the +X, +Y, and +Z directions.

[0078] Figure 4 This is a diagram illustrating an embodiment of the operation of the memory controller 200 in the event of a sudden power failure.

[0079] Reference Figure 4 The memory controller 200 may include a sudden power failure detector 210, a memory buffer 220, and a power loss controller 230. In one embodiment, the sudden power failure detector 210 may detect a sudden power failure (SPO). In one embodiment, a sudden power failure (SPO) may occur in a memory device (e.g., Figure 1 The phenomenon of momentary power outage during operation (100%). When power is restored after a sudden power outage (SPO), an SPO recovery operation can be performed to resume the operation that was suspended due to the sudden power outage (SPO).

[0080] In an embodiment, when the sudden power failure detector 210 detects an SPO, the sudden power failure detector 210 can output a detection signal DETECT_SIG to the power loss controller 230. In an embodiment, the memory buffer 220 can be accessed from the host (e.g., Figure 1 The 300) receives host data HOST_DATA. Host data HOST_DATA can be data to be programmed into a memory device (e.g., ...). Figure 1 (100) of the data.

[0081] In the host (e.g., Figure 1 After receiving the host data HOST_DATA, the memory buffer 220 can temporarily store it in the memory buffer 220, the memory buffer 220 can output the host data HOST_DATA to the memory device (e.g., Figure 1 100). When host data HOST_DATA is output to a memory device (e.g., Figure 1 When the value is 100), the host data HOST_DATA can be programmed into the memory device (e.g., Figure 1 (of 100).

[0082] However, the host data HOST_DATA stored in memory buffer 220 is programmed into the memory device (e.g., Figure 1 A sudden power outage (SPO) may occur before 100) is reached. This is because the host data HOST_DATA has not yet been programmed into the memory device (e.g., Figure 1(100), so host data HOST_DATA may be lost due to sudden power outage (SPO).

[0083] In an embodiment, to prevent the loss of host data HOST_DATA, the power loss controller 230 can receive dump data DUMP_DATA from the memory buffer 220 based on the detection signal DETECT_SIG from the sudden power outage (SPO) detector 210.

[0084] For example, when the power loss controller 230 receives the detection signal DETECT_SIG from the sudden power failure detector 210, the host data HOST_DATA stored in the memory buffer 220 can be dumped to the power loss controller 230. The host data HOST_DATA stored in the memory buffer 220 can be provided to the power loss controller 230, for example, as dump data DUMP_DATA.

[0085] Subsequently, before the power is disconnected, the power loss controller 230 can output the dump data DUMP_DATA received from the memory buffer 220 to the memory device (e.g., Figure 1 100), and the dump data DUMP_DATA can be stored in a memory device (e.g., Figure 1 In the 100), this allows data to be retained without loss. Subsequently, when a recovery operation corresponding to a sudden power outage (SPO) is performed, the memory device (e.g., Figure 1 The dump data DUMP_DATA stored in memory buffer 100 can be output to memory buffer 220 again.

[0086] However, when a sudden power outage (SPO) occurs while the auxiliary power supply to the power loss controller 230 is not fully charged, the host data HOST_DATA stored in the memory buffer 220 may not be dumped to the power loss controller 230. If the host data HOST_DATA is not dumped to the power loss controller 230, the host data HOST_DATA may be lost without being programmed into the memory device (e.g., Figure 1 (of 100).

[0087] Figure 5 This is a diagram illustrating an embodiment of the operation of the memory controller 200 in the event of a sudden power failure.

[0088] Reference Figure 4 and Figure 5 , in order to Figure 4Similar to the memory controller 200, the memory controller 200 may include a sudden power outage detector 210, a memory buffer 220, and a power loss controller 230. Furthermore, the power loss controller 230 may include a recovery area 231. The recovery area 231 may be an area that stores data dumped from the memory buffer 220 in the event of a sudden power outage (SPO).

[0089] In an embodiment, from the host (e.g., Figure 1 The host data HOST_DATA output from the host (e.g., 300) can be stored in the memory buffer 220 and then output to the memory device 100. Here, the host data HOST_DATA can be from the host (e.g., Figure 1 The 300) receives and is to be programmed into the memory device 100.

[0090] To improve storage devices (e.g., Figure 1 The performance of 50) when from the host (e.g., Figure 1 When all host data HOST_DATA received by the host (e.g., 300) is stored in memory buffer 220, even before the host data HOST_DATA is programmed into memory device 100, it can be sent to the host (e.g., Figure 1 The 300) output program completes the response.

[0091] In this embodiment, a sudden power outage (SPO) may occur during the operation of the memory device 100. When a sudden power outage (SPO) occurs, the memory device 100 may suspend its operation, and therefore the data stored in the memory buffer 220 may be lost.

[0092] Therefore, to prevent the loss of data stored in memory buffer 220, the data stored in memory buffer 220 can be output and programmed into memory device 100. In one embodiment, power loss controller 230 can supply auxiliary power to gradually disconnect the power supply, and the auxiliary power can be used to program the data stored in memory buffer 220 into memory device 100.

[0093] For example, after the auxiliary power supply of the power loss controller 230 has finished charging and a sudden power outage (SPO) occurs, auxiliary power can be supplied to the memory device 100 via the auxiliary power supply. Furthermore, based on the auxiliary power supplied by the auxiliary power supply, the host data HOST_DATA stored in the memory buffer 220 can be output as dump data DUMP_DATA to the recovery area 231. The dump data DUMP_DATA stored in the recovery area 231 can then be dumped and stored in the memory device 100.

[0094] When dump data DUMP_DATA is stored in recovery area 231, information indicating the dump frequency can be stored together with the dump data DUMP_DATA. The dump frequency information can indicate the number of times different items of host data have been dumped to recovery area 231. For example, the dump frequency can be a value that increments by "1" each time dump data DUMP_DATA is dumped to recovery area 231. In one embodiment, the dump frequency can be a value obtained by cumulatively counting the number of times dump data DUMP_DATA has been dumped to recovery area 231, and the cumulative count can represent the dump count. The dump frequency can be sequentially incremented by "1" from a default value (e.g., "0").

[0095] For example, when dump data DUMP_DATA is first dumped from memory buffer 220 to recovery area 231, the corresponding dump data DUMP_DATA can be stored in recovery area 231 together with information indicating a dump frequency of "1", which is obtained by counting the number of times data is dumped to recovery area 231. Subsequently, when dump data DUMP_DATA is dumped from memory buffer 220 to recovery area 231 again, the corresponding dump data DUMP_DATA can be stored in recovery area 231 together with a dump frequency of "2", which is obtained by counting the number of times data is dumped to recovery area 231.

[0096] The dump data DUMP_DATA and dump frequency stored in recovery region 231 can be dumped to memory device 100. Subsequently, in a recovery operation corresponding to a sudden power outage (SPO), the dump data DUMP_DATA (which has been dumped to memory device 100) and information indicating the dump frequency can be output from memory device 100 to recovery region 231. When the SPO recovery operation is completed based on the dump data DUMP_DATA, the dump frequency can be stored in a metadata region, for example, a region storing metadata indicating the dump frequency.

[0097] Therefore, in the event of a sudden power outage (SPO), the power loss controller 230 can operate even when the data exists only in the memory buffer 220, thereby preventing the loss of data stored in the memory buffer 220 and ensuring that the data stored in the memory buffer 220 can be programmed. During the SPO recovery operation, the data dumped to the memory device 100 can be output to the recovery area 231, and the recovery operation can be performed based on the data output to the recovery area 231.

[0098] However, when the auxiliary power supply of the power loss controller 230 is delayed or incomplete in charging and a sudden power outage (SPO) occurs, auxiliary power cannot be supplied to the memory device 100 via the auxiliary power supply. When the power loss controller 230 is not operational in these situations, the host data HOST_DATA stored in the memory buffer 220 may not be output to the recovery area 231 as dump data DUMP_DATA.

[0099] In this case, the host data HOST_DATA stored in memory buffer 220 can be programmed in force unit access mode (FUAMODE). For example, this programming operation can be performed in such a way that after programming the host data HOST_DATA stored in memory buffer 220 to memory device 100 and updating the mapping data, the host (e.g., ...) is then... Figure 1 The 300) output completes the response.

[0100] Therefore, when the auxiliary power supply of the power loss controller 230 is delayed or has not yet completed charging, the host data HOST_DATA stored in the memory buffer 220 can be programmed in FUA mode, and then the power supply can be disconnected. This prevents data loss. In an embodiment, an SPO recovery operation can be performed when power is restored after a sudden power outage (SPO).

[0101] However, when the host data HOST_DATA stored in memory buffer 220 is programmed in FUA mode and a sudden power outage (SPO) occurs, followed by power restoration, it may be impossible to know whether the dump data DUMP_DATA stored in recovery area 231 has been dumped and programmed into memory device 100. For example, it may be impossible to determine whether power was disconnected after the dump data DUMP_DATA stored in recovery area 231 had been dumped and stored in memory device 100, or whether power was disconnected if the dump data DUMP_DATA stored in recovery area 231 had not been dumped into memory device 100.

[0102] When an SPO occurs, if it is determined that the dump data DUMP_DATA stored in recovery region 231 is dumped and stored in memory device 100, and an SPO recovery operation is not performed based on the dump data DUMP_DATA stored in recovery region 231, host data HOST_DATA may be lost.

[0103] Conversely, when an SPO occurs, if it is determined that the dump data DUMP_DATA stored in recovery region 231 was not dumped and stored in memory device 100, and an SPO recovery operation is performed based on the dump data DUMP_DATA stored in recovery region 231, the host data HOST_DATA can be changed to the previous data.

[0104] Therefore, according to one or more embodiments, a method can be provided to retain data even when the charging of the auxiliary power supply of the power loss controller 230 is delayed and incomplete.

[0105] Figure 6 This is a diagram illustrating an embodiment of auxiliary power supply for providing auxiliary power and monitoring the auxiliary power supply.

[0106] Reference Figure 6 The power loss controller 230 may include an auxiliary power supply 233 and a monitoring component (e.g., a monitor or monitoring logic) 235. In the event of a sudden power outage (SPO), the auxiliary power supply 233 may supply power to a memory device (e.g., Figure 5 The auxiliary power supply ASSIST_POWER (100) provides auxiliary power (e.g., supplementary power). The monitoring component 235 can monitor the power supply capacity of the auxiliary power supply 233.

[0107] In this embodiment, the auxiliary power supply 233 may include multiple capacitors. The auxiliary power supply 233 can receive host power (HOST_POWER) from an external system and can charge the multiple capacitors using the host power (HOST_POWER). In the event of a sudden power outage (SPO), the auxiliary power supply 233 can supply power to a memory device (e.g., ...) through the multiple charged capacitors. Figure 5 100) Supply assistance power ASSIST_POWER.

[0108] For example, in the event of a sudden power outage (SPO), auxiliary power supply 233 from... Figure 4 SPO detectors (e.g., Figure 4 When the auxiliary power supply 233 receives the detection signal DETECT_SIG, it can supply power to the memory device (e.g., Figure 5 100) Supply assistance power ASSIST_POWER.

[0109] In this embodiment, to cope with sudden power outages (SPO) and / or other predetermined conditions, the performance of the auxiliary power supply 233 can be monitored at preset time intervals. For example, the monitoring component 235 can monitor the auxiliary power supply 233 and output a discharge signal DISCHARGE_SIG to the auxiliary power supply 233 at preset time intervals.

[0110] When the monitoring component 235 outputs a discharge signal DISCHARGE_SIG to the auxiliary power supply 233 at preset time intervals, the auxiliary power supply 233 can pause the charging of the capacitor and then discharge the capacitor. Based on the level of capacitor discharge, the ability of the auxiliary power supply 233 to provide auxiliary power (ASSIST_POWER) can be assessed.

[0111] For example, if the capacitor takes a long time to discharge (e.g., longer than the predetermined time), it can be assessed that a larger amount of auxiliary power ASSIST_POWER can be supplied. When the performance of auxiliary power supply 233 (e.g., its ability to supply auxiliary power) is completed, the capacitor in auxiliary power supply 233 can be recharged.

[0112] In this embodiment, a sudden power outage (SPO) may occur when the capacitor in the auxiliary power supply 233 is discharging or charging. In this case, if the capacitor charging is delayed or not yet complete, the auxiliary power ASSIST_POWER may not be supplied to the memory device (e.g., Figure 5 (of 100).

[0113] Furthermore, when the power loss controller 230 is not in operation, the memory buffer (e.g., Figure 5 The host data HOST_DATA stored in (220) may not be output to the recovery area as dump data DUMP_DATA (e.g., Figure 5 (231).

[0114] Therefore, memory buffers (e.g., Figure 5 The host data HOST_DATA stored in memory buffer 220 can be programmed in Forced Cell Access Mode (FUA MODE). For example, this programming operation can be performed in such a way that the host data HOST_DATA stored in the memory buffer is programmed into the memory device (e.g., ...). Figure 5 After updating the mapping data (100), send it to the host (e.g., Figure 1 The 300) output completes the response.

[0115] However, when programming the host data HOST_DATA in FUA mode, it may be impossible to determine the recovery area (e.g., when power is turned on after an SPO). Figure 5 Has the dump data DUMP_DATA stored in (231) been dumped and stored in a memory device (e.g., Figure 5In the case of 100), for example, it may be impossible to determine whether the power was disconnected after the dump data DUMP_DATA stored in the recovery area had been dumped and stored in the memory device, or whether the power was disconnected if the dump data DUMP_DATA stored in the recovery area was not dumped to the memory device.

[0116] In this embodiment, in order to store the host data HOST_DATA stored in the memory buffer into the memory device via the power loss controller 230, the auxiliary power supply 233 should be charged. However, a problem may arise where another operation cannot be performed while the auxiliary power supply 233 is charging.

[0117] Therefore, according to one or more embodiments, a method can be provided to ensure data reliability without data loss even during charging delays of the auxiliary power supply 233.

[0118] Figure 7 An example of a process for performing a recovery operation based on dump data in the recovery area is shown.

[0119] Reference Figure 7 The power loss controller 230 may include a recovery area 231, a recovery controller 237, and a meta-area 239. Figure 7 The process corresponds to the case where a sudden power outage (SPO) occurs, and a sudden power outage (SPO) recovery operation (SPO RECOVERY) is performed based on the dump data DUMP_DATA output from recovery area 231.

[0120] exist Figure 7 In this context, we assume that the sixth dump data DD6 corresponds to the data from the host (e.g., Figure 1 The sixth host data (HOST_DATA6) output by the 300) and the seventh dump data (DD7) are the data corresponding to the slave host (e.g., Figure 1 The seventh host data (HOST_DATA7) output by the 300) is the data. In one embodiment, for the same SPO or different SPOs, different dump data can be output from the host at different times.

[0121] Moreover, in one embodiment, it can be assumed that from the host (e.g., Figure 1 A sudden power outage (SPO) occurred before the 300) received the seventh host data HOST_DATA7, and the memory buffer (e.g., Figure 5The sixth dump data DD6, corresponding to the sixth host data HOST_DATA6 stored in memory device 100, is dumped and stored in recovery area 231 due to a sudden power outage (SPO). Further, it is assumed that the sixth dump data DD6 is output from recovery area 231 and stored in memory device 100. Thereafter, it can be assumed that during the SPO recovery operation, the recovery operation is completed based on the sixth dump data DD6 output from memory device 100 and stored in recovery area 231.

[0122] Here, it is assumed that the dump frequency (AGE) corresponding to the sixth dump data DD6 is "6". Here, the dump frequency (AGE) can indicate the number of times data is dumped to recovery area 231. For example, the dump frequency can be a value that increments by "1" each time dump data DUMP_DATA is dumped to recovery area 231. In one embodiment, the dump frequency can be a value obtained by accumulating a count of the number of times dump data DUMP_DATA is dumped to recovery area 231, where the accumulated count corresponds to the dump count. The dump frequency can be sequentially incremented by "1" from a predetermined default value (e.g., "0"). Therefore, when the dump frequency (AGE) is "6", data is retrieved from the memory buffer (e.g., Figure 5 The total number of times 220 is dumped to recovery area 231 can be "6".

[0123] In this embodiment, programming operations can be performed on the seventh host data HOST_DATA7. For example, the seventh host data HOST_DATA7 may be generated from the host (e.g., ...) along with the programming request. Figure 1 The programming data output by (300) and the seventh host data HOST_DATA7 can be stored in a memory buffer (e.g., Figure 5 In 220), the seventh host data HOST_DATA7 stored in the memory buffer can be output and programmed into memory device 100.

[0124] However, a sudden power outage (SPO) may occur before the seventh host data HOST_DATA7 is programmed. When a sudden power outage (SPO) occurs at this time, the seventh host data HOST_DATA7 stored in the memory buffer can be dumped to the recovery area 231 of the power loss controller 230, and then stored in the memory device 100.

[0125] For example, after the seventh dump data DD7 corresponding to the seventh host data HOST_DATA7 has been stored in the recovery area 231, the seventh dump data DD7 stored in the recovery area 231 can be dumped into the memory device 100. Here, the dump frequency (AGE) corresponding to the seventh dump data DD7 can be "7". Because the dump frequency (AGE) is "7", the total number of times data is dumped from the memory buffer to the recovery area 231 can be "7".

[0126] However, when the auxiliary power supply of the power loss controller 230 (e.g., Figure 6 When a sudden power outage (SPO) occurs while the capacitor in 233 is discharging or charging, the seventh host data HOST_DATA7 stored in the memory buffer can be programmed in forced cell access mode (FUAMODE) without being dumped to recovery area 231.

[0127] In one embodiment, it is assumed that the auxiliary power supply (e.g., Figure 6 The capacitor in 233) is fully charged. Therefore, when a sudden power outage (SPO) occurs before the seventh host data HOST_DATA7 is programmed, the seventh host data HOST_DATA7 can be dumped to recovery area 231 and then stored in memory device 100. For example, when a sudden power outage (SPO) occurs before the seventh host data HOST_DATA7 is programmed, the seventh host data HOST_DATA7 stored in the memory buffer can be dumped to recovery area 231.

[0128] After the seventh host data HOST_DATA7 has been dumped to recovery area 231, the sixth dump data DD6 and the seventh dump data DD7 stored in recovery area 231 can be output and stored in memory device 100. The sixth dump data DD6 can be data dumped from the memory buffer before the seventh dump data DD7. Power can be disconnected when the sixth dump data DD6 and the seventh dump data DD7 are stored in memory device 100.

[0129] Subsequently, during the SPO recovery operation, the sixth dump data DD6 and the seventh dump data DD7 can be output from the memory device 100 and stored in the recovery area 231. When the sixth dump data DD6 and the seventh dump data DD7 are stored in the recovery area 231, the recovery controller 237 can perform the SPO recovery operation based on the sixth dump data DD6 and the seventh dump data DD7.

[0130] According to one or more embodiments, before performing an SPO recovery operation, the recovery controller 237 may receive information from the recovery region 231 indicating the dump frequency (AGE) corresponding to each item of dump data. The recovery controller 237 may perform the recovery operation by comparing the received dump frequencies (AGE) with each other. For example, before performing an SPO recovery operation, the recovery controller 237 may receive from the recovery region 231 the sixth dump frequency DD6_AGE "6" corresponding to the sixth dump data DD6 and the seventh dump frequency DD7_AGE "7" corresponding to the seventh dump data DD7.

[0131] Upon receiving information indicating the sixth dump frequency DD6_AGE and the seventh dump frequency DD7_AGE, the recovery controller 237 can perform a recovery operation based on the dump data corresponding to the maximum dump frequency (AGE). For example, as a result of comparing the sixth dump frequency DD6_AGE and the seventh dump frequency DD7_AGE with each other, the recovery controller 237 can perform a recovery operation based on the seventh dump data DD7 corresponding to the seventh dump frequency DD7_AGE, which is the maximum dump frequency.

[0132] In this embodiment, after performing a recovery operation based on the seventh dump data DD7, the recovery controller 237 can store the meta-age of the metadata META_DATA corresponding to the seventh dump data DD7 in the meta-region 239. Here, the metadata corresponding to the seventh dump data DD7 can be the seventh metadata, and may include mapping data, etc.

[0133] Subsequently, when another SPO occurs, a recovery operation can be performed based on the dump frequency (AGE) stored in recovery region 231 and the meta frequency AGE stored in meta region 239.

[0134] Figure 8 Shown in Figure 7 An embodiment of a situation where another sudden power outage occurs after the recovery operation corresponding to a sudden power outage has been completed. Figure 8 The diagram illustrates a situation where an additional SPO occurs after the recovery controller 237 has already performed a recovery operation based on the dump frequency of each item of the dump data stored in the recovery region 231. In this case, upon checking the slave host (e.g., Figure 1 While performing programming operations on the eighth host data HOST_DATA8 received by the 300), another SPO may occur. Therefore, Figure 8 Implementations may include situations where an additional SPO occurs after the recovery controller 237 has performed a recovery operation based on the seventh dump data DD7.

[0135] In an embodiment, during the charging of multiple capacitors, monitoring of the auxiliary power supply (e.g., during the charging of multiple capacitors) is performed at preset time intervals. Figure 6 A sudden power outage (SPO) may occur during or after the operation of (233) monitoring. For example, a sudden power outage (SPO) may occur while a capacitor in the auxiliary power supply is charging.

[0136] In this situation, the power loss controller 230 may not operate due to a delay in the auxiliary power supply's charging or because the charging process is not yet complete. For example, the eighth host data HOST_DATA8, which is not yet fully programmed and stored in the memory buffer, may not have been dumped to the recovery area 231. Therefore, the eighth host data HOST_DATA8 can be programmed in Forced Unit Access Mode (FUA MODE).

[0137] For example, the programming operation can be performed in such a way that after the eighth host data HOST_DATA8 stored in the memory buffer is programmed into the memory device and the mapping data is updated, a completion response is output to the host.

[0138] Subsequently, during the SPO recovery operation, the dump data output from the memory device can be output and stored in the recovery region 231. When the dump data is stored in the recovery region 231, the recovery controller 237 can receive information (from the recovery region 231) indicating the dump frequency (AGE) corresponding to each item of the dump data DUMP_DATA before performing the SPO recovery operation. Further, the recovery controller 237 can receive the meta frequency (AGE) corresponding to the metadata META_DATA from the meta region 239.

[0139] In an embodiment, the recovery controller 237 can perform a recovery operation by comparing the received dump frequency (AGE) and the meta frequency with each other. For example, the recovery controller 237 can perform a recovery operation based on the result of comparing the maximum value of the received dump frequency with the most recently stored meta frequency.

[0140] Reference Figure 8 The recovery controller 237 can receive from the recovery region 231 the sixth dump frequency DD6_AGE "6" corresponding to the sixth dump data DD6 and the seventh dump frequency DD7_AGE "7" corresponding to the seventh dump data DD7. Furthermore, the recovery controller 237 can receive the seventh meta-frequency MD7_AGE "7" corresponding to the seventh meta-frequency MD7. Of the sixth dump frequency DD6_AGE and the seventh dump frequency DD7_AGE, the larger value is the seventh dump frequency DD7_AGE, i.e., "7". Therefore, the values ​​corresponding to the seventh dump frequency DD7_AGE and the seventh meta-frequency MD7_AGE may be the same.

[0141] When the value corresponding to the seventh dump frequency DD7_AGE and the value corresponding to the seventh meta frequency MD7_AGE are both "7", the recovery controller 237 can determine that a recovery operation has been performed based on the dump data stored in the recovery area 231. Therefore, it can be determined that the recovery controller 237 has completed the recovery operation based on the seventh dump data DD7 stored in the recovery area 231. In this case, the recovery controller 237 can perform the recovery operation without considering the seventh dump data DD7. That is, when the maximum value of the dump frequency is compared with the value of the most recently stored meta frequency, and the two values ​​are the same, a recovery operation can be performed, and this operation can be performed without considering the dump data stored in the recovery area 231.

[0142] Because the recovery controller 237 performs the recovery operation by comparing the dump frequency with the original frequency, and because the dump data that has already been recovered will not be reprogrammed into the memory device, the eighth host data HOST_DATA8 in FUA mode (e.g., new data programmed into the memory device) may not be replaced by the seventh host data HOST_DATA7.

[0143] Figure 9 Shown in Figure 7 An embodiment of a sudden power outage occurring before the SPO recovery operation is complete. Figure 9 The diagram shows that when the recovery controller 237 executes the action corresponding to... Figure 7 During a sudden power outage (SPO) recovery operation, the dumped data transferred to the memory device is re-output and stored in the recovery area 231. However, in this case, the recovery operation is not completed, and another SPO occurs.

[0144] therefore, Figure 9 An embodiment may include the following situation: while the recovery controller 237 is performing a recovery operation based on the seventh dump data DD7 according to the result of comparing the sixth dump frequency DD6_AGE and the seventh dump frequency DD7_AGE with each other, another SPO occurs.

[0145] In this embodiment, while programming operations are being performed on the seventh host data HOST_DATA7, another SPO may occur. When another SPO occurs, the sixth dump data DD6 and the seventh dump data DD7 stored in recovery region 231 can be output and stored in a memory device.

[0146] Subsequently, when the sixth dump data DD6 and the seventh dump data DD7 are output from the memory device and stored in the recovery region 231, the recovery controller 237 can receive the sixth dump frequency DD6_AGE corresponding to the sixth dump data DD6 and the seventh dump frequency DD7_AGE corresponding to the seventh dump data DD7 from the recovery region 231, and can perform a recovery operation based on the result of comparing the sixth dump frequency DD6_AGE and the seventh dump frequency DD7_AGE. For example, when the seventh dump frequency DD7_AGE is greater than the sixth dump frequency DD6_AGE (7>6), the recovery controller 237 can perform a recovery operation based on the seventh dump data DD7 corresponding to the seventh dump frequency DD7_AGE.

[0147] However, in Figure 9 During the recovery process, a separate SPO may occur while the recovery controller 237 is performing a recovery operation. When a separate SPO occurs, the sixth dump data DD6 and the seventh dump data DD7 stored in the recovery region 231 can be output and stored in the memory device.

[0148] In this case, with Figure 7 Unlike other methods, because the recovery operation based on the seventh dump data DD7 has not yet been completed, the recovery controller 237 cannot store the metafrequency AGE of the metadata META_DATA corresponding to the seventh dump data DD7 in the meta-region 239. Therefore, the metafrequency most recently stored in the meta-region can be the sixth metafrequency MD6_AGE corresponding to the sixth metadata MD6.

[0149] Subsequently, during the SPO recovery operation, the dump data output from the memory device can be output again and stored in the recovery area 231. When the dump data is stored in the recovery area 231, the recovery controller 237 can (before performing the SPO recovery operation, from the recovery area 231) receive information indicating the dump frequency (AGE) corresponding to each item of the dump data DUMP_DATA. Further, the recovery controller 237 can receive information from the meta area 239 indicating the meta frequency (AGE) corresponding to the most recently stored metadata META_DATA.

[0150] In an embodiment, the recovery controller 237 can perform a recovery operation by comparing the received dump frequency (AGE) and the meta frequency with each other. For example, the recovery controller 237 can perform a recovery operation based on the result of comparing the maximum value of the received dump frequency with the value of the most recently stored meta frequency.

[0151] Reference Figure 9The recovery controller 237 can receive from the recovery region 231 the sixth dump frequency DD6_AGE "6" corresponding to the sixth dump data DD6 and the seventh dump frequency DD7_AGE "7" corresponding to the seventh dump data DD7. Furthermore, the recovery controller 237 can receive the sixth meta-frequency MD6_AGE "6" corresponding to the sixth meta-frequency MD6. Because the larger of the sixth dump frequency DD6_AGE and the seventh dump frequency DD7_AGE is the seventh dump frequency DD7_AGE (i.e., "7"), the value corresponding to the seventh dump frequency DD7_AGE and the value corresponding to the most recently stored sixth meta-frequency MD6_AGE can be different from each other.

[0152] When the value corresponding to the seventh dump frequency DD7_AGE and the value corresponding to the sixth dump frequency MD6_AGE are different from each other, the recovery controller 237 can determine that a recovery operation has not yet been performed based on the dump data stored in the recovery area 231.

[0153] Therefore, since the recovery operation based on the seventh dump data DD7 stored in recovery area 231 has not yet been performed, the recovery controller 237 can perform the recovery operation based on the seventh dump data DD7. For example, as a result of comparing the maximum value of the dump frequency with the value of the most recently stored meta frequency, when the two values ​​are different from each other, the recovery operation can be performed based on the dump data stored in recovery area 231.

[0154] Therefore, because the recovery controller 237 performs the recovery operation by comparing the dump frequency with the original frequency, it is possible to perform a programming operation on the memory device based on the dump data for which no recovery operation was performed. This prevents the loss of the seventh host data HOST_DATA7 corresponding to the seventh dump data DD7.

[0155] Figure 10 This is a flowchart illustrating an embodiment of a method of operating a memory controller, which may correspond, for example, to one or more embodiments of the memory controller described herein.

[0156] Reference Figure 10 In S1001, the memory controller can perform the operation of monitoring the auxiliary power supply. The auxiliary power supply may be included in or connected to the memory controller, and can supply auxiliary (or assist) power to the memory device in the event of a sudden power outage (SPO).

[0157] In an embodiment, to address sudden power outages (SPO) or other forms of power interruption, the performance of the auxiliary power supply can be monitored, for example, at preset time intervals. Performance can be monitored based, for instance, on the level of capacitor discharge in the auxiliary power supply.

[0158] In S1003, a sudden power outage (SPO) may occur. For example, an SPO may occur after the capacitor in the auxiliary power supply has finished charging, or an SPO may occur while the capacitor is discharging or charging.

[0159] In S1005, the memory controller can determine whether the capacitor charging operation in the auxiliary power supply has been completed. For example, the memory controller can determine whether a spontaneous emission (SPO) has occurred after the capacitor charging in the auxiliary power supply has been completed, or whether an SPO has occurred while multiple capacitors are discharging or charging.

[0160] The process can proceed to S1007 if the capacitor charging in the auxiliary power supply is not complete (e.g., in the case of "No"). The process can proceed to S1009 if the capacitor charging in the auxiliary power supply is complete (e.g., in the case of "Yes").

[0161] In S1007, the memory controller can program the data stored in the memory buffer to the memory device in Forced Cell Access Mode (FUA MODE). For example, when an SPO occurs while a capacitor in the auxiliary power supply is discharging or charging (e.g., while the capacitor in the auxiliary power supply is not yet fully charging), the auxiliary power supply cannot provide auxiliary power. In this case, the memory controller can program the data stored in the memory buffer in FUA mode. For example, the programming operation can be performed such that the data stored in the memory buffer is programmed to the memory device and the mapped data is updated, after which a completion response is output to the host.

[0162] In S1009, the memory controller can dump the data stored in the memory buffer to the recovery area. For example, when an SPO occurs after the capacitor charging in the auxiliary power supply has been completed, the auxiliary power supply can provide auxiliary power. In this case, the memory controller can use the auxiliary power to dump the data stored in the memory buffer to the recovery area, and can store the dumped data in the memory device.

[0163] In S1011, the memory controller can perform a recovery operation based on frequency information received from the recovery region and the metadata region. For example, when the maximum value of the dump frequency corresponding to the dump data stored in the recovery region is equal to the value of the metadata frequency corresponding to the most recently stored metadata, the recovery operation can be performed without considering the data stored in the recovery region.

[0164] However, when the maximum value of the dump frequency corresponding to the dump data stored in the recovery area differs from the value of the meta frequency corresponding to the most recently stored metadata, a recovery operation can be performed based on the dump data corresponding to the maximum value of the dump frequency. When the memory controller performs a recovery operation based on the dump data, the memory controller can store the dump frequency corresponding to the dump data in the meta area.

[0165] Figure 11 This is a flowchart illustrating an embodiment of an operation method of a memory controller, which may be, for example, one or more of the foregoing embodiments of a memory controller. (Refer to...) Figure 10 and Figure 11 ,exist Figure 11 The diagram shows the subdivision. Figure 10 The operation obtained from operation S1011.

[0166] In S1101, the memory controller can compare frequencies based on information received from the recovery region and the meta region. For example, the memory controller can receive dump frequencies corresponding to items of dump data stored in the recovery region and meta frequencies corresponding to metadata stored in the meta region, respectively. The memory controller can then compare the maximum value of the received dump frequencies with the value of the most recently stored meta frequency.

[0167] In S1103, the memory controller can determine whether the maximum value of the received dump frequency is equal to the most recently stored meta frequency. When it is determined that the maximum value is equal to the most recently stored meta frequency (e.g., in the case of "yes"), the process can proceed to operation S1105. When it is determined that the maximum value is different from the most recently stored meta frequency (e.g., in the case of "no"), the process can proceed to operation S1107.

[0168] In S1105, the memory controller can perform a recovery operation without considering the dump data stored in the recovery area. For example, when the maximum value of the dump frequency is equal to the most recently stored meta frequency (e.g., in the "Yes" case), the memory controller can determine that a recovery operation has been performed based on the dump data stored in the recovery area. Therefore, since the memory controller has already completed the recovery operation based on the dump data stored in the recovery area, the memory controller can perform the recovery operation without considering the dump data.

[0169] In S1107, the memory controller can perform a recovery operation based on the dump data stored in the recovery area. For example, when the maximum value of the dump frequency is not equal to the most recently stored primitive frequency, the memory controller can determine that a recovery operation has not yet been performed based on the dump data stored in the recovery area. Because no recovery operation has been performed, the memory controller can perform a recovery operation based on the dump data stored in the recovery area.

[0170] Figure 12 This is a diagram illustrating an embodiment of a memory controller, which may correspond, for example, to any of the embodiments of the memory controller described herein.

[0171] The memory controller 1000 is coupled to the host and the memory device. The memory controller 1000 can access the memory device in response to requests from the host. For example, the memory controller 1000 can be configured to control write operations, read operations, erase operations, and background operations of the memory device. The memory controller 1000 can serve as an interface between the memory device and the host. The memory controller 1000 can execute instructions for controlling the memory device (e.g., running firmware).

[0172] Reference Figure 12 The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction code (ECC) circuit 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, and a bus 1070. The bus 1070 may provide a channel between the components of the memory controller 1000.

[0173] The processor 1010 can control all operations of the memory controller 1000 and can perform various logical operations. The processor 1010 can communicate with an external host via the host interface 1040 and with the memory device via the memory interface 1060. Furthermore, the processor 1010 can communicate with the memory buffer 1020 via the buffer control circuit 1050. The processor 1010 can use the memory buffer 1020 as working memory, cache memory, or buffer memory to control the operation of the memory device.

[0174] In one embodiment, processor 1010 can perform the functions of a Flash Translation Layer (FTL). Processor 1010 can use the FTL to translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs). The FTL can receive LBAs and use a mapping table to translate LBAs into PBAs. Examples of address mapping methods performed by the FTL, depending on the mapping unit, can include various methods. Representative address mapping methods include page mapping methods, block mapping methods, and hybrid mapping methods.

[0175] The processor 1010 can randomize data received from the host. For example, the processor 1010 can randomize data received from the host using a randomization seed. The randomized data can be provided to a memory device as data to be stored and can be programmed into a memory cell array.

[0176] The processor 1010 may run software or firmware to perform randomization or derandomization operations. In this embodiment, the processor 1010 may run software or firmware to perform randomization and derandomization operations.

[0177] The memory buffer 1020 can be used as the working memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0178] ECC circuit 1030 can perform error correction. For example, ECC circuit 1030 can perform error correction code (ECC) encoding based on data to be written to the memory device through memory interface 1060. ECC-encoded data can be transmitted to the memory device through memory interface 1060. ECC circuit 1030 can perform ECC decoding based on data received from the memory device through memory interface 1060. In this example, ECC circuit 1030 may be included in memory interface 1060.

[0179] The host interface 1040 can communicate with an external host under the control of the processor 1010. The host interface 1040 can perform communication using at least one of a variety of communication methods. Examples include Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Reduced Load DIMM (LRDIMM) communication methods.

[0180] The buffer control circuit 1050 can control the memory buffer 1020 under the control of the processor 1010.

[0181] The memory interface 1060 can communicate with the memory device under the control of the processor 1010. The memory interface 1060 can transmit or receive commands, addresses, and data to or from the memory device via channels.

[0182] In an embodiment, the memory controller 1000 may not include the memory buffer 1020 and the buffer control circuit 1050.

[0183] In one embodiment, processor 1010 may use code to control the operation of memory controller 1000. Processor 1010 may load code from a non-volatile memory device (e.g., ROM) in memory controller 1000. In another embodiment, processor 1010 may load code from a memory device via memory interface 1060.

[0184] In an embodiment, the bus 1070 of the memory controller 1000 may include a control bus and a data bus. The data bus may be configured to transmit data within the memory controller 1000, and the control bus may be configured to transmit control information such as commands or addresses within the memory controller 1000. The data bus and the control bus may be separate from each other and may not interfere with or affect each other. The data bus may be connected to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0185] In an embodiment, when in a memory device (e.g., Figure 1 When a sudden power outage (SPO) occurs while the processor 1010 is performing a programming operation, the processor 1010 can control the operation after the SPO. For example, when an SPO is detected, data stored in memory buffer 1020 can be programmed into the memory device in Forced Cell Access Mode (FUA MODE), after which the power can be disconnected. In one embodiment, the data stored in memory buffer 1020 can be dumped to the recovery area in memory controller 1000, and then stored in the memory device, after which the power can be disconnected.

[0186] In one embodiment, the SPO may occur after charging of multiple capacitors in the auxiliary power supply of the memory controller 1000 has been completed. In another embodiment, the SPO may occur while the capacitors are discharging or charging.

[0187] The auxiliary power supply cannot provide additional power while the capacitor is not fully charged. Therefore, in this situation, the power supply can be disconnected after the processor 1010 can program the data stored in the memory buffer 1020 in FUA mode.

[0188] When the capacitor is fully charged, the auxiliary power supply can provide additional power. Therefore, in this situation, the processor 1010 can use the additional power to dump the data stored in the memory buffer 1020 to the recovery area, and can store the dumped data already transferred to the recovery area in the memory device.

[0189] Subsequently, when power is turned on and an SPO recovery operation is performed, the processor 1010 can perform the recovery operation based on the maximum value of the dump frequency corresponding to the dump data stored in the recovery area and the value of the meta frequency corresponding to the most recently stored metadata. The dump frequency can indicate the number of times data is dumped to the recovery area. The meta frequency can be a value corresponding to the dump frequency at which the recovery operation is performed.

[0190] For example, if the maximum value of the dump frequency corresponding to the dump data stored in the recovery area is not equal to the value of the metadata frequency corresponding to the most recently stored metadata, it can be determined that a recovery operation has not yet been performed. Therefore, the processor 1010 can perform a recovery operation based on the dump data stored in the recovery area.

[0191] When the maximum value of the dump frequency corresponding to the dump data stored in the recovery area is equal to the value of the metadata frequency corresponding to the most recently stored metadata, it can be determined that a recovery operation has been performed. Therefore, the processor 1010 can perform a recovery operation without considering (e.g., disregarding) the dump data stored in the recovery area.

[0192] Figure 13 This is a block diagram illustrating an embodiment of a memory card system, any of the embodiments of the storage device described herein can be applied to this memory card system.

[0193] Reference Figure 13 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300. The memory controller 2100 is coupled to and can access the memory device 2200. The memory controller 2100 can control read operations, write operations, erase operations, and / or background operations of the memory device 2200. The memory controller 2100 can serve as an interface between the memory device 2200 and a host. The memory controller 2100 can execute instructions for controlling the memory device 2200 (e.g., running firmware). The memory device 2200 can be configured with reference to... Figure 1 The memory device described is implemented in the same manner.

[0194] In an embodiment, the memory controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and / or ECC circuitry.

[0195] The memory controller 2100 can communicate with external devices (e.g., a host) via connector 2300 based on one or more communication protocols. Examples include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe) protocols. In embodiments, connector 2300 may be compatible with at least one of these communication protocols.

[0196] In embodiments, the memory device 2200 may be implemented as a non-volatile memory device. Examples include electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0197] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure the memory card. Examples include PC cards (Personal Computer Memory Card International Association: PCMCIA), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC or eMMC), SD cards (SD, mini SD, micro SD or SDHC), or universal flash memory (UFS).

[0198] In one embodiment, when a sudden power outage (SPO) occurs while the memory device 2200 is performing a programming operation, the memory controller 2100 can control the operations following the SPO. For example, upon detecting an SPO, data stored in a memory buffer can be programmed into the memory device 2200 in Forced Cell Access Mode (FUA MODE), after which power can be disconnected. In another embodiment, the data stored in the memory buffer can be dumped to a recovery area in the memory controller 2100, and then stored in the memory device 2200, after which power can be disconnected.

[0199] In one embodiment, the SPO may occur after charging of multiple capacitors in the auxiliary power supply of the memory controller 2100 has been completed. In another embodiment, the SPO may occur while the capacitors are discharging or charging.

[0200] The auxiliary power supply cannot provide additional power while the capacitor is not fully charged. In this situation, the power supply can be disconnected after the memory controller 2100 can program the data stored in the memory buffer in FUA mode.

[0201] When the capacitor is fully charged, the auxiliary power supply can provide supplementary power. In this case, the memory controller 2100 can use the supplementary power to dump the data stored in the memory buffer to the recovery area, and the dumped data to the recovery area can be stored in the memory device 2200.

[0202] Subsequently, when power is turned on and an SPO recovery operation is performed, the memory controller 2100 can perform the recovery operation based on the maximum value of the dump frequency corresponding to the dump data stored in the recovery area and the value of the meta frequency corresponding to the most recently stored metadata. The dump frequency can indicate the number of times data is dumped to the recovery area, and the meta frequency can be a value corresponding to the dump frequency at which the recovery operation is performed.

[0203] For example, if the maximum value of the dump frequency corresponding to the dump data stored in the recovery area is not equal to the value of the metadata frequency corresponding to the most recently stored metadata, it can be determined that a recovery operation has not yet been performed. Therefore, the memory controller 2100 can perform a recovery operation based on the dump data stored in the recovery area.

[0204] When the maximum value of the dump frequency corresponding to the dump data stored in the recovery area is equal to the value of the metadata frequency corresponding to the most recently stored metadata, it can be determined that a recovery operation has been performed. Therefore, the memory controller 2100 can perform a recovery operation without considering (e.g., disregarding) the dump data stored in the recovery area.

[0205] Figure 14 This is a block diagram illustrating an embodiment of a solid-state drive (SSD) system, and any of the storage devices described herein can be applied to this SSD system.

[0206] Reference Figure 14 The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals SIG with the host 3100 through a signal connector 3001 and can receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a cache memory 3240.

[0207] In this embodiment, the SSD controller 3210 can perform a reference... Figure 1 The memory controller described (e.g., Figure 1 The SSD controller 3210 can control flash memory 3221 to 322n in response to a signal SIG from host 3100. In embodiments, the signal SIG can be a signal compatible with the interface of host 3100 and SSD 3200. Examples of interfaces include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe) interfaces.

[0208] Auxiliary power supply 3230 can be connected to host 3100 via power connector 3002. Power PWR can be supplied from host 3100 to auxiliary power supply 3230, and auxiliary power supply 3230 can be charged, for example, based on power PWR. Auxiliary power supply 3230 can supply power to SSD 3200 when the power supply from host 3100 does not meet a predetermined level or pattern (e.g., unstable performance). In embodiments, auxiliary power supply 3230 can be in or external to SSD 3200 and connected to SSD 3200. For example, auxiliary power supply 3230 can be in the motherboard and can supply auxiliary power to SSD 3200.

[0209] Buffer memory 3240 serves as a buffer for SSD 3200. For example, buffer memory 3240 may temporarily store data from host 3100 or from flash memory 3221 to 322n, and / or may temporarily store metadata (e.g., mapping tables) of flash memory 3221 to 322n. Buffer memory 3240 may be volatile memory (e.g., DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM) or non-volatile memory (e.g., FRAM, RRAM, STT-MRAM, PRAM).

[0210] In an embodiment, when a sudden power outage (SPO) occurs while any of the flash memories 3221 to 322n is performing a programming operation, the SSD controller 3210 can control the operation after the SPO. For example, when an SPO is detected, data stored in the buffer memory 3240 can be programmed into one or more of the flash memories 3221 to 322n in Forced Cell Access Mode (FUA MODE). Then, the power can be disconnected. In one embodiment, the data stored in the buffer memory 3240 can be dumped to a recovery area in the SSD controller 3210, and then stored in the flash memories 3221 to 322n before the power is disconnected.

[0211] In one scenario, an SPO may occur after charging of one or more capacitors in the auxiliary power supply 3230 has been completed. In another scenario, an SPO may occur while one or more capacitors are discharging or charging.

[0212] The auxiliary power supply 3230 cannot provide auxiliary power while the capacitor is not fully charging. In this case, the power supply can be disconnected after the SSD controller 3210 has programmed the data stored in the buffer memory 3240 in FUA mode.

[0213] When one or more capacitors have finished charging, the auxiliary power supply 3230 can provide supplementary power. In this case, the SSD controller 3210 can use the supplementary power to dump data stored in the buffer memory 3240 to the recovery area, and can store the dumped data (to the recovery area) in at least one of the flash memories 3221 to 322n.

[0214] When power is restored and an SPO recovery operation is performed, the SSD controller 3210 can perform the recovery operation based on the maximum value of the dump frequency corresponding to the dump data stored in the recovery area and the value of the meta frequency corresponding to the most recently stored metadata. The dump frequency can indicate the number of times data has been dumped to the recovery area, and the meta frequency can be a value corresponding to the dump frequency at which the recovery operation is performed.

[0215] For example, if the maximum value of the dump frequency (corresponding to the dump data stored in the recovery area) is not equal to the value of the metadata frequency corresponding to the most recently stored metadata, it can be determined that a recovery operation has not yet been performed. Therefore, the SSD controller 3210 can perform a recovery operation based on the dump data stored in the recovery area.

[0216] When the maximum value of the dump frequency (corresponding to the dump data stored in the recovery area) is equal to the value of the metadata frequency corresponding to the most recently stored metadata, it can be determined that a recovery operation has been performed. Therefore, the SSD controller 3210 can perform a recovery operation without considering (e.g., disregarding) the dump data stored in the recovery area.

[0217] Figure 15 This is a block diagram illustrating an embodiment of a user system 4000, wherein a storage device according to any of the embodiments described herein can be applied to the user system 4000.

[0218] Reference Figure 15 User system 4000 may include application processor 4100, memory module 4200, network module 4300, storage module 4400, and user interface 4500. Application processor 4100 may run components, operating system (OS), and / or user programs within user system 4000. In embodiments, application processor 4100 may include controllers, interfaces, graphics engines, and / or other features to control components within user system 4000. In one embodiment, application processor 4100 may be configured as a system-on-a-chip (SoC).

[0219] The memory module 4200 can be used as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include one or more volatile RAMs (e.g., DRAM, SDRAM, DDRSDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM) or one or more non-volatile RAMs (e.g., PRAM, RRAM, MRAM, FRAM). In embodiments, the application processor 4100 and the memory module 4200 may be packaged, for example, in a stacked package (POP), and in this case, may be configured as a single semiconductor package.

[0220] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communication. Examples include Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi communication. In an embodiment, network module 4300 may be located within application processor 4100.

[0221] Storage module 4400 can store, for example, data received from application processor 4100. In one embodiment, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. In an embodiment, storage module 4400 can be implemented as a non-volatile semiconductor memory device. Examples include phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In an embodiment, storage module 4400 can include a removable storage medium (e.g., a removable drive), such as a memory card of user system 4000 or an external drive.

[0222] In an embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may, for example, be referenced. Figure 2 and Figure 3 The memory device described operates in the same manner. The memory module 4400 can, for example, operate in the same manner as... Figure 1 It operates in the same way as the storage device 50.

[0223] User interface 4500 may include one or more interfaces that input data or instructions to application processor 4100 and / or output data to external devices. In embodiments, user interface 4500 may include user input interfaces such as: keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may further include user output interfaces such as: liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0224] In this embodiment, when a sudden power outage (SPO) occurs while the storage module 4400 is performing a programming operation, the application processor 4100 can control the operations following the SPO. For example, upon detecting an SPO, data stored in the memory module 4200 can be programmed into the storage module 4400 in Forced Cell Access Mode (FUA MODE), after which the power can be disconnected. In this embodiment, the data stored in the memory module 4200 can be dumped to a recovery area in the application processor 4100 and then stored in the storage module 4400, after which the power can be disconnected.

[0225] In one scenario, an SPO may occur after charging of one or more capacitors in the auxiliary power supply of the application processor 4100 has been completed. In another scenario, an SPO may occur while one or more capacitors are discharging or charging.

[0226] The auxiliary power supply cannot provide additional power when one or more capacitors are not fully charged. In this situation, the power supply can be disconnected after the application processor 4100 has programmed the data stored in the memory module 4200 in FUA mode.

[0227] However, when one or more capacitors have finished charging, an auxiliary power supply can provide supplementary power. Therefore, in this situation, the application processor 4100 can use the supplementary power to dump data stored in the memory module 4200 to the recovery area, and the dumped data (to the recovery area) can be stored in the memory module 4400.

[0228] Subsequently, when power is turned on and an SPO recovery operation is performed, the application processor 4100 can perform the recovery operation based on the maximum value of the dump frequency corresponding to the dump data stored in the recovery area and the value of the meta frequency corresponding to the most recently stored metadata. The dump frequency can indicate the number of times data is dumped to the recovery area, and the meta frequency can be a value corresponding to the dump frequency at which the recovery operation is performed.

[0229] For example, if the maximum value of the dump frequency (corresponding to the dump data stored in the recovery area) is not equal to the value of the metadata frequency corresponding to the most recently stored metadata, it can be determined that a recovery operation has not yet been performed. Therefore, the application processor 4100 can perform a recovery operation based on the dump data stored in the recovery area.

[0230] When the maximum value of the dump frequency (corresponding to the dump data stored in the recovery area) is equal to the value of the metadata frequency corresponding to the most recently stored metadata, it can be determined that a recovery operation has been performed. Therefore, the application processor 4100 can perform a recovery operation without considering (e.g., disregarding) the dump data stored in the recovery area.

[0231] According to one or more embodiments, when a sudden power outage occurs and the index of the recovery region matches the index of the meta region, a recovery operation is performed without referencing the data in the recovery region. The index may include, for example, a frequency corresponding to the dumps as described above. When their indexes do not match each other, a recovery operation is performed by referencing the data in the recovery region, thereby preventing data reliability degradation due to a sudden power outage.

[0232] According to one embodiment, an apparatus includes a storage region configured to store instructions and a controller configured to execute instructions. The storage region may be contained in a non-transitory computer-readable medium (e.g., memory module 420, or another instruction storage region within a volatile or non-volatile memory region), and the controller may correspond to any of the embodiments of the controller described herein.

[0233] When the command is executed, the controller can store dump data and information indicating the dump frequency in a recovery area based on the detection of a sudden power outage. The dump data may correspond to data stored in a memory buffer, and the recovery area may be within the controller or in a device coupled to the controller (e.g., power loss controller 230 or other controllers). The controller can perform a recovery operation based on the information indicating the dump frequency. The dump frequency may correspond to any of the embodiments described herein; for example, it may indicate the number of times different items of host data corresponding to the dump data have been dumped with respect to the same SPO or different SPOs.

[0234] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or those other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0235] When implemented at least partially in software, controllers, processors, devices, managers, components, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or those other than those described herein. Because the algorithms underlying the methods (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can transform a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0236] While this disclosure has been shown and described with reference to certain exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0237] In the above embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps need not be performed in the described order, and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to aid in understanding this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0238] Furthermore, exemplary embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, those terms are merely for interpreting embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations can exist within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein. Embodiments can be combined to form other embodiments.

Claims

1. A memory controller comprising: a sudden power off (SPO) detector that outputs a detection signal upon detecting a sudden power off; a memory buffer that stores host data output from a host; and a power loss controller that receives dump data corresponding to the host data from the memory buffer based on the detection signal, stores the dump data and a dump frequency corresponding to the dump data, and outputs the dump data and the dump frequency to a memory device, wherein the dump frequency indicates a number of times that different items of the host data have been dumped from the memory buffer to the power loss controller, and wherein the power loss controller receives the dump data and the dump frequency from the memory device during a recovery operation corresponding to the sudden power off, and controls the recovery operation based on the dump frequency and a meta frequency, wherein the meta frequency indicates a dump frequency of the dump frequencies that corresponds to dump data for which a recovery operation was most recently performed. 2.The memory controller of claim 1, wherein: the power loss controller includes an auxiliary power supply that supplies aid power upon occurrence of the sudden power off; and the auxiliary power supply includes one or more capacitors. 3.The memory controller of claim 2, wherein: when the sudden power off occurs while charging of the one or more capacitors is delayed or has not been completed, the memory buffer outputs the host data to be programmed into the memory device. 4.The memory controller of claim 2, wherein: when the sudden power off occurs while charging of the one or more capacitors is completed, the memory buffer dumps the host data to the power loss controller. 5.The memory controller of claim 1, wherein: the power loss controller includes a recovery controller that controls the recovery operation, and during the recovery operation, the power loss controller receives two or more items of dump data stored in the memory device and dump frequencies respectively corresponding to the two or more items of dump data. 6.The memory controller of claim 5, wherein the recovery controller controls the recovery operation based on dump data of a maximum dump frequency of the dump frequencies respectively corresponding to the two or more items of dump data received from the memory device and stored in the power loss controller. 7.The memory controller of claim 6, wherein: when the recovery operation is completed based on dump data corresponding to the maximum dump frequency of the dump frequencies, the recovery controller stores the maximum dump frequency as the meta frequency in a meta region.

8. The memory controller of claim 7, wherein, after the meta frequency has been stored in the meta region and an additional sudden power off occurs, the power loss controller, during the recovery operation: receiving the two or more items of dump data stored in the memory device and a dump frequency corresponding to the two or more items of dump data, respectively; and controlling the recovery operation based on the dump frequency and the meta frequency.

9. The memory controller of claim 8, wherein the recovery controller controls the recovery operation based on dump data corresponding to the maximum one of the dump frequencies.

10. The memory controller of claim 8, wherein: when the maximum dump frequency is equal to the meta frequency, the recovery controller performs the recovery operation without regard to the dump data.

11. The memory controller of claim 8, wherein: when the maximum dump frequency is different from the meta frequency, the recovery controller performs the recovery operation based on the dump data.

12. An apparatus comprising: a memory device; and a memory controller: based on detection of a sudden power loss, storing dump data and information indicating a dump frequency corresponding to data temporarily stored in a memory buffer of the memory controller in a power loss controller of the memory controller; outputting the dump data and information indicating the dump frequency to the memory device; and during a recovery operation corresponding to the sudden power loss, receiving the dump data and information indicating the dump frequency from the memory device and performing a recovery operation based on the information indicating the dump frequency stored in the memory device and a meta frequency, wherein the information indicating the dump frequency indicates a number of different items of host data corresponding to the dump data that have been dumped from the memory buffer to the power loss controller, and wherein the meta frequency indicates a dump frequency of the dump frequencies corresponding to dump data for which a recovery operation was most recently performed.

13. A method of operating a memory controller, the method comprising: storing host data from a host in a memory buffer; when a sudden power loss is detected, storing dump data and a dump frequency corresponding to the dump data in a power loss controller of the memory controller, the dump data corresponding to the host data stored in the memory buffer; outputting the dump data and the dump frequency to a memory device; during a recovery operation corresponding to the sudden power loss, receiving the dump data and the dump frequency from the memory device and performing a recovery operation corresponding to the sudden power loss based on the dump frequency and a meta frequency, wherein the dump frequency indicates a number of different items of the host data that have been dumped from the memory buffer to the power loss controller, wherein the meta frequency indicates a dump frequency of the dump frequencies corresponding to dump data for which a recovery operation was most recently performed.

14. The method of claim 13, wherein: when the sudden power loss occurs while charging of one or more capacitors in an auxiliary power supply is delayed or has not been completed, the host data to be programmed into the memory device is output from the memory buffer. ​ ​ 15. The method of claim 14, wherein: the sudden power down occurs when charging of the one or more capacitors is complete, the host data is dumped to the power loss controller.

16. The method of claim 13, wherein: performing the recovery operation includes receiving the dump data and the dump frequency from the memory device, and when two or more items of the dump data and dump frequencies respectively corresponding to the two or more items of the dump data are received from the memory device, the recovery operation is performed based on dump data corresponding to a maximum dump frequency of the dump frequencies.

17. The method of claim 16, wherein performing the recovery operation includes: when the recovery operation is completed based on dump data corresponding to the maximum dump frequency, the maximum dump frequency is stored as the meta frequency in a meta region.

18. The method of claim 17, wherein performing the recovery operation includes: when an additional sudden power down occurs after the meta frequency has been stored in the meta region, the recovery operation is performed based on the dump frequency received from the memory device and the meta frequency received from the meta region.

19. The method of claim 18, wherein performing the recovery operation includes: when the maximum dump frequency is equal to the meta frequency, the recovery operation is performed without consideration of the dump data.

20. The method of claim 19, wherein performing the recovery operation includes: when the maximum dump frequency is different from the meta frequency, the recovery operation is performed based on the dump data.

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