Hybrid physical memory protection method and system

Abstract

The present invention provides a hybrid physical memory protection method and system, comprising: when a physical memory protection method based on a segment protection model performs physical address protection, a flag bit in a configuration register in the segment protection mode is modified to convert to a table protection mode, and in the table protection mode, a table protection mechanism is used to check permissions; when the flag bit is cleared, the segment protection model is still used to check permissions; the table protection mechanism uses multi-level table entries to perform permission control and protection on access to physical memory; the permission bits in each level of table entries include readable R, writable W and executable X; the segment protection model is a model that divides the physical memory into segments for access permission control and protection; the table protection model is a model that uses a table to perform access permission control and protection on the physical memory.

Description

Technical Field

[0001] The present invention relates to the field of application security, and more specifically, to a hybrid physical memory protection method and system, and more specifically, to a hybrid physical memory protection isolation method and system that can provide a dynamic use of segment protection models and table protection models for RISC-V architecture to implement trusted execution environments, trusted virtual machines and other capabilities. Background Art

[0002] RISC-V: is an open source instruction set architecture (ISA) based on the principles of the Reduced Instruction Set (RISC), which can be simply explained as a kind of "open source hardware" corresponding to the open source software movement. The project started at the University of California, Berkeley in 2010, but many contributors are volunteers and industry workers outside the university.

[0003] PMP (Physical Memory Protection): PMP is a memory isolation mechanism provided by RISC-V, which consists of 8 configuration registers (64 bits, 16 under 32 bits) and 64 address registers. Its function is to divide the memory into different areas. Only processes with permissions to the area can access the corresponding area. The check of this mechanism is completed by hardware, so the performance is good. The disadvantage is that the number of continuous physical memory areas that can be protected is limited by the number of PMP registers (64).

[0004] GPT (Granule Protection Tables) technology: GPT is a new mechanism provided by ARMv9 after the introduction of two additional security states (root, realm), which is used to provide a new method of controlling memory access for these additional security states. GPT defines the physical memory range that each security state can access. When a program attempts to access memory beyond the limit allowed by its security state, a granular protection check triggers an exception.

[0005] Security Monitor: Security Monitor is a trusted privileged software running in Machine Mode (RISC-V), usually a component of TCB (Trusted Computing Base). In scenarios such as confidential computing, trusted execution environment, and confidential virtual machine, Monitor is responsible for managing the declaration cycle of the isolated environment, memory isolation (such as using RISC-V's PMP), local verification, remote verification, defense against side channel attacks, and other functions. It is the part that needs to be managed by the software solution in this patent.

[0006] Patent document CN111651778A (application number: 202010456182.9) discloses a physical memory isolation method based on the RISC-V instruction architecture. It is a physical memory isolation technology spMP that can be configured in Supervisor mode on the basis of the existing Machine mode configurable physical memory isolation technology PMP of the RISC-V instruction architecture; the physical memory isolation technology spMP relies on several groups of spMP registers that can only be read and written by Machine mode programs and Supervisor mode programs. Summary of the invention

[0007] In view of the defects in the prior art, an object of the present invention is to provide a hybrid physical memory protection method and system.

[0008] A hybrid physical memory protection method provided by the present invention includes:

[0009] When the physical memory protection method based on the segment protection model performs physical address protection, a flag bit in the configuration register in the segment protection mode is modified to convert to the table protection mode. In the table protection mode, the table protection mechanism is used to check permissions; when the flag bit is cleared, the segment protection model is still used to check permissions;

[0010] The table protection mechanism uses multi-level table entries to control and protect the access to physical memory; the permission bits in each level of table entries include readable R, writable W, and executable X;

[0011] The segment protection model is a model that divides physical memory into segments for access control and protection;

[0012] The table protection model is a model that controls and protects access rights of physical memory using tables.

[0013] Preferably, the multi-level table entry includes a root table entry and a leaf table entry or a root table entry, an intermediate table entry and a leaf table entry;

[0014] The multi-level table entry includes the base address and physical address range of the protection area; the physical address range includes the address register and the configuration register;

[0015] Using an additional address register to specify a base address of a root table entry; the address register includes a Mode field and a PPN field;

[0016] The Mode field in the address register indicates the protection mode;

[0017] The PPN field in the address register indicates the base address of the previous protection layer.

[0018] Preferably, it includes:

[0019] Step S1: Get the first matching segment protection mode entry for a given physical memory address;

[0020] Step S2: judging a flag bit of the configuration register in the segment protection mode, when it is 0, the current segment protection mode entry and the original entry have the same function; otherwise, the current entry is in the table protection mode;

[0021] Step S3: Obtain the base address of the root table entry at the specified location in table protection mode;

[0022] Step S4: obtaining a relative position based on a difference between the target physical address and the base address of the current protection area;

[0023] Step S5: Find the target table entry by indexing in the multi-level table according to the relative position, so as to implement the permission check according to the information contained in the table entry.

[0024] Preferably, in the root table entry or the intermediate table entry, the R, W, and X bits respectively indicate whether it is readable, writable, and executable; when R, W, and X are all zero, the root table entry points to a pointer to the next level of protection table; otherwise, the R, W, and X bits together constitute the final permission for memory access.

[0025] Preferably, in a leaf table entry, the leaf table entry records the permissions of the physical page, and the permissions of each physical page need to correspond to at least R, W, and X bits; the R bit indicates whether the current page is readable; the W bit indicates whether the current page is writable; the X bit indicates whether the current page is executable; each page table entry records the permissions of multiple physical pages.

[0026] Preferably, a software trusted base is used to manage the multi-level table structure.

[0027] A hybrid physical memory protection system provided according to the present invention includes:

[0028] When the physical memory protection method based on the segment protection model performs physical address protection, a flag bit in the configuration register in the segment protection mode is modified to convert to the table protection mode. In the table protection mode, the table protection mechanism is used to check permissions; when the flag bit is cleared, the segment protection model is still used to check permissions;

[0029] The table protection mechanism uses multi-level table entries to control and protect the access to physical memory; the permission bits in each level of table entries include readable R, writable W, and executable X;

[0030] The segment protection model is a model that divides physical memory into segments for access control and protection;

[0031] The table protection model is a model that controls and protects access rights of physical memory using tables.

[0032] Preferably, the multi-level table entry includes a root table entry and a leaf table entry or a root table entry, an intermediate table entry and a leaf table entry;

[0033] The multi-level table entry includes the base address and physical address range of the protection area; the physical address range includes the address register and the configuration register;

[0034] Using an additional address register to specify a base address of a root table entry; the address register includes a Mode field and a PPN field;

[0035] The Mode field in the address register indicates the protection mode;

[0036] The PPN field in the address register indicates the base address of the previous protection layer.

[0037] Preferably, it includes:

[0038] Module M1: Get the first matching segment protection mode entry for a given physical memory address;

[0039] Module M2: Determine a flag bit of the configuration register in the segment protection mode. When it is 0, the current segment protection mode entry has the same function as the original entry; otherwise, the current entry is in the table protection mode.

[0040] Module M3: Get the base address of the root table entry at the specified location in table protection mode;

[0041] Module M4: Obtaining a relative position based on the difference between the target physical address and the base address of the current protection area;

[0042] Module M5: Find the target table entry by indexing in the multi-level table according to the relative position, so as to implement permission check according to the information contained in the table entry.

[0043] Preferably, in the root table entry or the intermediate table entry, the R, W, and X bits respectively indicate whether it is readable, writable, and executable; when R, W, and X are all zero, the root table entry points to a pointer to the next layer of protection table; otherwise, the R, W, and X bits together constitute the final permission for memory access;

[0044] In the leaf table entry, the leaf table entry records the permissions of the physical page. The permissions of each physical page need to correspond to at least R, W, and X bits; the R bit indicates whether the current page is readable; the W bit indicates whether the current page is writable; and the X bit indicates whether the current page is executable. Each page table entry records the permissions of multiple physical pages.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] 1. Compared with the protection mechanism of the existing physical memory segment protection model, the present invention can select metadata cost as needed. In a platform that implements table protection mode extension, if the system does not use table extension, no additional metadata cost is required.

[0047] 2. Compared with other existing physical memory segment protection mechanisms, the present invention is more flexible. We use radix-tree to record physical page permissions, making the management of permissions more flexible. We can even use multiple radix-trees and switch them to support more complex scenarios.

[0048] 3. The invention is based on the existing physical memory segment protection model technology and is compatible with the existing design. The extension of the protection table mechanism provides fine-grained physical memory protection for the trusted virtual machine, but does not introduce a new protection mechanism layer. Instead, it directly uses the original technology for protection.

[0049] 4. The design of the present invention has good performance. When there are many available table entries, the newly added protection table extension only needs to use two-level tables to protect the physical memory, which can improve indexing performance. At the same time, multiple tables can be used to protect more physical pages. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0051] Figure 1 The figure is an overall flow chart of an embodiment of the present invention.

[0052] Figure 2 FIG. 4 is an example diagram of a PMP configuration register in an embodiment.

[0053] Figure 3 Schematic representation of two-level PMP in the embodiment.

[0054] Figure 4 FIG. 4 is a schematic diagram of the formats of the root PMP table entry and the intermediate PMP table entry in the embodiment.

[0055] Figure 5 FIG. 1 is a schematic diagram of the format of a leaf PMP table entry in an embodiment. DETAILED DESCRIPTION

[0056] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0057] The present invention provides a hybrid physical memory protection method and system that combines a segment protection model and a table protection model. Physical memory protection is an important security capability of various current architectures such as Trusted Execution Environment (Trusted Execution Environment) and Confidential Virtual Machine (Confidential Virtual Machine). Existing methods usually select one of the segment protection model or the table protection model, which has performance or scalability issues. The present invention proposes a hybrid physical memory protection method (hardware extension) of segment protection and table protection, which allows trusted system software to dynamically use the two models on demand to protect physical memory, thereby achieving both fine-grained memory protection and high performance requirements.

[0058] Example 1

[0059] A hybrid physical memory protection method provided by the present invention includes:

[0060] When the physical memory protection method based on the segment protection model performs physical address protection, a flag bit in the configuration register in the segment protection mode is modified to convert to the table protection mode. In the table protection mode, the table protection mechanism is used to check permissions; when the flag bit is cleared, the segment protection model is still used to check permissions;

[0061] The table protection mechanism uses multi-level table entries to control and protect the access to physical memory; the permission bits in each level of table entries include readable R, writable W, and executable X;

[0062] The segment protection model is a model that divides physical memory into segments for access control and protection. It is usually protected by multiple entries, each of which usually includes an address register and a configuration register. The address register contains the base address and physical address range of the protection area corresponding to the entry, and the configuration register contains information such as access rights.

[0063] The table protection model is a model that controls and protects access rights of physical memory in a table. It is usually protected by one or more multi-level tables, and each table entry is for a section of physical memory (such as a 4KB or 2MB physical page) and their permission information.

[0064] Specifically, the multi-level table entry includes a root table entry and a leaf table entry or a root table entry, an intermediate table entry and a leaf table entry;

[0065] The multi-level table entry includes the base address and physical address range of the protection area; the physical address range includes the address register and the configuration register;

[0066] Using an additional address register to specify a base address of a root table entry; the address register includes a Mode field and a PPN field;

[0067] The Mode field in the address register indicates the protection mode;

[0068] The PPN field in the address register is the Physical Page Number, which indicates the base address of the previous protection layer.

[0069] Specifically, it includes:

[0070] Step S1: Get the first matching segment protection mode entry for a given physical memory address;

[0071] Since the segment protection model usually has multiple entries to protect different physical memory segments, the physical memory segments corresponding to these entries are allowed to overlap. Therefore, when matching, it is necessary to consider how to select the entry when multiple entries can be matched at the same time. Here, the first matching entry (according to the entry number from small to large) is used as the final entry for permission checking.

[0072] Step S2: judging a flag bit of the configuration register in the segment protection mode, when it is 0, the current segment protection mode entry and the original entry have the same function; otherwise, the current entry is in the table protection mode;

[0073] Step S3: Obtain the base address of the root table entry at the specified location in table protection mode;

[0074] Step S4: obtaining a relative position based on a difference between the target physical address and the base address of the current protection area;

[0075] Step S5: Find the target table entry by indexing in the multi-level table according to the relative position, so as to implement the permission check according to the information contained in the table entry.

[0076] Specifically, in the root table entry or the intermediate table entry, the R, W, and X bits respectively indicate whether it is readable, writable, and executable; when R, W, and X are all zero, the root table entry points to the pointer of the next layer of protection table; otherwise, the R, W, and X bits together constitute the final permission for memory access.

[0077] Specifically, in the leaf table entry, the leaf table entry records the permissions of the physical page, and the permissions of each physical page need to correspond to at least R, W, and X bits; the R bit indicates whether the current page is readable; the W bit indicates whether the current page is writable; the X bit indicates whether the current page is executable; each page table entry records the permissions of multiple physical pages.

[0078] Specifically, a software trusted base is used to manage the multi-level table structure. The software trusted base usually refers to the partially trusted code of the software in the entire computer, which is usually the software layer with the highest permission level in the system, such as the code in the Machine mode under the RISC-V architecture.

[0079] A hybrid physical memory protection system provided according to the present invention includes:

[0080] When the physical memory protection method based on the segment protection model performs physical address protection, a flag bit in the configuration register in the segment protection mode is modified to convert to the table protection mode. In the table protection mode, the table protection mechanism is used to check permissions; when the flag bit is cleared, the segment protection model is still used to check permissions;

[0081] The table protection mechanism uses multi-level table entries to control and protect the access to physical memory; the permission bits in each level of table entries include readable R, writable W, and executable X;

[0082] The segment protection model is a model that divides physical memory into segments for access control and protection. It is usually protected by multiple entries, each of which usually includes an address register and a configuration register. The address register contains the base address and physical address range of the protection area corresponding to the entry, and the configuration register contains information such as access rights.

[0083] The table protection model is a model that controls and protects access rights of physical memory in a table. It is usually protected by one or more multi-level tables, and each table entry is for a section of physical memory (such as a 4KB or 2MB physical page) and their permission information.

[0084] Specifically, the multi-level table entry includes a root table entry and a leaf table entry or a root table entry, an intermediate table entry and a leaf table entry;

[0085] The multi-level table entry includes the base address and physical address range of the protection area; the physical address range includes the address register and the configuration register;

[0086] Using an additional address register to specify a base address of a root table entry; the address register includes a Mode field and a PPN field;

[0087] The Mode field in the address register indicates the protection mode;

[0088] The PPN field in the address register is the Physical Page Number, which indicates the base address of the previous protection layer.

[0089] Specifically, it includes:

[0090] Module M1: Get the first matching segment protection mode entry for a given physical memory address;

[0091] Since the segment protection model usually has multiple entries to protect different physical memory segments, the physical memory segments corresponding to these entries are allowed to overlap. Therefore, when matching, it is necessary to consider how to select the entry when multiple entries can be matched at the same time. Here, the first matching entry (according to the entry number from small to large) is used as the final entry for permission checking.

[0092] Module M2: Determine a flag bit of the configuration register in the segment protection mode. When it is 0, the current segment protection mode entry has the same function as the original entry; otherwise, the current entry is in the table protection mode.

[0093] Module M3: Get the base address of the root table entry at the specified location in table protection mode;

[0094] Module M4: Obtaining a relative position based on the difference between the target physical address and the base address of the current protection area;

[0095] Module M5: Find the target table entry by indexing in the multi-level table according to the relative position, so as to implement permission check according to the information contained in the table entry.

[0096] Specifically, in the root table entry or the intermediate table entry, the R, W, and X bits respectively indicate whether it is readable, writable, and executable; when R, W, and X are all zero, the root table entry points to the pointer of the next layer of protection table; otherwise, the R, W, and X bits together constitute the final permission for memory access.

[0097] Specifically, in the leaf table entry, the leaf table entry records the permissions of the physical page, and the permissions of each physical page need to correspond to at least R, W, and X bits; the R bit indicates whether the current page is readable; the W bit indicates whether the current page is writable; the X bit indicates whether the current page is executable; each page table entry records the permissions of multiple physical pages.

[0098] Specifically, a software trusted base is used to manage the multi-level table structure. The software trusted base usually refers to the partially trusted code of the software in the entire computer, which is usually the software layer with the highest permission level in the system, such as the code in the Machine mode under the RISC-V architecture.

[0099] Example 2

[0100] Embodiment 2 is a preferred embodiment of Embodiment 1

[0101] According to the present invention, a hybrid physical memory protection method and system combining a physical memory segment protection model and a table protection model are provided. The present invention proposes a hybrid protection model combining a segment protection model and a table protection model, which is different from the traditional physical memory segment protection model. The trusted system software can dynamically use the two models on demand to protect the physical memory. When using the physical memory protection method based on the segment model to protect the physical address, a flag bit in the configuration register in the segment protection mode can be modified to convert it into a table protection mode, and then the table protection mechanism will be used to check the permissions. The table protection mechanism includes a multi-level table (supporting two or more levels), and the permission bits in the table entry include at least R (readable), W (writable), and X (executable). At the same time, if the flag bit is not set, the entry will still maintain the function of the original entry. The trusted system software (such as a security monitor) dynamically uses two models to protect the complete operation of the physical memory, including the following steps:

[0102] Step 1: For a given (CPU-initiated) physical memory address, find the first matching segment protection mode entry; the matching strategy will still use the same strategy as before, and the introduced table extension will not change the priority and matching logic.

[0103] Step 2: Determine a flag bit of the configuration register in the segment protection mode. If it is 0, the segment protection mode entry has the same effect as the original entry. Otherwise, the entry is in the table protection mode, and the corresponding permissions will be checked according to the table protection mechanism.

[0104] Step 3: In table protection mode, the permission bits in the original configuration register will be ignored. In table protection mode, a multi-level table (divided into root table, intermediate table and leaf table) is used. First, a specified location (usually a specific register) will be specified to read the base address of the root table;

[0105] Step 4: Obtain the relative position by calculating the difference between the target physical address and the base address of the current protection area. When the current table is a secondary table, the relative position must contain at least the following four parts: OFF[1], OFF[0], Page index, and Page offset;

[0106] Step 5: Use OFF[1] to index the root table to obtain the corresponding root table entry. When the permission bits (R, W, X bits) in the table entry are all zero, the root table entry is a pointer to the next level of protection table; otherwise, these permission bits together constitute the final permission for memory access;

[0107] Step 6: If the root table entry points to the next level protection table, use OFF[0] to index the leaf table to obtain the corresponding leaf table entry. The leaf table entry will identify one (or more) permissions for the corresponding physical page.

[0108] Step 7: Use the Page index to index the leaf table entry to obtain the corresponding permissions;

[0109] Step 8: Check the R, W, and X permission bits. The meaning is the same as that in the root table entry. If the permission check fails, the corresponding operation cannot be performed. If the check passes, the step is completed.

[0110] Specifically, a new bit needs to be introduced in the original configuration register to indicate whether the table entry is in table protection mode. When this bit is cleared, the entry has the same effect as the existing entry. Otherwise, in table protection mode, the corresponding permissions will be checked according to the table protection mechanism.

[0111] Specifically, a multi-level table is used in table protection mode, which has a base address and a physical address range, which is represented by the address register and the configuration register. The table structure supports multiple levels: the first-level table is called the root table, the middle-level table is called the intermediate table, and the last-level table is called the leaf table.

[0112] Specifically, an additional address register is needed to specify the base address of the root table. The address register contains Mode and PPN.

[0113] Specifically, the Mode field in the base address register of the record root table is used to indicate which protection mode is enabled. Currently, 0 is used to indicate the enablement of two-level table protection. New modes can be introduced to support more physical memory ranges. The physical address range is represented by the address register and the corresponding configuration register.

[0114] Specifically, in the root entry, the R, W, and X bits indicate whether it is readable, writable, and executable, respectively. When R, W, and X are all zero, the root entry is a pointer to the next level of protection table (i.e., leaf table), similar to the "large page" in the paging-based virtual memory; otherwise, the R, W, and X bits together constitute the final permission for memory access.

[0115] Specifically, the leaf table entry records the permissions of the 4KiB physical page. The permissions of each physical page need to correspond to at least three bits (R, W, X). The R bit indicates whether the page is readable, the W bit indicates whether the page is writable, and the X bit indicates whether the page is executable. Each leaf table entry can record the permissions of multiple physical pages.

[0116] Specifically, the offset processing of the physical address is different from that in normal situations. In order to index permissions, the relative position is obtained by calculating the difference between the target physical address and the base address of the current protection area. In the secondary table, the relative position should contain at least four parts, OFF[1], OFF[0], Page index and Page offset, where OFF[1] is used to index the root table. If R, W, and X in the root table entry are all 0, then the root table entry points to the leaf table. Then use OFF[0] to index the leaf table to find the corresponding entry, and then use the Page index to index the permissions in the leaf table entry.

[0117] Specifically, a software layer with the highest permission level is needed to manage multi-level table structures, such as the code in the Machine mode under the RISC-V architecture.

[0118] Example 3

[0119] Embodiment 3 is a preferred embodiment of Embodiment 1 and / or Embodiment 2.

[0120] The combination of the physical memory segment protection model and the table protection model allows trusted system software to dynamically use the two models on demand, while achieving fine-grained memory protection and high performance requirements. This embodiment is implemented based on the PMP physical memory segment protection mechanism under RISC-V. The process and system state of the present invention will be described in detail below through specific embodiments.

[0121] like Figure 1 As shown in the figure: A software tries to access a physical address. After finding the first matching PMP entry, if the T bit of the corresponding PMP configuration register is not set (PMP-0), the normal PMP rules are used to check permissions. The example diagram of the PMP configuration register is as follows: Figure 2 As shown, the present solution extends the T bit on the existing PMP configuration register to indicate whether a PMP is in the PMP table mode. Figure 2 Bit-5 of the configuration register is used to represent the T bit. In addition, other reserved bits in the configuration register may also be used as the T bit.

[0122] If the T bit is set (PMP-1), the PMP table is used to check permissions. First, the value of the next PMP address register (PMP-2) is read to obtain the base address of the root PMP table, and then the offset of the physical address is obtained through phy_addr-range_base, which is divided into four parts: OFF[1], OFF[0], Page index and Page offset. Figure 3As shown in the figure, this figure considers a two-level PMP table, so it only contains OFF[1] and OFF[0]. For PMP tables with more levels, the relative position may need to be divided into more segments (such as OFF[2]). First use OFF[1] to index the root PMP table to obtain the corresponding root PMP table entry. If the R, W, and X bits are not all zero, the final permission for memory access is constructed based on the R, W, and X bits in the table entry. Otherwise, the table entry is a pointer to the next level of protection table. In RV64 and RV32, the root PMP table entry manages 32MB of physical memory. In RV64, the format of the root PMP table entry and the intermediate PMP table entry is as follows: Figure 4 As shown in the figure, X, W, R, and V represent executable permission, writable permission, readable permission, and valid bit respectively. The first three are the same as the permissions in PMP. Note that X, W, R, V, and PPN here can have different positions. The reserved bits can be used for other extensions.

[0123] Next, use OFF[0] to index the leaf PMP table to obtain the corresponding leaf PMP table entry. Each 4 bits in the leaf PMP table entry identify the permission of a physical page. Use Page index to index the leaf PMP table entry to obtain the corresponding 4-bit permission. Finally, check the 4-bit permission (R, W, X and a reserved bit). The meaning is the same as that in the root PMP table entry. If the permission check fails, the corresponding operation cannot be performed. If the check passes, the steps are completed. Under RV32, the format of the leaf PMP table entry is as follows: Figure 5 As shown in the figure, a table entry contains 32 bits, corresponding to the permissions of 8 4KB pages. Each permission contains 4 bits, namely X, W, R and a reserved bit. Note that more bits are also extended here to represent permissions. In addition, the granularity of the page is not limited to 4KB pages, but can vary according to the specific implementation.

[0124] In summary, the present invention proposes a hybrid physical memory protection that combines the physical memory segment protection model and the table protection model, allowing trusted system software to dynamically use the two models on demand. In order to implement the table protection model, the present invention uses a reserved bit of the original PMP configuration register as the T bit, which is used to indicate whether the table mode is enabled. If T is set, the PMP table will be used to check permissions, including R, W, X and a reserved bit. When the T bit is 0, the PMP entry has the same function as the original entry. In order to support more physical memory ranges, the present invention adopts a two-level table. When R, W, and X in the root PMP table entry are all zero, it is a pointer to the next level of protection table. Through this scheme, in RV64, the maximum protection range of a single PMP table is limited to 16GB. Through 64 PMP entries, the PMP table can represent access rights to up to 512GB of physical memory.

[0125] Those skilled in the art know that, in addition to implementing the system, device and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0126] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A hybrid physical memory protection method, characterized in that: The method combines the segment protection model and the table protection model; including: When the physical memory protection method based on the segment protection model performs physical address protection, a flag bit in the configuration register in the segment protection mode is modified to convert to the table protection mode. In the table protection mode, the table protection mechanism is used to check permissions; when the flag bit is cleared, the segment protection model is still used to check permissions; The table protection mechanism uses multi-level table entries to control and protect the access to physical memory; the permission bits in each level of table entries include readable R, writable W, and executable X; The segment protection model is a model that divides physical memory into segments for access control and protection; The table protection model is a model that controls and protects access rights of physical memory using tables; include: Step S1: Get the first matching segment protection mode entry for a given physical memory address; Step S2: judging a flag bit of the configuration register in the segment protection mode, when it is 0, the current segment protection mode entry and the original entry have the same function; otherwise, the current entry is in the table protection mode; Step S3: Obtain the base address of the root table entry at the specified location in table protection mode; Step S4: obtaining a relative position based on a difference between the target physical address and the base address of the current protection area; Step S5: Find the target table entry by indexing in the multi-level table according to the relative position, so as to implement the permission check according to the information contained in the table entry.

2. The hybrid physical memory protection method according to claim 1, characterized in that: The multi-level table items include root table items and leaf table items or root table items, intermediate table items and leaf table items; The multi-level table entry includes the base address and physical address range of the protection area; the physical address range includes the address register and the configuration register; Using an additional address register to specify a base address of a root table entry; the address register includes a Mode field and a PPN field; The Mode field in the address register indicates the protection mode; The PPN field in the address register indicates the base address of the previous protection layer.

3. The hybrid physical memory protection method according to claim 2, characterized in that: In the root table entry or intermediate table entry, the R, W, and X bits respectively indicate whether it is readable, writable, and executable; when R, W, and X are all zero, the root table entry points to the pointer of the next layer of protection table; otherwise, the R, W, and X bits together constitute the final permission for memory access.

4. The hybrid physical memory protection method according to claim 2, characterized in that: In the leaf table entry, the leaf table entry records the permissions of the physical page. The permissions of each physical page need to correspond to at least R, W, and X bits; the R bit indicates whether the current page is readable; the W bit indicates whether the current page is writable; and the X bit indicates whether the current page is executable. Each leaf table entry records the permissions of multiple physical pages.

5. The hybrid physical memory protection method according to claim 1, characterized in that: Use software trust base to manage multi-level table structures.

6. A hybrid physical memory protection system, characterized in that: The system combines segment protection model and table protection model; including: When the physical memory protection method based on the segment protection model performs physical address protection, a flag bit in the configuration register in the segment protection mode is modified to convert to the table protection mode. In the table protection mode, the table protection mechanism is used to check permissions; when the flag bit is cleared, the segment protection model is still used to check permissions; The table protection mechanism uses multi-level table entries to control and protect the access to physical memory; the permission bits in each level of table entries include readable R, writable W, and executable X; The segment protection model is a model that divides physical memory into segments for access control and protection; The table protection model is a model that controls and protects access rights of physical memory using tables; include: Module M1: Get the first matching segment protection mode entry for a given physical memory address; Module M2: Determine a flag bit of the configuration register in the segment protection mode. When it is 0, the current segment protection mode entry has the same function as the original entry; otherwise, the current entry is in the table protection mode. Module M3: Get the base address of the root table entry at the specified location in table protection mode; Module M4: Obtaining a relative position based on the difference between the target physical address and the base address of the current protection area; Module M5: Find the target table entry by indexing in the multi-level table according to the relative position, so as to implement the permission check according to the information contained in the table entry.

7. The hybrid physical memory protection system according to claim 6, characterized in that: The multi-level table items include root table items and leaf table items or root table items, intermediate table items and leaf table items; The multi-level table entry includes the base address and physical address range of the protection area; the physical address range includes the address register and the configuration register; Using an additional address register to specify a base address of a root table entry; the address register includes a Mode field and a PPN field; The Mode field in the address register indicates the protection mode; The PPN field in the address register indicates the base address of the previous protection layer.

8. The hybrid physical memory protection system according to claim 7, characterized in that: In the root table entry or the intermediate table entry, the R, W, and X bits indicate whether it is readable, writable, and executable respectively; when R, W, and X are all zero, the root table entry points to the pointer of the next layer of protection table; otherwise, the R, W, and X bits together constitute the final permission for memory access; In the leaf table entry, the leaf table entry records the permissions of the physical page. The permissions of each physical page need to correspond to at least R, W, and X bits; the R bit indicates whether the current page is readable; the W bit indicates whether the current page is writable; and the X bit indicates whether the current page is executable. Each leaf table entry records the permissions of multiple physical pages.

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