Display motherboard and manufacturing method thereof, display substrate, and display panel

Abstract

The present disclosure provides a display motherboard and a manufacturing method thereof, a display substrate and a display panel. The display motherboard includes: a substrate and a wire, the substrate includes: a plurality of display substrate areas for forming a plurality of display substrates and a spacing area located outside the display substrate area, the wire is located on the spacing area; the display substrate area includes a display area and a non-display area located outside the display area, the non-display area includes: a wiring layer, arranged on one side of the substrate, the wiring layer includes a plurality of signal lines and / or data lines; an insulating layer, arranged on one side of the substrate and covering the wiring layer; a lead layer, arranged on a side of the insulating layer away from the substrate, the lead layer includes a plurality of leads, the leads are connected to the wiring in the wiring layer one by one, and the leads extend to the spacing area and are connected to the wires; a passivation layer, arranged on a side of the lead layer away from the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display motherboard, a method for manufacturing a display motherboard, a display substrate, and a display panel. Background Art

[0002] In the actual mass production manufacturing process of display devices, a display motherboard of a larger size (such as an array substrate motherboard) is usually formed first, and then the display motherboard is cut to form a single display substrate. In order to further improve the utilization rate of the substrate (such as a glass substrate) of the display motherboard, the areas where the display substrates to be formed are located are very close to each other, which makes the spacing between conductive structures such as wiring located outside each area smaller. When the static charges accumulated in adjacent areas have a large potential difference, it is easy to cause the wiring closest to the adjacent areas to be connected.

[0003] The instantaneous high current generated by ESD discharge (Electro-Static Discharge) will be transmitted through the above-mentioned wiring and other structures to the electronic devices electrically connected to them, such as the electronic devices in the GOA (Gate Driver on Array) area and the electronic devices in the AA (Active Area) area, thereby causing breakdown of the electronic devices in these areas and affecting the product yield.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a display motherboard, a method for manufacturing the display motherboard, a display substrate and a display panel, which can avoid defects such as ESD from occurring in the display panel during the manufacturing process.

[0006] According to one aspect of the present disclosure, a display motherboard is provided, the display motherboard comprising: a substrate and a wire, the substrate comprising: a plurality of display substrate areas for forming a plurality of display substrates and a spacer area located at the periphery of the display substrate area, the wire being located on the spacer area;

[0007] The display substrate area includes a display area and a non-display area located outside the display area, and the non-display area includes:

[0008] A wiring layer, disposed on one side of the substrate, the wiring layer comprising a plurality of signal lines and / or data lines;

[0009] An insulating layer, disposed on one side of the substrate and covering the wiring layer;

[0010] A lead layer is provided on a side of the insulating layer away from the substrate, the lead layer comprises a plurality of leads, the leads are connected to the routing lines in the routing layer in a one-to-one correspondence, and the leads extend to the spacing area and are connected to the wires;

[0011] The passivation layer is arranged on a side of the lead layer away from the substrate.

[0012] In an exemplary embodiment of the present disclosure, the non-display area includes a chip input pin area and a flexible circuit board input pin area, and the chip input pin area also includes: a first metal layer, which is connected to the wiring layer; the orthographic projection of the first metal layer on the substrate at least partially overlaps with the orthographic projection of the portion where the lead layer and the wiring layer are connected on the substrate.

[0013] In an exemplary embodiment of the present disclosure, the non-display area includes a chip input pin area and a flexible circuit board input pin area, and the orthographic projection of the lead on the substrate is at least partially located in the flexible circuit board input pin area.

[0014] In an exemplary embodiment of the present disclosure, the non-display area includes a chip input pin area and a flexible circuit board input pin area, and the non-display area also includes:

[0015] A second metal layer is located in the chip input pin area, the second metal layer is located on the insulating layer and connected to the lead layer, and the second metal layer is connected to the routing layer through a via.

[0016] In an exemplary embodiment of the present disclosure, the chip input pin area also includes: a first metal layer, the first metal layer is connected to the wiring layer; the orthographic projection of the first metal layer on the substrate at least partially overlaps with the orthographic projection of the portion where the lead layer and the second metal layer are connected on the substrate.

[0017] In an exemplary embodiment of the present disclosure, an orthographic projection of the lead on the substrate is at least partially located in an input pin region of the flexible circuit board.

[0018] According to another aspect of the present disclosure, a method for manufacturing a display motherboard is provided, the manufacturing method comprising:

[0019] A substrate is provided, the substrate comprising a plurality of display substrate areas for forming a plurality of display substrates and a spacer area located outside the display substrate area, and a conductive line is formed on the spacer area; the display substrate area comprises a display area and a non-display area located outside the display area;

[0020] Forming a wiring layer on one side of the non-display area of ​​the substrate, the wiring layer comprising a plurality of signal lines and / or data lines;

[0021] forming an insulating layer covering the wiring layer on one side of the substrate;

[0022] A lead layer is formed on a side of the insulating layer away from the substrate, wherein the lead layer includes a plurality of leads, the leads are connected to the routing lines in the routing layer in a one-to-one correspondence, and the leads extend to the spacing area and are connected to the wires;

[0023] A passivation layer is formed on a side of the lead layer facing away from the substrate.

[0024] According to another aspect of the present disclosure, a display substrate is provided. The display substrate is formed by cutting the above-mentioned display motherboard.

[0025] In an exemplary embodiment of the present disclosure, a coating layer is provided on the cross section of the display substrate from which the lead wires are led out after being cut.

[0026] According to yet another aspect of the present disclosure, a display panel is provided. The display panel includes the above-mentioned display substrate.

[0027] The display motherboard provided by the present disclosure can connect the wiring layer to the wires in the spacing area through the lead layer, connect the display substrate metals by using the lead layer of the front metal layer, and lead them out to the outside of the display substrate, and connect all the display substrates on the substrate to form a large electrostatic loop, so as to achieve the technical effect of dispersing large currents and reducing ESD (Electro-Static discharge) damage in the array process, and solve the problem of low product yield caused by ESD damage.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 A schematic diagram of a display motherboard provided for an embodiment of the present disclosure;

[0031] Figure 2 A schematic diagram of a display motherboard provided for another embodiment of the present disclosure;

[0032] Figure 3 A partial cross-sectional view of a display motherboard provided for the first embodiment of the present disclosure;

[0033] Figure 4 A partial cross-sectional view of a display motherboard provided for a second embodiment of the present disclosure;

[0034] Figure 5 A partial cross-sectional view of a display motherboard provided for a third embodiment of the present disclosure;

[0035] Figure 6 A partial cross-sectional view of a display motherboard provided for a fourth embodiment of the present disclosure;

[0036] Figure 7 A partial cross-sectional view of a display motherboard provided for a fifth embodiment of the present disclosure;

[0037] Figure 8 A partial cross-sectional view of a display motherboard provided for a sixth embodiment of the present disclosure;

[0038] Fig. 9 A partial cross-sectional view of a display motherboard provided for a seventh embodiment of the present disclosure;

[0039] Fig.10 A partial cross-sectional view of a display motherboard provided for an eighth embodiment of the present disclosure;

[0040] Fig.11 A schematic diagram of a method for manufacturing a display motherboard provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0042] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0043] The terms "a", "an", "the", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second" are used merely as labels and are not intended to limit the quantity of their objects.

[0044] The embodiment of the present disclosure first provides a display motherboard, such as Figure 1-Figure 10 As shown, the display motherboard 10 includes: a substrate 210 and a wire 130, the substrate 210 includes: a plurality of display substrate areas 120 for forming a plurality of display substrates 210 and a spacer area 110 located at the periphery of the display substrate area 120, and the wire 130 is located on the spacer area 110;

[0045] The display substrate area 120 includes a display area and a non-display area located outside the display area. The non-display area includes: a routing layer 220, an insulating layer 230, a lead layer 240, the lead layer 240 and a passivation layer 260. The routing layer 220 is arranged on one side of the substrate 210, and the routing layer 220 includes a plurality of signal lines and / or data lines; the insulating layer 230 is arranged on one side of the substrate 210 and covers the routing layer 220; the lead layer 240 is arranged on the side of the insulating layer 230 away from the substrate 210, and the lead layer 240 includes a plurality of leads. The lead layer 240 is connected to the routing lines in the routing layer 220 one by one, and the leads extend to the spacing area 110 and are connected to the wires 130; the passivation layer 260 is arranged on the side of the lead layer 240 away from the substrate 210.

[0046] In the display motherboard provided by the present disclosure, the routing layer 220 can be connected to the wire 130 of the spacer area 110 through the lead layer 240. The display substrate metal is connected by the lead layer 240 of the front metal layer and led out to the outside of the display substrate, and all display substrates on the substrate 210 are connected to form a large electrostatic loop, so as to achieve the technical effect of dispersing large currents and reducing ESD (Electro-Static discharge) damage in the array process, thereby solving the problem of low product yield caused by ESD damage.

[0047] Specifically, the routing layer 220 includes a plurality of GOA (Gate on Array) signal lines or data lines, or includes a plurality of GOA signal lines and data lines at the same time. The GOA signal line connects the GOA unit, controls the gate of the driving transistor in the display area through the GOA unit, and integrates the gate switch circuit on the display substrate of the display panel through the GOA technology, thereby saving the gate drive integrated circuit part, so as to reduce the product cost from both material cost and manufacturing process. Each GOA signal line is connected to the input pin of the IC (chip). The data line connects the source of the driving transistor to write data. The routing layer 220 includes a plurality of GOA signal lines and data lines at the same time, which can prevent the damage of the GOA unit and the driving transistor caused by ESD caused by static electricity, and improve the product yield.

[0048] like Figure 3-Figure 6 As shown, in the manufacturing process of the display motherboard of this embodiment, the wiring layer 220 is first formed, and then holes are punched through the insulating layer 230, and then the second metal layer 250 is formed to connect the second metal layer 250 to the wiring layer 220. The second metal layer 250 is formed after the lead layer 240 and is connected to the lead layer 240.

[0049] The insulating layer 230 is a gate insulating layer (GI), and the material forming the insulating layer 230 may be silicon oxide, silicon oxynitride, silicon nitride or other suitable insulating materials (such as organic polymer compounds) or a combination of the above materials. The insulating layer 230 may be formed by, for example, physical vapor deposition, chemical vapor deposition, spin coating or a combination thereof.

[0050] The wiring layer 220 is a conductive material, and the conductive material can be platinum, gold, silver, aluminum, chromium, nickel, copper, titanium, magnesium, calcium, barium, sodium, palladium, iron, indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, or a combination thereof. The method of forming the wiring layer 220 is, for example, physical vapor deposition, chemical vapor deposition, spin coating, or a combination thereof. The method of removing part of the wiring layer 220 to perform patterning to form wiring is, for example, dry etching, wet etching, or a combination thereof.

[0051] The material of the lead layer 240 may be indium tin oxide (ITO), that is, the lead layer 240 is an ITO layer.

[0052] Among them, the second metal layer 250 is a source-drain metal layer, and the material of the source-drain metal layer may include a metal, a conductive oxide or a combination thereof. For example, the metal may be titanium, platinum, ruthenium, gold, silver, aluminum, tungsten, copper or an alloy thereof or a combination of the above materials. The conductive oxide may be IZO, AZO, ITO, GZO, ZTO or a combination thereof. The method of forming the source-drain metal layer is, for example, physical vapor deposition, chemical vapor deposition, spin coating or a combination thereof. The method of removing part of the source-drain metal layer for patterning is, for example, dry etching, wet etching or a combination thereof.

[0053] The material of the passivation layer 260 may be silicon oxide, silicon oxynitride, silicon nitride, organic materials or a combination thereof. The passivation layer 260 may be formed by physical vapor deposition, chemical vapor deposition, spin coating or a combination thereof.

[0054] For example, Figure 3 As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the second metal layer 250 is located on the insulating layer 230 and connected to the lead layer 240. The second metal layer 250 is connected to the wiring layer 220 through the via hole of the insulating layer 230. The chip input pin area also includes: a first metal layer 270, and the first metal layer 270 is connected to the wiring layer 220 through the via hole of the passivation layer 260 and the via hole of the insulating layer 230; the orthographic projection of the first metal layer 270 on the substrate 210 at least partially overlaps with the orthographic projection of the part where the lead layer 240 and the second metal layer 250 are connected on the substrate 210, that is, the signal line or data line of the wiring layer 220 is led out in the chip input pin area. The orthographic projection of the lead on the substrate 210 is at least partially located in the flexible circuit board input pin area, that is, the lead passes through the flexible circuit board input pin area and extends to the spacer area 110 to connect with the wire 130. The first metal layer 270 may be used as a chip input pin, and the material of the first metal layer 270 may be indium tin oxide (ITO).

[0055] For example, Figure 4 As shown, the second metal layer 250 is located on the insulating layer 230 and connected to the lead layer 240, and the second metal layer 250 is connected to the wiring layer 220 through the via hole of the insulating layer 230. The part where the lead layer 240 is connected to the second metal layer 250 is located in the area outside the chip input pin area, that is, the wiring layer 220 is directly led out of the display substrate through the lead layer 240. Among them, the orthographic projection of the lead on the substrate 210 is at least partially located in the flexible circuit board input pin area, that is, the lead passes through the flexible circuit board input pin area and extends to the spacing area 110 to connect with the wire 130.

[0056] For example, Figure 5As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the second metal layer 250 is located on the insulating layer 230 and connected to the lead layer 240. The second metal layer 250 is connected to the wiring layer 220 through the via hole in the insulating layer 230. The chip input pin area also includes: a first metal layer 270, and the first metal layer 270 is connected to the wiring layer 220 through the via hole in the passivation layer 260 and the via hole in the insulating layer 230; the orthographic projection of the first metal layer 270 on the substrate 210 at least partially overlaps with the orthographic projection of the part where the lead layer 240 and the second metal layer 250 are connected on the substrate 210, that is, the signal line or data line of the wiring layer 220 is led out in the chip input pin area. The orthographic projection of the lead on the substrate 210 has no overlapping part with the flexible circuit board input pin area, that is, the lead does not extend through the flexible circuit board input pin area to the spacer area 110 to connect with the wire 130, and can be led out from both sides of the flexible circuit board input pin area. The first metal layer 270 may be used as a chip input pin, and the material of the first metal layer 270 may be indium tin oxide.

[0057] For example, Figure 6 As shown, the second metal layer 250 is located on the insulating layer 230 and connected to the lead layer 240, and the second metal layer 250 is connected to the wiring layer 220 through the via hole of the insulating layer 230. The part where the lead layer 240 is connected to the second metal layer 250 is located outside the chip input pin area, that is, the wiring layer 220 is directly led out of the display substrate through the lead layer 240. Among them, the orthographic projection of the lead on the substrate 210 has no overlapping part with the input pin area of ​​the flexible circuit board, that is, the lead does not extend through the input pin area of ​​the flexible circuit board to the spacer area 110 to connect with the wire 130, and can be led out from both sides of the input pin area of ​​the flexible circuit board.

[0058] like Figure 7-10 As shown, in the manufacturing process of the display motherboard of this embodiment, the via holes of the insulating layer 230 are first formed, and then the lead layer 240 is formed, so that the lead layer 240 is connected to the wiring layer 220 through the via holes of the insulating layer 230. The lead layer 240 is a source and drain metal layer.

[0059] For example, Figure 7As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the lead layer 240 is located on the insulating layer 230 and connected to the lead layer 240 through the insulating layer 230 via hole. The chip input pin area also includes: a first metal layer 270, the first metal layer 270 is connected to the wiring layer 220 through the passivation layer 260 via hole and the insulating layer 230 via hole; the orthographic projection of the first metal layer 270 on the substrate 210 is at least partially overlapped with the orthographic projection of the part where the lead layer 240 and the second metal layer 250 are connected on the substrate 210, that is, the signal line or data line of the wiring layer 220 is led out in the chip input pin area. The orthographic projection of the lead on the substrate 210 is at least partially located in the flexible circuit board input pin area, that is, the lead passes through the flexible circuit board input pin area and extends to the spacer area 110 to connect with the wire 130. The first metal layer 270 can be used as a chip input pin, and the material of the first metal layer 270 can be indium tin oxide.

[0060] For example, Figure 8 As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the lead layer 240 is located on the insulating layer 230 and is connected to the lead layer 240 through the insulating layer 230 via holes. The portion where the lead layer 240 is connected to the routing layer 220 is located outside the chip input pin area, that is, the routing layer 220 is directly led out of the display substrate through the lead layer 240. Among them, the orthographic projection of the lead on the substrate 210 is at least partially located in the flexible circuit board input pin area, that is, the lead passes through the flexible circuit board input pin area and extends to the spacing area 110 to connect with the wire 130.

[0061] For example, Fig. 9 As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the lead layer 240 is located on the insulating layer 230 and is connected to the lead layer 240 through the insulating layer 230 via hole. The chip input pin area also includes: a first metal layer 270, the first metal layer 270 is connected to the wiring layer 220 through the passivation layer 260 via hole and the insulating layer 230 via hole; the orthographic projection of the first metal layer 270 on the substrate 210 at least partially overlaps with the orthographic projection of the portion where the lead layer 240 and the second metal layer 250 are connected on the substrate 210, that is, the signal line or data line of the wiring layer 220 is led out in the chip input pin area. The orthographic projection of the lead on the substrate 210 has no overlapping part with the flexible circuit board input pin area, that is, the lead does not pass through the flexible circuit board input pin area to extend to the spacer area 110 to connect with the wire 130, and can be led out from both sides of the flexible circuit board input pin area. The first metal layer 270 may be used as a chip input pin, and the material of the first metal layer 270 may be indium tin oxide.

[0062] For example, Fig.10As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the lead layer 240 is located on the insulating layer 230 and is connected to the lead layer 240 through the insulating layer 230 via holes. The portion where the lead layer 240 is connected to the routing layer 220 is located outside the chip input pin area, that is, the routing layer 220 is directly led out of the display substrate through the lead layer 240. Among them, the orthographic projection of the lead on the substrate 210 has no overlap with the flexible circuit board input pin area, that is, the lead does not pass through the flexible circuit board input pin area to extend to the spacer area 110 to connect with the wire 130, and can be led out from both sides of the flexible circuit board input pin area.

[0063] For example, Figure 1 As shown, the leads of the display substrate area 120 are all connected to the wire 130. Connected wires 130 are set on the spacer areas 110 outside each display substrate area 120 on the display motherboard, and on the spacer areas 110 between adjacent rows of the display substrate, so that all display substrate areas 120 are connected to form a large electrostatic loop, so as to achieve the technical effect of dispersing large currents and reducing ESD damage in the array process, and solve the problem of low product yield caused by ESD damage. Of course, the wire 130 can also be set in other routing modes on the spacer area 110 to form a large electrostatic loop, and the present disclosure does not limit this. Any change in the routing mode of the wire 130 on the spacer area belongs to the protection scope of the present disclosure.

[0064] For example, the width of the wire 130 is 15μm-25μm, such as 15μm, 18μm, 20μm, 22μm, 25μm, etc., which are not listed here in the present disclosure; of course, the width of the wire 130 may also be less than 15μm or greater than 25μm, which is not limited in the present disclosure.

[0065] For example, the material of the wire 130 is a metal conductive material, and the metal conductive material may be the same as the material of the lead wire. For example, the material of the wire 130 includes ITO, iron, copper, aluminum, titanium, etc., and the present disclosure does not limit this.

[0066] The embodiment of the present disclosure also provides a method for manufacturing a display motherboard, such as Fig.11 As shown, the manufacturing method includes:

[0067] Step S310, providing a substrate 210, wherein the substrate 210 includes a plurality of display substrate areas 120 for forming a plurality of display substrates and a spacer area 110 located outside the display substrate area 120, and a conductive line 130 is formed on the spacer area 110; the display substrate area 120 includes a display area and a non-display area located outside the display area;

[0068] Step S320, forming a wiring layer 220 on one side of the non-display area of ​​the substrate 210, wherein the wiring layer 220 includes a plurality of signal lines and / or data lines;

[0069] Step S330, forming an insulating layer 230 covering the wiring layer 220 on one side of the substrate 210;

[0070] Step S340, forming a lead layer 240 on a side of the insulating layer 230 away from the substrate 210, wherein the lead layer 240 includes a plurality of leads, the leads are connected to the wirings in the wiring layer 220 in a one-to-one correspondence, and the leads extend to the spacer 110 and are connected to the wires 130;

[0071] Step S350 , forming a passivation layer 260 on a side of the lead layer 240 facing away from the substrate 210 .

[0072] The manufacturing method of the display motherboard provided by the present disclosure is that the routing layer 220 can be connected to the wire 130 of the spacer area 110 through the lead layer 240, and the display substrate metal is connected by using the lead layer 240 of the front metal layer and led out to the outside of the display substrate, and all the display substrates on the substrate 210 are connected to form a large electrostatic loop, so as to achieve the technical effect of dispersing large currents and reducing ESD damage in the array process, and solve the problem of low product yield caused by ESD damage.

[0073] like Figure 3-Figure 6 As shown, in the manufacturing method of the display motherboard of this embodiment, the wiring layer 220 is first formed, and then holes are punched through the insulating layer 230, and then the second metal layer 250 is formed, so that the second metal layer 250 is connected to the wiring layer 220, and the second metal layer 250 is formed after the lead layer 240 and connected to the lead layer 240. Among them, the second metal layer 250 is a source and drain metal layer, and the lead layer 240 is an ITO layer. The following are four embodiments of the manufacturing method of the display motherboard of this embodiment:

[0074] For example, Figure 4 As shown, the second metal layer 250 is located on the insulating layer 230 and connected to the lead layer 240, and the second metal layer 250 is connected to the wiring layer 220 through the via hole of the insulating layer 230. The part where the lead layer 240 is connected to the second metal layer 250 is located in the area outside the chip input pin area, that is, the wiring layer 220 is directly led out of the display substrate through the lead layer 240. Among them, the orthographic projection of the lead on the substrate 210 is at least partially located in the flexible circuit board input pin area, that is, the lead passes through the flexible circuit board input pin area and extends to the spacing area 110 to connect with the wire 130.

[0075] For example, Figure 5As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the second metal layer 250 is located on the insulating layer 230 and connected to the lead layer 240. The second metal layer 250 is connected to the wiring layer 220 through the via hole in the insulating layer 230. The chip input pin area also includes: a first metal layer 270, and the first metal layer 270 is connected to the wiring layer 220 through the via hole in the passivation layer 260 and the via hole in the insulating layer 230; the orthographic projection of the first metal layer 270 on the substrate 210 at least partially overlaps with the orthographic projection of the part where the lead layer 240 and the second metal layer 250 are connected on the substrate 210, that is, the signal line or data line of the wiring layer 220 is led out in the chip input pin area. The orthographic projection of the lead on the substrate 210 has no overlapping part with the flexible circuit board input pin area, that is, the lead does not extend through the flexible circuit board input pin area to the spacer area 110 to connect with the wire 130, and can be led out from both sides of the flexible circuit board input pin area. The first metal layer 270 can be used as a chip input pin.

[0076] For example, Figure 6 As shown, the second metal layer 250 is located on the insulating layer 230 and connected to the lead layer 240, and the second metal layer 250 is connected to the wiring layer 220 through the via hole of the insulating layer 230. The part where the lead layer 240 is connected to the second metal layer 250 is located outside the chip input pin area, that is, the wiring layer 220 is directly led out of the display substrate through the lead layer 240. Among them, the orthographic projection of the lead on the substrate 210 has no overlapping part with the input pin area of ​​the flexible circuit board, that is, the lead does not extend through the input pin area of ​​the flexible circuit board to the spacer area 110 to connect with the wire 130, and can be led out from both sides of the input pin area of ​​the flexible circuit board.

[0077] like Figure 7-10 As shown, in the manufacturing method of the display motherboard of this embodiment, the insulating layer 230 via hole is first formed, and then the lead layer 240 is formed, so that the lead layer 240 and the wiring layer 220 are connected through the insulating layer 230 via hole. The lead layer 240 is a source and drain metal layer. The following are four embodiments of the manufacturing method of the display motherboard of this embodiment:

[0078] For example, Figure 7As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the lead layer 240 is located on the insulating layer 230 and is connected to the lead layer 240 through the insulating layer 230 via hole. The chip input pin area also includes: a first metal layer 270, the first metal layer 270 is connected to the wiring layer 220 through the passivation layer 260 via hole and the insulating layer 230 via hole; the orthographic projection of the first metal layer 270 on the substrate 210 is at least partially overlapped with the orthographic projection of the part where the lead layer 240 and the second metal layer 250 are connected on the substrate 210, that is, the signal line or data line of the wiring layer 220 is led out in the chip input pin area. The orthographic projection of the lead on the substrate 210 is at least partially located in the flexible circuit board input pin area, that is, the lead passes through the flexible circuit board input pin area and extends to the spacer area 110 to connect with the wire 130. The first metal layer 270 can be used as a chip input pin.

[0079] For example, Figure 8 As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the lead layer 240 is located on the insulating layer 230 and is connected to the lead layer 240 through the insulating layer 230 via holes. The portion where the lead layer 240 is connected to the routing layer 220 is located outside the chip input pin area, that is, the routing layer 220 is directly led out of the display substrate through the lead layer 240. Among them, the orthographic projection of the lead on the substrate 210 is at least partially located in the flexible circuit board input pin area, that is, the lead passes through the flexible circuit board input pin area and extends to the spacing area 110 to connect with the wire 130.

[0080] For example, Fig. 9 As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the lead layer 240 is located on the insulating layer 230 and is connected to the lead layer 240 through the insulating layer 230 via hole. The chip input pin area also includes: a first metal layer 270, the first metal layer 270 is connected to the routing layer 220 through the passivation layer 260 via hole and the insulating layer 230 via hole; the orthographic projection of the first metal layer 270 on the substrate 210 is at least partially overlapped with the orthographic projection of the part where the lead layer 240 and the second metal layer 250 are connected on the substrate 210, that is, the signal line or data line of the routing layer 220 is led out in the chip input pin area. The orthographic projection of the lead on the substrate 210 has no overlap with the flexible circuit board input pin area, that is, the lead does not pass through the flexible circuit board input pin area to extend to the spacer area 110 to connect with the wire 130, and can be led out from both sides of the flexible circuit board input pin area. The first metal layer 270 can be used as a chip input pin.

[0081] For example, Fig.10As shown, the non-display area includes a chip input pin area and a flexible circuit board input pin area. In the chip input pin area, the lead layer 240 is located on the insulating layer 230 and is connected to the lead layer 240 through the insulating layer 230 via holes. The portion where the lead layer 240 is connected to the routing layer 220 is located outside the chip input pin area, that is, the routing layer 220 is directly led out of the display substrate through the lead layer 240. Among them, the orthographic projection of the lead on the substrate 210 has no overlap with the flexible circuit board input pin area, that is, the lead does not pass through the flexible circuit board input pin area to extend to the spacer area 110 to connect with the wire 130, and can be led out from both sides of the flexible circuit board input pin area.

[0082] An embodiment of the present disclosure further provides a display substrate, which is formed by cutting the above-mentioned display motherboard.

[0083] Among them, a coating layer is provided on the section of the lead wire after the display substrate is cut. The lead wire can be covered by widening the module FPC design, and the lead wire section is sealed when the FPC back glue is coated. There is no additional process, which reduces production costs and improves production efficiency.

[0084] The embodiment of the present disclosure further provides a display panel, which includes the above-mentioned display substrate. The display panel can be an organic light-emitting display panel, or of course, a liquid crystal display panel, and its type is not particularly limited here. The display panel can be used in a mobile phone, a tablet computer or other terminal devices, and its beneficial effects can refer to the beneficial effects of the above-mentioned manufacturing method, which will not be described in detail here.

[0085] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0086] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display motherboard, characterized in that: include: A substrate and a conductive line, wherein the substrate comprises: a plurality of display substrate areas for forming a plurality of display substrates and a spacer area located at the periphery of the display substrate area, and the conductive line is located on the spacer area; The display substrate area includes a display area and a non-display area located outside the display area, and the non-display area includes: A wiring layer, disposed on one side of the substrate, the wiring layer comprising a plurality of signal lines and / or data lines; An insulating layer, disposed on one side of the substrate and covering the wiring layer; A lead layer is provided on a side of the insulating layer away from the substrate, the lead layer comprises a plurality of leads, the leads are connected to the routing lines in the routing layer in a one-to-one correspondence, and the leads extend to the spacing area and are connected to the wires; A passivation layer is provided on a side of the lead layer away from the substrate; The non-display area includes a chip input pin area and a flexible circuit board input pin area, and the chip input pin area also includes: a first metal layer, the first metal layer is connected to the wiring layer; the orthographic projection of the first metal layer on the substrate at least partially overlaps with the orthographic projection of the portion where the lead layer and the wiring layer are connected on the substrate; Wherein, the non-display area further includes: a second metal layer, in the chip input pin area, the second metal layer is located on the insulating layer and connected to the lead layer, and the second metal layer is connected to the routing layer through a via.

2. The display motherboard according to claim 1, characterized in that: The non-display area includes a chip input pin area and a flexible circuit board input pin area, and the orthographic projection of the lead on the substrate is at least partially located in the flexible circuit board input pin area.

3. The display motherboard according to claim 1, characterized in that: The chip input pin area also includes: a first metal layer, the first metal layer is connected to the wiring layer; the orthographic projection of the first metal layer on the substrate at least partially overlaps with the orthographic projection of the portion where the lead layer and the second metal layer are connected on the substrate.

4. The display motherboard according to claim 1 or 3, characterized in that: The orthographic projection of the lead on the substrate is at least partially located in the input pin area of ​​the flexible circuit board.

5. A method for manufacturing a display motherboard, characterized in that: include: A substrate is provided, the substrate comprising a plurality of display substrate areas for forming a plurality of display substrates and a spacer area located outside the display substrate area, and a conductive line is formed on the spacer area; the display substrate area comprises a display area and a non-display area located outside the display area; Forming a wiring layer on one side of the non-display area of ​​the substrate, the wiring layer comprising a plurality of signal lines and / or data lines; forming an insulating layer covering the wiring layer on one side of the substrate; A lead layer is formed on a side of the insulating layer away from the substrate, wherein the lead layer includes a plurality of leads, the leads are connected to the routing lines in the routing layer in a one-to-one correspondence, and the leads extend to the spacing area and are connected to the wires; forming a passivation layer on a side of the lead layer facing away from the substrate; The non-display area includes a chip input pin area and a flexible circuit board input pin area, and the chip input pin area also includes: a first metal layer, the first metal layer is connected to the wiring layer; the orthographic projection of the first metal layer on the substrate at least partially overlaps with the orthographic projection of the portion where the lead layer and the wiring layer are connected on the substrate; Wherein, the non-display area further includes: a second metal layer, in the chip input pin area, the second metal layer is located on the insulating layer and connected to the lead layer, and the second metal layer is connected to the routing layer through a via.

6. A display substrate, characterized in that: It is formed by cutting the display motherboard described in any one of claims 1 to 4.

7. The display substrate according to claim 6, characterized in that: A coating layer is provided on the cross section where the lead wires are led out after the display substrate is cut.

8. A display panel, characterized in that: Comprising the display substrate according to claim 6 or 7.

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