Array test sub-circuit, test circuit, test method and display panel

Abstract

Embodiments of the present application relate to the technical field of display panel testing, and disclose an array test sub-circuit, which can control the signal of a plurality of data lines connected with a single test unit to be sequentially output from a test port through two test signal lines (a first test signal line and a second test signal line), so as to realize short circuit test of the data lines in the display panel. The array test sub-circuit, test circuit, test method and display panel provided by the embodiments of the present application reduce the number of test leads in the array test sub-circuit and lower the difficulty of layout.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display panel testing, in particular to an array test sub-circuit, a test circuit, a test method and a display panel. BACKGROUND

[0002] With the rapid development of display technology, display panels are increasingly widely used. The safety requirements for display panels are also increasingly high.

[0003] A display panel includes a display area and a non-display area. A plurality of traces are concentrated in the non-display area, and the traces include data lines. In the trace dense area, the possibility of short circuit between adjacent data lines is high. Once a short circuit occurs between the data lines, it will adversely affect the display effect of the display panel, thereby causing yield loss of the display panel. Therefore, before the display panel is shipped, an array test sub-circuit is used to test whether the data lines are short-circuited, but the current array test sub-circuit has many test leads, and there is a problem of insufficient space for placement and difficult layout. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide an array test sub-circuit, a test circuit, a test method and a display panel, which reduce the number of test leads in the array test sub-circuit and reduce the difficulty of layout.

[0005] To solve the above technical problems, the embodiments of the present application provide an array test sub-circuit, which includes a first test signal line, a second test signal line, a plurality of test ports, and a plurality of test units connected to the first test signal line, the second test signal line and the plurality of test ports; each test unit includes three switching modules, each switching module includes a control end, an input end, a first output end and a second output end, wherein when the control end is configured as a first level signal, the first output end outputs a signal and the second output end does not output a signal, when the control end is configured as a second level signal, the first output end does not output a signal and the second output end outputs a signal, and the first level signal and the second level signal are opposite in polarity; the three switching modules include a first switching module, a second switching module and a third switching module; the control end of the first switching module and the control end of the second switching module are connected to the first test signal line, and the first output end and the second output end of the first switching module are used to connect data lines of a display panel; the control end of the third switching module is connected to the second test signal line, the first output end of the third switching module is connected to the input end of the first switching module, and the second output end of the third switching module is connected to the input end of the second switching module; and the input end of the third switching module is connected to one test port.

[0006] In addition, each of the switching modules comprises two test switches, each of the test switches comprises a gate, a first pole and a second pole; the two test switches comprise a first test switch and a second test switch, wherein the first test switch is turned on under the first level signal and is not turned on under the second level signal; the second test switch is not turned on under the first level signal and is turned on under the second level signal; the first pole of the first test switch and the first pole of the second test switch are connected as the input end; the gate of the first test switch and the gate of the second test switch are connected as the control end; the second pole of the first test switch is connected as the first output end; and the second pole of the second test switch is connected as the second output end.

[0007] In addition, the first test switch is an N-type switch tube, and the second test switch is a P-type switch tube.

[0008] The embodiment of the present application further provides a test circuit, comprising: a panel test sub-circuit comprising a panel test switch unit, the panel test switch unit being connected with a data line of a display panel, the panel test sub-circuit being used for controlling the panel test switch unit to be turned on or turned off to transmit a plurality of panel test signals according to a plurality of received panel test control signals; an array test sub-circuit comprising a first test signal line, a second test signal line, a plurality of test ports and a plurality of test units connecting the first test signal line, the second test signal line and the plurality of test ports; each of the test units comprises three switching modules, each of the switching modules comprises a control end, an input end, a first output end and a second output end, wherein when the control end is configured as a first level signal, the first output end outputs a signal and the second output end does not output a signal, and when the control end is configured as a second level signal, the first output end does not output a signal and the second output end outputs a signal, the first level signal and the second level signal are opposite in polarity; the three switching modules comprise a first switching module, a second switching module and a third switching module; the control end of the first switching module and the control end of the second switching module are connected with the first test signal line, and the first output end and the second output end of the first switching module are connected with the data line respectively; the control end of the third switching module is connected with the second test signal line, the first output end of the third switching module is connected with the input end of the first switching module, and the second output end of the third switching module is connected with the input end of the second switching module; and the input end of the third switching module is connected with one of the test ports.

[0009] In addition, each of the switching modules comprises two test switches, each of the test switches comprises a gate, a first pole and a second pole; the two test switches comprise a first test switch and a second test switch, wherein the first test switch is turned on under the first level signal and is not turned on under the second level signal; the second test switch is not turned on under the first level signal and is turned on under the second level signal; the first pole of the first test switch and the first pole of the second test switch are connected as the input end; the gate of the first test switch and the gate of the second test switch are the control end; the second pole of the first test switch is the first output end; and the second pole of the second test switch is the second output end.

[0010] In addition, the first test switch is an N-type switch tube, and the second test switch is a P-type switch tube.

[0011] The embodiment of the application further provides a test method applied to the test circuit, the test method comprising: in a test period, the first test signal line outputs a first test signal formed by the first level signal and the second level signal in a first preset order, the second test signal line outputs a second test signal formed by the first level signal and the second level signal in a second preset order, and the test unit is controlled; according to the plurality of panel test signals transmitted by the panel test sub-circuit, a short-circuit judgment signal output by the test port is received, and the short-circuit judgment signal is used to judge whether the data line in the display panel has a short circuit.

[0012] In addition, in a test period, according to the time sequence, the first test signal and the second test signal comprise four groups of level states, and sequentially comprise: the first test signal is the first level, and the second test signal is the first level; the first test signal is the second level, and the second test signal is the first level; the first test signal is the first level, and the second test signal is the second level; and the first test signal is the second level, and the second test signal is the second level.

[0013] In addition, after the short-circuit judgment signal output by the test port is received according to the plurality of panel test signals transmitted by the panel test sub-circuit, the method further comprises: judging whether the amplitude of the short-circuit judgment signal exceeds a preset signal standard amplitude range; and if the short-circuit judgment signal exceeds the preset signal standard amplitude range, it is determined that the data line has a short circuit.

[0014] The embodiment of the application provides a display panel comprising the array test sub-circuit or the test circuit.

[0015] The array test sub-circuit provided by the embodiment of the present application can output signals from the first output end of the third switch module when the second test signal line is configured as the first level signal, and output signals from the second output end of the third switch module when the first test signal line is configured as the first level signal and the second level signal in this state. At this time, the first output end and the second output end of the first switch module output signals in turn, that is, the test port can receive signals from the data line connected to the first output end of the first switch module and signals from the data line connected to the second output end of the first switch module in turn. Then, the array test sub-circuit can output signals from the second output end of the third switch module when the second test signal line is configured as the second level signal, and output signals from the first output end of the second switch module when the first test signal line is configured as the first level signal and the second level signal in this state. At this time, the first output end and the second output end of the second switch module output signals in turn, that is, the test port can receive signals from the data line connected to the first output end of the second switch module and signals from the data line connected to the second output end of the second switch module in turn. In this way, the signals of the plurality of data lines connected to a single test unit can be controlled to be output from one test port in turn by using two test signal lines (the first test signal line and the second test signal line), so that the short circuit test of the data lines in the display panel is realized, the number of test leads in the array test sub-circuit is reduced, and the difficulty of layout is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are included to further provide explanatory embodiments and not limitation of the embodiments. Elements shown with the same reference numeral in different figures represent like elements unless otherwise specified. The figures are not necessarily drawn to scale.

[0017] Figure 1 is a structural schematic diagram of an existing array test sub-circuit;

[0018] Figure 2 is a structural schematic diagram of an array test sub-circuit according to the embodiment of the present application;

[0019] Figure 3 is Figure 2 is a waveform diagram of the first test signal line and the second test signal line in the array test sub-circuit shown in FIG. 4;

[0020] Figure 4 is a structural schematic diagram of an existing test circuit;

[0021] Figure 5is a structural schematic diagram of a test circuit according to an embodiment of the present application;

[0022] Figure 6 is a flowchart of a test method according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0024] As shown in Figure 1 , the existing array test sub-circuit for short circuit test of data lines of a display panel includes four array test control signal lines, namely AT_mux1, AT_mux2, AT_mux3 and AT_mux4. The array test sub-circuit adopts a cyclic design of four TFT switches, wherein T1, T2, T3 and T4 form a cycle, and T5, T6, T7 and T8 form a cycle, which are respectively controlled by AT_mux1 to AT_mux4. The first end of each TFT switch is connected to a data line of the display panel, and the second end of a group of four TFT switches is commonly connected to the same test port, for example D1 or D2 in Figure 1 , so as to collect the signals of four data lines with one test port, thereby avoiding the problem that the one-to-one correspondence between the data lines and the test ports on the needle card cannot be realized due to the size and precision of the needle card. Figure 1 As can be seen from , the array test sub-circuit has the problems of insufficient space and difficult layout due to the large number of test leads.

[0025] Figure 2 To solve the above problems, an array test sub-circuit is provided in the embodiments of the present application, as shown in , which includes a first test signal line, a second test signal line, a plurality of test ports, and a plurality of test units connected to the first test signal line, the second test signal line and the plurality of test ports.

[0026] Each test unit includes three switching modules, and each switching module includes a control end, an input end, a first output end and a second output end. When the control end is configured as a first level signal, the first output end outputs a signal and the second output end does not output a signal. When the control end is configured as a second level signal, the first output end does not output a signal and the second output end outputs a signal. The first level signal and the second level signal are opposite in polarity.

[0027] The three switching modules include a first switching module, a second switching module and a third switching module; the control end of the first switching module and the control end of the second switching module are connected with the first test signal line, and the first output end and the second output end of the first switching module are respectively used for connecting the data lines of the display panel; the control end of the third switching module is connected with the second test signal line, the first output end of the third switching module is connected with the input end of the first switching module, and the second output end of the third switching module is connected with the input end of the second switching module; and the input end of the third switching module is connected with a test port.

[0028] Since the control end of each switching module is configured as the first level signal, the first output end outputs the signal, and the second output end does not output the signal, and the control end of each switching module is configured as the second level signal, the first output end does not output the signal, and the second output end outputs the signal, the first level signal and the second level signal are opposite in polarity. In a test period of the test process, the second test signal line is first configured as the first level signal, at this time, the first output end of the third switching module outputs the signal; in this state, the first test signal line is configured as the first level signal and the second level signal in turn, at this time, the first output end and the second output end of the first switching module output the signal in turn, that is, the test port can receive the signal of the data line connected with the first output end of the first switching module and the signal of the data line connected with the second output end of the first switching module in turn. Then, by configuring the second test signal line as the second level signal, at this time, the second output end of the third switching module outputs the signal; in this state, the first test signal line is configured as the first level signal and the second level signal in turn, at this time, the first output end and the second output end of the second switching module output the signal in turn, that is, the test port can receive the signal of the data line connected with the first output end of the second switching module and the signal of the data line connected with the second output end of the second switching module in turn.

[0029] In a test period, the test port can receive the signal of the data line connected with the first output end of the first switching module, the signal of the data line connected with the second output end of the first switching module, the signal of the data line connected with the first output end of the second switching module and the signal of the data line connected with the second output end of the second switching module in turn. The signal of the four data lines is collected by one test port, thereby avoiding the one-to-one correspondence relationship between the data lines and the test terminals on the needle card due to the influence of the size and accuracy of the needle card. And in the embodiment, the signal of the four data lines connected with a single test unit can be output from one test port in turn by two test signal lines (the first test signal line and the second test signal line), thereby realizing the short circuit test of the data lines in the display panel, reducing the number of test leads in the array test subcircuit and reducing the difficulty of layout.

[0030] In one example, each switching module includes two test switches, each of which includes a gate, a first pole and a second pole; the two test switches include a first test switch and a second test switch, wherein the first test switch is turned on under a first level signal and is not turned on under a second level signal; the second test switch is not turned on under the first level signal and is turned on under the second level signal; the first pole of the first test switch and the first pole of the second test switch are connected as an input terminal; the gate of the first test switch and the gate of the second test switch are connected as a control terminal; the second pole of the first test switch is a first output terminal; and the second pole of the second test switch is a second output terminal. Since the first level signal and the second level signal are opposite in polarity, if the first level signal is a positive level, the second level signal is a negative level; if the first level signal is a negative level, the second level signal is a positive level. Alternatively, if the test switch is a MOS tube, the first pole is a drain, and the second pole is a source.

[0031] Alternatively, the first test switch is an N-type switch tube, and the second test switch is a P-type switch tube. The N-type switch tube conducts electrons, that is, the N-type switch tube is turned on at a positive control terminal and is cut off at a negative control terminal; the P-type switch tube conducts holes, that is, the P-type switch tube is turned on at a negative control terminal and is cut off at a positive control terminal.

[0032] Since the first test switch is turned on under the first level signal and is not turned on under the second level signal; the second test switch is not turned on under the first level signal and is turned on under the second level signal. Therefore, if the first test switch is an N-type switch tube and the second test switch is a P-type switch tube, the first level signal is a positive level and the second level signal is a negative level; if the first test switch is a P-type switch tube and the second test switch is an N-type switch tube, the first level signal is a negative level and the second level signal is a positive level.

[0033] The circuit structure of the array test sub-circuit P2 is exemplarily described below with the first test switch being an N-type switch tube and the second test switch being a P-type switch tube as an example: the array test sub-circuit P2 includes a first test signal line AT_demux1, a second test signal line AT_demux2, two test units (a first test unit 100 and a second test unit 200), and two test ports D1 and D2.

[0034] The first test unit 100 includes a first switching module formed by connecting the drain of N1 and the drain of P1, a second switching module formed by connecting the drain of N2 and the drain of P2, and a third switching module formed by connecting the drain of N3 and the drain of P3.

[0035] The second test unit 200 includes a first switching module formed by connecting the first pole of N4 and the first pole of P4, a second switching module formed by connecting the first pole of N5 and the first pole of P5, and a third switching module formed by connecting the first pole of N6 and the first pole of P6.

[0036] The gate of N1, P1, N2, P2, N4, P4, N5, P5 is connected with the first test signal line AT_demux1, and the gate of N3, P3, N6, P6 is connected with the second test signal line AT_demux2.

[0037] The source of N3 is connected with the drain of N1 and P1, the source of P3 is connected with the drain of N2 and P2, the source of N6 is connected with the drain of N4 and P5, and the source of P6 is connected with the drain of N5 and P5.

[0038] The source of N1 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, the source of P1 is connected with the data line connecting the green sub-pixel, the source of N2 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, the source of P2 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, the source of N4 is connected with the data line connecting the green sub-pixel, the source of P4 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, the source of N5 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, and the source of P5 is connected with the data line connecting the green sub-pixel.

[0039] The four working states of the first test unit 100 in a test period of the array test sub-circuit are described in turn, taking the first test switch as an N-type switch tube, the second test switch as a P-type switch tube, the first level signal as a positive level, and the second level signal as a negative level as an example. Figure 3

[0040] It is worth noting that, in the embodiment, only eight data lines are listed, and the number of data lines in actual products is much more than eight. The accompanying drawings of the embodiment are only for illustration. Figure 5

[0041] (1) The first test signal line AT_demux1 inputs a first level signal (a positive level signal), and the second test signal line AT_demux2 inputs a first level signal (a positive level signal). At this time, N3 in the third switching module is turned on, and P3 is turned off; N1 in the first switching module is turned on, and P1 is turned off; N2 in the second switching module is turned on, and P2 is turned off, and the data line data1 is connected to the test port D1. Whether the data line data1 is short-circuited can be judged according to the signal of the test port D1.

[0042] ​​(2) the first test signal line AT_demux1 input is the second level signal (negative level signal), the second test signal line AT_demux2 input first level signal (positive level signal). At this time, the third switching module N3 is on, P3 is off; the first switching module N1 is off, P1 is on; the second switching module N2 is off, P2 is on, the data line data2 is connected to the test port D1, and whether the data line data2 is short-circuited can be judged according to the signal of the test port D1.

[0043] (3) the first test signal line AT_demux1 input is the first level signal (positive level signal), the second test signal line AT_demux2 input second level signal (negative level signal). At this time, the third switching module N3 is off, P3 is on; the first switching module N1 is on, P1 is off; the second switching module N2 is on, P2 is off, the data line data3 is connected to the test port D1, and whether the data line data3 is short-circuited can be judged according to the signal of the test port D1.

[0044] (4) the first test signal line AT_demux1 input is the second level signal (negative level signal), the second test signal line AT_demux2 input second level signal (negative level signal). At this time, the third switching module N3 is off, P3 is on; the first switching module N1 is off, P1 is on; the second switching module N2 is off, P2 is on, the data line data4 is connected to the test port D1, and whether the data line data4 is short-circuited can be judged according to the signal of the test port D1.

[0045] The test circuit of the display panel generally includes a panel test sub-circuit (CT test sub-circuit) and an array test sub-circuit (AT test sub-circuit). As shown in Figure 4 , the existing test circuit of the display panel includes a panel test sub-circuit P1 as shown in Figure 1 , therefore, the number of test leads is large, and there is a problem of insufficient space and difficult layout.

[0046] In view of this, the test circuit of the display panel is also given in the embodiment, as shown in Figure 5 , including a panel test sub-circuit P1 and an array test sub-circuit P2 as shown in Figure 2 , the specific structure of the panel test sub-circuit P1 in the existing test circuit as shown in Figure 4 , the structure of the panel test sub-circuit P1 in the test circuit as shown in Figure 5 in the embodiment is the same. Since the number of test leads in the array test sub-circuit P2 in the test circuit in the embodiment is less than that of the existing array test sub-circuit P2, the difficulty of layout of the display panel in the embodiment is reduced.

[0047] The panel test sub-circuit P1 in the embodiment includes a plurality of panel test switch units. The panel test switch units are connected with the data lines of the display panel. The panel test switch units can be specifically a switching device such as a thin film transistor (TFT) and the like, which is not limited herein. The panel test sub-circuit P1 is configured to control the panel test switch units to be turned on or turned off according to a plurality of received panel test control signals, so as to transmit a plurality of panel test signals.

[0048] The panel test control signals can be generated by the panel test control signal terminals and transmitted through the panel test control signal lines. The panel test signals can be generated by the panel test signal terminals and transmitted through the panel test signal lines. Specifically, the number of the panel test control signals can be a plurality, and the number of the panel test signals can be a plurality. Correspondingly, the number of the panel test control signal terminals can be a plurality, and the number of the panel test signal control lines can be a plurality. The number of the panel test signal terminals can be a plurality, and the number of the panel test signal lines can be a plurality. The number of the panel test control signals and the number of the panel test signals are not limited herein.

[0049] The panel test sub-circuit P1 in the embodiment will be described below by taking a specific circuit structure as an example. The panel test sub-circuit P1 includes three panel test control signal lines, namely D_SW1, D_SW2 and D_SW3. The panel test sub-circuit P1 includes three panel test signal lines, namely D_R, D_B and D_G. The panel test switch units specifically include K1 to K13. The array test switch units include T1 to T8. For the convenience of corresponding description, the signal lines and the signals generated by the signal lines are represented by the same reference signs, for example, the panel test control signal generated by the panel test control signal line D_SW1 is also represented by D_SW1.

[0050] The control terminals of the panel test switch units K1, K4, K6, K9 and K11 are connected with the panel test control signal line D_SW1. The control terminals of the panel test switch units K2, K5, K7, K10 and K12 are connected with the panel test control signal line D_SW2. The control terminals of the panel test switch units K3, K8 and K13 are connected with the panel test control signal line D_SW3.

[0051] The first terminals of the panel test switch units K1, K4, K6, K9 and K11 are connected with the panel test signal line D_R. The first terminals of the panel test switch units K2, K5, K7, K10 and K12 are connected with the panel test signal line D_B. The first terminals of the panel test switch units K3, K8 and K13 are connected with the panel test signal line D_G.

[0052] The second end of the panel test switch unit K1 is connected with a blue sub-pixel, the second end of the K2 is connected with a red sub-pixel, the second end of the K3 is connected with a green sub-pixel, the second end of the K4 is connected with a red sub-pixel, the second end of the K5 is connected with a blue sub-pixel, the second end of the K6 is connected with a blue sub-pixel, the second end of the K7 is connected with a red sub-pixel, the second end of the K8 is connected with a green sub-pixel, the second end of the K9 is connected with a red sub-pixel, the second end of the K10 is connected with a blue sub-pixel, the second end of the K11 is connected with a blue sub-pixel, the second end of the K12 is connected with a red sub-pixel, and the second end of the K13 is connected with a green sub-pixel.

[0053] It should be noted that, since the panel test sub-circuit P1 in the embodiment has the same circuit structure as the panel test sub-circuit P1 in the prior test circuit, the working principle of the panel test sub-circuit P1 in the embodiment will not be described again.

[0054] The array test sub-circuit in the embodiment includes a first test signal line, a second test signal line, a plurality of test ports, and a plurality of test units connecting the first test signal line, the second test signal line and the plurality of test ports.

[0055] Each test unit includes three switching modules, each switching module includes a control end, an input end, a first output end and a second output end, wherein when the control end is configured as a first level signal, the first output end outputs a signal and the second output end does not output a signal, when the control end is configured as a second level signal, the first output end does not output a signal and the second output end outputs a signal, and the first level signal and the second level signal are opposite in polarity.

[0056] The three switching modules include a first switching module, a second switching module and a third switching module; the control end of the first switching module and the control end of the second switching module are both connected with the first test signal line, and the first output end and the second output end of the first switching module are respectively connected with a data line; the control end of the third switching module is connected with the second test signal line, the first output end of the third switching module is connected with the input end of the first switching module, and the second output end of the third switching module is connected with the input end of the second switching module; and the input end of the third switching module is connected with one test port.

[0057] In the test process, the first test signal line is configured as the first level signal, and the first output end of the third switch module outputs a signal. In this state, the first test signal line is configured as the first level signal and the second level signal in sequence, and the first output end and the second output end of the first switch module output signals in sequence, that is, the test port can receive the signal of the data line connected to the first output end of the first switch module and the signal of the data line connected to the second output end of the first switch module in sequence. Then, the second test signal line is configured as the second level signal, and the second output end of the third switch module outputs a signal. In this state, the first test signal line is configured as the first level signal and the second level signal in sequence, and the first output end and the second output end of the second switch module output signals in sequence, that is, the test port can receive the signal of the data line connected to the first output end of the second switch module and the signal of the data line connected to the second output end of the second switch module in sequence.

[0058] In the test process, the test port can receive the signal of the data line connected to the first output end of the first switch module, the signal of the data line connected to the second output end of the first switch module, the signal of the data line connected to the first output end of the second switch module, and the signal of the data line connected to the second output end of the second switch module in sequence. The signals of the four data lines are collected by one test port, so that the one-to-one correspondence between the data lines and the test ports on the needle card cannot be realized due to the size and precision of the needle card. In the embodiment, the signals of the four data lines connected to a single test unit are controlled to be output from one test port in sequence by two test signal lines (the first test signal line and the second test signal line), so that the short circuit test of the data lines in the display panel is realized, the number of test leads in the array test subcircuit is reduced, and the layout difficulty is reduced.

[0059] In one example, each switching module includes two test switches, each of which includes a gate, a first pole and a second pole; the two test switches include a first test switch and a second test switch, wherein the first test switch is turned on under a first level signal and is not turned on under a second level signal; the second test switch is not turned on under the first level signal and is turned on under the second level signal; the first pole of the first test switch and the first pole of the second test switch are connected as an input terminal; the gate of the first test switch and the gate of the second test switch are connected as a control terminal; the second pole of the first test switch is a first output terminal; and the second pole of the second test switch is a second output terminal. Since the first level signal and the second level signal are opposite in polarity, if the first level signal is a positive level, the second level signal is a negative level; if the first level signal is a negative level, the second level signal is a positive level. Alternatively, if the test switch is a MOS tube, the first pole is a drain, and the second pole is a source.

[0060] Alternatively, the first test switch is an N-type switch tube, and the second test switch is a P-type switch tube. The N-type switch tube conducts electrons, that is, the N-type switch tube is turned on at a positive control terminal and is cut off at a negative control terminal; the P-type switch tube conducts holes, that is, the P-type switch tube is turned on at a negative control terminal and is cut off at a positive control terminal.

[0061] Since the first test switch is turned on under the first level signal and is not turned on under the second level signal; the second test switch is not turned on under the first level signal and is turned on under the second level signal. Therefore, if the first test switch is an N-type switch tube and the second test switch is a P-type switch tube, the first level signal is a positive level and the second level signal is a negative level; if the first test switch is a P-type switch tube and the second test switch is an N-type switch tube, the first level signal is a negative level and the second level signal is a positive level.

[0062] The circuit structure of the array test sub-circuit P2 will be described below with the first test switch being an N-type switch tube and the second test switch being a P-type switch tube as an example: the array test sub-circuit P2 includes a first test signal line AT_demux1, a second test signal line AT_demux2, two test units (a first test unit 100 and a second test unit 200), and two test ports D1 and D2.

[0063] The first test unit 100 includes a first switching module formed by connecting the drain of N1 and the drain of P1, a second switching module formed by connecting the drain of N2 and the drain of P2, and a third switching module formed by connecting the drain of N3 and the drain of P3.

[0064] The second test unit 200 includes a first switching module formed by connecting the first pole of N4 and the first pole of P4, a second switching module formed by connecting the first pole of N5 and the first pole of P5, and a third switching module formed by connecting the first pole of N6 and the first pole of P6.

[0065] The gate of N1, P1, N2, P2, N4, P4, N5, P5 is connected with the first test signal line AT_demux1, and the gate of N3, P3, N6, P6 is connected with the second test signal line AT_demux2.

[0066] The source of N3 is connected with the drain of N1 and P1, the source of P3 is connected with the drain of N2 and P2, the source of N6 is connected with the drain of N4 and P5, and the source of P6 is connected with the drain of N5 and P5.

[0067] The source of N1 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, the source of P1 is connected with the data line connecting the green sub-pixel, the source of N2 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, the source of P2 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, the source of N4 is connected with the data line connecting the green sub-pixel, the source of P4 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, the source of N5 is connected with the data line connecting the blue sub-pixel and the red sub-pixel, and the source of P5 is connected with the data line connecting the green sub-pixel.

[0068] It is worth mentioning that the embodiment of the present application only lists eight data lines, and the number of data lines in the actual product is much more than eight. The attached drawings of the embodiment are only for illustration. Figure 5 The following will be described in combination with the attached waveform diagram. Taking the first test switch as an N-type switch tube, the second test switch as a P-type switch tube, the first level signal as a positive level, and the second level signal as a negative level as an example, the four working states of the first test unit 100 of the array test sub-circuit in a test period are sequentially described.

[0069] Figure 3 (1) The first test signal line AT_demux1 inputs the first level signal (positive level signal), and the second test signal line AT_demux2 inputs the first level signal (positive level signal). At this time, N3 in the third switching module is turned on, and P3 is turned off; N1 in the first switching module is turned on, and P1 is turned off; N2 in the second switching module is turned on, and P2 is turned off, and the data line data1 is connected to the test port D1. Whether the data line data1 is short-circuited can be judged according to the signal of the test port D1.

[0070] (1) The first test signal line AT_demux1 inputs the first level signal (positive level signal), and the second test signal line AT_demux2 inputs the first level signal (positive level signal). At this time, N3 in the third switching module is turned on, and P3 is turned off; N1 in the first switching module is turned on, and P1 is turned off; N2 in the second switching module is turned on, and P2 is turned off, and the data line data1 is connected to the test port D1. Whether the data line data1 is short-circuited can be judged according to the signal of the test port D1.

[0071] ​(2) the first test signal line AT_demux1 inputs a second level signal (a negative level signal), and the second test signal line AT_demux2 inputs a first level signal (a positive level signal). At this time, N3 in the third switching module is turned on, and P3 is turned off; N1 in the first switching module is turned off, and P1 is turned on; N2 in the second switching module is turned off, and P2 is turned on, so that the data line data2 is connected to the test port D1, and whether the data line data2 is short-circuited can be judged according to the signal of the test port D1.

[0072] (3) the first test signal line AT_demux1 inputs a first level signal (a positive level signal), and the second test signal line AT_demux2 inputs a second level signal (a negative level signal). At this time, N3 in the third switching module is turned off, and P3 is turned on; N1 in the first switching module is turned on, and P1 is turned off; N2 in the second switching module is turned on, and P2 is turned off, so that the data line data3 is connected to the test port D1, and whether the data line data3 is short-circuited can be judged according to the signal of the test port D1.

[0073] (4) the first test signal line AT_demux1 inputs a second level signal (a negative level signal), and the second test signal line AT_demux2 inputs a second level signal (a negative level signal). At this time, N3 in the third switching module is turned off, and P3 is turned on; N1 in the first switching module is turned off, and P1 is turned on; N2 in the second switching module is turned off, and P2 is turned on, so that the data line data4 is connected to the test port D1, and whether the data line data4 is short-circuited can be judged according to the signal of the test port D1.

[0074] The embodiment of the application further provides a test method applied to the test circuit, as shown in the figure, the test method comprises the following contents. Figure 6

[0075] Step S11: in a test period, the first test signal line outputs a first test signal formed by a first level signal and a second level signal according to a first preset order, the second test signal line outputs a second test signal formed by the first level signal and the second level signal according to a second preset order, and the test unit is controlled.

[0076] Specifically, in a test period, the first test signal and the second test signal include four groups of level states according to the time sequence, and sequentially include: the first test signal is the first level, and the second test signal is the first level; the first test signal is the second level, and the second test signal is the first level; the first test signal is the first level, and the second test signal is the second level; and the first test signal is the second level, and the second test signal is the second level. Wherein, the polarity of the first test signal and the second test signal is opposite, for example: the first test signal is a positive level, and the second test signal is a negative level; or the second test signal is a positive level, and the first test signal is a negative level.​

[0077] Step S12: receiving the short-circuit judging signal outputted by the test port according to the panel test signals transmitted by the panel test sub-circuit, the short-circuit judging signal being used to judge whether there is a data line in the display panel which has a short-circuit.

[0078] Specifically, when the test signal is transmitted through the first test signal line and the second test signal line, the signal of the data line connecting the sub-pixels of different colors is inputted into the test port, at this time, the panel test sub-circuit provides the panel test signal for the data line of the sub-pixel of this color which is inputted into the test port. If the data line connecting the sub-pixel of this color is not short-circuited, the short-circuit judging signal outputted by the test port is the panel test signal; if the data line connecting the sub-pixel of this color is short-circuited, the short-circuit judging signal outputted by the test port is not the panel test signal.

[0079] Optionally, after receiving the short-circuit judging signal outputted by the test port according to the panel test signals transmitted by the panel test sub-circuit, the method further comprises: judging whether the amplitude of the short-circuit judging signal exceeds the preset signal standard amplitude range; if the short-circuit judging signal exceeds the preset signal standard amplitude range, it is determined that there is a data line which has a short-circuit. The preset signal standard amplitude range is determined according to the current panel test signal.

[0080] The embodiment of the present application further provides a display panel comprising the array test sub-circuit or the test circuit.

[0081] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. An array test sub-circuit, characterized in that, It includes a first test signal line, a second test signal line, multiple test ports, and multiple test units connecting the first test signal line, the second test signal line, and the multiple test ports; Each test unit includes three switching modules. Each switching module includes a control terminal, an input terminal, a first output terminal, and a second output terminal. When the control terminal is configured to a first level signal, the first output terminal outputs a signal, and the second output terminal does not output a signal. When the control terminal is configured to a second level signal, the first output terminal does not output a signal, and the second output terminal outputs a signal. The first level signal and the second level signal have opposite polarities. The three switching modules include a first switching module, a second switching module, and a third switching module; the control terminal of the first switching module and the control terminal of the second switching module are both connected to the first test signal line, and the first output terminal and the second output terminal of the first switching module are respectively used to connect to the data line of the display panel; the control terminal of the third switching module is connected to the second test signal line, the first output terminal of the third switching module is connected to the input terminal of the first switching module, and the second output terminal of the third switching module is connected to the input terminal of the second switching module; the input terminal of the third switching module is connected to a test port.

2. The array test sub-circuit according to claim 1, characterized in that, Each of the switching modules includes two test switches, each test switch including a gate, a first electrode, and a second electrode; the two test switches include a first test switch and a second test switch, wherein the first test switch is turned on under the first level signal and not turned on under the second level signal; the second test switch is not turned on under the first level signal and is turned on under the second level signal; The first terminal of the first test switch and the first terminal of the second test switch are connected to each other as the input terminal; the gate of the first test switch and the gate of the second test switch are the control terminal; the second terminal of the first test switch is the first output terminal; and the second terminal of the second test switch is the second output terminal.

3. The array test sub-circuit according to claim 2, characterized in that, The first test switch is an N-type switch, and the second test switch is a P-type switch.

4. A test circuit, characterized in that, include: The panel test sub-circuit includes a panel test switch unit, which is connected to the data line of the display panel. The panel test sub-circuit is used to control the panel test switch unit to be turned on or off according to multiple received panel test control signals, so as to transmit multiple panel test signals. The array test sub-circuit includes a first test signal line, a second test signal line, multiple test ports, and multiple test units connecting the first test signal line, the second test signal line, and the multiple test ports; Each test unit includes three switching modules. Each switching module includes a control terminal, an input terminal, a first output terminal, and a second output terminal. When the control terminal is configured to a first level signal, the first output terminal outputs a signal, and the second output terminal does not output a signal. When the control terminal is configured to a second level signal, the first output terminal does not output a signal, and the second output terminal outputs a signal. The first level signal and the second level signal have opposite polarities. The three switching modules include a first switching module, a second switching module, and a third switching module; the control terminal of the first switching module and the control terminal of the second switching module are both connected to the first test signal line, and the first output terminal and the second output terminal of the first switching module are respectively connected to the data line; the control terminal of the third switching module is connected to the second test signal line, the first output terminal of the third switching module is connected to the input terminal of the first switching module, and the second output terminal of the third switching module is connected to the input terminal of the second switching module; the input terminal of the third switching module is connected to a test port.

5. The test circuit according to claim 4, characterized in that, Each of the switching modules includes two test switches, each test switch including a gate, a first electrode, and a second electrode; the two test switches include a first test switch and a second test switch, wherein the first test switch is turned on under the first level signal and not turned on under the second level signal; the second test switch is not turned on under the first level signal and is turned on under the second level signal; The first terminal of the first test switch and the first terminal of the second test switch are connected to each other as the input terminal; the gate of the first test switch and the gate of the second test switch are the control terminal; the second terminal of the first test switch is the first output terminal; and the second terminal of the second test switch is the second output terminal.

6. The test circuit according to claim 5, characterized in that, The first test switch is an N-type switch, and the second test switch is a P-type switch.

7. A testing method, characterized in that, The test method, applied to the test circuit as described in any one of claims 4 to 6, comprises: Within a test cycle, the first test signal line outputs a first test signal formed by the first level signal and the second level signal in a first preset order, and the second test signal line outputs a second test signal formed by the first level signal and the second level signal in a second preset order to control the test unit; The test port outputs a short-circuit judgment signal based on the plurality of panel test signals transmitted by the panel test sub-circuit. The short-circuit judgment signal is used to determine whether there is a short circuit in the data line within the display panel.

8. The test method according to claim 7, characterized in that, Within one test cycle, the first test signal and the second test signal, in chronological order, comprise four sets of level states, which are as follows: The first test signal is at a first level, and the second test signal is at a first level; The first test signal is at a second level, and the second test signal is at a first level; The first test signal is at a first level, and the second test signal is at a second level; The first test signal is at the second level, and the second test signal is at the second level.

9. The test method according to claim 7, characterized in that, After receiving the short-circuit judgment signal output from the test port based on the plurality of panel test signals transmitted by the panel test sub-circuit, the method further includes: Determine whether the amplitude of the short-circuit judgment signal exceeds the preset standard amplitude range; If the short-circuit detection signal exceeds the preset signal standard amplitude range, it is determined that a short circuit has occurred on the data line.

10. A display panel, characterized in that, It includes the array test sub-circuit as described in any one of claims 1 to 3, or the test circuit as described in any one of claims 4 to 6.

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