A MOM capacitor

Abstract

Disclosed is a MOM capacitor, comprising: a substrate; a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in layers on the substrate, the first conductive layer and the fourth conductive layer each being one pole plate, the second conductive layer comprising a plurality of first electrode strips and second electrode strips spaced apart from each other, the third conductive layer comprising a plurality of third electrode strips and fourth electrode strips spaced apart from each other; and a plurality of through holes for electrically connecting the first conductive layer, the first electrode strips of the second conductive layer, the third electrode strips of the third conductive layer and the fourth conductive layer to form a first electrode, and for electrically connecting the second electrode strips of the second conductive layer and the fourth electrode strips of the third conductive layer to form a second electrode; wherein the plurality of second electrode strips are distributed in the same direction, and each second electrode strip surrounds the first electrode strips; the fourth electrode strips are one pole plate, and the plurality of third electrode strips surround the fourth electrode strips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a MOM capacitor. Background Technology

[0002] In the field of capacitor array structures, capacitors are fundamental and crucial components. Metal-Oxide-Metal (MOM) capacitors and Metal-Insulator-Metal (MIM) capacitors are two common types. MIM capacitors use metal patterns located in the same or different layers to form the same electrode; their capacitance primarily consists of the capacitance formed by the different conductor layers. MOM capacitors, on the other hand, use metal patterns in the same layer to simultaneously form two electrodes of opposite polarity, thus their capacitance can include the capacitance formed by the same conductor layer.

[0003] refer to Figure 1 As shown, the MOM capacitor 100 includes a substrate 101 and a conductor layer M1. The conductor layer M1 includes a first electrode 102 and a second electrode 103 with two comb-shaped structures. The first and second electrodes have opposite polarities. The electrode strips contained in each of the two comb-shaped structures are arranged in an alternating manner, thereby forming a capacitance between the electrode strips of different electrodes. The capacitance value of the capacitor 100 is equal to the sum of the capacitances formed by these electrode strips. This design of the MOM capacitor helps to increase the capacitance per unit area, thereby helping to reduce the area occupied by the MOM capacitor and thus helping to improve the integration density of semiconductor circuits. To increase the capacitance value, Figure 1 The MOM capacitor shown can also be designed in a stacked manner, so that the total capacitance is mainly equal to the sum of the capacitance in the same layer, the capacitance between different layers, and the capacitance between each electrode strip and the through hole.

[0004] However, due to design constraints, the spacing between the horizontal traces and the vertical traces of the electrode strip are different, which limits the wiring of the electrode strip. Summary of the Invention

[0005] In view of the above problems, the object of the present invention is to provide a MOM capacitor to improve the utilization rate of capacitor area.

[0006] This invention provides a MOM capacitor, comprising:

[0007] Substrate;

[0008] A first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer are stacked on the substrate. The first conductive layer and the fourth conductive layer are each an electrode plate. The second conductive layer includes a plurality of spaced-apart first and second electrode strips. The third conductive layer includes a plurality of spaced-apart third and fourth electrode strips.

[0009] Multiple through holes are used to electrically connect the first conductive layer, the first electrode strip of the second conductive layer, the third electrode strip of the third conductive layer and the fourth conductive layer to form a first electrode, and to electrically connect the second electrode strip of the second conductive layer and the fourth electrode strip of the third conductive layer to form a second electrode;

[0010] Among them, multiple second electrode strips are distributed in the same direction, and each second electrode strip is surrounded by a first electrode strip; the fourth electrode strip is an electrode plate, and multiple third electrode strips surround the fourth electrode strip.

[0011] Preferably, the plurality of second electrode strips are independent finger electrodes.

[0012] Preferably, the plurality of first electrode strips are a plurality of rectangular frames connected together, and each rectangular frame has a second electrode strip separated from the rectangular frame.

[0013] Preferably, the fourth electrode strip further includes finger-shaped electrode strips connected to the electrode plate around its perimeter.

[0014] Preferably, the electrode plate is rectangular, and the finger electrode strips are located on the four sides of the electrode plate, perpendicular to the four sides of the electrode plate, and connected to the four sides of the electrode plate.

[0015] Preferably, the third electrode strip is a rectangular frame with openings on its four sides.

[0016] Preferably, the projection of the second electrode strip onto the third conductive layer is located within the region of the fourth electrode strip.

[0017] Preferably, the second conductive layer comprises any number of layers, which are stacked and located between the first conductive layer and the third conductive layer.

[0018] Preferably, the second electrode strips in each second conductive layer are arranged in the same first direction.

[0019] Preferably, the second electrode strips in the same second conductive layer are arranged in the same direction, and the second electrode strips in different second conductive layers are arranged in different directions.

[0020] Preferably, the first electrode strips of adjacent second conductive layers are electrically connected; the second electrode strips of adjacent second conductive layers are electrically connected.

[0021] Preferably, the substrate includes a second conductive layer and a third conductive layer of arbitrary number, wherein the number of second and third conductive layers in any layer is the same, and the second and third conductive layers are alternately stacked along a direction perpendicular to the substrate.

[0022] Preferably, the system further includes a virtual layer located between the substrate and the first conductive layer. The virtual layer comprises, from bottom to top, a well layer, an active layer, a virtual active layer, and a virtual gate layer, wherein the well layer and the active layer are connected by a contact hole.

[0023] Preferably, the projections of the first conductive layer and the second conductive layer onto the substrate fall into the region where the well layer is located.

[0024] The MOM capacitor provided by this invention utilizes two conductive layers. One conductive layer includes multiple electrodes distributed in the same direction, while the other conductive layer has an electrode strip that is a single electrode plate, covering the electrodes distributed in the same direction. The electrodes are distributed in the same direction, which eliminates the limitation of crisscrossing wiring and simplifies the wiring of the electrodes. At the same time, using a single electrode plate as the electrode increases the capacitance area.

[0025] Furthermore, the MOM capacitor provided in this embodiment of the invention uses the electrode strip of the first electrode to protect the electrode strip of the second electrode, thereby introducing parasitic capacitance only between the power supply ground and the first electrode, and the parasitic capacitance between the second electrode and the power supply ground can be basically ignored.

[0026] In a preferred embodiment, the overall capacitance of the MOM capacitor is increased by using a fourth conductive layer and a second conductive layer with a stacked design.

[0027] In a preferred embodiment, a well layer, an active layer, a virtual active layer, and a virtual gate layer are disposed within the semiconductor substrate to block noise from the semiconductor substrate, thereby preventing noise from entering the MOM capacitor. Attached Figure Description

[0028] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0029] Figure 1 A three-dimensional structural schematic diagram of a prior art MOM capacitor is shown;

[0030] Figure 2 A three-dimensional structural schematic diagram of the MOM capacitor according to the first embodiment of the present invention is shown;

[0031] Figure 3 A top view of the second conductive layer according to a first embodiment of the present invention is shown;

[0032] Figure 4 A top view of the third conductive layer according to a first embodiment of the present invention is shown;

[0033] Figure 5 A three-dimensional structural schematic diagram of the MOM capacitor according to the second embodiment of the present invention is shown;

[0034] Figure 6 A three-dimensional structural schematic diagram of the MOM capacitor according to the third embodiment of the present invention is shown;

[0035] Figure 7 A cross-sectional view of the MOM capacitor according to the fourth embodiment of the present invention is shown. Detailed Implementation

[0036] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0037] This invention can be presented in various forms, some of which will be described below.

[0038] Figure 2 A three-dimensional structural schematic diagram of the MOM capacitor 200 according to the first embodiment of the present invention is shown; as follows: Figure 2 As shown, the MOM capacitor 200 includes a substrate 201, multiple conductive layers 202 located on the substrate 201, and insulating layers filled between the conductive layers 202 and between the electrode strips of the same conductive layer 202. The conductive layers 202 include a first conductive layer 21, a second conductive layer 22, a third conductive layer 23, and a fourth conductive layer 24.

[0039] Each of the first conductive layer 21 to the fourth conductive layer 24 can be made of various metals. The first conductive layer 21 is located above the substrate 201. The first conductive layer 21 and the fourth conductive layer 24 are a metal electrode plate without any openings or perforations. A second conductive layer 22 is formed above the first conductive layer 21, a third conductive layer 23 is formed above the second conductive layer 22, and a fourth conductive layer 24 is formed above the third conductive layer 23. The second conductive layer 22 and the third conductive layer 23 include multiple electrode strips; a portion of the electrode strips of the second conductive layer 22 are electrically connected to the first conductive layer 21 via through-holes 25; a portion of the electrode strips of the third conductive layer 23 are electrically connected to the fourth conductive layer 24 via through-holes 25; and the remaining portion of the electrode strips of the second conductive layer 22 and the remaining portion of the electrode strips of the third conductive layer 23 are electrically connected. In the MOM capacitor 200, a first conductive layer 21, a fourth conductive layer 24, a portion of an electrode strip of a second conductive layer 22 electrically connected to the first conductive layer 21, and a portion of an electrode strip of a third conductive layer 23 electrically connected to the fourth conductive layer 24 serve as the first electrode. The remaining portion of the electrode strips of the second conductive layer and the remaining portion of the electrode strips of the third conductive layer serve as the second electrode. The first electrode and the second electrode have opposite polarities, thereby forming a capacitor between the first electrode and the second electrode.

[0040] Figure 3 A top view of the second conductive layer according to a first embodiment of the present invention is shown, as follows: Figure 3 As shown, the second conductive layer 22 includes a first electrode strip 221 and a second electrode strip 222 spaced apart from each other. The second electrode strip 222 consists of a plurality of independent finger electrodes, which are distributed in the same direction in the plane of the second conductive layer 22. Each second electrode strip 222 is surrounded by the first electrode strip 221.

[0041] In this embodiment, the second conductive layer 22 includes two finger-shaped second electrode strips 222, which are distributed along a first direction in the plane of the second conductive layer 22. The first electrode strip 221 is a plurality of rectangular frames connected together, and a second electrode strip 222 is distributed inside the first electrode strip 221 of each rectangular frame, so that each second electrode strip 222 is surrounded by the first electrode strip 221.

[0042] Figure 4 A top view of the third conductive layer according to a first embodiment of the present invention is shown, as follows: Figure 4 As shown, the third conductive layer 23 includes a third electrode strip 231 and a fourth electrode strip 232 spaced apart from each other. The fourth electrode strip 232 is a single piece of metal plate, and the third electrode strip 231 surrounds the fourth electrode strip 232.

[0043] In this embodiment, the fourth electrode strip 232 includes a rectangular fourth electrode strip 2321 and a plurality of finger-shaped fourth electrode strips 2322; wherein, the plurality of finger-shaped fourth electrode strips 2322 are located on the four sides of the rectangular fourth electrode strip 2321, perpendicular to the four sides of the rectangular fourth electrode strip 2321, and connected to the four sides of the rectangular fourth electrode strip 2321, and the plurality of finger-shaped fourth electrode strips 2322 extend from the four sides of the rectangular fourth electrode strip 2321 in a direction away from the rectangular fourth electrode strip 2321.

[0044] The third electrode strip 231 is a rectangular frame surrounding the fourth electrode strip 232. The four sides of the rectangular frame have openings 2311. The finger-shaped fourth electrode strip 2322 passes through the openings 2311 and extends to the outside of the third electrode strip 231, connecting with the adjacent MOM capacitor.

[0045] The projection of the second electrode strip 222 onto the third conductive layer 23 is located within the area of ​​the fourth electrode strip 232, that is, the fourth electrode strip 232 covers the entire projection of the second electrode strip 122 onto the third conductive layer 23.

[0046] The first electrode strip 221 of the second conductive layer 22 is connected to the first conductive layer 21 through the first through hole 251, the third electrode strip 231 of the third conductive layer 23 is connected to the fourth conductive layer 24 through the second through hole 252, each second electrode strip 222 of the second conductive layer 22 is connected to the fourth electrode strip 232 of the third conductive layer through the third through hole 253; the first electrode strip 221 of the second conductive layer 22 is connected to the third electrode strip 231 of the third conductive layer through the fourth through hole 254.

[0047] In the MOM capacitor 200, the first electrode consists of the first conductive layer 21, the fourth conductive layer 24, the first electrode strip 221 electrically connected to the first conductive layer 21, and the third electrode strip 231 electrically connected to the fourth conductive layer 24. The remaining second electrode strip 222 of the second conductive layer 22 and the remaining fourth electrode strip 232 of the third conductive layer 23 serve as the second electrode. The first and second electrodes have opposite polarities, thereby forming a capacitance between the first and second electrodes.

[0048] For ease of explanation, Figure 3 and Figure 4 A specific layout design is shown, but the implementation of the invention is not limited to this layout design. For example, using... Figure 3The layout design shown is intended to illustrate the core concept that "the electrode strips serving as the second electrode in the second conductive layer are distributed in the same direction, and the electrode strips serving as the second electrode in the third conductive layer are a single electrode plate." In other layout designs, any number of first and second electrode strips can be used, as long as the above core concept is satisfied, the same or similar effects can be produced.

[0049] In this embodiment, two conductive layers cooperate to form a first electrode and a second electrode. One conductive layer includes multiple electrodes distributed in the same direction, and the electrode strip in the other conductive layer is a whole electrode plate, which covers the electrodes distributed in the same direction. The electrodes are distributed in the same direction, which removes the restriction of crisscrossing wiring and makes the wiring of the electrodes relatively simple. At the same time, using a whole electrode plate as an electrode increases the capacitance area.

[0050] Furthermore, in this embodiment, since the first conductive layer and the third conductive layer have a planar shape and are used as the first electrode, only the first electrode faces the power ground. Therefore, parasitic capacitance is only introduced between the power ground and the first electrode facing it. The electrode strip used as the second electrode is surrounded by the electrode strip used as the first electrode, so the parasitic capacitance between the second electrode and the power ground is essentially negligible. Therefore, in this embodiment, the parasitic capacitance between the second electrode and the power ground can be significantly reduced. Moreover, although increasing the surface area of ​​the first conductive layer increases the parasitic capacitance between the first electrode and the power ground, it further reduces the parasitic capacitance between the second electrode and the power ground.

[0051] Of course, the surface area of ​​the first conductive layer can also be appropriately reduced to further reduce costs. For example, the surface area of ​​the first conductive layer can be reduced just enough to shield the ends of the electrode strips used as the second electrode in the second conductive layer. Although the parasitic capacitance between the second electrode and the power supply ground may increase, the increase is within a tolerable range. Generally, the parasitic capacitance should be less than 5% of the capacitance between the first and second electrodes. In summary, although the MOM capacitor provided in this embodiment has parasitic capacitance between the first electrode and the power supply ground, the parasitic capacitance between the second electrode and the power supply ground is very small, even close to zero, because the second electrode is almost completely protected by the first electrode.

[0052] Figure 5 A three-dimensional structural schematic diagram of the MOM capacitor according to a second embodiment of the present invention is shown; as follows: Figure 5As shown, compared to the first embodiment, the conductive layer 202 of the MOM capacitor in this embodiment is provided with an arbitrary number of second conductive layers 22, which are stacked and located between the first conductive layer 21 and the third conductive layer 23. In this embodiment, the overall capacitance value of the MOM capacitor is increased by the stacked design of the second conductive layers 22. However, the core idea of ​​this layout design is essentially the same as the aforementioned layout design.

[0053] Specifically, the first electrode strip 221 and the second electrode strip 222 in each second conductive layer 22 have the same shape. The distribution direction of the second electrode strips 222 in different second conductive layers 22 can be the same or different. For example, in this embodiment, the second electrode strips 222 in each second conductive layer 22 are arranged in the same first direction. In other embodiments, the arrangement direction of the second electrode strips 222 in the same second conductive layer 22 is the same, and the second electrode strips 222 in different second conductive layers 22 can be arranged in different directions (e.g., mutually perpendicular directions).

[0054] The first electrode strips 221 of adjacent second conductive layers 22 are electrically connected to each other, the first electrode strips 221 of the second conductive layer adjacent to the first conductive layer 21 are electrically connected to the first conductive layer 21, the first electrode strips 221 of the second conductive layer 22 adjacent to the third conductive layer 23 are electrically connected to the third electrode strips 231 of the third conductive layer 23; the second electrode strips 222 of adjacent second conductive layers 22 are electrically connected to each other, and the second electrode strips 222 of the second conductive layer 22 adjacent to the third conductive layer 23 are electrically connected to the fourth electrode strips 232 of the third conductive layer 23.

[0055] Figure 6 A three-dimensional structural schematic diagram of the MOM capacitor according to the third embodiment of the present invention is shown; as follows: Figure 6 As shown, compared with the first embodiment, the conductive layer 202 of the MOM capacitor in this embodiment can be provided with any number of second conductive layers 22 and third conductive layers 23. The number of second conductive layers 22 and third conductive layers 23 is the same, and the second conductive layers 22 and third conductive layers 23 are alternately stacked along the direction perpendicular to the substrate.

[0056] Figure 6 In this design, two sets of second conductive layers 22 and third conductive layers 23 are disposed in a direction perpendicular to the substrate, and the second and third conductive layers 23 are alternately stacked along the direction perpendicular to the substrate. In this embodiment, the overall capacitance value of the MOM capacitor is increased by using multiple sets of second conductive layers 22 and third conductive layers 23 in a stacked design. However, the core idea of ​​this layout design is essentially the same as the aforementioned layout design.

[0057] Figure 7A cross-sectional view of a MOM capacitor according to a fourth embodiment of the present invention is shown. Figure 7 As shown, compared with the first embodiment, the MOM capacitor shown in this embodiment also includes a virtual layer located between the substrate 201 and the first conductive layer 21. The virtual layer includes a well layer 401, an active layer 402, a virtual active layer 403 and a virtual gate layer 404 from bottom to top. The well layer 401 and the active layer 402 are connected by a contact hole 405.

[0058] In the semiconductor device of this embodiment, the well layer 401 and the active layer 402 can block noise from the semiconductor substrate 201, thereby preventing noise from entering the MOM capacitor.

[0059] One approach is to adjust the design so that the projection of the MOM capacitor onto the upper surface of the semiconductor substrate 201 falls entirely within the region containing the well layer 401. This design can better prevent noise from the semiconductor substrate 201 from entering the MOM capacitor.

[0060] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A MOM capacitor, characterized in that, include: Substrate; A first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer are stacked on the substrate. The first conductive layer and the fourth conductive layer are each an electrode plate. The second conductive layer includes a plurality of first electrode strips and second electrode strips spaced apart from each other. The third conductive layer includes a plurality of third electrode strips and fourth electrode strips spaced apart from each other. as well as Multiple through holes are used to electrically connect the first conductive layer, the first electrode strip of the second conductive layer, the third electrode strip of the third conductive layer and the fourth conductive layer to form a first electrode, and to electrically connect the second electrode strip of the second conductive layer and the fourth electrode strip of the third conductive layer to form a second electrode; Among them, multiple second electrode strips are distributed in the same direction, and each second electrode strip is surrounded by a first electrode strip; the fourth electrode strip is an electrode plate, and multiple third electrode strips surround the fourth electrode strip. It also includes a virtual layer located between the substrate and the first conductive layer. The virtual layer includes, from bottom to top, a well layer, an active layer, a virtual active layer, and a virtual gate layer, wherein the well layer and the active layer are connected by a contact hole.

2. The MOM capacitor according to claim 1, characterized in that, Multiple second electrode strips are independent finger electrodes.

3. The MOM capacitor according to claim 1, characterized in that, The multiple first electrode strips are multiple rectangular frames connected together, and each rectangular frame contains a second electrode strip separated from the rectangular frame.

4. The MOM capacitor according to claim 1, characterized in that, The fourth electrode strip also includes finger-shaped electrode strips connected to the electrode plate around its perimeter.

5. The MOM capacitor according to claim 4, characterized in that, The electrode plate is rectangular, and the finger electrode strips are located on the four sides of the electrode plate, perpendicular to the four sides of the electrode plate, and connected to the four sides of the electrode plate.

6. The MOM capacitor according to claim 1, characterized in that, The third electrode strip is a rectangular frame with openings on its four sides.

7. The MOM capacitor according to claim 1, characterized in that, The projection of the second electrode strip onto the third conductive layer lies within the region of the fourth electrode strip.

8. The MOM capacitor according to claim 1, characterized in that, The second conductive layer includes any number of layers, which are stacked and located between the first conductive layer and the third conductive layer.

9. The MOM capacitor according to claim 8, characterized in that, In each second conductive layer, the second electrode strips are arranged in the same first direction.

10. The MOM capacitor according to claim 8, characterized in that, The second electrode strips in the same second conductive layer are arranged in the same direction, while the second electrode strips in different second conductive layers are arranged in different directions.

11. The MOM capacitor according to claim 8, characterized in that, The first electrode strips of adjacent second conductive layers are electrically connected; the second electrode strips of adjacent second conductive layers are electrically connected.

12. The MOM capacitor according to claim 1, characterized in that, It includes a second conductive layer and a third conductive layer of arbitrary number, wherein the number of second and third conductive layers in any layer is the same, and the second and third conductive layers are alternately stacked along a direction perpendicular to the substrate.

13. The MOM capacitor according to claim 1, characterized in that, The projections of the first conductive layer and the second conductive layer onto the substrate fall into the region where the well layer is located.

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