An underfill method for forming a three-dimensional stacked chip structure

Abstract

The application discloses a kind of bottom filling methods of forming three-dimensional stacked chip structure, for the single chip of size difference little that has been sliced, through temporary bonding process, to be filled product is fixed between upper and lower two slides, make out that glue area, after glue solidification, again unbonding removes temporary bonding slide, slide plays the role of bearing glue and forms a capillary channel, temporary bonding material can be well connected and protected between product and slide, it will not cause glue to flow into product and slide between and contaminate product surface, and after glue solidification, by unbonding process, temporary bonding material and slide can be conveniently removed.The disclosure of the method is beneficial to reduce three-dimensional integration size, improve integration, the method does not need the use of multiple filling glue, and the process is simple.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics technology, and particularly relates to a bottom filling method for forming a three-dimensional stacked chip structure. BACKGROUND

[0002] Multi-chip integration is developing from two-dimensional structure to three-dimensional structure, and the filling process is the key to ensuring the reliability of three-dimensional stacked products. In the non-fluidity bottom filling process, the glue needs to have a soldering function, and the solidification of the glue needs to be later than the formation of the solder ball, which has many limiting factors, has a higher thermal expansion coefficient and a low fracture toughness, and is prone to cause fracture failure between the solder joint, the chip, the substrate and the glue. Therefore, the commonly used filling process is still the fluidity bottom filling process under capillary action. However, due to the increasing integration and the continuous reduction in size of multi-layer stacked products, the size of each layer is often the same size when designing, and there is no reserved space for filling glue, so when filling, the glue will seep into the space between the product bottom and the bearing platform, which makes it difficult to separate the product and the bearing platform and the product is contaminated and scrapped; in addition, the traditional bottom filling glue has small viscosity and large fluidity, so the glue climbing height is effective, and the glue cannot spontaneously flow to the higher layer gap under the action of capillary flow, which limits the application of the fluidity bottom filling process in multi-layer stacked products. In summary, how to better fill is the key to the three-dimensional stacking of single-chip with small size difference.

[0003] A method for forming a multi-layer stacked structure is described in US patent US8138023B2, which is specifically a packaging method for 3D multi-layer stacked products by using the processes of stacking, filling and cutting alternately, the bottom chip has sufficient space for glue application, and the bottom chip is used as a glue application bearing platform during glue application; in addition, different viscosity of the filling glue is also needed in the process to meet the filling process requirements of different positions, and the structure 6 is difficult to realize, and there are multiple interfaces between the structure 2 and the structure 6 in the structure, which affects the reliability. However, for the chips that have been cut into single chips, the three-dimensional structure forming method described in the patent US8138023B2 is no longer applicable when the structure 2 described in the above patent cannot be formed. SUMMARY

[0004] The present application aims to overcome the shortcomings of the prior art, and provides a bottom filling method for forming a three-dimensional stacked chip structure, to solve the problem that there is no sufficient reserved space for glue application in the multi-layer stacked product, and the glue easily flows into the space between the product and the carrier and contaminates the surface of the product.

[0005] To achieve the above-mentioned purpose, the following technical solutions are adopted in the present application:

[0006] A kind of bottom filling method for forming three-dimensional stacked chip structure, comprising the following steps:

[0007] Step 1, stacked chip, interconnect bonding is carried out to adjacent chips, and stacked bonded chip structure is formed;

[0008] Step 2, temporary bonding material is coated on temporary bonding carrier, and stacked bonded chip structure is placed on temporary bonding carrier, and temporary bonding material is formed between temporary bonding carrier and stacked bonded chip structure, process stacked structure one;

[0009] Step 3, external force is input to process stacked structure one, and process stacked structure two is formed;

[0010] Step 4, for process stacked structure two, bottom filling glue is applied on temporary bonding carrier, and after glue flows and fills the gap between chips, bottom filling solidification is carried out, and process stacked structure three is formed;

[0011] Step 5, process stacked structure three is debonded to remove temporary bonding carrier, and temporary bonding material is removed by solution immersion.

[0012] Further improvement of the application is that:

[0013] Preferably, in step 1, pick-and-place machine, flip-chip bonder or die bonder is used to complete stacked chip by repeating "pick-position-paste" process.

[0014] Preferably, in step 1, all chips are of the same shape, and the length of lower chip is greater than or equal to the length of upper chip, and the width of lower chip is greater than or equal to the width of upper chip.

[0015] Preferably, the difference between the length of lower chip and upper chip is in the range of 0-1.5mm, and the difference between the width of lower chip and upper chip is in the range of 0-1.5mm.

[0016] Preferably, in step 1, interconnect bonding between adjacent chips is completed by inputting external force.

[0017] Preferably, in step 2, when the height of stacked bonded chip structure is greater than 1.2mm, temporary bonding material is coated on two temporary bonding carriers, and stacked bonded chip structure is placed between the two temporary bonding carriers.

[0018] In step 4, bottom filling glue is applied on lower temporary bonding carrier.

[0019] Preferably, in step 5, debonding is carried out by inputting light, heat, electricity, force or by solution immersion.

[0020] Preferably, in step 5, temporary bonding material is removed by soaking limonene.

[0021] Preferably, after step 5, a dicing process is performed to remove the excess filling material.

[0022] Preferably, the difference between the long side of the temporary bonding carrier and the bottom layer chip is ≥1mm, and the difference between the width sides is ≥1mm.

[0023] Compared with the prior art, the present application has the following beneficial effects:

[0024] The application discloses a bottom filling method for forming a three-dimensional stacked chip structure. For single chips which have been diced and have little size difference, a temporary bonding process is used to fix the filling products between upper and lower carriers, a glue applying area is made, and after the glue is solidified, the temporary bonding carrier is removed by debonding. The carrier plays a role of bearing the glue and forms a capillary channel. The temporary bonding material can well connect and protect the products and the carrier, and the glue cannot flow into the space between the products and the carrier to contaminate the product surface. After the glue is solidified, the temporary bonding material and the carrier can be conveniently removed by the debonding process. The disclosure of the method is beneficial to reducing the three-dimensional integration size and improving the integration degree. The method does not need to use multiple filling glues, and the process is simple.

[0025] Further, the method of the application is suitable for the case that all the chips have the same size or the size difference between the edge of the lower chip and the upper chip is small, so that the glue climbing operation is facilitated.

[0026] Further, the interconnection bonding between adjacent chips is completed by hot press welding, the problem of solder joint remelting caused by repeated reflow is avoided, and the process time is saved by one reflow.

[0027] Further, the temporary bonding carrier is cut and then bonded (by using the temporary bonding carrier, no blank area needs to be reserved on the stacked structure), so that the size of the stacked structure is small, which is beneficial to the miniaturization of products. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a cross-sectional view of the first layer to the fifth layer of chips after dicing;

[0029] Figure 2 is a cross-sectional view of the three-dimensional structure of the five-layer chip stack after stacking;

[0030] Figure 3 is a schematic view of the five-layer chip stack three-dimensional structure with a temporary bonding carrier;

[0031] Figure 4 is a schematic view of the bottom filling of the three-dimensional stack structure;

[0032] Figure 5 is a schematic view of the three-dimensional stack structure after debonding the temporary bonding.

[0033] Figure 6 A schematic view of a three-dimensional stacked structure after dicing;

[0034] Figure 7 A flow chart of an embodiment;

[0035] Figure 8 A schematic view of a cross section of three chips to be stacked in Example 2;

[0036] Figure 9 A top view of a size comparison of three chips to be stacked in Example 2;

[0037] Figure 10 A schematic view of a cross section of temporary bonding of a three-layer stacked structure and a carrier in Example 2;

[0038] Figure 11 A top view of temporary bonding of a three-layer stacked structure and a carrier in Example 2;

[0039] Figure 12 A schematic view of filling of a three-layer stacked structure with a carrier glass in Example 2;

[0040] Figure 13 A schematic view of a three-layer stacked structure after releasing temporary bonding in Example 2;

[0041] Wherein, 1. Substrate; 2. Interconnection bump; 3. TSV (Through Silicon Via); 4. Temporary bonding material; 5. Temporary bonding carrier; 6. Underfill glue; 100-1. Chip one; 100-2. Chip two; 100-3. Chip three; 100-4. Chip four; 100-5. Chip five; 110-1. Chip six; 110-2. Chip seven; 110-3. Chip eight. DETAILED DESCRIPTION

[0042] The application will be further described in conjunction with the accompanying drawings:

[0043] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application; the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance; in addition, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0044] The present application discloses a bottom filling method for forming a three-dimensional stacked chip structure, which is a bottom filling method for forming a three-dimensional stacked structure for single chips with little size difference after dicing. The steps of the method mainly include:

[0045] Step 1, as shown in Figure 1 , the pick-and-place steps are repeated four times by using a chip mounter, a flip-chip bonder or a die bonder, the interconnection bonding is completed by heat pressing or reflow or thermal ultrasonic or electric induction or laser heating process, and a stacked bonding chip structure as shown in Figure 2 is obtained; in the stacked chips, all the chips have the same shape, and in the adjacent chips, the length of the lower chip is greater than or equal to the length of the upper chip, and the width of the lower chip is greater than or equal to the width of the upper chip, so that the edge of the final structure is stepped, or all the edges of the chips are on the same plane;

[0046] In this step, the positions of the interconnection bumps 2 of all the chips correspond to each other, and the positions of the TSV through holes can be adjusted according to the requirements inside the chip.

[0047] Step 2, as shown in Figure 3 , a temporary bonding material 4 is coated on a temporary bonding wafer 5, the temporary bonding material 4 is temporary bonding glue, the stacked bonding chip structure is placed between the two temporary bonding wafers 5, and the temporary bonding material 4 is coated on the temporary bonding wafers 5, and the upper and lower surfaces of the stacked bonding chip structure are in contact, forming a process stacked structure 1. When the height of the chip stack is greater than 1.2mm, glue needs to be applied between the two temporary bonding wafers in the subsequent process, so two temporary bonding wafers 5 are provided, and the temporary bonding material 4 is coated on the two temporary bonding wafers 5, and the stacked bonding chip structure is placed between the two temporary bonding wafers 5.

[0048] Step 3, input an external force to the process stack structure, so that Figure 2 The 5-layer stack bonding chip structure is temporarily bonded with the upper temporary bonding wafer 5 and the lower temporary bonding wafer 5 to form a process stack structure two. The input external force can be pressure, heating, ultrasonic, and laser bonding.

[0049] Step 4, as shown in Figure 4 , the bottom filling glue is applied on the lower temporary bonding wafer 5, and the glue flows and climbs up under capillary action, flows to the gaps between adjacent chips, and fills the gaps between adjacent chips. After the filling is completed, the entire structure is subjected to bottom filling post-curing to form a process stack structure three.

[0050] Step 5, the upper temporary bonding wafer 5 and the lower temporary bonding wafer 5 of the process stack structure three are debonded by laser debonding process, and the temporary bonding wafer is removed; then solution immersion is performed to remove the temporary bonding material, as shown in Figure 5 .

[0051] Step 6, the structure is subjected to dicing processing to remove the excess filling material, and the structure shown in Figure 6 is obtained.

[0052] The following further describes in combination with specific embodiments:

[0053] Embodiment one:

[0054] The bottom filling method of a three-dimensional stack chip structure in this embodiment includes the following steps:

[0055] In this embodiment, a three-dimensional structure composed of 5 layers of chips needs to be realized. The first layer to the fifth layer of chips are completely consistent in size, as shown in Figure 1 100-1~100-5 in .

[0056] In step 1, as shown in Figure 7 , a chip mounter, flip chip bonder, or die bonder is used to repeat the “pick-up-alignment-mounting” steps four times to complete the stacking of the chip one 100-1~chip five 100-5 structure. The chip one 100-1 is the bottom chip, and the chip five 100-5 is the uppermost chip. The interconnection bonding between the 5 layers of chips is completed by thermal compression welding in one time to obtain the stack bonding chip structure shown in Figure 2 . The stacking method can avoid the problem of solder remelting caused by repeated reflow, and one reflow saves process time.

[0057] Step 2, as shown in Figure 3 , the temporary bonding material 4 is coated on the two temporary bonding wafers 5, and the temporary bonding wafers 5 are temporarily bonded by pressure. Figure 2The 5-layer stack structure is temporarily bonded on the upper and lower carrier wafers. When the temporary bonding material 4 is coated, the temporary bonding carrier 5 can be a 6-inch or 8-inch or 12-inch wafer. After the coating of the temporary bonding material 4 is completed, the coated carrier 5 is cut into small pieces according to the size of the three-dimensional stacked product. The size of the small pieces is at least 1 mm larger than the size of the three-dimensional stacked product, so that the adhesive can be used for bearing when the underfilling is performed.

[0058] Step 3, the stack structure one is pressed to form a stack structure two, as shown in Figure 3

[0059] Step 4, as shown in Figure 4 , the underfill adhesive is applied on the lower temporary bonding carrier 5. The adhesive flows into the gap between the stacked chips under the capillary action and fills the gap. Then, the stack structure is subjected to the underfilling and curing to form a stack structure three.

[0060] Step 5, the upper temporary bonding carrier 5 of the stack structure three is debonded by the laser debonding process. The upper temporary bonding carrier 5 is removed. The product is reversed, and the lower temporary bonding carrier 5 is debonded by the laser debonding process. The temporary bonding material 4 that is not completely separated from the product is soaked in limonene to completely remove the temporary bonding material 4, as shown in Figure 5

[0061] Step 6, the structure in which the temporary bonding material 4 and the temporary bonding carrier 5 are removed in step 5 is subjected to the scribing process to remove the excess underfill adhesive, and the structure shown in Figure 6 is obtained.

[0062] Example Two

[0063] In this example, a three-dimensional structure formed by stacking three chips is needed. The sizes of the first layer to the third layer chips are not completely consistent, as shown in Figure 8 , Figure 9 The size of the bottom chip and the size of each side of the middle chip are different by D1, D2, D3 and D4, respectively. The size of the middle chip and the size of each side of the uppermost chip are different by D5, D6, D7 and D8, respectively. Since the adhesive application edge under the capillary action generally needs to be ≥1.5 mm to ensure that the adhesive does not flow to the bottom of the bearing chip during filling and cause contamination, the values of D1 to D8 in this application are all 0-1.5 mm. That is, when the size difference between the upper and lower chips is ≤1.5 mm, the method mentioned in this application can achieve ideal results, but the values of D1 to D8 are not limited to within 1.5 mm.

[0064] ​​Step 1: Use a flip-chip bonding machine to pick up chip 110-2 of chip 8, then align and mount chip 110-2 of chip 8 with chip 110-3 of chip 9. Repeat the pick-up, alignment and mounting actions to mount chip 110-1 of chip 7 with chip 110-2 of chip 8. Then, use a thermoforming process to complete the welding interconnection between 110-1, 110-2 and 110-3 in one go. The bottom of chips 110-1 and 110-2 has pre-made tin-silver bumps, forming a stacked bonded chip structure.

[0065] Step 2: Temporarily bond the 3-layer stacked component to the temporary bonding carrier 5, which has been coated with temporary bonding material 4. The temporary bonding carrier 5 is made of glass. Figure 10 , Figure 11 As shown. Due to the low overall thickness, the adhesive easily creeps to the top weld seam. Therefore, when using temporary bonding to extend the filler, only a temporary glass substrate is bonded to the bottom substrate as an adhesive support platform, such as... Figure 12 As shown. Among them, the thickness of chip 7 110-1, chip 8 110-2 and chip 9 110-3 is 50μm, and the height of the solder joints formed between adjacent layers is 40μm. The total thickness of the module formed by stacking these three chips is about 240μm, forming the stacked structure one.

[0066] Step 3: During the pressurization process, stacked structure one is formed to create process stacked structure two;

[0067] Step 4: Apply underfill adhesive to the lower temporary bonding substrate 5. After the adhesive flows and fills the gaps between the chips, perform underfill curing to form the third process stack structure.

[0068] Step 5: Apply fluid bottom filler adhesive to the glass substrate, ensuring sufficient adhesive volume to fill the weld gaps. Then, perform post-curing, with post-curing parameters based on the recommended adhesive curve.

[0069] Step 6: The temporary bonding substrate is debonded using a laser debonding process. The temporary bonding film is then removed. Any remaining areas of the temporary bonding film are cleaned by soaking in limonene. Figure 13 As shown.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method of underfilling for forming a three-dimensional stacked chip structure, characterized by, The method comprises the following steps: Step 1, stacking chips, interconnecting and bonding adjacent chips to form a stacked bonded chip structure; In step 1, all the chips have the same shape, and the length of the lower layer chip is greater than or equal to the length of the upper layer chip, and the width of the lower layer chip is greater than or equal to the width of the upper layer chip; Step 2, applying a temporary bonding material (4) on a temporary bonding wafer (5), placing the stacked bonded chip structure on the temporary bonding wafer (5), and forming a process stacking structure one between the temporary bonding wafer (5) and the stacked bonded chip structure; In step 2, the height of the stacked bonded chip structure is greater than 1.2 mm, the temporary bonding material (4) is applied on two temporary bonding wafers (5), and the stacked bonded chip structure is placed between the two temporary bonding wafers (5); Step 3, inputting an external force to the process stacking structure one to form a process stacking structure two; Step 4, for the process stacking structure two, applying a bottom filling glue on the temporary bonding wafer (5), and after the glue flows and fills the gap between the chips, performing bottom filling curing to form a process stacking structure three; In step 4, the bottom filling glue is applied on the two temporary bonding wafers (5); Step 5, debonding the process stacking structure three to remove the temporary bonding wafer (5), and removing the temporary bonding material (4) by solution immersion.

2. The underfill method of forming a three-dimensional stacked chip structure according to claim 1, wherein, In step 1, a pick-and-place machine, a flip chip bonder or a die bonder is used to complete the stacking of chips by repeating the pick-and-place process.

3. The underfill method of forming a three-dimensional stacked chip structure according to claim 1, wherein, The length difference between the lower layer chip and the upper layer chip is in the range of 0-1.5 mm, and the width difference is in the range of 0-1.5 mm.

4. The underfill method of forming a three-dimensional stacked chip structure according to claim 1, wherein, In step 1, the interconnection and bonding between adjacent chips is completed by inputting an external force.

5. The underfill method of forming a three-dimensional stacked chip structure according to claim 1, wherein, In step 5, debonding is performed by inputting light, heat, electricity, force or by solution immersion.

6. The underfill method of forming a three-dimensional stacked chip structure according to claim 1, wherein, In step 5, the temporary bonding material (4) is removed by soaking limonene.

7. The underfill method of forming a three-dimensional stacked chip structure according to claim 1, wherein, After step 5, the wafer is scribed to remove the excess filling material.

8. The underfill method of forming a three-dimensional stacked chip structure according to any one of claims 1 to 7, wherein The difference between the temporary bonding wafer (5) and the longest side of the bottom layer chip is greater than or equal to 1 mm, and the difference between the temporary bonding wafer (5) and the widest side of the bottom layer chip is greater than or equal to 1 mm.

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