Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising a semiconductor substrate and a gate structure buried in the semiconductor substrate. The gate structure includes a gate electrode layer, a barrier layer disposed over the gate electrode layer, and a semiconductor layer disposed over the barrier layer. The semiconductor structure further includes an air gap located in the semiconductor substrate and exposing the barrier layer and the semiconductor layer of the gate structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure, and more particularly to a dynamic random access memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronic products. In order to increase the component density within a DRAM device and improve its overall performance, current manufacturing technologies for DRAM devices continuously strive towards miniaturization of component sizes. However, when component sizes continue to shrink, many challenges arise. For example, improving gate induced drain leakage (GIDL). Therefore, the industry still needs to improve the manufacturing methods of DRAM devices to overcome the problems caused by component size reduction. Summary of the Invention

[0003] Embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a gate structure buried in the semiconductor substrate. The gate structure includes a gate electrode layer, a barrier layer disposed on the gate electrode layer, and a semiconductor layer disposed on the barrier layer. The semiconductor structure further includes an air gap located in the semiconductor substrate and exposing the barrier layer and the semiconductor layer of the gate structure.

[0004] Embodiments of the present invention provide a method for forming a semiconductor structure. The method includes forming a trench in the semiconductor substrate, forming a gate liner along a lower portion of the trench, and filling a gate electrode layer in the lower portion of the trench and on the gate liner. The method further includes forming a first sacrificial layer along sidewalls of an upper portion of the trench, and forming a barrier layer along sidewalls of the first sacrificial layer and a top surface of the gate electrode layer. The method further includes removing a first portion of the barrier layer along the sidewalls of the first sacrificial layer, thereby leaving a second portion of the barrier layer along the top surface of the gate electrode layer. The method further includes forming a semiconductor layer on the second portion of the gate electrode layer, removing the first sacrificial layer, and forming a capping layer on the semiconductor layer. Brief Description of the Drawings

[0005] To make the features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows:

[0006] Figures 1A to 1O are cross-sectional schematic diagrams showing the formation of a semiconductor structure at different stages according to some embodiments of the present invention.

[0007] Figure 2 is according to some embodiments of the present invention, showing Figure 1O modifications of the semiconductor structure.

[0008] Figure 3 According to some embodiments of the present invention, it shows a plan view of a semiconductor structure.

[0009] Symbol description

[0010] 100: Semiconductor structure

[0011] 101: Isolation region

[0012] 102: Semiconductor substrate

[0013] 103: Active region

[0014] 104: Isolation structure

[0015] 105: Truncated region

[0016] 106: Trench

[0017] 106’: Trench

[0018] 107: Gap

[0019] 108: Gate dielectric layer

[0020] 110: Gate liner

[0021] 112: Gate electrode layer

[0022] 112A: Top surface

[0023] 112B: Top surface

[0024] 114: First sacrificial layer

[0025] 116: Barrier layer

[0026] 118: Filling layer

[0027] 120: Second sacrificial layer

[0028] 122: Semiconductor layer

[0029] 124: Gate structure

[0030] 126: Capping layer

[0031] 128: Air gap

[0032] 200: Semiconductor structure Detailed implementation manners

[0033] The following will more comprehensively elaborate on this disclosure with reference to the diagrams of the embodiments of the present invention. However, this disclosure can also be implemented in various different embodiments and should not be limited to the embodiments described herein. The thicknesses of the layers and regions in the diagrams may be enlarged for clarity, and the same or similar reference numerals in each diagram represent the same or similar elements.

[0034] Figures 1A to 1O is a schematic cross-sectional view showing different stages of forming a semiconductor structure according to some embodiments of the present invention. Figure 3 is a schematic plan view showing a semiconductor structure according to some embodiments of the present invention, wherein Figures 1A to 1O is taken along Figure 3 section A-A in

[0035] Figure 3 shows a semiconductor structure 100. The semiconductor structure 100 includes a semiconductor substrate 102. The semiconductor substrate 102 includes an active region 103, an isolation region 101, and a chop region 105. The active region 103 is a semiconductor block extending along a first direction D1, and each active region 103 is defined by two isolation regions 101 and two chop regions 105. Isolation structures (not shown) are formed in the isolation regions 101 and the chop regions 105 of the semiconductor substrate 102 to surround and electrically isolate these active regions 103.

[0036] The isolation regions 101 extend along the first direction D1 and are arranged at intervals in a second direction D2, thereby dividing the semiconductor substrate 102 into a plurality of semiconductor strips (not shown). The first direction D1 is the channel extension direction, and the second direction D2 is the gate extension direction. An acute angle is formed between the first direction D1 and the second direction D2, and the range is, for example, from about 10 degrees to about 80 degrees. The chop regions 105 (shown as dashed lines) are arranged corresponding to the semiconductor strips and truncate the semiconductor strips into a plurality of active regions 103. In the second direction D2, adjacent chop regions 105 may be misaligned or non-overlapping. For example, in the second direction D2, the chop regions 105 may be arranged periodically (e.g., overlapping) in a manner of every plurality of semiconductor strips (e.g., 2 to 5).

[0037] The semiconductor structure 100 further includes a gate structure 124. The gate structure 124 is buried in the semiconductor substrate 102 and extends along the second direction D2. Each gate structure 124 extends alternately through the active region 103 and the isolation structure. Two gate structures 124 extend through a single active region 103, and two gate structures 124 extend through the chop regions 105 on both sides of this active region 103. For the clarity of the diagram, Figure 3 only the above components are shown, and the remaining components of the semiconductor structure 100 can be seen in Figures 1A to 1O the schematic cross-sectional view, which is alongFigure 3 taken along the A-A cross-section.

[0038] The following describes a method for forming a semiconductor structure. Please refer to Figure 1A , a semiconductor substrate 102 is provided, and an isolation structure 104 is formed in the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 is an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate.

[0039] The isolation structure 104 extends downward from the upper surface of the semiconductor substrate 102. The isolation structure 104 is configured to define an active region 103 of the semiconductor substrate 102. In some embodiments, the isolation structure 104 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), and / or a combination of the foregoing.

[0040] The formation of the isolation structure 104 may include forming trenches corresponding to Figure 3 the isolation regions 101 and the truncation regions 105 using one or more etching processes, and then depositing a dielectric material for the isolation structure 104 using chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). Thereafter, a planarization process is performed on the semiconductor structure 100, such as a re-etching process and / or chemical mechanical polishing.

[0041] A patterning process is performed on the semiconductor structure 100 to form trenches 106 in the semiconductor substrate 102, as Figure 1B shown. The trenches 106 extend through the isolation structure 104 and the active region of the semiconductor substrate 102. Figure 1B Only the portion of the trenches 106 located in the isolation structure 104 is shown, and the trenches 106 also include other portions located in the active region 103 of the semiconductor substrate 102.

[0042] The patterning process may include one or more deposition processes, one or more etching processes, and one or more photolithography processes. For example, a hard mask layer may be formed on the semiconductor substrate 102 through a deposition process. A patterned photoresist layer may be formed on the hard mask layer through a photolithography process. The opening pattern of the patterned photoresist layer may be transferred to the hard mask layer and then to the semiconductor substrate 102 through an etching process, thereby forming the trenches 106.

[0043] Form a gate dielectric layer 108, a gate liner layer 110, and a gate electrode layer 112 in sequence in the trench 106, as Figure 1C shown. The gate liner layer 110 is lined between the gate dielectric layer 108 and the gate electrode layer 112.

[0044] Form the gate dielectric layer 108 along the sidewalls and bottom surface of the trench 106 to partially fill the trench 106. Figure 1C Only the part of the gate dielectric layer 108 lined on the isolation structure 104 is shown. The gate dielectric layer 108 also includes other parts lined on the active region 103 of the semiconductor substrate 102. In some embodiments, the gate dielectric layer 108 is formed of silicon oxide, silicon nitride, silicon oxynitride, and / or a high-k dielectric material. In some embodiments, the gate dielectric layer 108 is formed using in-situ steam generation (ISSG), chemical vapor deposition (CVD), and / or atomic layer deposition (ALD).

[0045] Form the gate liner layer 110 in the lower part of the trench 106 on the gate dielectric layer 108 to partially fill the trench 106. In some embodiments, the gate liner layer 110 is formed of titanium nitride (TiN), tungsten nitride (WN), and / or tantalum nitride (TaN). Chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD) can be used to deposit the gate liner layer 110.

[0046] Form the gate electrode layer 112 on the gate liner layer 110 to fill the lower part of the trench 106. The gate electrode layer 112 is nested within the gate liner layer 110. In some embodiments, the gate electrode layer 112 is formed of a metal material, for example, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), and / or other metal materials. Physical vapor deposition (PVD), chemical vapor deposition (CVD), and / or atomic layer deposition (ALD) can be used to deposit the gate electrode layer 112.

[0047] After depositing the materials for the gate dielectric layer 108, the gate liner layer 110, and the gate electrode layer 112, the gate liner layer 110 and the gate electrode layer 112 can be etched back.

[0048] Form a first sacrificial layer 114 on the semiconductor substrate 102 to partially fill the trench 106, as Figure 1DAs shown. The first sacrificial layer 114 covers and extends along the sidewalls of the gate dielectric layer 108, the top surface of the gate liner layer 110, and the top surface of the gate electrode layer 112. According to some embodiments, the thickness of the first sacrificial layer 114 along the gate dielectric layer 108 is equal to or greater than the thickness of the gate liner layer 110. In some embodiments, the first sacrificial layer 114 is formed of a dielectric material, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination of the foregoing. There is an etch selectivity between the first sacrificial layer 114 and the isolation structure 104. For example, when the isolation structure 104 is formed of silicon nitride, the first sacrificial layer 114 is formed of silicon oxide. When the isolation structure 104 is formed of silicon oxide, the first sacrificial layer 114 is formed of silicon nitride. Chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) can be used to deposit the first sacrificial layer 114.

[0049] An etching process is performed on the first sacrificial layer 114 to remove the horizontal portions of the first sacrificial layer 114 along the upper surface of the semiconductor 102 and along the top surface of the gate electrode layer 112, as Figure 1E shown. After the etching process, the top surface of the gate electrode layer 112 is exposed, and the vertical portions of the first sacrificial layer 114 along the gate dielectric layer 108 are left. The vertical portions of the first sacrificial layer 114 completely cover the top surface of the gate liner layer 110. The vertical portions of the first sacrificial layer 114 may also partially cover the gate electrode layer 112. In some embodiments, the etching process may include an over-etch step to slightly etch the gate electrode layer 112 such that the gate electrode layer 112 has a top surface 112A that is horizontally lower than the top surface of the gate liner layer 110.

[0050] A barrier layer 116 is formed over the semiconductor substrate 102 to partially fill the trench 106, as Figure 1F shown. The barrier layer 116 covers and extends along the sidewalls of the first sacrificial layer 114 and the top surface of the gate electrode layer 112. The barrier layer 116 does not contact the gate liner layer 110.

[0051] There is an etch selectivity between the barrier layer 116 and the gate electrode layer 112. In some embodiments, the barrier layer 116 is formed of titanium nitride (TiN), tungsten nitride (WN), and / or tantalum nitride (TaN). Physical vapor deposition (PVD), chemical vapor deposition (CVD), and / or atomic layer deposition (ALD) can be used to deposit the barrier layer 116. In some embodiments, the barrier layer 116 and the gate liner layer 110 are formed of the same material.

[0052] A fill layer 118 is formed over the barrier layer 116 to overfill the upper portion of the trench 106, as Figure 1GAs shown. In some embodiments, the filling layer 116 is formed of a carbon-rich material, for example, spin-on coating (SOC). The filling layer 118 can be formed using a spin coating process.

[0053] A re-etching process is performed on the filling layer 118 to remove the portion of the filling layer 118 formed above the upper surface of the semiconductor substrate 102, and to etch the portion of the filling layer 118 formed in the trench 106, as Figure 1H shown. After the re-etching process, the upper portion of the trench 106 is formed again and labeled as trench 106'. After the re-etching process, the barrier layer 116 is exposed from the trench 106' along the upper portion of the vertical part of the first sacrificial layer 114.

[0054] According to some embodiments, one or more etching processes are performed on the barrier layer 116 to remove the portion of the barrier layer 116 located above the upper surface of the semiconductor substrate 102 and along the vertical part of the first sacrificial layer 114 until the gate electrode layer 112 is exposed, as Figure 1I shown. During the etching process, the filling layer 118 protects the horizontal portion of the barrier layer 116 along the top surface of the gate electrode layer 112 from being removed.

[0055] Due to the etching selectivity between the barrier layer 116 and the gate electrode layer 112, the etching process can be preferably controlled by detecting the etching end point. In addition, during the etching process, the first sacrificial layer 114 covers and protects the gate liner 110, such that the gate liner 110 is substantially not etched.

[0056] In some embodiments, the etching process may include an over-etching step to slightly etch the gate electrode layer 112 such that the gate electrode layer 112 has a top surface 112B, the level of which is lower than the level of the top surface of the gate liner 110 and the level of the top surface 112A of the gate electrode layer.

[0057] The filling layer 118 is etched and removed to expose the barrier layer 116, as Figure 1J shown.

[0058] A second sacrificial layer 120 is formed on the semiconductor substrate 102 to partially fill the trench 106', as Figure 1KAs shown. The second sacrificial layer 120 covers and extends along the sidewalls of the first sacrificial layer 114 and the top surface of the barrier layer 116. In some embodiments, the second sacrificial layer 120 is formed of a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination of the foregoing. There is an etch selectivity between the second sacrificial layer 120 and the isolation structure 104. For example, when the isolation structure 104 is formed of silicon nitride, the second sacrificial layer 120 is formed of silicon oxide. When the isolation structure 104 is formed of silicon oxide, the second sacrificial layer 120 is formed of silicon nitride. The second sacrificial layer 120 may be formed of the same material as the first sacrificial layer 114. For clarity, Figure 1K shows the interface between the first sacrificial layer 114 and the second sacrificial layer 120, however, there may be no physical interface between the first sacrificial layer 114 and the second sacrificial layer 120. Chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) may be used to deposit the second sacrificial layer 120.

[0059] An etching process is performed on the second sacrificial layer 120 to remove the horizontal portions of the second sacrificial layer 120 along the upper surface of the semiconductor 102 and along the top surface of the barrier layer 116, as Figure 1L shown. After the etching process, the top surface of the barrier layer 116 is exposed, and the vertical portions of the second sacrificial layer 120 along the first sacrificial layer 114 are left. The top surfaces 112A and 112B of the gate electrode layer 112 are covered by the barrier layer 116 and the second sacrificial layer 120, respectively.

[0060] A semiconductor layer 122 is formed in the trench 106' to fill the lower portion of the trench 106', as Figure 1M shown. The gate dielectric layer 108, the gate liner 110, the gate electrode layer 112, the barrier layer 116, and the semiconductor layer 122 together form a gate structure 124. The gate structure 124 may be configured as a word line of the resulting semiconductor memory device, such as a buried word line (BWL). In some embodiments, the barrier layer 116 and the semiconductor layer 122 may serve as work function adjustment layers of the gate structure 124. In some embodiments, the semiconductor layer 122 is formed of polysilicon. The formation of the semiconductor layer 122 may include depositing the semiconductor layer 122 using a chemical vapor deposition process (CVD) to overfill the trench 106', and then etching back the semiconductor layer 122.

[0061] In some embodiments, the sidewalls of the semiconductor layer 122 are substantially aligned with the sidewalls of the barrier layer 116. The widths of the semiconductor layer 122 and the barrier layer 116 are less than the maximum width of the gate electrode layer 112. For example, the ratio of the widths of the semiconductor layer 122 and the barrier layer 116 to the maximum width of the gate electrode layer 112 ranges from about 0.5 to about 0.9. Since the top surface of the gate electrode layer 112 is covered by the second sacrificial layer 120 and the barrier layer 116, the semiconductor layer 122 may be formed not to contact the top surface of the gate electrode layer 112. In the case where the semiconductor layer contacts the gate electrode layer, silicon from the semiconductor layer and the metal of the gate electrode layer may form metal silicide, thereby increasing the overall resistance value of the gate structure.

[0062] Etch away the first sacrificial layer 114 and the second sacrificial layer 120 until the gate electrode layer 112 and the gate liner 110 are exposed, as Figure 1N shown. After the etching process, a gap 107 is formed between the semiconductor layer 122 (and the barrier layer 116) and the gate dielectric layer 108.

[0063] Form a capping layer 126 in the trench 106’, as Figure 1O shown. The capping layer 126 seals the gap 107 to form an air gap 128 between the semiconductor layer 122 (and the barrier layer 116) and the gate dielectric layer 108.

[0064] Additional components, such as source / drain regions in the semiconductor substrate 102, contact plugs connected to the source / drain regions, bit lines, capacitors, and / or other components, may be formed over the semiconductor structure 100 to fabricate a semiconductor memory device. In some embodiments, the semiconductor memory device is a dynamic random access memory (DRAM).

[0065] According to an embodiment of the present invention, the gate structure 124 includes a dual work function adjustment layer (i.e., the barrier layer 116 and the semiconductor layer 122), which can reduce the electric field strength generated by the gate electrode layer 112 of the gate structure 124, thereby reducing the gate induced drain leakage (GIDL). In addition, the semiconductor structure 100 includes air gaps 128 on both sides of the semiconductor layer 122 (and the barrier layer 116), which can further reduce the gate induced drain leakage, improving the reliability and manufacturing yield of the semiconductor memory device. Furthermore, according to an embodiment of the present invention, the dual work function adjustment layer of the gate structure 124 does not need to be formed through an additional mask. Thus, the overlay window limitation of the lithography process is avoided. Moreover, according to an embodiment of the present invention, by forming the first sacrificial layer 114 to protect the gate liner 110, during the etching process of the barrier layer 116, the loss of the gate liner 110 can be significantly reduced and the termination point of the etching process can be better controlled. Furthermore, by forming the second sacrificial layer 120 to cover the top surface 112B of the gate electrode layer 112, the contact between the semiconductor layer 122 and the gate electrode layer 112 to form metal silicide is avoided. Thus, an increase in the resistance value of the gate structure 124 due to the formation of metal silicide is avoided.

[0066] Figure 2 is a modification of the semiconductor structure according to some embodiments of the present invention, showing Figure 1O of the semiconductor structure. Figure 2 The semiconductor structure 200 shown is similar to Figure 1O the semiconductor structure 100, except that the barrier layer 116 surrounds the lower part of the semiconductor layer 122.

[0067] In Figure 1I the steps described above, part of the barrier layer 116 is etched away along the vertical part of the first sacrificial layer 114. After the etching process, the remaining barrier layer 116 has a U-shaped profile. The gate electrode layer 112 is covered by the remaining barrier layer 116 and not exposed. Then, Figure 1J the steps described above are performed to remove the fill layer 118 to expose the barrier layer 116.

[0068] Omit Figure 1K and Figure 1L the steps described above, and perform Figures 1M to 1O the steps described above. A semiconductor layer 122 is formed in the trench 106'. The semiconductor layer 122 includes a lower part surrounded by the barrier layer 116 and an upper part formed on top of the top surface of the barrier layer 116, as Figure 2 shown. A capping layer 126 is formed in the trench 106' to form an air gap 128 between the semiconductor layer 122 (and the barrier layer 116) and the gate dielectric layer 108 to obtain the semiconductor structure 200.

[0069] According to the above, embodiments of the present invention provide a semiconductor structure including an embedded gate structure and a method for forming the same. The embedded gate structure includes a dual work function adjustment layer and air gaps on both sides of the dual work function adjustment layer. Therefore, gate-induced drain leakage current is reduced, which improves the reliability and manufacturing yield of the semiconductor memory device.

[0070] Although the present invention has been disclosed as above in the foregoing embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A semiconductor substrate; And A gate structure buried in the semiconductor substrate and comprising: A gate electrode layer; A barrier layer disposed on the gate electrode layer; and A semiconductor layer disposed on the barrier layer; and A gate liner, wherein the gate electrode layer is nested within the gate liner and the top surface of the gate liner is higher than the top surface of the gate electrode layer; and An air gap located in the semiconductor substrate and exposing the barrier layer and the semiconductor layer of the gate structure.

2. The semiconductor structure according to claim 1, wherein Further comprising: A capping layer disposed on the gate structure and sealing the air gap.

3. The semiconductor structure according to claim 1, wherein The sidewalls of the semiconductor layer are aligned with the sidewalls of the barrier layer, and the width of the barrier layer is less than the width of the gate electrode layer.

4. The semiconductor structure according to claim 1, characterized in that, Further comprising: An isolation structure disposed in the semiconductor substrate, wherein the gate structure is at least partially buried in the isolation structure.

5. The semiconductor structure according to claim 4, wherein, The gate structure further comprises: A gate dielectric layer lining on the isolation structure, wherein a part of the gate dielectric layer is exposed by the air gap.

6. The semiconductor structure according to claim 1, wherein, The semiconductor layer is formed of polysilicon, and the barrier layer is formed of titanium nitride.

7. The semiconductor structure according to claim 1, characterized in that, The barrier layer has a U-shaped profile.

8. A method for forming a semiconductor structure, characterized in that Comprising: Forming a trench in a semiconductor substrate; Forming a gate liner along a lower portion of the trench; Filling a gate electrode layer into the lower portion of the trench and on the gate liner; Forming a first sacrificial layer along sidewalls of an upper portion of the trench; Forming a barrier layer along sidewalls of the first sacrificial layer and the top surface of the gate electrode layer; Removing a first portion of the barrier layer along sidewalls of the first sacrificial layer, thereby leaving a second portion of the barrier layer along the top surface of the gate electrode layer; Forming a semiconductor layer on the second portion of the barrier layer; Removing the first sacrificial layer; And Forming a capping layer on the semiconductor layer.

9. The method for forming a semiconductor structure according to claim 8, wherein, Further comprising: Before removing the first portion of the barrier layer, forming a filling layer on the barrier layer to fill the upper portion of the trench; Etching the filling layer to at least partially expose the first portion of the barrier layer; And After removing the first portion of the barrier layer, removing the filling layer to expose the second portion of the barrier layer.

10. The method for forming a semiconductor structure as described in claim 8, wherein, Further comprising: Before forming the semiconductor layer, forming a second sacrificial layer along sidewalls of the first sacrificial layer and the top surface of the barrier layer; And Removing a first portion of the second sacrificial layer along the top surface of the barrier layer, wherein after removing the first portion of the second sacrificial layer, a second portion of the second sacrificial layer along sidewalls of the first sacrificial layer partially covers the gate electrode layer.

11. The method for forming a semiconductor structure according to claim 10, wherein, Further comprising: While removing the first sacrificial layer, removing the second portion of the second sacrificial layer, wherein removing the first sacrificial layer and the second sacrificial layer forms a gap between the semiconductor layer and the semiconductor substrate, and forming the capping layer to seal the gap.

12. The method for forming a semiconductor structure according to claim 8, wherein, The first sacrificial layer has a first thickness along the upper portion of the trench, and the gate liner has a second thickness along the lower portion of the trench, and the first thickness is greater than the second thickness.

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