Integrated circuit structure and method for forming a multilayer interconnect structure for a memory

Abstract

Embodiments herein disclose configurations of metal layers of an interconnect structure that can improve memory performance, such as static random access memory (SRAM) memory performance, and / or logic performance. For example, embodiments herein place bitlines in a metal one (M1) layer, which is the lowest metallization level of the interconnect structure of a memory cell, to minimize bitline capacitance, and configure the bitlines as the widest metal lines of the M1 layer to minimize bitline resistance. In some embodiments, the interconnect structure has a dual wordline structure to reduce wordline resistance. In some embodiments, the interconnect structure has a dual voltage line structure to reduce voltage line resistance. In some embodiments, steps are added to the wordlines and / or voltage lines to reduce their respective resistances. In some embodiments, via shapes of the interconnect structure are configured to reduce resistance of the interconnect structure. Embodiments of the invention also relate to integrated circuit structures and methods for forming a multi-layer interconnect structure of a memory.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to integrated circuit structures and methods for forming a multi-layer interconnect structure for a memory. BACKGROUND

[0002] The integrated circuit (IC) industry has experienced exponential growth. The pace of that growth is best described by the consistent halfing of feature size (or, resolution) every 18 months to two years. This accelerating shift in design complexity necessitates a fundamental shift in design methodologies, methodology, verification, and manufacturing. In the pursuit of smaller geometry, the industry has developed new design methodologies and design structures. For example, the industry's initial response to smaller geometry has been the introduction of deep sub-micron technology. These design methodologies give rise to a new set of challenges and problems that require innovative solutions to keep pace with other components of the design community. One such area of concern is the impact on the performance of the memory (e.g., static random access memory (SRAM)) in the IC. As the geometry of the IC continues to shrink, the performance of the memory in the IC becomes increasingly sensitive to the resistance and capacitance of the interconnects in the memory. As the resistance and capacitance of the interconnects in the memory increase, the performance of the memory decreases. This is particularly true for advanced memory (e.g., SRAM) that requires faster speeds (e.g., fast write / read). Thus, while existing MLI structures for memory-based ICs and their interconnects have generally been adequate for their intended purpose, they have not been entirely satisfactory in all respects. SUMMARY

[0003] Embodiments of the invention provide an integrated circuit structure comprising: a memory cell connected to a bit line, an inverted bit line, a first voltage line to receive a first voltage, a word line, and a second voltage line to receive a second voltage different from the first voltage; and an interconnect structure disposed above the memory cell, wherein: the interconnect structure comprises the bit line, the inverted bit line, the first voltage line, the word line, and the second voltage line, wherein the bit line, the inverted bit line, the first voltage line, and the second voltage line extend along a first longitudinal direction, and the word line extends along a second longitudinal direction different from the first longitudinal direction, the interconnect structure has a bottommost metal layer having a metal line connected to the memory cell, wherein the metal line comprises the bit line, the first voltage line, a voltage line bond pad connected to the second voltage line, and a word line bond pad connected to the word line, and wherein a width of the bit line is a widest width of the metal line.

[0004] Another embodiment of the invention provides an integrated circuit structure comprising: a memory cell; and an interconnect structure disposed above and electrically connected to the memory cell, wherein the interconnect structure comprises: a first metal layer electrically connected to the memory cell, wherein the first metal layer comprises a bit line, a first voltage line configured to receive a first voltage, a first voltage line bond pad, and a first word line bond pad, a second metal layer disposed above the first metal layer, wherein the second metal layer comprises a first word line electrically connected to the first word line bond pad and a second voltage line bond pad electrically connected to the first voltage line bond pad, a third metal layer disposed above the second metal layer, wherein the third metal layer comprises a second voltage line electrically connected to the second voltage line bond pad, wherein the second voltage line is configured to receive a second voltage, a fourth metal layer disposed above the third metal layer, wherein the fourth metal layer comprises a second word line, and wherein the bit line, the first voltage line, and the second voltage line extend along a first longitudinal direction, the first word line and the second word line extend along a second longitudinal direction different from the first longitudinal direction, and a first width of the bit line is greater than a second width of the first voltage line.

[0005] Yet another embodiment of the present invention provides a method for forming a multi-layer interconnect structure of a memory, comprising: forming a first metallization layer, the first metallization layer comprising a bit line, an inverted bit line, and a first voltage line configured to receive a first voltage, wherein the bit line, the inverted bit line, and the first voltage line extend along a first routing direction, the first metallization layer is a bottommost metallization layer of the multi-layer interconnect structure, and a bit line width of the bit line has a widest width of metal lines of the first metallization layer; forming a second metallization layer above the first metallization layer, wherein the second metallization layer comprises a first word line extending along a second routing direction different from the first routing direction; forming a third metallization layer above the second metallization layer, wherein the third metallization layer comprises a second voltage line and a third voltage line, the second voltage line and the third voltage line are configured to receive a second voltage different from the first voltage, and the second voltage line and the third voltage line extend along the first routing direction; and forming a fourth metallization layer disposed above the third metal layer, wherein the fourth metallization layer comprises a second word line extending along the second routing direction. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present invention can best be understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a partial diagrammatic plan view of a memory, such as a static random access memory (SRAM), in accordance with various aspects of the present invention.

[0008] Figure 2 is a circuit diagram of a memory cell, such as an SRAM cell, that can be implemented in a memory of Figure 1

[0009] Figure 3 is another circuit diagram of a memory cell, such as an SRAM cell, that can be implemented in a memory of Figure 1

[0010] Figure 4 is a partial diagrammatic cross-sectional view of various layers of a portion or entirety of a memory, in accordance with various aspects of the present invention.

[0011] Figure 5A and Figure 5B is a partial diagrammatic view of a portion or entirety of a memory cell, such as an SRAM cell, in accordance with various aspects of the present invention.

[0012] ​​Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E are various top plan views of various layers of portions or all of memory cells of Figure 5A and Figure 5B are various top plan views of various layers of portions or all of memory cells of

[0013] Figure 7 are partial diagrammatic plan views of portions or all of memory having dual word line structures according to various aspects of the present application.

[0014] Figure 8A , Figure 8B and Figure 8C are various top plan views of various layers of portions or all of memory having dual voltage line structures according to various aspects of the present application.

[0015] Figure 9A and Figure 9B are partial schematic views of the bottom most metal layer of interconnect structures of portions or all of SRAM cells and logic cells, respectively, according to various aspects of the present application.

[0016] Figure 10 are top plan views of portions or all of SRAM cells having variable width voltage lines and word lines according to various aspects of the present application.

[0017] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E are various top plan views of various layers of portions or all of memory cells of Figure 10 . DETAILED DESCRIPTION

[0018] The present application relates generally to integrated circuit (IC) devices, and more particularly to interconnect structures for memory-based IC devices.

[0019] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features can not be in direct contact. In some embodiments, the first and second features can be formed in direct contact.

[0020] Furthermore, the present application can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not indicate a relationship between the embodiments and / or configurations discussed herein. Moreover, in the following detailed description of the present application, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", "vertical", "horizontal", "up", "down", "top", "bottom", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0021] Disclosed herein are configurations of metal layers of an interconnect structure that can improve memory performance, such as static random access memory (SRAM) memory performance and / or logic performance. For example, embodiments herein place bitlines in metal one, which is the lowest metallization layer of the interconnect structure of a memory cell, to minimize bitline capacitance, and configure the bitlines to be the widest metal lines of metal one to minimize bitline resistance. In some embodiments, the interconnect structure has a dual wordline structure to reduce wordline resistance. In some embodiments, the wordline strips (i.e., connections) in the dual wordline structure are configured and placed within the memory to reduce wordline resistance. In some embodiments, the interconnect structure has a dual voltage line structure to reduce voltage line resistance. In some embodiments, steps are added to the wordlines and / or voltage lines to reduce their respective resistances. In some embodiments, the via shape of the interconnect structure is configured to reduce the resistance of the interconnect structure. In some embodiments, the size of the metal lines of metal one in a memory region are configured relative to the size of the metal lines of metal one in a logic region to collectively optimize memory performance and logic performance, e.g., by minimizing resistance. As described below, the SRAM configurations disclosed herein thus optimize electrical characteristics and SRAM density. Different embodiments can have different advantages, and no particular advantage is required of any embodiment.

[0022] Figure 1is a partial diagrammatic plan view of a memory 10 according to various aspects of the present application. The memory 10 can be included in a microprocessor, memory, and / or other IC device. In some embodiments, the memory 10 can be part of an IC chip, a system on a chip (SoC), or part thereof, including various passive and active electronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal oxide semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffusion MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. Depending on the design requirements of the memory 10, the various transistors can be planar transistors or multi-gate transistors, such as FinFETs or GAA transistors. For clarity, various components have been simplified Figure 1 to better understand the inventive concepts of the present application. Additional components can be added in the memory 10, and some of the components described below can be replaced, modified, or eliminated in other embodiments of the memory 10.

[0023] Memory 10 includes a memory array 12 that includes memory cells 15 (also referred to as bit cells) for storing data. In some embodiments, memory 10 is configured as a static random access memory (SRAM), and memory cells 15 are SRAM cells. Memory cells 15 include various transistors, such as p-type transistors and / or n-type transistors, configured to facilitate reading and writing of data of memory cells 15. Memory cells 15 are arranged in columns 1 (Cl) to columns N (CN) that extend along a first direction (e.g., a y-direction) and rows 1 (Rl) to rows M (RM) that extend along a second direction (e.g., an x-direction), where N and M are positive integers. Each of columns Cl to CN includes bit line pairs, such as a bit line (BL) and an inverted bit line (BLB) (also referred to as a complementary bit line), that extend along the first direction, which facilitate reading data from and / or writing data to respective memory cells 15 in a column-wise fashion in a true form and a complementary form. Each of rows Rl to RM includes a word line (WL) that facilitates accessing respective memory cells 15 in a row-wise fashion. Each memory cell 15 is electrically connected to a respective BL, a respective BLB, and a respective WL. BLs and BLBs are electrically connected to a controller 20, and WLs are electrically connected to a controller 25. Controllers 20 and 25 are configured to generate one or more signals to select at least one WL and at least one bit line pair (here, BL and BLB) to access at least one of memory cells 15 for a read operation and / or a write operation. Each of controllers 20 and 25 includes circuitry to facilitate the read / write operation, such as a column decoder circuit, a row decoder circuit, a column selection circuit, a row selection circuit, a read / write circuit (e.g., configured to read data from and / or write data to memory cells 15 that correspond to a selected bit line pair (in other words, a selected column)), other suitable circuitry, or a combination thereof. In some embodiments, controller 20 and / or controller 25 includes at least one sense amplifier configured to detect and / or amplify a voltage difference of a selected bit line pair. In some embodiments, the sense amplifier is configured to latch or otherwise store a data value of the voltage difference.

[0024] The outer periphery of the memory 10 is configured with dummy cells, such as edge dummy cells and / or well strip cells, to facilitate uniformity of fabrication and / or performance of the memory cells 15. The dummy cells are configured physically and / or structurally similar to the memory cells 15, but do not store data. For example, the dummy cells can include p-type wells, n-type wells, channels (e.g., formed in one or more fins or one or more suspended channel layers (e.g., nanowires or nanosheets)), gate structures, source / drain and / or interconnects (e.g., contacts, vias and / or metal lines). The well strip cells generally refer to dummy cells configured to electrically connect a voltage to an n-well of the memory cells 15, a p-well of the memory cells 15, or both. For example, an n-type well strip is configured to electrically connect an n-well corresponding to at least one p-type transistor of the memory cells 15 to a voltage source, and a p-type well strip is configured to electrically connect a p-well corresponding to at least one n-type transistor of the memory cells 15 to a voltage source. In the depicted embodiment, the memory 10 includes edge cells 30 (collectively referred to as edge cells, well strip cells, and / or other dummy cells) arranged in edge cell columns 35A and 35B along a first direction (e.g., the y-direction), with each of the rows R1 to RM of memory cells 15 disposed between one of the edge cells 30 in the edge cell column 35A and one of the edge cells 30 in the edge cell column 35B. In further embodiments of the depicted embodiment, each of the columns C1 to CN of memory cells 15 is disposed between a respective pair of edge cells 30. In some embodiments, the edge cell columns 35A and / or 35B are substantially parallel to at least one bit line pair (here, BL and BLB) of the memory 10. In some embodiments, the edge cells 30 connect the respective memory cells 15 to the respective WLs. In some embodiments, the edge cells 30 include circuitry for driving the WLs. In some embodiments, the edge cells 30 are electrically connected to a power supply voltage V DD (e.g., a positive power supply voltage) and / or a power supply voltage V SS (e.g., electrical ground).

[0025] Figure 2 is a circuit diagram of an SRAM circuit 90 that can be implemented in a memory cell of an SRAM according to various aspects of the application. Figure 3 is an alternative circuit diagram of an SRAM circuit 90 according to various aspects of the application, to be discussed Figure 2 simultaneously with Figure 3In some embodiments, one or more memory cells 15 are configured as SRAM circuits 90. The SRAM circuit 90 includes six transistors: a pass gate transistor PG-1, a pass gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. The SRAM circuit 90 is thus optionally referred to as a 6T SRAM cell. The storage portion of the SRAM circuit 90 includes a cross-coupled pair of inverters (which can be referred to as a latch), such as inverter-1 and inverter-2 Figure 3 ). The inverter-1 includes the pull-up transistor PU-1 and the pull-down transistor PD-1, and the inverter-2 includes the pull-up transistor PU-2 and the pull-down transistor PD-2. The pass gate transistor PG-1 is connected to the output of the inverter-1 and the input of the inverter-2, and the pass gate transistor PG-2 is connected to the output of the inverter-2 and the input of the inverter-1. In operation, the pass gate transistors PG-1 and PG-2 provide access to the storage portion of the SRAM circuit 90 (i.e., the inverters-1 and -2), and can be optionally referred to as access transistors of the SRAM circuit 90. In the depicted embodiment, the SRAM circuit 90 is a single-port SRAM cell. The present disclosure contemplates embodiments in which the SRAM circuit 90 is a multi-port SRAM cell, such as a dual-port SRAM cell, and / or includes more or fewer transistors, such as an 8T SRAM cell. For clarity, some components described below have been simplified Figure 2 and Figure 3 to better understand the inventive concepts of the present disclosure. Additional components can be added in the SRAM circuit 90, and some components described below can be replaced, modified, or eliminated in other embodiments of the SRAM circuit 90.

[0026] The SRAM circuit 90 is connected to a first supply voltage (such as a positive supply voltage) and a second supply voltage (such as a ground voltage or reference voltage (which can be an electrical ground)) and is powered by the first supply voltage. The gate of the pull-up transistor PU-1 is between the source (via a voltage node V DD electrically connected to the first supply voltage) and a first common drain (CD1) (i.e., the drain of the pull-up transistor PU-1 and the drain of the pull-down transistor PD-1). The gate of the pull-down transistor PD-1 is between the source (via a first V SS node electrically connected to the second supply voltage) and the first common drain. The gate of the pull-up transistor PU-2 is between the source (via a voltage node V DD electrically connected to the first supply voltage) and a second common drain (CD2) (i.e., the drain of the pull-up transistor PU-2 and the drain of the pull-down transistor PD-2). The gate of the pull-down transistor PD-2 is between the source (via a second V SSThe node is electrically connected between the second supply voltage and the second common drain. In some embodiments, the first common drain is a storage node SN that stores data in a true form and the second common drain is a storage node SNB that stores data in a complementary form. The gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 are connected together and to the second common drain, and the gate of the pull-up transistor PU-2 and the gate of the pull-down transistor PD-2 are connected together and to the first common drain. The gate of the pass gate transistor PG-1 is between a drain connected to a bit line node (BLN) that is electrically connected to a bit line BL and a source electrically connected to the first common drain. The gate of the pass gate transistor PG-2 is between a drain connected to a complementary bit line node (BLBN) that is electrically connected to a complementary bit line BLB and a source electrically connected to the second common drain. The gates of the pass gate transistors PG-1, PG-2 are connected to and controlled by a word line WL, which allows the SRAM circuit 90 to be selected for reading / writing. In some embodiments, the pass gate transistors PG-1, PG-2 provide access to the storage nodes SN, SNB during a read operation and / or a write operation, which can store a bit (e.g., a logic 0 or a logic 1). For example, the pass gate transistors PG-1, PG-2 connect the storage nodes SN, SNB to the bit lines BL, BLB, respectively, in response to a voltage applied to the gates of the pass gate transistors PG-1, PG-2 by the WL.

[0027] In some embodiments, the pull-up transistors PU-1, PU-2 are configured as p-type multi-gate devices, such as p-type FinFETs or p-type GAA transistors, and the pull-down transistors PD-1, PD-2 are configured as n-type multi-gate devices, such as n-type FinFETs or n-type GAA transistors. For example, each of the pull-up transistors PU-1, PU-2 includes a gate structure disposed over a channel region of an n-type fin structure (including one or more n-type fins) such that the gate structure is between p-type source / drain regions (e.g., p-type epitaxial source / drain portions) of the n-type fin structure, with the gate structure and the n-type fin structure disposed over an n-type well; and each of the pull-down transistors PD-1, PD-2 includes a gate structure disposed over a channel region of a p-type fin structure (including one or more p-type fins) such that the gate structure is between n-type source / drain regions (e.g., n-type epitaxial source / drain portions) of the p-type fin structure, with the gate structure and the p-type fin structure disposed over a p-type well. In some embodiments, the pass-gate transistors PG-1, PG-2 are also configured as n-type FinFETs. For example, each of the pass-gate transistors PG-1, PG-2 includes a gate structure disposed over a channel region of a p-type fin structure (including one or more p-type fins) such that the gate structure is between n-type source / drain regions (e.g., n-type epitaxial source / drain portions) of the p-type fin structure, with the gate structure and the p-type fin structure disposed over a p-type well.

[0028] Figure 4 are partial diagrammatic cross-sectional views of various layers (levels) that can be fabricated over a semiconductor substrate (or wafer) 105 to form portions of a memory (such as memory 10) and / or portions of an SRAM cell (such as SRAM circuit 90) in accordance with various aspects of the present disclosure. In the following figures, like reference numerals are used to refer to like elements throughout. Figure 1 Figure 2 Figure 3 Figure 4 ​​​In particular embodiments, each layer includes a device layer DL and a multilayer interconnect MLI disposed above the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain components). In some embodiments, the device layer DL includes a substrate 105, doped regions 110 (e.g., n-wells and / or p-wells) disposed in the substrate 105, isolation components 115, and a transistor T. In the depicted embodiment, the transistor T includes a suspended channel layer 120 disposed between source / drain 130 and a gate structure 125, where the gate structure 125 wraps around and / or surrounds the suspended channel layer 120. Each gate structure 125 has a metal gate stack formed from a gate electrode 134 disposed above a gate dielectric 136 and a gate spacer 138 disposed along sidewalls of the metal gate stack. The multilayer interconnect MLI electrically connects various devices and / or components of the device layer DL so that the various devices and / or components can operate as specified by design requirements for the memory. In the depicted embodiment, the multilayer interconnect MLI includes a contact layer (CO level or metal zero (M0) level), a via zero layer (V0 level), a metal one layer (Ml level), a via one layer (VI level), a metal two layer (M2 level), a via two layer (V2 level), a metal three layer (M3 level), a via three layer (V3 level), and a metal four layer (M4 level). The present disclosure contemplates that the multilayer interconnect MLI has more or fewer layers and / or levels, e.g., up to MX level and V(X-l) level, where X is the total number of metal layers (levels) of the multilayer interconnect MLI. Each level of the multilayer interconnect MLI includes conductive components (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., interlayer dielectric (ILD) layers and contact etch stop layers (CESL)). In some embodiments, the conductive components at the same level of the multilayer interconnect MLI, such as the Ml level, are formed simultaneously. In some embodiments, the conductive components at the same level of the multilayer interconnect MLI have substantially planar top surfaces to each other and / or substantially planar bottom surfaces to each other.The CO layer includes source / drain contacts (MD) disposed in the dielectric layer 150; the V0 layer includes a gate via VG, a source / drain via V0, and a mating contact disposed in the dielectric layer 150; the M1 layer includes an M1 metal line disposed in the dielectric layer 150, wherein the gate via VG connects the gate structure 125 to the M1 metal line, the source / drain via V0 connects the source / drain 130 to the M1 metal line, and the mating contact connects the gate structure 125 and the source / drain 130 together. The M1 layer includes a V1 via in dielectric layer 150, connecting the M1 metal line to the M2 metal line; the M2 layer includes an M2 metal line in dielectric layer 150; the V2 layer includes a V2 via in dielectric layer 150, connecting the M2 line to the M3 line; the M3 layer includes an M3 metal line in dielectric layer 150; the V3 layer includes a V3 via in dielectric layer 150, connecting the M3 line to the M4 line. For clarity, this has been simplified. Figure 4 To better understand the inventive concept of the present invention. Additional components can be added to the various layers of the memory, and some of the described components can be replaced, modified, or eliminated in other embodiments of the memory. Figure 4 This is just an example and may not reflect the actual cross-sectional view of memory 10 and / or SRAM circuitry 90.

[0029] Figure 5A and Figure 5B This is a partial or overall schematic diagram of an SRAM cell 200 according to various aspects of the present invention. In particular, Figure 5A This is a top view of SRAM cell 200, and Figure 5B It is along Figure 5A A schematic cross-sectional view of the SRAM cell 200 of line AA. Figure 6A to Figure 6E It is according to various aspects of the present invention Figure 5A and Figure 5B The top-view plan view of each layer of the SRAM cell 200. For example, Figure 6A This is a top plan view of conductive components in the device layer (DL), contact layer (CO), and via zero (V0) layer (e.g., DL / CO / V0) of a portion or entirely of an SRAM cell 200 according to various aspects of the present invention. Figure 6B This is a top plan view of conductive components in the V0 layer, metal layer (M1) and via layer (V1) (e.g., V0 / M1 / V1) of a portion or all of an SRAM cell 200 according to various aspects of the present invention. Figure 6Cis a top plan view of conductive features in a V1 layer, a metal two (M2) layer, and a via two (V2) layer (e.g., V1 / M2 / V2) of a portion or all of SRAM cell 200 according to various aspects of the present application; Figure 6D is a top plan view of conductive features in a V2 layer, a metal three (M3) layer, and a via three (V3) layer (e.g., V2 / M3 / V3) of a portion or all of SRAM cell 200 according to various aspects of the present application; and Figure 6E is a top plan view of conductive features in a M3 layer, a V3 layer, and a metal four (M4) layer (e.g., M3 / V3 / M4) of a portion or all of SRAM cell 200 according to various aspects of the present application. The CO layer connects the device layer to the V0 layer, the V0 layer connects the CO layer to the M1 layer, the V1 layer connects the M1 layer to the M2 layer, the V2 layer connects the M2 layer to the M3 layer, and the V3 layer connects the M3 layer to the M4 layer. SRAM cell 200 can be implemented in memory 10 of Figure 1 In some embodiments, the components of SRAM cell 200 are configured to provide an SRAM circuit such as depicted in Figure 2 and / or Figure 3 For clarity, the Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E have been simplified to better understand the inventive concept of the present application. Additional components can be added in SRAM cell 200, and some of the components described below can be replaced, modified, or eliminated in other embodiments of SRAM cell 200.

[0030] SRAM cell 200 has a cell boundary MC having a first dimension along a first direction (e.g., an x-pitch along an x-direction) such as a cell width W and a second dimension along a second direction (e.g., a y-pitch along a y-direction) such as a cell height H. In some embodiments, such as depicted, the cell width W is greater than the cell height H. For example, the ratio of the cell width W to the cell height H is greater than 1. When SRAM cell 200 is repeated in a memory array such as memory array 12, the cell width W can represent and be referred to as a memory cell pitch in the memory array along the x-direction, and the cell height H can represent and be referred to as a memory cell pitch in the memory array along the y-direction.

[0031] The device layer includes device components and / or device components, such as a substrate (wafer) 202, an n-well 204 disposed in the substrate 202, p-wells 206A and 206B disposed in the substrate 202, fins 210A-210F (also referred to as fin structures or active fin regions) disposed above and / or extending from the substrate 202, isolation components 215 disposed in and / or above the substrate 202, gate structures 220A-220D disposed above the substrate 202 and the isolation components 215, and epitaxial source / drain components 230A-230J. The fins 210A-210F are oriented substantially parallel to each other and extend longitudinally along the y-direction (i.e., length is defined in the y-direction, width is defined in the x-direction, and height is defined in the z-direction), and the gate structures 220A-220D are oriented substantially parallel to each other and extend longitudinally along the x-direction (i.e., length is defined in the x-direction, width is defined in the y-direction, and height is defined in the z-direction, such that the orientation of the gate structures 220A-220D is substantially orthogonal to the fins 210A-210F). The gate structure 220A wraps around a first channel region of the fin 210A and a first channel region of the fin 210B, and is disposed between an epitaxial source / drain component 230A and an epitaxial source / drain component 230B, both of which are disposed above and / or in source / drain regions of the fin 210A and the fin 210B. The gate structure 220B wraps around a second channel region of the fin 210A, a second channel region of the fin 210B, and a channel region of the fin 210C, is disposed between the epitaxial source / drain component 230B and an epitaxial source / drain component 230C, both of which are disposed above and / or in the source / drain regions of the fin 210A and the fin 210B, and is disposed between an epitaxial source / drain component 230D and an epitaxial source / drain component 230E, both of which are disposed above and / or in the source / drain regions of the fin 210C. The gate structure 220C wraps around a channel region of the fin 210D, a first channel region of the fin 210E, and a first channel region of the fin 210F, is disposed between an epitaxial source / drain component 230F and an epitaxial source / drain component 230G, both of which are disposed above and / or in the source / drain regions of the fin 210D, and is disposed between an epitaxial source / drain component 230H and an epitaxial source / drain component 230I, both of which are disposed above and / or in the source / drain regions of the fin 210E and the fin 210F.The gate structure 220C also wraps around the end regions of the fin 210C, such that the gate structure 220C is disposed adjacent to the epitaxial source / drain component 230D. The gate structure 220D wraps around the second channel regions of the fin 210E and the second channel regions of the fin 21 OF, and is disposed between the epitaxial source / drain component 230I and the epitaxial source / drain component 230J, both of which are disposed over and / or in the source / drain regions of the fin 210E and the fin 21 OF. The gate structures 220A-220D engage the respective channel regions of the fins 210A-210F, such that current can flow between the respective epitaxial source / drain components 230A-230J and / or the respective source / drain regions of the fins 210A-210F during operation. Each of the gate structures 220A-220D includes a metal gate stack and a gate spacer. For example, the gate structure 220A has a metal gate stack that includes a gate dielectric 222A, a gate electrode 224A, and a hardmask 226A and a gate spacer 228A disposed along the sidewalls of the metal gate stack.

[0032] Device components and / or device parts at the device layer are combined to form electronic devices. For example, SRAM cell 200 includes six transistors formed at the device layer from device components and / or device parts, such as passgate transistor PG-1, passgate transistor PG-2, pull-up transistor PU-1, pull-up transistor PU-2, pull-down transistor PD-1, and pull-down transistor PD-2. Pull-down transistor PD-1 and passgate transistor PG-1 are multi-fin FinFETs (including, for example, fin 210A and fin 210B disposed over and electrically connected to p-well 206A), pull-up transistor PU-1 is a single-fin FinFET (including, for example, fin 210C disposed over and electrically connected to n-well 204), pull-up transistor PU-2 is a single-fin FinFET (including, for example, fin 210D disposed over and electrically connected to n-well 204), and pull-down transistor PD-2 and passgate transistor PG-2 are multi-fin FinFETs (including, for example, fin 210E and fin 210F disposed over and electrically connected to p-well 206B). Passgate transistor PG-1 has a gate (e.g., gate structure 220A) disposed between a source (e.g., epitaxial source / drain part 230B) and a drain (e.g., epitaxial source / drain part 230A). Pull-down transistor PD-1 has a gate (e.g., gate structure 220B) disposed between a source (e.g., epitaxial source / drain part 230C) and a drain (e.g., epitaxial source / drain part 230B). Pull-up transistor PU-1 has a gate (e.g., gate structure 220B) disposed between a source (e.g., epitaxial source / drain part 230E) and a drain (e.g., epitaxial source / drain part 230D). Pull-up transistor PU-2 includes a gate (e.g., gate structure 220C) disposed between a source (e.g., epitaxial source / drain part 230F) and a drain (e.g., epitaxial source / drain part 230G). Pull-down transistor PD-2 includes a gate (e.g., gate structure 220C) disposed between a source (e.g., epitaxial source / drain part 230H) and a drain (e.g., epitaxial source / drain part 230I). Passgate transistor PG-2 includes a gate (e.g., gate structure 220D) disposed between a source (e.g., epitaxial source / drain part 230I) and a drain (e.g., epitaxial source / drain part 230J). The source / drain of pull-down transistor PD-1, PD-2, passgate transistor PG-1, PG-2, and / or pull-up transistor PU-1, PU-2 is also formed from a respective source / drain region of fin 210A-210F below epitaxial source / drain part 230A-230J.With such a configuration, pull-down transistor PD-1 and pull-up transistor PU-1 share a gate (i.e., the gate of pull-down transistor PD-1 and the gate of pull-up transistor PU-1 are formed by respective portions of gate structure 220B), pull-down transistor PD-2 and pull-up transistor PU-2 share a gate (i.e., the gate of pull-down transistor PD-2 and the gate of pull-up transistor PU-2 are formed by respective portions of gate structure 220C), pass gate transistor PG-1 and pull-down transistor PD-1 share an epitaxial source / drain component 230B (i.e., the source of pass gate transistor PG-1 and the drain of pull-down transistor PD-1 are formed by epitaxial source / drain component 230B), and pass gate transistor PG-2 and pull-down transistor PD-2 share an epitaxial source / drain component 230I (i.e., the source of pass gate transistor PG-2 and the drain of pull-down transistor PD-2 are formed by epitaxial source / drain component 230I). In the depicted embodiment, pull-up transistors PU-1, PU-2 are configured as p-type FinFETs, and pull-down transistors PD-1, PD-2 and pass gate transistors PG-1, PG-2 are configured as n-type FinFETs. In some embodiments, fins 210A, 210B, 210E, and 210F are p-doped (e.g., p-doped silicon fins); fins 210C and 210D are n-doped (e.g., n-doped silicon fins); epitaxial source / drain components 230A-230C and 230H-230J are n-doped (e.g., silicon or carbon-silicon epitaxial sources / drains doped with phosphorus, arsenic, and / or other n-type dopants); and epitaxial source / drain components 230D-230G are p-doped (e.g., silicon-germanium epitaxial sources / drains doped with boron, indium, and / or other p-type dopants).

[0033] The CO layer includes conductive components, such as source / drain contacts 250A- 250H (collectively, device-level contacts), that connect the device layer to conductive components of the VO layer, such as gate via 260A, gate via 260B, abutment gate contact 265A, and abutment gate contact 265B, and source / drain vias 270A-270F. Source / drain contact 250A is between and physically contacts and connects epitaxial source / drain component 230A and source / drain via 270A. Source / drain contact 250B physically contacts and connects epitaxial source / drain component 230B and abutment gate contact 265B. Source / drain contact 250B is also between and physically contacts and connects epitaxial source / drain component 230E and abutment gate contact 265B. Source / drain contact 250C is between and physically contacts and connects epitaxial source / drain component 230C and source / drain via 270B. Source / drain contact 250D is between and physically contacts and connects epitaxial source / drain component 230F and source / drain via 270C. Source / drain contact 250E is between and physically contacts and connects epitaxial source / drain component 230E and source / drain via 270D. Source / drain contact 250F is between and physically contacts and connects epitaxial source / drain component 230H and source / drain via 270E. Source / drain contact 250G is between and physically contacts and connects epitaxial source / drain component 230G and abutment gate contact 265A. Source / drain contact 250G also physically contacts and connects epitaxial source / drain component 230I and abutment gate contact 265A. Source / drain contact 250H is between and physically contacts and connects epitaxial source / drain component 230J and source / drain via 270F. Abutment gate contact 265A physically contacts gate structure 220B (e.g., the gate electrode of gate structure 220B) and source / drain contact 250G, such that gate structure 220B is electrically connected to epitaxial source / drain component 230G and epitaxial source / drain component 230I through abutment gate contact 265A and source / drain contact 250G.The abutment gate contact 265B physically contacts the gate structure 220C (e.g., the gate electrode of the gate structure 220C) and the source / drain contact 250B, such that the gate structure 220C is electrically connected to the epitaxial source / drain component 230D and the epitaxial source / drain component 230B through the abutment gate contact 265B and the source / drain contact 250B. With such a contact layer configuration, the source / drain contact 250B electrically connects the drain of the pull-down transistor PD-1 and the drain of the pull-up transistor PU-1, such that the common drain of the pull-down transistor PD-1 and the pull-up transistor PU-1 can provide the storage node SN, which is electrically connected to the gate of the pull-up transistor PU-2 and the gate of the pull-down transistor PD-2 through the abutment gate contact 265B. In addition, the source / drain contact 250G electrically connects the drain of the pull-down transistor PD-2 and the drain of the pull-up transistor PU-2, such that the common drain of the pull-down transistor PD-2 and the pull-up transistor PU-2 forms the storage node SNB, which is electrically connected to the gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 through the abutment gate contact 265A and the source / drain contact 250G.

[0034] The conductive portions of the CO layer, the Ml layer, the M2 layer, the M3 layer, and the M4 layer are routed along a first routing direction or a second routing direction different from the first routing direction. For example, the first routing direction is the x-direction (and is substantially parallel to the longitudinal direction of the gate structures 220A-220D), and the second routing direction is the y-direction (and is substantially parallel to the longitudinal direction of the fins 210A-210F). In the depicted embodiment, the source / drain contacts 250A-250H have a longitudinal (lengthwise) direction that is substantially along the x-direction (i.e., the first routing direction), and the landing gate contacts 265A, 265B have a longitudinal direction that is substantially along the y-direction (i.e., the second routing direction). In other words, the longest dimension (e.g., length) of the source / drain contacts 250A-250H is along the x-direction, and the longest dimension of the landing gate contacts 265A, 265B is along the y-direction. The source / drain contacts 250A-250H and the landing gate contacts 265A, 265B are substantially rectangular (i.e., each has a length that is greater than its width), but the present application contemplates that the source / drain contacts 250A-250H and / or the landing gate contacts 265A, 265B have different shapes and / or combinations of shapes to optimize and / or improve performance (e.g., lower resistance) and / or layout footprint (e.g., lower density). The source / drain contact 250A spans the fin 210A and the fin 210B; the source / drain contact 250B spans the fin 210A, the fin 210B, and the fin 210C; the source / drain contact 250C spans the fin 210A and the fin 210B; the source / drain contact 250D spans the fin 210D; the source / drain contact 250E spans the fin 210C; the source / drain contact 250F spans the fin 210E and the fin 210F; the source / drain contact 250G spans the fin 210D, the fin 210E, and the fin 210F; and the source / drain contact 250H spans the fin 210E and the fin 210F. In the depicted embodiment, the source / drain contact 250A, the source / drain contact 250D, and the source / drain contact 250F overlap the upper edge of the cell boundary MC, and the source / drain contact 250C, the source / drain contact 250E, and the source / drain contact 250H overlap the lower edge of the cell boundary MC. In some embodiments, the source / drain contact 250A, the source / drain contact 250D, and the source / drain contact 250F overlap two memory cells, such as the SRAM cell 200 and a memory cell directly above and adjacent to the upper edge of the SRAM cell 200. In some embodiments, the source / drain contact 250C, the source / drain contact 250E, and the source / drain contact 250H overlap two memory cells, such as the SRAM cell 200 and a memory cell directly below and adjacent to the lower edge of the SRAM cell 200.In a further described embodiment, the source / drain contact 250C also overlaps with the left edge of the cell boundary MC, and the source / drain contact 250F also overlaps with the right edge of the cell boundary MC. In some embodiments, the source / drain contact 250C overlaps with a third memory cell, such as a memory cell directly adjacent to the left edge of the SRAM cell 200, and / or the source / drain contact 250F overlaps with a third memory cell, such as a memory cell directly adjacent to the right edge of the SRAM cell 200.

[0035] Conductive components of the V0 layer (such as gate vias 260A, 260B, and source / drain vias 270A-270F) connect the CO layer to conductive components of the M1 layer, such as bit line 280A, anti-phase line 280B, and are electrically connected to a first voltage (e.g., a positive power supply voltage, such as V). DD The first voltage line (e.g., V) DD Word line 280C), word line bonding pads (e.g., word line bonding pad 280D (WL LP1)) and word line bonding pad 280E (WL LP2) corresponding to the word lines of SRAM cell 200, and electrically connected to a second voltage (e.g., ground voltage, such as V). SS The voltage line bonding pads corresponding to the second voltage line of the SRAM cell 200 (e.g., the first V) SS 280F bonding pad (first V) SS LP1)) and are also electrically connected to a second voltage (e.g., V). SS The voltage line bonding pad corresponding to the third voltage line of the SRAM cell 200 (e.g., the second V) SS 280G bonding pad (second V) SS LP1). A source / drain via 270A is located between source / drain contact 250A and bit line 280A, physically contacting both source / drain contact 250A and bit line 280A, and connecting source / drain contact 250A to bit line 280A. A source / drain via 270F is located between source / drain contact 250H and anti-phase line 280B, physically contacting both source / drain contact 250H and anti-phase line 280B, and connecting source / drain contact 250H to anti-phase line 280B. A source / drain via 270C is located between source / drain contact 250D and V... DD Between line 280C, physical contact source / drain contacts 250D and V DD Line 280C and connect source / drain contacts 250D to V. DD Line 280C, and source / drain via 270D is located between source / drain contact 250E and V. DDbetween lines 280C, physically contacts the source / drain contact 250E, and connects the source / drain contact 250E to V DD between lines 280C, physically contacts the source / drain contact 250E, and connects the source / drain contact 250E to V DD between lines 280C. With such a configuration, the drain of the pass gate transistor PG-1 is electrically connected to the bit line 280A through the source / drain contact 250A and the source / drain via 270A, the drain of the pass gate transistor PG-2 is electrically connected to the inverted bit line 280B through the source / drain contact 250H and the source / drain via 270F, the source of the pull-up transistor PU-1 is electrically connected to V DD between lines 280C, and the source of the pull-up transistor PU-2 is electrically connected to V DD between lines 280C. The gate via 260A is located between the gate structure 220A (e.g., a gate electrode thereof) and the word line bond pad 280D, physically contacts the gate structure 220A and the word line bond pad 280D, and connects the gate structure 220A to the word line bond pad 280D. The gate via 260B is located between the gate structure 220D (e.g., a gate electrode thereof) and the word line bond pad 280E, physically contacts the gate structure 220D and the word line bond pad 280E, and connects the gate structure 220D to the word line bond pad 280E. The source / drain via 270B is located between the source / drain contact 250C and the first V SS bond pad 280F, physically contacts the source / drain contact 250C and the first V SS bond pad 280F, and connects the source / drain contact 250C to the first V SS bond pad 280F. The source / drain via 270E is located between the source / drain contact 250F and the second V SS bond pad 280G, physically contacts the source / drain contact 250F and the second V SS bond pad 280G, and connects the source / drain contact 250F to the second V SS bond pad 280G.

[0036] The VI layer includes conductive components, such as vias 285A-285D, that connect conductive components of the Ml layer to conductive components of the M2 layer, such as the first word line 290A, a voltage line bond pad (e.g., a first V SS bond pad 290B (a first V SS LP2 corresponding to a second voltage line), and a voltage line bond pad (e.g., a second V SS bond pad 290C (a second V SSThe via 285A is between the word line bond pad 280D and the word line 290A, physically contacts the word line bond pad 280D and the word line 290A, and connects the word line bond pad 280D to the word line 290A, and the via 285B is between the word line bond pad 280E and the word line 290A, physically contacts the word line bond pad 280E and the word line 290A, and connects the word line bond pad 280E to the word line 290A. With such a configuration, the gate of the pass gate transistor PG-1 is electrically connected to the word line 290A through the gate via 260A, the word line bond pad 280D, and the via 285A, and the gate of the pass gate transistor PG-2 is electrically connected to the word line 290A through the gate via 260B, the word line bond pad 280E, and the via 285B. The via 285C is between the first V SS bond pad 280F and the first V SS line 300A, physically contacts the first V SS bond pad 280F and the first V SS line 300A, and connects the first V SS bond pad 280F to the first V SS line 300A, and the via 295B is between the second V SS bond pad 280G and the second V SS line 300B, physically contacts the second V SS bond pad 280G and the second V SS line 300B, and connects the second V SS bond pad 280G to the second V SS line 300B.

[0037] The V2 layer includes conductive components, such as vias 295A-295C, that connect the conductive components of the M2 layer to the conductive components of the M3 layer, such as the first V SS line 300A, the second V SS line 300B, and the word line bond pad 300C (WL LP3). The V3 layer includes conductive components, such as a via 305, that connect the conductive components of the M3 layer to the conductive components of the M4 layer, such as the second word line 310. The via 295A is between the first V SS bond pad 290B and the first V SS line 300A, physically contacts the first V SS bond pad 290B and the first V SS line 300A, and connects the first V SS bond pad 290B to the first V SS line 300A, and the via 295B is between the second V SS bond pad 290C and the second V SSbetween the line 300B, physically contacts the second V SS the bonding pad 290C and the second V SS the line 300B and connects the second V SS the bonding pad 290C is connected to the second V SS the line 300B. With such a configuration, the source of the pull-down transistor PD-1 is electrically connected to the ground voltage and / or the reference voltage, such as V SS the bonding pad 280F, the via 285A, the first V SS the bonding pad 290B and the via 295A are electrically connected to the first V SS the line 300A, and the source of the pull-down transistor PD-2 is electrically connected to the ground voltage and / or the reference voltage, such as V SS the bonding pad 280G, the via 285D, the second V SS the bonding pad 290C and the via 295B are electrically connected to the second V SS the line 300B, so that the source of the pull-down transistor PD-1 and the source of the pull-down transistor PD-2 are both electrically connected to the ground voltage and / or the reference voltage, such as V SS The via 295C is located between the first word line 290A and the word line bonding pad 300C, physically contacts the first word line 290A and the word line bonding pad 300C and connects the first word line 290A to the word line bonding pad 300C, and the via 305 is located between the word line bonding pad 300C and the second word line 310, physically contacts the word line bonding pad 300C and the second word line 310 and connects the word line bonding pad 300C to the second word line 310. With such a configuration, the first word line 290A is electrically connected to the second word line 310 through the via 295C, the word line bonding pad 300C and the via 305, so that the gate of the pass gate transistor PG-1 and the gate of the pass gate transistor PG-2 are electrically connected to the first word line 290A and the second word line 310.

[0038] In the SRAM cell 200, the metal lines of the odd metal layers (i.e., the M1 layer and the M3 layer) are routed along the y direction (i.e., the second routing direction), and the metal lines of the even metal layers (i.e., the M2 layer and the M4 layer) are routed along the x direction (i.e., the first routing direction). For example, the bit line 280A, the inverted bit line 280B, the V DD the line 280C, the word line bonding pad 280D, the word line bonding pad 280E, the first V SS the bonding pad 280F and the second V SS the bonding pad 280G has a longitudinal direction substantially along the y direction; the first word line 290A, the first V SS the bonding pad 290B and the second V SSThe bond pad 290C has a longitudinal direction substantially along the x-direction; the first V SS line 300A, the second V SS line 300B, and the word line bond pad 300C have a longitudinal direction substantially along the y-direction; and the second word line 310 has a longitudinal direction substantially along the x-direction. In other words, the bit line 280A, the inverted bit line 280B, the V DD line 280C, the word line bond pad 280D, the word line bond pad 280E, the first V SS bond pad 280F, the second V SS bond pad 280G, the first V SS line 300A, the second V SS line 300B, and the word line bond pad 300C have a longitudinal direction substantially along the y-direction; and the second word line 310 has a longitudinal direction substantially along the x-direction. In other words, the bit line 280A, the inverted bit line 280B, the V SS bond pad 290B, the second V SS bond pad 290C, and the second word line 310 have a longitudinal direction along the x-direction. The metal lines of the Ml layer, the M2 layer, the M3 layer, and the M4 layer are substantially rectangular (i.e., each has a length greater than its width), but the present invention contemplates that the Ml layer, the M2 layer, the M3 layer, and / or the M4 layer have different shapes and / or combinations of shapes to optimize and / or improve performance (e.g., reduce resistance) and / or layout footprint (e.g., reduce density).

[0039] A "bond pad" generally refers to a metal line in a metal layer that provides intermediate local interconnections for the SRAM cell 200, such as (1) intermediate local interconnections between a device-level component (e.g., a gate or a source / drain) and a bit line (e.g., the bit line 280A and / or the inverted bit line 280B), a word line (e.g., the first word line 290A and / or the second word line 310), or a voltage line (e.g., the V DD line 280C, the first V SS line 300A, and / or the second V SS line 300B) or (2) intermediate local interconnections between a bit line, a word line, or a voltage line. For example, the first word line 290A in the M2 layer is connected to the gates of the pass gate transistors PG-1, PG-2 in the device layer DL through the word line bond pad 280D (in the Ml layer) and the word line bond pad 280E (in the Ml layer), respectively; the first V SS line 300A is connected to the source of the pull-down transistor PD-1 in the device layer DL through the first V SS bond pad 290B (in the M2 layer) and the first V SS bond pad 280F (in the Ml layer); the second V SS line 300B is connected to the drain of the pull-down transistor PD-1 in the device layer DL through the second V SSbonding pad 290C (in the M2 layer) and the second V SS bonding pad 280G (in the M1 layer) is connected to the source of the pull-down transistor PD-2 in the device layer DL; and the second word line 310 of the M4 layer is connected to the first word line 290A in the M2 layer through the word line bonding pad 300C (in the M3 layer). The bonding pads of the SRAM cell 200 have a longitudinal dimension that is large enough to provide sufficient bonding area for the vias above them (and thus to minimize the coverage issue and to provide greater patterning flexibility) and smaller than the longitudinal dimension of the bit lines, word lines, and / or voltage lines of the SRAM cell 200. In the depicted embodiment, the dimensions of the bonding pads of the SRAM cell 200 are smaller than the dimensions of the SRAM cell 200, such as smaller than the dimension along the x-direction of the cell width W and smaller than the dimension along the y-direction of the cell height H, while the dimensions of the bit lines, word lines, and voltage lines of the SRAM cell 200 are larger than the dimensions of the SRAM cell 200, such as larger than the dimension along the x-direction of the cell width W and / or larger than the dimension along the y-direction of the cell height H. For example, in the M1 layer, the bit line 280A, the inverted bit line 280B, and the V DD line 280C have a length along the y-direction that is greater than the cell height H, while the word line bonding pad 280D, the word line bonding pad 280E, the first V SS bonding pad 280F, and the second V SS bonding pad 280G have a length along the y-direction that is smaller than the cell height H. In another example, in the M2 layer, the first word line 290A has a length along the x-direction that is greater than the cell width W, while the first V SS bonding pad 290B, and the second V SS bonding pad 290C have a length along the x-direction that is smaller than the cell width W. In yet another example, in the M3 layer, the first V SS line 300A, and the second V SS line 300B have a length along the y-direction that is greater than the cell height H, while the word line bonding pad 300C has a length along the y-direction that is smaller than the cell height H. In some embodiments, the length of the bit line 280A and / or the length of the inverted bit line 280B is sufficient to allow multiple SRAM cells in a column to be electrically connected to the bit line 280A and / or the inverted bit line 280B. In some embodiments, the length of the V DD line 280C is sufficient to allow multiple SRAM cells in a column to be electrically connected to the V DD line 280C. In some embodiments, the length of the first word line 290A and / or the length of the second word line 310 is sufficient to allow multiple SRAM cells in a row to be electrically connected to the first word line 290A and / or the second word line 310. In some embodiments, the length of the first V SS line 300A and / or the length of the second V SSThe length of the line 300B is sufficient to allow multiple SRAM cells in a column to be electrically connected to the first V SS The line 300A and / or the second V SS The line 300B.

[0040] As SRAM cell sizes are scaled down to implement SRAM cells with faster operating speeds on scaled IC technology nodes (such as 20 nm nodes to 10 nm nodes to 3 nm nodes and below), bit line capacitance and / or bit line resistance have become important factors affecting SRAM performance. For example, scaling down SRAM cell sizes should result in reduced resistance-capacitance (RC) delay, which generally represents a delay in the speed of electrical signals through an IC due to the product of resistance (R), which is the impedance of a material to the flow of electrical current, and capacitance (C), which is the ability of a material to store electrical charge. However, as SRAM cell sizes are scaled down (and SRAM cell densities are increased), it has been observed that bit line capacitance and / or bit line resistance increase as bit line size and / or bit line pitch decrease, undesirably increasing RC delay and reducing SRAM speed, such as write / read speed. A tradeoff between bit line capacitance and bit line resistance must therefore be considered to optimize SRAM performance. For example, as bit line capacitance increases with the number of interconnects (e.g., contacts, vias, and / or metal lines) between the bit line and device layers, and routing density generally increases as the metallization level of the MLI component decreases (i.e., routing density of Ml layers is greater than routing density of M2 layers or routing density of M3 layers), bit lines placed in the lowest metallization layer of the MLI component (i.e., Ml layers) can reduce bit line capacitance, but increase bit line resistance (e.g., only one via is needed to connect the bit line and the drain of the pass gate transistor, but a narrower and / or thinner bit line is needed to meet higher routing specifications), while bit lines placed in higher metallization levels of the MLI component (e.g., M2 layers or M3 layers) can increase bit line capacitance but reduce bit line resistance (e.g., by requiring more than one via and at least one landing pad to connect the bit line and the drain of the pass gate transistor, but allowing a wider and / or thicker bit line to meet routing density specifications that are lower than the routing density specifications of Ml layers).

[0041] The SRAM cell 200 addresses these challenges by placing the bit lines (here, bit line 280A and inverted bit line 280B) in the Ml layer, which is the lowest metallization layer of the MLI component above the substrate 202, to minimize bit line capacitance, and configuring the bit lines as the widest metal lines of the Ml layer to minimize bit line resistance. For example, each of the bit line 280A and the inverted bit line 280B has a width Wl, the first V DD The line 280C has a width W2, each of the word line landing pad 280D and the word line landing pad 280E has a width W3, and the first V SSbonding pad 280F and a second V SS Each of bonding pad 280G has a width W4, where width Wl is the widest, maximum width of the metal lines in the Ml layer, and width W2, width W3, and width W4 are each less than width Wl. In some embodiments, the ratio of width Wl to width W2 (i.e., Wl :W2) is about 1.1 to about 2, the ratio of width Wl to width W3 (i.e., Wl :W3) is about 1.1 to about 2, and / or the ratio of width Wl to width W4 (i.e., Wl :W4) is about 1.1 to about 2. Bitline / other Ml line width ratios less than about 1.1 can not provide bitlines with a width that is sufficiently wide to reduce bitline resistance, thereby reducing SRAM performance, such as write capability (e.g., higher bitline resistance results in worse (i.e., greater) bitline IR drop), while bitline / other Ml line width ratios greater than about 2 can provide bitlines with a width that increases bitline resistance (i.e., the bitlines are too wide) and / or can impact cell size (i.e., a larger cell size can be needed to address the greater width ratio), both of which reduce SRAM performance, such as read speed. In some embodiments, the ratio of width Wl to width W2 is about 1.1 to about 1.4, the ratio of width Wl to width W3 is about 1.1 to about 1.4, and / or the ratio of width Wl to width W4 (i.e., Wl :W4) is about 1.1 to about 1.4 to optimize SRAM performance. In the further depicted embodiments, V DD Line 280C has the smallest width of the metal lines in the Ml layer of SRAM cell 200 (i.e., width W2 is also less than width W3 and width W4). In some embodiments, width W2 is greater than width W3 and / or width W4. In some embodiments, width W2 is substantially the same as width W3 and / or width W4. Width W3 is greater than, less than, or substantially equal to width W4. In some embodiments, word line bonding pad 280D and word line bonding pad 280E have different widths. In some embodiments, first V SS Bonding pad 280F and a second V SS Bonding pad 280G has different widths.

[0042] By placing bit line 280A and inverted bit line 280B in the Ml layer to reduce bit line capacitance, while configuring bit line 280A and inverted bit line 280B as the widest metal lines of the Ml layer to reduce bit line resistance, SRAM cell 200 is provided with optimized electrical characteristics and SRAM cell density compared to conventional SRAM cells. In some embodiments, the bit line resistance reduction provided by configuring bit line 280A and / or inverted bit line 280B as the widest metal lines of the Ml layer reduces bit line IR drop (i.e., the voltage drop across the bit line when current flows through the bit line), which increases SRAM read / write speed and / or reduces the minimum operating voltage (Vmin For example, during a write operation, such as when writing a logic 0 to a memory node SN, the transmission gate transistor PG-1 needs to dominate the pull-up transistor PU-1 to cause the voltage on the bit line BL(0) to drop, rather than remaining at the supply voltage V. DD Bit lines with a large IR drop reduce the drive capability of the transmission gate transistor PG-1, thus requiring a higher minimum operating voltage. In contrast, because bit lines 280A and / or anti-phase lines 280B are placed and configured within the SRAM cell 200 to exhibit minimal resistance, bit lines 280A and / or anti-phase lines 280B exhibit a lower IR drop than those observed in the bit lines of a conventional SRAM cell, thereby improving SRAM performance.

[0043] The vias of the SRAM cell 200 (such as gate via 260A, gate via 260B, source / drain vias 270A-270F, vias 285A-285D, vias 295A-295C, and via 305) are substantially square and / or circular (i.e., each dimension along the x-direction is substantially the same as its dimension along the y-direction). The vias of the SRAM cell 200 may have different sizes, different shapes, and / or combinations of sizes and / or shapes to optimize and / or improve performance (e.g., reduce resistance) and / or layout footprint (e.g., reduce the density and / or size of the SRAM cell 200). In the depicted embodiment, the V of the SRAM cell 200... SS The corresponding source / drain vias (such as source / drain vias 270B and 270E) are substantially rectangular and / or elliptical (i.e., the dimension D1 along the x-direction of each is different from the dimension D2 along the y-direction) to reduce the interconnection structure from the source of pull-down transistors PD-1 and PD-2 to the M1 layer (i.e., connecting the epitaxial source / drain component 230C to the first V). SS The source / drain contact 250C and source / drain via 270B of the bonding pad 280F are connected, and the epitaxial source / drain component 230H is connected to the second V. SS The contact resistance associated with the source / drain contact 250F and source / drain via 270E of the bonding pad 280G. This source / drain via can also be referred to as a slot via. In some embodiments, the ratio of size D1 to size D2 (i.e., D1:D2) is about 1.5 to about 3. A ratio less than about 1.5 is associated with V... SS The ratio of the longest to the shortest source / drain via corresponding to the line provides a circular or near-circular shape for the source / drain via, which increases resistance and / or negatively impacts critical dimensional accuracy. A ratio greater than approximately 3 with V SSThe ratio of the longest dimension / shortest dimension of the source / drain via corresponding to the bit line can negatively impact the bit line width. For example, as the dimension Dl increases to provide a longest dimension / shortest dimension ratio of the source / drain via 270B, 270E greater than about 3, the source / drain via 270B, 270E will begin to extend into and overlap the bit line region / area of the Ml layer, such as the region / area where the bit line 280A and the inverted bit line 280B are located within the Ml layer. The bit line width (e.g., width Wl) will thus undesirably decrease to accommodate the longest dimension / shortest dimension ratio greater than about 3, for example, to prevent undesired electrical connections of the source / drain via 270B and the bit line 280A and / or the source / drain via 270E and the inverted bit line 280B. Furthermore, when the longest dimension / shortest dimension ratio is greater than about 3, the width of the Ml landing pad, such as the first V SS landing pad 280F and the second V SS landing pad 280G can be increased to ensure proper electrical connection or improved coverage of the Ml landing pad and the source / drain via 270B, 270E, which can also require undesirably decreasing the bit line width. A longest dimension / shortest dimension ratio of the source / drain via less than about 3 thus minimizes the source / drain via resistance while accommodating the bit line width, such as disclosed herein, maximizes the bit line resistance reduction. In some embodiments, the V SS line corresponding source / drain contact, such as the source / drain contact 250C and the source / drain contact 250F, is also configured with a length to width ratio that can further reduce the contact resistance associated with the interconnect structure from the source of the pull-down transistor PD-1, PD-2 to the Ml layer. For example, the ratio of the length along the x-direction of the source / drain contact 250C and / or the source / drain contact 250F to the width along the y-direction of the source / drain contact 250C and / or the source / drain contact 250F (i.e., L / W) is greater than about 3. In some embodiments, adjacent SRAM cells can share interconnects, such as the source / drain contact (e.g., the source / drain contact 250C and the source / drain contact 250F) corresponding to the V SS line. In such embodiments, the length to width ratio of the source / drain contact corresponding to the V SS line can not extend to the cell boundary MC shared with the adjacent SRAM cell. In some embodiments, the length to width ratio of the source / drain contact corresponding to the V SS line is greater than about 3. In such embodiments, the length to width ratio of the source / drain contact corresponding to the V SSThe length / width ratio of the source / drain contacts corresponding to the lines can ensure that the source / drain contacts 250C, 250F extend beyond the cell boundary MC into the adjacent SRAM cell.

[0044] The present disclosure contemplates various arrangements of vias and metal lines for the SRAM cell 200. In the depicted embodiment, the bit line 280A, the inverted bit line 280B, and the V DD The line 280C spans the cell height H and overlaps and extends beyond the upper and lower edges of the cell boundary MC; the first word line 290A in the M2 layer spans the cell width W and overlaps and extends beyond the left and right edges of the cell boundary MC; the first V SS The line 300A and the second V SS The line 300B spans the cell height H and overlaps and extends beyond the upper and lower edges of the cell boundary MC; and the second word line 310 in the M4 layer spans the cell width W and overlaps and extends beyond the left and right edges of the cell boundary MC. In such embodiments, the bit line 280A, the inverted bit line 280B, the V DD The line 280C, the first V SS The line 300A and the second V SS The line 300B can overlap with three memory cells, such as the SRAM cell 200, an SRAM cell located directly above and adjacent to the SRAM cell 200, and an SRAM cell located directly below and adjacent to the SRAM cell 200. In such embodiments, the first word line 290A and the second word line 310 can overlap with three memory cells, such as the SRAM cell 200, an SRAM cell located directly to the left of and adjacent to the SRAM cell 200, and an SRAM cell located directly to the right of and adjacent to the SRAM cell 200. In further described embodiments, the source / drain via 270A, the source / drain via 270C, the source / drain via 270E, the second V SS The landing pad 280G, the via 285D, the second V SS The landing pad 290C and the via 295B overlap with the upper edge of the cell boundary MC; the source / drain via 270B, the source / drain via 270D, the source / drain via 270F, the first V SS The landing pad 280F, the via 285C, the first V SS The landing pad 290B and the via 295A overlap with the lower edge of the cell boundary MC; the gate via 260A, the source / drain via 270B, the word line landing pad 280D, the first V SS The landing pad 280F, the via 285A, the first V SSBond pad 290B and via 295A overlap the left edge of cell boundary MC; and gate via 260B, source / drain via 270E, word line bond pad 280E, second V SS Bond pad 280G, via 285B, second V SS Bond pad 290C and via 295B overlap the right edge of cell boundary MC. In such embodiments, source / drain via 270A and source / drain via 270C can overlap two memory cells, such as SRAM cell 200 and an SRAM cell located directly above and adjacent to SRAM cell 200; source / drain via 270D and source / drain via 270F can overlap two memory cells, such as SRAM cell 200 and an SRAM cell located directly below and adjacent to SRAM cell 200; gate via 260A, word line bond pad 280D, and via 285A can overlap two memory cells, such as SRAM cell 200 and an SRAM cell located directly to the left of and adjacent to SRAM cell 200; and gate via 260B, word line bond pad 280E, and via 285B can overlap two memory cells, such as SRAM cell 200 and an SRAM cell located directly to the right of and adjacent to SRAM cell 200. In such embodiments, source / drain via 270E, second V SS Bond pad 280G, via 285D, second V SS Bond pad 290C and via 295B can overlap four memory cells, such as SRAM cell 200, an SRAM cell located directly to the right of and adjacent to SRAM cell 200, an SRAM cell located directly above and adjacent to SRAM cell 200, and an SRAM cell directly diagonal to and adjacent to SRAM cell 200 (e.g., an SRAM cell sharing a cell boundary with the SRAM cell directly to the right and the SRAM cell directly above). In such embodiments, source / drain via 270B, first V SS Bond pad 280F, via 285C, first V SSThe bond pad 290B and the via 295A can overlap with four memory cells, such as the SRAM cell 200, an SRAM cell directly to the left of the SRAM cell 200 and adjacent to the SRAM cell 200, an SRAM cell directly below the SRAM cell 200 and adjacent to the SRAM cell 200, and an SRAM cell directly diagonal to the SRAM cell 200 and adjacent to the SRAM cell 200 (e.g., an SRAM cell sharing a cell boundary with the SRAM cell directly to the left and the SRAM cell directly below).

[0045] Configuring the SRAM cell 200 with a dual word line structure (i.e., a first word line 290A in the M2 layer and a second word line 310 in the M4 layer, both electrically connected to the pass gate transistor PG-1 and the pass gate transistor PG-2) can further optimize SRAM performance by reducing word line resistance compared to a single word line structure. In some embodiments, it has been observed that two parallel and electrically connected together metal word lines can reduce word line resistance by at least 50%. For example, if the resistance of the first word line 290A in the M2 layer is 1X and the resistance of the second word line 310 in the M4 layer is 0.8X, then stacking and connecting the first word line 290A in the M2 layer with the second word line 310 in the M4 layer to provide a dual word line structure can provide an equivalent word line resistance of approximately 0.444X (e.g., 1 / (1 / 1 + 1 / 0.8)X ~ 0.444X). The interconnect structure between the first word line 290A and the second word line 310 (here formed by the via 295C, the word line bond pad 300C, and the via 305) is referred to hereinafter as a word line strip, a word line strip module, and / or a word line pick-up region. In the depicted embodiment, the SRAM cell 200 includes a single word line strip in a central region of the SRAM cell 200 above the V DD line 280C. In some embodiments, the SRAM cell 200 includes multiple word line strips connecting the first word line 290A and the second word line 310. In some embodiments, the word line strip is not located in the SRAM cell 200, but is located in an SRAM cell that shares the dual word line structure with the SRAM cell 200. For example, in the case that the SRAM cell 200 is incorporated into a memory array having SRAM cells arranged in rows and columns, the word line strip can be located in an SRAM cell in the same row as the SRAM cell 200. This is depicted in Figure 7 , Figure 7 is a partial diagrammatic plan view of an SRAM-based memory 400 having a dual word line structure in accordance with various aspects of the present application. For clarity and simplicity, Figure 1 the memory 100 in Figure 7 the memory 400 in Figure 7In this configuration, memory array 12 is a 4×8 SRAM array (i.e., four columns, eight rows), wherein each row has four SRAM cells 200 between a pair of edge cells 30, and each column has eight SRAM cells 200 between a pair of edge cells 30. Each row of SRAM cells 200 shares a first word line, such as a first word line 290A at layer M2, and a second word line, such as a second word line 310 at layer M4, wherein each row has a word line located in at least one SRAM cell 200 (i.e., bit cell) of the row and a word line located in at least one edge cell 30 of the row. For example, each of rows R1-R8 has a corresponding word line 410A located in one of its SRAM cells 200 (i.e., the four SRAM cells 200 in the row share the first word line, the second word line, and the corresponding word line 410A) and a corresponding word line 410B located in one of its edge cells 30. In the depicted embodiments, each of rows R1-R8 has a corresponding word line 410B located in two corresponding edge units 30. In embodiments with more than four SRAM units 200 per row, word lines can be formed and shared by every four SRAM units in a row, every eight SRAM units in a row, or other numbers of SRAM units in a row. In some embodiments, word lines 410A are arranged in different columns. In some embodiments, word lines 410A are arranged in the same column. Figure 7 In the memory array 12, column C1 has one word line 410A, column C2 has two word lines 410A, column C3 has three word lines 410A, and column C4 has two word lines 410A, wherein the word lines 410A are not directly adjacent to SRAM cells 200 along the y-direction. This invention contemplates any configuration of the word lines 410A in the memory array 12. For clarity, a simplified representation has been provided. Figure 7 To better understand the inventive concept of the present invention, additional components may be added to the memory 400, and some of the aforementioned components may be replaced, modified, or eliminated in other embodiments of the memory 400.

[0046] With single V SS Compared to the linear structure, the configuration has a double V SS The line-structured SRAM cell 200 can reduce V SS Line resistance is used to further optimize SRAM performance. In some embodiments, similar to a double-word line structure, two parallel and electrically connected metal V lines have been observed. SS The line can connect V SS Line resistance is reduced by at least 50%. Figure 8A to Figure 8C It is according to various aspects of the invention having a double V SS Top-view diagrams of each layer of a line-structured SRAM-based memory. Figure 8Ais a top plan view of conductive components in the M2 layer, V2 layer, M3 layer, V3 layer, and M4 layer (e.g., M2 / V2 / M3 / V3 / M4) of a portion or entirety of an SRAM-based memory according to various aspects of the present application; Figure 8B is a top plan view of conductive components in the M2 layer, V2 layer, and M3 layer (e.g., M2 / V2 / M3) of a portion or entirety of an SRAM-based memory according to various aspects of the present application; and Figure 8C is a top plan view of conductive components in the M3 layer, V3 layer, and M4 layer (e.g., M3 / V3 / M4) of a portion or entirety of an SRAM-based memory according to various aspects of the present application. For clarity, some components have been simplified Figure 8A to Figure 8C to better understand the inventive concepts of the present application. Additional components can be added in the SRAM-based memory, and some of the components described below can be replaced, modified, or eliminated in other embodiments of the SRAM-based memory.

[0047] In Figure 8A to Figure 8CIn this diagram, SRAM cell 200 is part of a memory array, which also includes SRAM cells 200-1, 200-2, 200-3, 200-4, 200-5, 200-6, and 200-7, each of which can be configured similarly to SRAM cell 200. Two adjacent columns (e.g., column N and column N+1, where N is the number of columns in the memory array) and four adjacent rows (e.g., row M, row M+1, row M+2, and row M+3, where M is the number of rows in the memory array) are depicted, with SRAM cell 200 located at row M and column N. The M2 layer includes a first word line 290A of SRAM cell 200, which extends continuously along row M such that the first word line 290A is shared by SRAM cell 200 and SRAM cell 200-4; a first word line 290D, which extends continuously along row M+1 such that the first word line 290D is shared by SRAM cell 200-1 and SRAM cell 200-5; a first word line 290E, which extends continuously along row M+2 such that the first word line 290E is shared by SRAM cell 200-2 and SRAM cell 200-6; and a first word line 290F, which extends continuously along row M+3 such that the first word line 290F is shared by SRAM cell 200-3 and SRAM cell 200-7. With this configuration, each SRAM cell in the memory array has a corresponding first word line (e.g., first word line 290A, first word line 290D, first word line 290E, or first word line 290F). The first word line is electrically connected to the gate of the corresponding pull-down transistor PD-1 and the gate of the corresponding pull-down transistor PD-2 through a corresponding first word line interconnect structure located below the M2 layer. The first word line interconnect structure includes a gate via in the V0 layer, a word line bonding pad in the M1 layer, and a via in the V1 layer.

[0048] The M3 layer includes the first V of SRAM cell 200. SS Line 300A, first V SS Line 300A extends continuously along the y-direction, making the first V SS Line 300A is shared by the SRAM cells of column N (here, SRAM cell 200, SRAM cell 200-1, SRAM cell 200-2 and SRAM cell 200-3); the second V of SRAM cell 200 SS Line 300B, second V SS Line 300B extends continuously along the y-direction, making the second V SSLine 300B is shared by SRAM cells in column N and SRAM cells in column N+1 (here, SRAM cells 200-4, 200-5, 200-6, and 200-7); and the first VSS line 300D extends continuously along the y-direction, such that the first VSS line... SS Line 300D is shared by the SRAM cells in column N+1. Second V SS Line 300B overlaps with the interface between the cell boundaries of the SRAM cells in column N and the cell boundaries of the SRAM cells in column N+1. With this configuration, each SRAM cell of the memory array has a V-shaped interface below layer M3. SS The interconnect structure is electrically connected to the source of the corresponding pull-down transistor PD-1 and the source of the corresponding pull-down transistor PD-2, respectively, via the corresponding first V. SS Line (e.g., the first V) SS Line 300A or first V SS Line 300D) and the corresponding second V SS Line (e.g., the second V) SS Line 300B), where each V SS The interconnect structure includes source / drain contacts in the CO layer, source / drain vias in the V0 layer, and a first V in the M1 layer. SS Bonding pads, vias in layer V1, and the second V in layer M2 SS Joining pads and vias in layer V2. Figure 8A to Figure 8C The text describes the V layer from M2 to V2. SS Parts of the interconnect structure, such as the first V shared by SRAM cell 200 and SRAM cell 200-1 SS Interconnection structure, first V SS The interconnect structure includes a first V SS Bonding pad 290B (first V) SS LP2) and via 295A; the second V shared by SRAM cell 200 and SRAM cell 200-4 SS Interconnection structure, second V SS The interconnect structure includes a second V SS Bonding pad 290C (second V) SS LP2) and via 295B; the first V shared by SRAM cell 200-2 and SRAM cell 200-3 SS Interconnection structure, first V SS The interconnect structure includes a first V SS 290G bonding pad (first V) SS LP2) and via 295D; the second V shared by SRAM cell 200-3 and SRAM cell 200-7 SS Interconnection structure, second VSS interconnect structure includes a second V SS bonding pad 290H (second V SS interconnect structure, a first V SS interconnect structure, first V SS interconnect structure includes a first V SS bonding pad 290I (first V SS interconnect structure, a second V SS interconnect structure, second V SS interconnect structure includes a second V SS bonding pad 290J (second V SS interconnect structure, a first V SS interconnect structure, first V SS interconnect structure includes a first V SS bonding pad 290K (first V SS interconnect structure, a first V

[0049] The M4 layer includes a second word line 310 of the SRAM cell 200 that extends continuously along row M such that the second word line 310 is shared by the SRAM cell 200 and the SRAM cell 200-4; a second word line 310A that extends continuously along row M+1 such that the second word line 310A is shared by the SRAM cell 200-1 and the SRAM cell 200-5; a second word line 310B that extends continuously along row M+2 such that the second word line 310B is shared by the SRAM cell 200-2 and the SRAM cell 200-6; and a second word line 310C that extends continuously along row M+3 such that the second word line 310C is shared by the SRAM cell 200-3 and the SRAM cell 200-7. With such a configuration, each SRAM cell of the memory array has a respective second word line (e.g., the second word line 310, the second word line 310A, the second word line 310B, or the second word line 310C) electrically connected to a respective first word line (e.g., the first word line 290A, the first word line 290D, the first word line 290E, or the first word line 290F) through a word line bar between the M2 layer and the M4 layer, each word line bar including a via in the V2 layer, a word line bonding pad in the M3 layer, and a via in the V3 layer. In Figure 8A to Figure 8CIn this configuration, word lines are shared by SRAM cells 200 and 200-4, and include via 295C, word line bonding pad 300C, and via 305; word lines are shared by SRAM cells 200-1 and 200-5, and include via 295I, word line bonding pad 300E, and via 305A; word lines are shared by SRAM cells 200-2 and 200-6, and include via 295J, word line bonding pad 300F, and via 305B; and word lines are shared by SRAM cells 200-3 and 200-7, and include via 295K, word line bonding pad 300G, and via 305C. Word line bonding pads 300E, 300F, and 300G form a portion of the M3 layer. Through-holes 305A, 305B, and 305C form the portion of layer V3.

[0050] To provide a power grid for the memory, each SRAM cell also has a third V in the M4 layer. SS Line, third V SS The line is connected to its corresponding first V. SS Line and its corresponding second V SS Line. For example, the M4 layer includes a third V. SS Line 320, third V SS Line 320 is electrically connected to the first VSS via the VSS trap bar (here, through-hole 305D). SS 300A line, via V SS The trap bar (here, through-hole 305E) is electrically connected to the first V. SS Line 300D, and through V SS The trap bar (here, through-hole 305F) is electrically connected to the second V. SS Line 300B. Through-holes 305D, 305E, and 305F form part of the V3 layer. Through-holes 305D-305E are used to connect the V3 layer in the M3 layer. SS Line (e.g., the first V) SS Line 300A, Second V SS Line 300B and the first V SS Line 300D) interconnects to V in M4 layer SS Line (e.g., the third V) SS Line 320) provides double V SS Wire structure (also known as power grid), double V SS Linear structure can reduce V SS Line resistance. Third V SS Line 320 is routed along the x-direction (i.e., the first route direction) and extends continuously, making the third V... SSThe longitudinal direction of line 320 is substantially along the x-direction (and substantially parallel to the second word line of layer M4). In the depicted embodiment, the third V SS Line 320 overlaps with the interface between the cell boundaries of the SRAM cells in row M+1 and the cell boundaries of the SRAM cells in row M+2, and is shared by eight SRAM cells (i.e., SRAM cells 200, 200-1, 200-2, 200-3, 200-4, 200-5, 200-6, and 200-7). In a further embodiment depicted, the third V SS Line 320 is located between the second letter line 310A and the second letter line 310B, making the third V SS Line 320 is arranged between every two second letter lines. In some embodiments, the third V SS Lines are placed between each pair of second word lines, each pair of second word lines, each four second word lines, each eight second word lines, or other numbers of second word lines. In some embodiments, four SRAM cells in a column (e.g., column N or column N+1) share a third V. SS Line. In some embodiments, two SRAM cells in a column share a third V. SS Line. In some embodiments, another number of SRAM cells in the column share a third V. SS Line. In the depicted embodiment, the third V SS The width of line 320 is smaller than the width of the second letter line. In some embodiments, the third V SS Line 320 has the narrowest metal wire in the M4 layer. In some embodiments, the third V SS The width of line 320 is greater than the width of the second character line.

[0051] In some embodiments, the SRAM cell 200 is fabricated on the same wafer as the logic cell (typically referred to as a standard cell). In such embodiments, the M1 layer of the SRAM cell 200 and the M1 layer of the logic cell can be configured to optimize SRAM performance and logic density (co-optimization). For example, Figure 9A This is a top plan view of the conductive components in the M1 layer of the SRAM cell 200, which is part or all of the invention, according to various aspects of the present invention, and along... Figure 9A A cross-sectional view of the conductive components in the M1 layer of SRAM cell 200 of line AA, and Figure 9B This is a top plan view of the conductive components in the M1 layer of a logic cell, representing a portion or the entirety of the present invention, and along... Figure 9BA cross-sectional view of a conductive feature in the M1 layer of a logic cell of line A-A. The logic cell has a cell boundary LC having a first dimension along a first direction, such as a cell width CW (e.g., an x-pitch along the x-direction), and a second dimension along a second direction, such as a cell height CH (e.g., a y-pitch along the y-direction). In some embodiments, such as depicted, the cell width CW is less than the cell width W, and the cell height CH is greater than the cell height H. The M1 layer of the logic cell includes metal lines electrically connected to the device layer, such as V DD line 410A, V SS line 410B, metal line 410C, metal line 410D, metal line 410E, and metal line 410F. The device layer of the logic cell includes transistors, such as NFETs and PFETs, a gate of each transistor disposed between a source and a drain, where the M1 layer of the logic cell is electrically connected to at least one gate, at least one source, and / or at least one drain of the transistors. In some embodiments, the gates of the transistors of the logic cell extend longitudinally along the same direction as the gates in the SRAM cell 200 (i.e., the x-direction), and the metal lines of the M1 layer of the logic cell have a routing direction substantially perpendicular to the longitudinal direction of the gates (i.e., the y-direction). In some embodiments, the metal lines of the M1 layer of the logic cell are electrically connected to the gates of the transistors of the device layer of the logic cell. DD line 410A, V SS line 410B, and metal lines 410C-410F extend longitudinally along the y-direction). The metal lines 410C-410F (also referred to as intra-cell M1 lines) have a pitch P, which is the minimum (smallest) pitch of the metal lines in the M1 layer of the logic cell. The metal lines (e.g., V DD line 410A, V SS line 410B, and metal lines 410C-410F) have a thickness T1 along the z-direction. The thickness T1 is greater than the pitch P to reduce and minimize the electrical resistance of the metal lines of the M1 layer in the logic cell. In some embodiments, the ratio of the thickness T1 to the pitch P (i.e., T1:P) is about 1.05 to about 2. A thickness / pitch ratio less than about 1.05 can not provide the desired reduction in metal resistance, while a thickness / pitch ratio greater than about 2 can provide a metal height-to-width ratio (i.e., the ratio of the metal thickness to the metal width) that is too large for seamless integration with conventional contact damascene fabrication processes. The metal lines of the M1 layer of the SRAM cell 200 (e.g., bit line 280A, inverted bit line 280B, V DD line 280C, word line bond pad 280D, word line bond pad 280E, first V SS bond pad 280F, and / or second V SSThe bonding pad 280F has a thickness T2 along the z-direction. In some embodiments, the thickness T2 is substantially the same as the thickness T1 to reduce the resistance in the M1 layer of the SRAM cell 200. In such embodiments, the M1 layer of the SRAM cell 200 and the M1 layer of the logic cell can be fabricated simultaneously, wherein in some embodiments, any difference between the thickness T2 and the thickness T1 that may be caused by loading effects (such as loading effects associated with etching, planarization, etc.) is less than about 10%. In some embodiments, the thickness T2 is less than the minimum pitch of the metal lines in the M1 layer of the SRAM cell 200. In some embodiments, the thickness T2 is greater than the minimum pitch of the metal lines in the M1 layer of the SRAM cell 200. In some embodiments, the thickness T2 is substantially the same as the minimum pitch of the metal lines in the M1 layer of the SRAM cell 200. For clarity, simplified... Figure 9A and Figure 9B To better understand the inventive concept of the present invention, additional components may be added to the SRAM cell 200 and / or logic cell, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the SRAM cell 200 and / or logic cell.

[0052] In some embodiments, cleavage steps can be added to the layout of the SRAM cell 200 to further optimize SRAM performance by increasing the cross-sectional area of ​​portions of the metal lines in layers M1 to M4 and thereby reducing the resistance of these metal lines. For example, V at layer M1 can be... DD Add a clef to the first word line at the line and / or M2 layer, such that it is similar to the V line with a substantially uniform width along its length. DD Compared to the first letter line, V DD The line and / or the first word line have varying widths along their length and exhibit lower resistance (due to their larger cross-sectional area). Figure 10 This is a top plan view of a portion or the entire SRAM cell 500 according to various aspects of the present invention, the SRAM cell 500 having a V-shaped width of varying width. DD Lines and letter lines. Figure 11A to Figure 11E It is according to various aspects of the present invention Figure 10 Various top-view plans of each layer of the SRAM cell 500. For example, Figure 11A This is a top plan view of conductive components in the device layer, CO layer, and VO layer (e.g., DL / CO / V0) of a portion or entirely of an SRAM cell 500 according to various aspects of the present invention. Figure 11B This is a top plan view of conductive components in the V0, M1 and V1 layers (e.g., V0 / M1 / V1) of a portion or all of an SRAM cell 500 according to various aspects of the present invention. Figure 11Cis a top plan view of conductive components in the V1 layer, M2 layer, and V2 layer (e.g., V1 / M2 / V2) of a portion or the entirety of the SRAM cell 500 according to various aspects of the present application; Figure 11D is a top plan view of conductive components in the V2 layer, M3 layer, and V3 layer (e.g., V2 / M3 / V3) of a portion or the entirety of the SRAM cell 500 according to various aspects of the present application; and Figure 11E is a top plan view of conductive components in the M3 layer, V3 layer, and M4 layer (e.g., M3 / V3 / M4) of a portion or the entirety of the SRAM cell 500 according to various aspects of the present application. For clarity and simplicity, Figure 5A , Figure 5B and Figure 6A to Figure 6E The SRAM cell 200 in Figure 10 and Figure 11A to Figure 11E is similar to the SRAM cell 500 in Figure 1 and / or the memory 400 in Figure 7 In some embodiments, the components of the SRAM cell 500 are configured to provide an SRAM circuit, such as depicted in Figure 2 and / or Figure 3 In some embodiments, the SRAM cell 500 is configured to have a power grid, such as depicted and described with reference to Figure 8A to Figure 8C and / or to have dimensions relative to logic cells, such as depicted and described with reference to Figure 9A and Figure 9B For clarity, the Figure 10 and Figure 11A to Figure 11E have been simplified to better understand the inventive concepts of the present application. Additional components can be added in the SRAM cell 500, and some of the components described below can be replaced, modified, or eliminated in other embodiments of the SRAM cell 500.

[0053] In Figure 10 and Figure 11A to Figure 11E The SRAM cell 500 includes a V DD line 580C in the M1 layer formed by a bar portion 582A having a width W2 corresponding to the V DD line 280C designed in the SRAM cell 200, a step portion 582B having a width W5 corresponding to a step added to a V DD line of an SRAM design layout of the SRAM cell (e.g., for the SRAM cell 200), and a V DDThe secant of the line corresponds to a secant portion 582C with a width W6. In some embodiments, widths W5 and W6 are the same. In some embodiments, widths W5 and W6 are different. For V DD The interconnect region (area) of the lines is increased by adding kerf steps to increase the cross-sectional area of ​​the interconnect region, thereby reducing V. DD The resistance of the line. In the depicted embodiment, the cleavage portion 582B has a V at the upper edge of the cell boundary MC. DD The interconnection area at the end of line 580C provides a V with a width of W7 (i.e., the sum of widths W2 and W5). DD Line 580C, and the secant portion 582C at the lower edge of the element boundary MC at V. DD The interconnection area at the end of line 580C provides a V with a width of W8 (i.e., the sum of widths W2 and W6). DD Line 580C. Widths W7 and W8 are both greater than width W2. In some embodiments, widths W7 and W8 are the same. In some embodiments, widths W7 and W8 are different. In a further embodiment depicted, widths W7 and W8 are both less than width W1 to ensure that bit line 280A and anti-phase line 280B have the maximum width of the metal lines in layer M1. Increase V DD The cross-sectional area of ​​the interconnecting region of the lines allows for an increase in V DD The cross-sectional area of ​​the source / drain vias in the V0 layer, where the lines connect to the source / drain contacts (and thus to the underlying source / drain regions). For example, SRAM cell 500 may include substantially rectangular and / or elliptical (i.e., each dimension D3 along the x-direction is different from the dimension D4 along the y-direction) source / drain vias 570C (instead of source / drain via 270C) and 570D (instead of source / drain via 270D) to reduce the cross-sectional area of ​​the source / drain vias from the sources of pull-up transistors PU-1, PU-2 to the V0 layer. DD The contact resistance associated with the interconnect structure of line 580C. This source / drain via can also be referred to as a slot via. In some embodiments, the ratio of size D3 to size D4 (i.e., D3:D4) is about 1.1 to about 2. A ratio less than about 1.1 corresponds to V... DD The ratio of the longest to the shortest source / drain via length may not provide the desired via resistance reduction, while a ratio greater than approximately 2 corresponds to V... DD The longest / shortest dimension ratio of the source / drain via can be too large and negatively impact the width of adjacent bit lines (e.g., by requiring a wider V). DD Line width and / or thinner bit line width to accommodate larger source / drain vias).

[0054] The SRAM cell 500 also includes a first word line 590A in the M2 layer formed by a bar portion 592A having a width W9 corresponding to the first word line 290A designed in the SRAM cell 200, a step portion 592B having a width W10 corresponding to a step added to the first word line of the SRAM design layout of the SRAM cell (e.g., for the SRAM cell 200), and a step portion 592C having a width W11 corresponding to a step added to the first word line of the SRAM design layout of the SRAM cell. In some embodiments, the width W10 and the width W11 are the same. In some embodiments, the width W10 and the width W11 are different. The step to the first word line increases the cross-sectional area of the interconnect region to decrease the resistance of the first word line and reduce word line delay. In the depicted embodiment, the step portion 592B extends from a first end of the bar portion 592A along a top of the length of the bar portion 592A, the step portion 592C extends from an opposite second end of the bar portion 592A along a bottom of the length of the bar portion 592A, and both the step portion 592B and the step portion 592C extend to overlap a central portion of the bar portion 592A. This configuration provides the first word line 590A with a central portion having a width W12 (i.e., the sum of the width W9, the width W10, and the width W11), end portions having a width W13 (i.e., the sum of the width W9 and the width W10) at end interconnect regions of the first word line 590A located at left edges of the cell boundary MC, and end portions having a width W14 (i.e., the sum of the width W9 and the width W11) at end interconnect regions of the first word line 590A located at right edges of the cell boundary MC. The width W13 and the width W14 are each less than the width W12, such that the central portion of the first word line 590A is wider than the end portions (e.g., cell boundary portions) of the first word line 590A. In some embodiments, the width W13 and the width W14 are the same. In some embodiments, the width W13 and the width W14 are different. In some embodiments, the width ratio of the central width (i.e., the width W12) to the edge width (i.e., the width W13 and / or the width W14) is about 1.1 to about 2. A central width / edge width ratio less than about 1.1 can not provide a desired reduction in word line resistance (e.g., the reduction in word line resistance can be negligible), and a central width / edge width ratio greater than about 2 can provide a central width that is too wide to provide sufficient isolation of the word line between adjacent metal lines and / or adjacent metal lines in the M2 layer (i.e., insufficient metal isolation margin).

[0055] The various conductive components (such as contacts, vias, and / or metal wires) of the MLI components described herein may include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, other low-resistivity metals, alloys thereof, or combinations thereof. In some embodiments, the conductive material of the conductive component of the V0 layer differs from the conductive material of the conductive component of the M1 layer. For example, the conductive component of the M1 layer includes copper, while the conductive component of the V0 layer includes tungsten or ruthenium. In some embodiments, the conductive material of the conductive component of the V0 layer is the same as the conductive material of the conductive component of the M1 layer. In some embodiments, the various layers of the MLI component described herein (such as CO layer, V0 layer, M1 layer, V1 layer, M2 layer, V2 layer, M3 layer, V3 layer, and / or M4 layer) may be fabricated by the following steps: depositing a dielectric layer (e.g., ILD layer and / or CESL) over a substrate; performing photolithography and etching processes to form one or more openings in the dielectric layer, the openings exposing one or more conductive components in the underlying layer; filling the one or more openings with a conductive material; and performing a planarization process to remove excess conductive material, such that the conductive components and the dielectric layer have substantially flat surfaces. The conductive material is formed by a deposition process (e.g., PVD, CVD, ALD, or other suitable deposition process) and / or an annealing process. In some embodiments, the conductive component includes a body layer (also referred to as a conductive plug). In some embodiments, the conductive component includes a barrier layer, an adhesive layer, and / or other suitable layers disposed between the body layer and the dielectric layer. In some embodiments, the barrier layer, adhesive layer, and / or other suitable layers include titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other suitable components, or combinations thereof. In some embodiments, the via layer (e.g., V0 layer) and metallization layer (e.g., M1 layer) of the MLI component can be formed by a single damascene or dual damascene process.

[0056] This invention provides many different embodiments. This document discloses configurations of metal layers in interconnect structures that can improve memory performance (such as SRAM memory performance) and / or logic performance. For example, embodiments herein place bit lines in an M1 layer, which is the bottommost metallization layer of the interconnect structure for memory cells, to minimize bit line capacitance, and configure the bit lines as the widest metal lines in the metal layer to minimize bit line resistance. In some embodiments, the interconnect structure has a dual word line structure to reduce word line resistance. In some embodiments, the interconnect structure has a dual voltage line structure to reduce voltage line resistance. In some embodiments, kerfs are added to the word lines and / or voltage lines to reduce their respective resistance. In some embodiments, the via shapes of the interconnect structure are configured to reduce the resistance of the interconnect structure.

[0057] An exemplary integrated circuit structure includes a memory cell connected to a bit line, an inverted bit line, a first voltage line to receive a first voltage, a word line, and a second voltage line to receive a second voltage different from the first voltage. The integrated circuit structure also includes an interconnect structure disposed above the memory cell. The interconnect structure includes the bit line, the inverted bit line, the first voltage line, the word line, and the second voltage line. The bit line, the inverted bit line, the first voltage line, and the second voltage line extend along a first longitudinal direction. The word line extends along a second longitudinal direction different from the first longitudinal direction. The interconnect structure has a bottommost metal layer having a metal line connected to the memory cell. The metal line includes the bit line, the first voltage line, a voltage line bond pad connected to the second voltage line, and a word line bond pad connected to the word line. A width of the bit line is a widest width of the metal line. In some embodiments, the width of the bit line is a first width, the first voltage line has a second width, and a ratio of the first width to the second width is about 1.1 to about 2 (in some embodiments, about 1.1 to about 1.4). In some embodiments, the width of the bit line is a first width, the voltage line bond pad has a second width, and a ratio of the first width to the second width is about 1.1 to about 2 (in some embodiments, about 1.1 to about 1.4). In some embodiments, the width of the bit line is a first width, the word line bond pad has a second width, and a ratio of the first width to the second width is about 1.1 to about 2 (in some embodiments, about 1.1 to about 1.4). In some embodiments, the width of the bit line is a first width, the metal line further includes the inverted bit line, the inverted bit line has a second width, and the second width is the same as the first width. In some embodiments, the first voltage line has a first portion and a second portion, the first portion has a first width, and the second portion has a second width greater than the first width. The second portion having the second width is an interconnect region of the first voltage line. In some embodiments, the integrated circuit structure further includes a logic cell connected to a third voltage line to receive a third voltage, wherein the interconnect structure includes the third voltage line extending along the first longitudinal direction, the metal line of the bottommost metal layer includes the third voltage line, and a first thickness of the bit line is the same as a second thickness of the third voltage line.

[0058] In some embodiments, the bottommost metal layer is a first metal layer and the metal lines are first metal lines, and the interconnect structure further has a second metal layer above the first metal layer and a third metal layer above the second metal layer, where the second metal layer has second metal lines including word lines and the third metal layer has third metal lines including second voltage lines. In such embodiments, the word lines can be first word lines, the word line bond pads can be first word line bond pads, and the third metal lines of the third metal layer can further include second word line bond pads connected to the first word lines. In such embodiments, the interconnect structure can further have a fourth metal layer above the third metal layer, where the fourth metal layer has fourth metal lines including second word lines, and the second word lines are connected to the second word line bond pads. In some embodiments, the memory cell further includes a third voltage line to receive a second voltage, the interconnect structure has a fourth metal layer above the third metal layer, the fourth metal layer has fourth metal lines including the third voltage line, and the third voltage line is connected to the second voltage line.

[0059] Another exemplary integrated circuit structure includes a memory cell and an interconnect structure disposed above the memory cell and electrically connected to the memory cell. The interconnect structure includes a first metal layer electrically connected to the memory cell, a second metal layer disposed above the first metal layer, a third metal layer disposed above the second metal layer, and a fourth metal layer disposed above the third metal layer. The first metal layer includes a bit line, a first voltage line configured to receive a first voltage, a first voltage line bond pad, and a first word line bond pad. The second metal layer includes a first word line electrically connected to the first word line bond pad and a second voltage line electrically connected to the first voltage line bond pad. The third metal layer includes a second voltage line electrically connected to the second voltage line, where the second voltage line is configured to receive a second voltage. The fourth metal layer includes a second word line. The bit line, the first voltage line, and the second voltage line extend along a first longitudinal direction, the first word line and the second word line extend along a second longitudinal direction different from the first longitudinal direction, and a first width of the bit line is greater than a second width of the first voltage line. In some embodiments, the first width of the bit line is greater than a third width of the first voltage line bond pad and a fourth width of the first word line bond pad. In some embodiments, the first metal layer further includes an inverted bit line extending along the first longitudinal direction, where a third width of the inverted bit line is greater than the second width of the first voltage line. In some embodiments, the third width of the inverted bit line is the same as the first width of the bit line. In some embodiments, the second word line is electrically connected to the first word line. In some embodiments, the integrated circuit structure further includes an edge cell, where the second word line is electrically connected to the first word line through a first connection in the memory cell and a second connection in the edge cell. In some embodiments, the fourth metal layer further includes a third voltage line configured to receive the second voltage. In some embodiments, the third voltage line is electrically connected to the second voltage line.

[0060] An exemplary method for forming a multilayer interconnect structure of a memory includes forming a first metallization layer including bit lines, inverted bit lines, and a first voltage line configured to receive a first voltage. The bit lines, inverted bit lines, and first voltage line extend along a first routing direction, the first metallization layer is a bottommost metallization layer of the multilayer interconnect structure, and a bit line width of the bit lines has a widest width of metal lines of the first metallization layer. The method also includes forming a second metallization layer above the first metallization layer. The second metallization layer includes first word lines extending along a second routing direction different from the first routing direction. The method also includes forming a third metallization layer above the second metallization layer. The third metallization layer includes second voltage lines and third voltage lines configured to receive a second voltage different from the first voltage, and the second voltage lines and third voltage lines extend along the first routing direction. The method also includes forming a fourth metallization layer disposed above the third metal layer. The fourth metallization layer includes second word lines extending along the second routing direction. In some embodiments, a ratio of the bit line width to a width of any one of the metal lines of the first metallization layer is about 1.1 to about 2 (in some embodiments, about 1.4).

[0061] The foregoing summary of features of several embodiments enables one of ordinary skill in the art to better understand the aspects of the present application. It should be understood by those of ordinary skill in the art that they can readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present application, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present application.

Claims

1. An integrated circuit structure, comprising: a memory cell connected to a bit line, an inverted bit line, a first voltage line for receiving a first voltage, a word line, and a second voltage line for receiving a second voltage different from the first voltage; and an interconnect structure disposed above the memory cell, wherein: the interconnect structure includes the bit line, the inverted bit line, the first voltage line, the word line, and the second voltage line, wherein the bit line, the inverted bit line, the first voltage line, and the second voltage line extend along a first longitudinal direction, and the word line extends along a second longitudinal direction different from the first longitudinal direction, the interconnect structure has a bottommost metal layer having a metal line connected to the memory cell, wherein the metal line includes the bit line, the first voltage line, a voltage line bond pad connected to the second voltage line, and a word line bond pad connected to the word line, and wherein a width of the bit line is a widest width of the metal line, wherein the bottommost metal layer is a first metal layer and the metal line is a first metal line, the interconnect structure has a second metal layer above the first metal layer and a third metal layer above the second metal layer, wherein the second metal layer has a second metal line including the word line, and the third metal layer has a third metal line including the second voltage line, wherein the word line is a first word line, the word line bond pad is a first word line bond pad, the third metal line of the third metal layer includes a second word line bond pad connected to the first word line, the interconnect structure has a fourth metal layer above the third metal layer, and the fourth metal layer has a fourth metal line including a second word line, wherein the second word line is connected to the second word line bond pad. a width of the bit line is a first width, the first voltage line has a second width, and a ratio of the first width to the second width is 1.1 to 2.

2. The integrated circuit structure of claim 1, wherein, a width of the bit line is a first width, the voltage line bond pad has a second width, and a ratio of the first width to the second width is 1.1 to 2.

3. The integrated circuit structure of claim 1, wherein, a width of the bit line is a first width, the word line bond pad has a second width, and a ratio of the first width to the second width is 1.1 to 2.

4. The integrated circuit structure of claim 1, wherein, a width of the bit line is a first width, the metal line further includes the inverted bit line, the inverted bit line has a second width, and the second width is the same as the first width.

5. The integrated circuit structure of claim 1, wherein, the first voltage line has a first portion and a second portion, the first portion has a first width, the second portion has a second width greater than the first width, wherein the second portion having the second width is an interconnect region of the first voltage line.

6. The integrated circuit structure of claim 1, wherein, 7. The integrated circuit structure of claim 1, wherein: the memory cell is a static random access memory cell. the static random access memory cell is a single port static random access memory cell.

8. The integrated circuit structure of claim 7, wherein, ​ 9. The integrated circuit structure of claim 7, wherein, The static random access memory cell is a dual-port static random access memory cell.

10. The integrated circuit structure of claim 1, further comprising: a logic cell connected to a third voltage line for receiving a third voltage; and wherein the interconnect structure includes the third voltage line extending along the first longitudinal direction, the metal line of the bottommost metal layer includes the third voltage line, and a first thickness of the bit line is the same as a second thickness of the third voltage line.

11. An integrated circuit structure, comprising: a memory cell; and an interconnect structure disposed above and electrically connected to the memory cell, wherein the interconnect structure includes: a first metal layer electrically connected to the memory cell, wherein the first metal layer includes a bit line, a first voltage line configured to receive a first voltage, a first voltage line bond pad, and a first word line bond pad, a second metal layer disposed above the first metal layer, wherein the second metal layer includes a first word line electrically connected to the first word line bond pad and a second voltage line bond pad electrically connected to the first voltage line bond pad, a third metal layer disposed above the second metal layer, wherein the third metal layer includes a second voltage line electrically connected to the second voltage line bond pad, wherein the second voltage line is configured to receive a second voltage, a fourth metal layer disposed above the third metal layer, wherein the fourth metal layer includes a second word line, and wherein the bit line, the first voltage line, and the second voltage line extend along a first longitudinal direction, the first word line and the second word line extend along a second longitudinal direction different from the first longitudinal direction, and a first width of the bit line is greater than a second width of the first voltage line.

12. The integrated circuit structure of claim 11, wherein, The first width of the bit line is greater than a third width of the first voltage line bond pad and a fourth width of the first word line bond pad.

13. The integrated circuit structure of claim 11, wherein, The first metal layer further includes an inverted bit line extending along the first longitudinal direction, wherein a third width of the inverted bit line is greater than the second width of the first voltage line.

14. The integrated circuit structure of claim 13, wherein, The third width of the inverted bit line is the same as the first width of the bit line.

15. The integrated circuit structure of claim 11, wherein, The second word line is electrically connected to the first word line.

16. The integrated circuit structure of claim 15, further comprising an edge cell, wherein, The second word line is electrically connected to the first word line through a first connection in the memory cell and a second connection in the edge cell.

17. The integrated circuit structure of claim 11, wherein, The fourth metal layer further includes a third voltage line configured to receive the second voltage.

18. The integrated circuit structure of claim 17, wherein, The third voltage line is electrically connected to the second voltage line.

19. A method for forming a multi-layer interconnect structure for a memory, comprising: forming a first metallization layer including a bit line, an inverted bit line, and a first voltage line configured to receive a first voltage, wherein the bit line, the inverted bit line, and the first voltage line extend along a first routing direction, the first metallization layer is a bottommost metallization layer of the multi-layer interconnect structure, and a bit line width of the bit line has a widest width of metal lines in the first metallization layer; forming a second metallization layer over the first metallization layer, wherein the second metallization layer includes first word lines extending along a second routing direction different from the first routing direction; forming a third metallization layer over the second metallization layer, wherein the third metallization layer includes second and third voltage lines configured to receive a second voltage different from the first voltage, and the second and third voltage lines extend along the first routing direction; and forming a fourth metal layer disposed over the third metallization layer, wherein the fourth metal layer includes second word lines extending along the second routing direction.

20. The method for forming a multilayer interconnect structure of a memory of claim 19, wherein, The ratio of the bit line width to the width of any one metal line of the first metallization layer is 1.1 to 2.

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