Cmos image sensor and method of forming the same

Abstract

A CMOS image sensor and a forming method thereof, wherein the forming method of the CMOS image sensor comprises: forming a substrate, a plurality of light-doped layers on the substrate, an isolation layer on the light-doped layers, and an active layer on the isolation layer, the substrate comprising a plurality of mutually separated pixel regions, each of the light-doped layers being located on each of the pixel regions; forming electrical devices in and on the active layer; and forming an interconnection structure in the isolation layer and the active layer, the interconnection structure electrically connecting the light-doped layers and the electrical devices. The forming method of the CMOS image sensor simultaneously increases the working area of the light-doped region and the reading circuit region, thereby improving the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a CMOS image sensor and a method for forming the same. Background Technology

[0002] A CMOS image sensor (Complementary-Metal-Oxide-Semiconductor Image Sensor, CIS) is a semiconductor device that converts light signals into electrical signals to achieve imaging. It is widely used in cameras, smartphones, medical imaging instruments, and other devices. In recent years, as the pixel density of CMOS image sensors has increased, the demands on device integration and performance have also risen.

[0003] A single pixel area of ​​a CMOS image sensor consists of a photosensitive area and a readout circuit area. The PN junction in the photosensitive area receives light signals, while the transistor devices in the readout circuit area act as switches. The larger the working area of ​​the photosensitive area, the higher the sensitivity of the CMOS image sensor to light signals. Furthermore, a larger working area of ​​the readout circuit area can accommodate more complex readout circuit devices, thereby improving device stability and reducing device noise. Therefore, for CMOS image sensors, increasing the working area of ​​both the photosensitive and readout circuit areas can significantly improve the overall device performance.

[0004] However, in the current technology, the photosensitive area and readout circuit area of ​​the CMOS image sensor are arranged in a planar manner. Therefore, with the pixel density remaining unchanged, the working area of ​​the photosensitive area and the readout circuit area needs to be balanced within the limited area of ​​each pixel area, which limits the improvement of device performance. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a CMOS image sensor and a method for forming the same, which increases the working area of ​​the photosensitive area and the readout circuit area, thereby improving the device performance.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a CMOS image sensor, comprising: forming a substrate, a plurality of photosensitive doped layers on the substrate, an isolation layer on the photosensitive doped layers, and an active layer on the isolation layer, wherein the substrate includes a plurality of mutually discrete pixel regions, and each of the photosensitive doped layers is located on each of the pixel regions; forming electrical devices within and on the active layer; and forming interconnect structures within the isolation layer and the active layer, wherein the interconnect structures electrically connect the photosensitive doped layers and the electrical devices.

[0007] Optionally, the method for forming the substrate, the plurality of photosensitive doped layers, the isolation layer, and the active layer includes: forming an initial substrate structure, the initial substrate structure including a substrate, an initial photosensitive doped layer located on the substrate, an isolation layer located on the initial photosensitive doped layer, and an active layer located on the isolation layer; forming an isolation structure within the initial substrate structure, the isolation structure penetrating the initial photosensitive doped layer, and the isolation structure also being located between adjacent pixel regions, such that the initial photosensitive doped layer forms a plurality of photosensitive doped layers.

[0008] Optionally, the isolation structure also extends through the active layer.

[0009] Optionally, the method for forming the initial substrate structure includes: providing an initial substrate; implanting first dopant ions into the initial substrate to form the substrate and the initial photosensitive doped layer; forming an isolation layer on the initial photosensitive doped layer; and forming an active layer on the isolation layer.

[0010] Optionally, the method for forming the initial substrate structure includes: providing an initial substrate, the initial substrate including a substrate, an isolation layer located on the substrate, and an active layer located on the isolation layer; implanting first dopant ions into the substrate to form a substrate and an initial photosensitive dopant layer located on the substrate.

[0011] Optionally, the formation process of the initial photosensitive doped layer includes an epitaxial growth process.

[0012] Optionally, the electrical device includes: a gate structure located on the substrate and source / drain regions located in active layers on both sides of the gate structure.

[0013] Optionally, the interconnect structure includes: a first plug located on the active layer, a second plug located on the photosensitive doped layer, and an electrical connection layer connecting the first plug and the second plug, wherein the first plug is electrically connected to the electrical device.

[0014] Optionally, the material of the interconnect structure includes metal.

[0015] Optionally, the method of forming the interconnect structure includes: forming an opening located in the active layer and the isolation layer, the opening penetrating the active layer and the isolation layer; forming an interconnect dielectric layer in the opening; forming a first plug on the active layer; forming a second plug penetrating the interconnect dielectric layer, the second plug being located on the surface of the photosensitive doped layer; and forming an electrical connection layer on the top surface of the first plug and the top surface of the second plug.

[0016] Optionally, the interconnect structure includes: an epitaxial layer located within the isolation layer, the epitaxial layer being in contact with the photosensitive doped layer and the active layer, and the epitaxial layer being electrically connected to the electrical device.

[0017] Optionally, the material of the interconnect structure includes silicon, silicon germanium, and silicon carbide.

[0018] Optionally, the interconnect structure forming method includes: forming an opening located within the active layer and the isolation layer, the opening penetrating the active layer and the isolation layer; and forming an epitaxial layer inside and outside the opening, the epitaxial layer being in contact with the sidewall of the active layer.

[0019] Optionally, the photosensitive doped layer is doped with N-type ions, and the substrate is doped with P-type ions.

[0020] Accordingly, the present invention also provides a CMOS image sensor, comprising: a substrate, a plurality of photosensitive doped layers on the substrate, an isolation layer on the photosensitive doped layers, and an active layer on the isolation layer, wherein the substrate comprises a plurality of mutually discrete pixel regions, and each of the photosensitive doped layers is located on each of the pixel regions; electrical devices located within and on the active layer; and interconnection structures located within the isolation layer and the active layer, wherein the interconnection structures electrically connect the photosensitive doped layers and the electrical devices.

[0021] Optionally, the CMOS image sensor further includes an isolation structure located between adjacent photosensitive doped layers and adjacent pixel regions, the isolation structure extending through the photosensitive doped layers.

[0022] Optionally, the isolation structure also extends through the active layer.

[0023] Optionally, the electrical device includes: a gate structure located on the substrate and source / drain regions located in active layers on both sides of the gate structure.

[0024] Optionally, the interconnect structure includes: a first plug located on the active layer, a second plug located on the photosensitive doped layer, and an electrical connection layer connecting the first plug and the second plug, wherein the first plug is electrically connected to the electrical device.

[0025] Optionally, the interconnect structure includes: an epitaxial layer located within the isolation layer, the epitaxial layer being in contact with the photosensitive doped layer and the active layer, and the epitaxial layer being electrically connected to the electrical device.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the CMOS image sensor formation method provided by the technical solution of the present invention, since electrical devices and photosensitive doped layers are formed in different layers, the space of the substrate, photosensitive doped layer and active layer in the direction perpendicular to the substrate surface can be fully utilized without being limited by the surface area of ​​the active layer. Therefore, the working area of ​​the electrical devices and photosensitive doped layer is increased at the same time, thereby improving the sensitivity of the photosensitive doped layer in the process of receiving light signals. It also allows the active layer to have more space to accommodate more complex electrical devices, thereby improving the stability of the CMOS image sensor, reducing noise and improving the overall performance of the device.

[0028] In the CMOS image sensor provided by the technical solution of the present invention, since the electrical devices and the photosensitive doped layer are located on different layers, the space of the substrate, the photosensitive doped layer and the active layer in the direction perpendicular to the substrate surface can be fully utilized. Therefore, the working area of ​​the electrical devices and the photosensitive doped layer is increased at the same time, thereby improving the sensitivity of the photosensitive doped layer in the process of receiving light signals, improving the stability of the CMOS image sensor, reducing noise and improving the overall performance of the device. Attached Figure Description

[0029] Figures 1 to 4 This is a cross-sectional structural schematic diagram of the formation process of a CMOS image sensor according to an embodiment of the present invention;

[0030] Figure 5 This is a cross-sectional structural schematic diagram of the formation process of a CMOS image sensor according to another embodiment of the present invention. Detailed Implementation

[0031] As described in the background art, in the prior art, the photosensitive area and readout circuit area of ​​a CMOS image sensor are arranged in a planar manner. Therefore, with the pixel density remaining unchanged, the working area of ​​the photosensitive area and the readout circuit area needs to be balanced within the limited area of ​​each pixel area, which limits the improvement of device performance.

[0032] To address the aforementioned technical problems, the present invention provides a method for forming a CMOS image sensor. By forming electrical devices and photosensitive doped layers located on different layers, the space of the substrate, photosensitive doped layer, and active layer in the direction perpendicular to the substrate surface is fully utilized. This increases the working area of ​​the electrical devices and photosensitive doped layer, thereby improving the sensitivity of the photosensitive doped layer in receiving light signals. It also allows the active layer to have more space to accommodate more complex electrical devices, thereby improving the stability of the CMOS image sensor, reducing noise, and enhancing the overall performance of the device.

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figures 1 to 4 This is a cross-sectional structural schematic diagram of the formation process of a CMOS image sensor according to an embodiment of the present invention.

[0035] First, a substrate, a plurality of photosensitive doped layers on the substrate, an isolation layer on the photosensitive doped layers, and an active layer on the isolation layer are formed. The substrate includes a plurality of mutually discrete pixel regions, and each of the photosensitive doped layers is located on each of the pixel regions.

[0036] The specific processes for forming the substrate, several photosensitive doped layers, the isolation layer, and the active layer are as follows: Figures 1 to 2 As shown.

[0037] Please refer to Figure 1 An initial substrate structure (not shown) is formed, the initial substrate structure including a substrate 100, an initial photosensitive doped layer 101 on the substrate 100, an isolation layer 102 on the initial photosensitive doped layer 101, and an active layer 103 on the isolation layer 102.

[0038] The substrate 100 includes several pixel regions (not shown), each pixel region providing a platform for the subsequent formation of photosensitive doped layers and electrical devices.

[0039] In this embodiment, the substrate 100 is doped with P-type ions; the initial photosensitive doped layer 101 is doped with N-type ions. A PN junction is formed between the substrate 100 and the initial photosensitive doped layer 101 to form a photodiode.

[0040] The active layer 103 provides space for the subsequent formation of electrical devices, which are then formed within and on the active layer 103.

[0041] The isolation layer 102 is used to isolate the initial photosensitive doped layer 101 from the active layer 103, thereby isolating the region of the photodiode from the region where electrical devices are subsequently formed.

[0042] In this embodiment, the method for forming the initial substrate structure includes: providing an initial substrate 100; implanting first dopant ions into the initial substrate 100 to form the substrate 100 and the initial photosensitive doped layer 101; forming an isolation layer 102 on the initial photosensitive doped layer 101; and forming an active layer 103 on the isolation layer 102.

[0043] The first doped ion is an N-type ion.

[0044] The active layer 103 is doped with P-type ions.

[0045] The material of the isolation layer 102 is silicon oxide.

[0046] In another embodiment, the substrate is doped with P-type ions; the initial photosensitive doped layer is doped with N-type ions. The initial photosensitive doped layer is formed on the substrate, and the formation process of the initial photosensitive doped layer includes an epitaxial growth process.

[0047] In other embodiments, the method of forming the initial substrate structure includes: providing an initial substrate, the initial substrate including a substrate, an isolation layer located on the substrate, and an active layer located on the isolation layer; implanting first dopant ions into the substrate to form a substrate and an initial photosensitive dopant layer located on the substrate.

[0048] Please refer to Figure 2 An isolation structure 104 is formed within the initial substrate structure. The isolation structure 104 penetrates the initial photosensitive doped layer 101 and is also located between adjacent pixel regions, thereby forming a plurality of photosensitive doped layers 106 in the initial photosensitive doped layer 101.

[0049] The isolation structure 104 penetrates the initial photosensitive doped layer 101, thereby making its bottom surface lower than the interface between the substrate 100 and the initial photosensitive doped layer 101. Therefore, the isolation structure 104 separates the initial photosensitive doped layer 101 into several photosensitive doped layers 106; simultaneously, the isolation structure 104 is also located between adjacent pixel regions, thereby dividing the portion of the substrate 100 in contact with the initial photosensitive doped layer 101 into several discrete portions, with each photosensitive doped layer 106 located on its respective pixel region.

[0050] Each photosensitive doped layer 106 and the portion of the substrate 100 in contact with it constitutes a plurality of discrete photodiodes, which serve as photosensitive areas 105 of each pixel region to receive light signals. The presence of the isolation structure 104 allows each photosensitive area 105 to operate independently.

[0051] In this embodiment, the isolation structure 104 also extends through the active layer 103, thereby making the subsequently formed electrical devices independent of each other.

[0052] In other embodiments, the isolation structure may not penetrate the active layer, thereby allowing subsequently formed electrical devices to share the source and drain regions located within the active layer.

[0053] Next, electrical devices are formed within and on the active layer 103.

[0054] The electrical device includes: a gate structure located on the substrate 100 and source / drain regions located in the active layers on both sides of the gate structure.

[0055] Specifically, in this embodiment, the formation process of the gate structure is as follows: Figure 3 As shown, the formation process of the source / drain region is as follows: Figure 4 As shown.

[0056] Please refer to Figure 3 A gate structure is formed on the active layer 103.

[0057] The gate structure includes: a gate dielectric layer 112 located on the active layer 103, a gate 110 located on the gate dielectric layer 112, and sidewalls 111 located on both sides of the gate 110.

[0058] In this embodiment, the method for forming the gate structure includes: forming a gate dielectric layer 112 on the active layer 103; forming a dummy gate (not shown) on the gate dielectric layer 112; forming a sidewall 111 on the sidewall of the dummy gate; forming an interlayer dielectric layer (not shown) surrounding the dummy gate and the sidewall 111; removing the dummy gate to form a gate opening; and forming a gate 110 in the gate opening.

[0059] Next, source / drain regions located within the active layer 103 and interconnect structures located within the isolation layer 102 and the active layer 103 are formed. The formation process of the source / drain regions and the interconnect structures in one embodiment of the present invention is as follows: Figure 4 As shown.

[0060] Please refer to Figure 4 The method for forming the source / drain region 113 includes: implanting second doped ions into the active layer 103 on both sides of the gate 110 to form the source / drain region 113.

[0061] The source / drain region 113 and the gate structure constitute an electrical device, which serves as a switch for the CMOS image sensor to control the conduction of current.

[0062] The second doped ion is an N-type ion.

[0063] Please continue to refer to this. Figure 4 An interconnect structure 124 is formed within the isolation layer 102 and the active layer 103, the interconnect structure 124 electrically connecting the photosensitive doped layer 106 and the electrical device.

[0064] In a CMOS image sensor, each of the electrical devices and each photosensitive area 105 constitutes a pixel unit. Each pixel unit works independently to convert light signals into electrical signals to achieve imaging.

[0065] In this embodiment, since the photosensitive doped layer 106 and the electrical device are located on different layers, the space of the substrate 100, the photosensitive doped layer 106, and the active layer 103 in the direction perpendicular to the surface of the substrate 100 can be fully utilized without being limited by the surface area of ​​the active layer 103. Therefore, while keeping the surface area of ​​each pixel unit unchanged, the working area of ​​the electrical device and the photosensitive area 105 is increased simultaneously, thereby improving the sensitivity of the photosensitive area 105 in the process of receiving light signals. It also allows the active layer 103 to have more space to accommodate more complex electrical devices, thereby improving the stability of the CMOS image sensor, reducing noise, and improving the overall performance of the device.

[0066] In this embodiment, the interconnect structure 124 includes: a first plug 121 located on the active layer 103, a second plug 122 located on the photosensitive doped layer 106, and an electrical connection layer 123 connecting the first plug 121 and the second plug 122, wherein the first plug 121 is electrically connected to the electrical device.

[0067] Specifically, the first plug 121 is connected to the source / drain region 113, while the second plug 122 is connected to the photosensitive doped layer 106, thereby enabling the interconnect structure 124 to electrically connect the electrical device to the photosensitive region 105.

[0068] In this embodiment, the interconnect structure 124 is made of metal, which results in lower resistance of the interconnect structure 124 and better electrical connection between the photosensitive doped layer 106 and the electrical device.

[0069] In this embodiment, the method for forming the interconnect structure 124 includes: forming an opening (not shown) located within the active layer 103 and the isolation layer 102, the opening penetrating the active layer 103 and the isolation layer 102; forming an interconnect dielectric layer 120 within the opening; forming a first plug 121 on the active layer 103; forming a second plug 122 penetrating the interconnect dielectric layer 120, the second plug 122 being located on the surface of the photosensitive doped layer 106; and forming an electrical connection layer 123 on the top surface of the first plug 121 and the top surface of the second plug 122.

[0070] Figure 5 This is a cross-sectional structural schematic diagram of the formation process of a CMOS image sensor according to another embodiment of the present invention.

[0071] Please Figure 3 Based on reference Figure 5 An interconnect structure is formed within the isolation layer and the active layer, the interconnect structure electrically connecting the photosensitive doped layer and the electrical device.

[0072] The interconnect structure includes an epitaxial layer 206 located within the isolation layer, the epitaxial layer 206 being in contact with the photosensitive doped layer and the active layer, and the epitaxial layer 206 being electrically connected to the electrical device.

[0073] The materials used in the interconnect structure include silicon, silicon germanium, and silicon carbide.

[0074] The interconnect structure forming method includes: forming an opening located within the active layer and the isolation layer, the opening penetrating the active layer and the isolation layer; forming an epitaxial layer 206 inside and outside the opening, the epitaxial layer 206 being in contact with the sidewall of the active layer.

[0075] Specifically, during the formation of the epitaxial layer 206, the epitaxial layer 206 is formed simultaneously on the sidewall surface of the active layer and the surface of the photosensitive doped layer until they come into contact with each other, thereby connecting the active layer and the photosensitive doped layer. Therefore, the formation process of the interconnect structure is relatively simple.

[0076] After the interconnect structure is formed, second doped ions are implanted on both sides of the gate and in the epitaxial layer 206, thereby forming source / drain regions 213 on both sides of the gate. The source / drain regions 213 are in contact with one end of the epitaxial layer 206, and the other end of the epitaxial layer 206 is in contact with the photosensitive doped layer, thereby electrically connecting the electrical device to the photosensitive region.

[0077] Since the processes of implanting second doped ions on both sides of the gate and in the epitaxial layer can be performed simultaneously, the fabrication process is simplified.

[0078] Accordingly, embodiments of the present invention also provide a CMOS image sensor formed using the above method.

[0079] Please continue to refer to this. Figure 4 The CMOS image sensor includes: a substrate 100, a plurality of photosensitive doped layers 106 on the substrate 100, an isolation layer 102 on the photosensitive doped layers 106, and an active layer 103 on the isolation layer 102. The substrate 100 includes a plurality of mutually discrete pixel regions, and each photosensitive doped layer 106 is located on each pixel region. Electrical devices are located within and on the active layer 103. An interconnect structure 124 is located within the isolation layer 102 and the active layer 103, and the interconnect structure 124 electrically connects the photosensitive doped layers 106 and the electrical devices.

[0080] In this embodiment, the CMOS image sensor further includes an isolation structure 104 located between adjacent photosensitive doped layers 106 and adjacent pixel areas, the isolation structure 104 penetrating the photosensitive doped layers 106.

[0081] In this embodiment, the isolation structure 104 also extends through the active layer 103.

[0082] In this embodiment, the electrical device includes: a gate structure located on the substrate 100 and source / drain regions 113 located in the active layers 103 on both sides of the gate structure.

[0083] In this embodiment, the interconnect structure 124 includes: a first plug 121 located on the active layer 103, a second plug 122 located on the photosensitive doped layer 106, and an electrical connection layer 123 connecting the first plug 121 and the second plug 122, wherein the first plug 121 is electrically connected to the electrical device.

[0084] Furthermore, in another embodiment of the present invention, the CMOS image sensor is as follows: Figure 5 As shown. Please refer to. Figure 5 , Figure 5 CMOS image sensor and Figure 4 The difference between the CMOS image sensors in the two is that... Figure 5 The interconnect structure of the CMOS image sensor includes: an epitaxial layer 206 located within the isolation layer, the epitaxial layer 206 being in contact with the photosensitive doped layer and the active layer, and the epitaxial layer 206 being electrically connected to the electrical device.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a CMOS image sensor, characterized in that, include: A substrate is formed, a plurality of photosensitive doped layers on the substrate, an isolation layer on the photosensitive doped layers, and an active layer on the isolation layer. The substrate includes a plurality of mutually discrete pixel regions, and each of the photosensitive doped layers is located on each of the pixel regions. Electrical devices are formed within and on the active layer; An interconnect structure is formed within the isolation layer and the active layer, the interconnect structure electrically connecting the photosensitive doped layer and the electrical device, wherein the projection of the electrical device onto the substrate surface does not exceed the projection range of the photosensitive doped layer onto the substrate surface. A method for forming the substrate, a plurality of photosensitive doped layers, an isolation layer, and an active layer includes: forming an initial substrate structure, the initial substrate structure including a substrate, an initial photosensitive doped layer on the substrate, an isolation layer on the initial photosensitive doped layer, and an active layer on the isolation layer; forming an isolation structure within the initial substrate structure, the isolation structure penetrating the initial photosensitive doped layer and also located between adjacent pixel regions, such that the initial photosensitive doped layer forms a plurality of photosensitive doped layers; An isolation structure is formed within the initial substrate structure, the isolation structure penetrates the initial photosensitive doped layer, and the isolation structure is also located between adjacent pixel regions, so that the initial photosensitive doped layer forms a plurality of photosensitive doped layers. The isolation structure also extends through the active layer.

2. The method for forming a CMOS image sensor as described in claim 1, characterized in that, The method for forming the initial substrate structure includes: providing an initial substrate; implanting first dopant ions into the initial substrate to form the substrate and the initial photosensitive doped layer; forming an isolation layer on the initial photosensitive doped layer; and forming an active layer on the isolation layer.

3. The method for forming a CMOS image sensor as described in claim 1, characterized in that, The method for forming the initial substrate structure includes: providing an initial substrate, the initial substrate including a substrate, an isolation layer located on the substrate, and an active layer located on the isolation layer; implanting first dopant ions into the substrate to form a substrate and an initial photosensitive dopant layer located on the substrate.

4. The method for forming a CMOS image sensor as described in claim 1, characterized in that, The formation process of the initial photosensitive doped layer includes an epitaxial growth process.

5. The method for forming a CMOS image sensor as described in claim 1, characterized in that, The electrical device includes: a gate structure located on the substrate and source / drain regions located in the active layers on both sides of the gate structure.

6. The method for forming a CMOS image sensor as described in claim 1, characterized in that, The interconnect structure includes: a first plug located on the active layer, a second plug located on the photosensitive doped layer, and an electrical connection layer connecting the first plug and the second plug, wherein the first plug is electrically connected to the electrical device.

7. The method for forming a CMOS image sensor as described in claim 6, characterized in that, The interconnect structure is made of metal.

8. The method for forming a CMOS image sensor as described in claim 6, characterized in that, The method for forming the interconnect structure includes: forming an opening located within the active layer and the isolation layer, the opening penetrating the active layer and the isolation layer; forming an interconnect dielectric layer within the opening; forming a first plug on the active layer; forming a second plug penetrating the interconnect dielectric layer, the second plug being located on the surface of the photosensitive doped layer; and forming an electrical connection layer on the top surface of the first plug and the top surface of the second plug.

9. The method for forming a CMOS image sensor as described in claim 1, characterized in that, The interconnect structure includes: an epitaxial layer located within the isolation layer, the epitaxial layer being in contact with the photosensitive doped layer and the active layer, and the epitaxial layer being electrically connected to the electrical device.

10. The method for forming a CMOS image sensor as described in claim 9, characterized in that, The materials used in the interconnect structure include silicon, silicon germanium, and silicon carbide.

11. The method for forming a CMOS image sensor as described in claim 10, characterized in that, The interconnect structure forming method includes: forming an opening located within the active layer and the isolation layer, the opening penetrating the active layer and the isolation layer; forming an epitaxial layer inside and outside the opening, the epitaxial layer contacting the sidewall of the active layer.

12. The method for forming a CMOS image sensor as described in claim 1, characterized in that, The photosensitive doped layer is doped with N-type ions, and the substrate is doped with P-type ions.

13. A CMOS image sensor, characterized in that, include: The substrate comprises a plurality of photosensitive doped layers on the substrate, an isolation layer on the photosensitive doped layers, and an active layer on the isolation layer. The substrate includes a plurality of mutually discrete pixel regions, and each of the photosensitive doped layers is located on each of the pixel regions. Electrical devices located within and on the active layer; An interconnect structure located within the isolation layer and the active layer, the interconnect structure electrically connecting the photosensitive doped layer and the electrical device, wherein the projection of the electrical device onto the substrate surface does not exceed the projection range of the photosensitive doped layer onto the substrate surface; An isolation structure is located between adjacent photosensitive doped layers and adjacent pixel regions, the isolation structure extending through the photosensitive doped layers and also through the active layer.

14. The CMOS image sensor as described in claim 13, characterized in that, The electrical device includes: a gate structure located on the substrate and source / drain regions located in the active layers on both sides of the gate structure.

15. The CMOS image sensor as described in claim 13, characterized in that, The interconnect structure includes: a first plug located on the active layer, a second plug located on the photosensitive doped layer, and an electrical connection layer connecting the first plug and the second plug, wherein the first plug is electrically connected to the electrical device.

16. The CMOS image sensor as described in claim 13, characterized in that, The interconnect structure includes: an epitaxial layer located within the isolation layer, the epitaxial layer being in contact with the photosensitive doped layer and the active layer, and the epitaxial layer being electrically connected to the electrical device.

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