PWM drive circuit and method

Abstract

Embodiments of the present disclosure relate to PWM drive circuits and methods. In one embodiment, a method for shaping a PWM signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: when the input PWM signal transitions with a first edge of the input PWM signal, transitioning the output PWM signal with a first edge of the output PWM signal; and, before the first edge of the output PWM signal transitions, when the input PWM signal transitions with a second edge, delaying a second edge of the output PWM signal based on the first edge of the output PWM signal.

Description

Technical Field

[0001] The present disclosure relates generally to electronic systems and methods, and in particular embodiments to pulse width modulation (PWM) drive circuits and methods. Background Art

[0002] Class D amplifiers are switching amplifiers that use the output transistors as electronic switches rather than operating in the linear region. Figure 1 A schematic diagram of a conventional class D amplifier 100 is shown for driving an audio speaker 114. Class D amplifier 100 includes a comparator 102, a drive circuit 104, an output stage 105, an inductor 110, and a capacitor 112.

[0003] During normal operation, comparator 502 receives an audio input signal 116 and a triangular waveform 118 (e.g., a sawtooth waveform) and generates a pulse width modulated (PWM) signal 120. PWM signal 120 is used to control driver circuit 104, which in turn drives transistors 106 and 108 of output stage 105 based on PWM signal 120. Output stage 105 produces an output signal 122 that drives speaker 114 through low pass filter (LPF) 109 (also known as a demodulation filter).

[0004] The PWM signal 120, which includes the amplified original audible signal and a high-frequency switching component above the human audible range (e.g., greater than 20 kHz), can be filtered by the LPF 109. For example, in some applications where EMI is not stringent, the LPF 109 can be removed because the impedance of the speaker 114 itself acts as a low-pass filter.

[0005] Figure 2 A schematic diagram of another conventional class D amplifier 200 is shown for driving an audio speaker 114. Class D amplifier 200 operates in a similar manner to class D amplifier 100. However, class D amplifier 200 includes an integrator 202 coupled to the comparator so as to drive comparator 102 based on audio output signal 116, and a feedback resistor 210 coupled between the output of output stage 105 and integrator 202.

[0006] During normal operation, the square wave output of output stage 105 is summed with audio input signal 116 to provide negative feedback. Integrator circuit 202 provides the resulting signal to comparator 102, which operates in a similar manner to class D amplifier 100. Summary of the Invention

[0007] According to an embodiment, a method for shaping a pulse width modulation (PWM) signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: when the input PWM signal transitions with a first edge of the input PWM signal, transitioning the output PWM signal with a first edge of the output PWM signal; and before the first edge of the output PWM signal transitions, when the input PWM signal transitions with a second edge, delaying a second edge of the output PWM signal based on the first edge of the output PWM signal, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

[0008] According to an embodiment, a method for shaping a pulse width modulated (PWM) signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal using a high-side transistor driven based on a high-side intermediate signal and a low-side transistor driven based on a low-side intermediate signal; driving the high-side intermediate signal and the low-side intermediate signal when the input PWM signal transitions with a first edge of the input PWM signal to cause the output PWM signal to transition with a first edge of the output PWM signal; and transitioning the high-side intermediate signal and the low-side intermediate signal based on the first edge of the output PWM signal to cause a second edge of the output PWM signal when the input PWM signal transitions with a second edge after the first edge of the output PWM signal transitions, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

[0009] According to an embodiment, a pulse width modulation (PWM) pre-regulation circuit includes: a PWM input configured to receive an input PWM signal; a high-side output and a low-side output, the high-side output and the low-side output configured to be coupled to control terminals of a high-side transistor and a low-side transistor, respectively; a switch detection input configured to be coupled to the high-side transistor and the low-side transistor to monitor an output PWM signal; and a controller configured to: when the input PWM signal transitions with a first edge of the input PWM signal, drive the high-side output and the low-side output to cause the output PWM signal to transition with the first edge of the output PWM signal; and when the input PWM signal transitions with a second edge before the first edge of the output PWM signal transitions, drive the high-side output and the low-side output based on the first edge of the output PWM signal to delay a second edge of the output PWM signal, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A schematic diagram showing a conventional Class D amplifier for driving an audio speaker;

[0012] Figure 2 shows a schematic diagram of another conventional Class D amplifier for driving an audio speaker;

[0013] Figure 3 A class D amplifier according to an embodiment of the present invention is shown;

[0014] Figure 4 A flow chart illustrating an exemplary method for adjusting a PWM signal according to an embodiment of the present invention is shown;

[0015] Figures 5 to 8 The embodiment according to the present invention is shown Figure 3 The waveform of the signal of the Class D amplifier;

[0016] Figure 9 and Figure 10 FIG. 1 shows an embodiment of the present invention. Figure 3 The duty cycle of the regulated pre-filtered output voltage of the Class D amplifier;

[0017] Figure 11FIGURE 1 illustrates an embodiment of the present invention in which a pre-conditioned Figure 3 Class D amplifiers and do not have pre-regulation Figure 3 The simulation results of the comparison between the power consumption of the Class D amplifier;

[0018] Figure 12 The diagram shows an embodiment of the present invention. Figure 3 The base-drain diode RMS current of the output power when the transistors of the output stage are implemented as n-type DMOS transistors;

[0019] Figure 13 and Figure 14 FIG. 1 shows an embodiment of the present invention. Figure 3 Simulation results of pre-filtered output signal and post-filtered output signal (with and without pre-conditioning) of a Class D amplifier;

[0020] Figure 15 The embodiment according to the present invention is shown Figure 3 Pre-regulation circuit;

[0021] Figures 16 to 19 The embodiment according to the present invention is shown Figure 15 The waveform of the signal associated with the pre-conditioning circuit;

[0022] Figure 20 The embodiment according to the present invention is shown Figure 15 Pre-regulation controller;

[0023] Figure 21A and Figure 21B The following diagrams respectively illustrate the embodiments according to the present invention. Figure 20 A-type pulse generator circuit and associated waveform;

[0024] Figure 22A and Figure 22B The embodiment of the present invention is shown respectively. Figure 20 Type B pulse generator circuit and associated waveform;

[0025] Figure 23A and Figure 23B The embodiment of the present invention is shown respectively. Figure 20 C-type delay circuit and associated waveform; and

[0026] Figure 24A and Figure 24B The embodiment of the present invention is shown respectively. Figure 20 A D-type delay circuit and associated waveforms.

[0027] Corresponding numerals and symbols in the different figures indicate corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0028] The following will discuss in detail the making and using of the disclosed embodiments. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific methods of making and using the present invention and do not limit the scope of the invention.

[0029] The following description describes various specific details to provide an in-depth understanding of some example embodiments according to this description. These embodiments can be obtained without one or more specific details, or by other methods, components, materials, etc. In other cases, known structures, materials or operations will not be shown or described in detail to avoid confusing different aspects of the embodiments. References to "one embodiment" in this description refer to the specific configuration, structure or feature described in connection with the embodiment being included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this description do not necessarily accurately indicate the same embodiment. In addition, specific configurations, structures or features can be combined in any appropriate manner in one or more embodiments.

[0030] Embodiments of the present invention will be described in the specific context of PWM circuits and methods implemented in a Class D amplifier (eg, for audio applications). Some embodiments may be implemented in other types of amplifiers / circuits and / or other types of applications.

[0031] In an embodiment of the present invention, a PWM signal provided to a driver for controlling an output stage of a Class-D amplifier is automatically modified based on the switching state of the output signal of the output stage. When the output signal approaches clipping, a pre-regulation circuit coupled between the PWM modulator and the driver dynamically limits the duty cycle of the PWM signal so that the duty cycle does not directly reach 0% or 100% within the top / bottom duty cycle range of the input. In some embodiments, the pre-regulation circuit removes (skips) PWM pulses having a pulse width less than the driver delay, which advantageously reduces power consumption while keeping oscillations at a relatively high frequency and inaudible frequency band without introducing additional delay to the input of the Class-D amplifier.

[0032] Figure 3Class D amplifier 300 includes processing circuits 304 and 306, PWM modulator 310, pre-regulation circuit 312, driver circuit 104, output stage 105, feedback circuits 314 and 316, soft clipping control circuit 308, and summing circuit 302.

[0033] During normal operation, the output stage 105 drives the speaker 114 based on the analog input signal via the low pass filter 109. The analog input is modified by the circuits 302, 304 and 306 to generate the signal V pwm_in The PWM modulator 310 , for example, in a similar manner to the PWM modulator 101 , is based on the analog signal V pwm_in Generate PWM signal V pwm_out .

[0034] The pre-regulation circuit 312 is based on the PWM signal V pwm_out , and based on the pre-filtered output voltage V out_pre Generates a regulated PWM signal V pwm_cond For example, in some embodiments, the pre-regulation circuit 312 generates a signal-conditioned PWM signal V pwm_cond , with the signal V out_pre When the duty cycle is close to clipping, the signal V out_pre The duty cycle is limited to the maximum (minimum) duty cycle, and the signal V out_pre The duty cycle is not close to clipping, so that the regulated PWM signal V pwm_cond With the PWM signal V pwm_out As will be described in more detail below, in some embodiments, the duty cycle clipping value is not a fixed preset value. Instead, in some embodiments, the duty cycle clipping value is determined by the output V out_pre The state of is dynamically determined and controlled, advantageously optimizing the clipping to a maximum (minimum) value close to 100% (0%) to allow full-scale PWM conversion according to variations in process, supply voltage level and temperature (PVT).

[0035] In some embodiments, the PWM signal V pwm_out The pre-regulator circuit 312 reduces the pulse width of the PWM signal V pwm_cond The pulse width of the signal V out_pre Start with V pwm_cond When the PWM signal V pwm_out When the second edge of the pulse occurs, the PWM signal V pwm_cond Has a preset width.

[0036] As in Figure 3As shown in FIG, in some embodiments, the pre-regulated PWM signal V pwm_cond A high-side signal V may be included for controlling a high-side transistor (eg, 106). pwm_condP and a low-side signal V for controlling a low-side transistor (eg, 108 ) pwm_condN .

[0037] Output stage 105 can be implemented in any manner known in the art, such as using NMOS transistors 106 and 108. Other implementations can also be used, such as using different types of transistors (e.g., p-type high-side transistors and n-type low-side transistors), and / or transistors of other technologies. For example, in some embodiments, transistors 106 and 108 are double-diffused MOSFET (DMOS) transistors.

[0038] In some embodiments, a bootstrap capacitor (not shown) may be used to drive transistors 106 and 108 in a manner known in the art.

[0039] The drive circuit 104 may be implemented in any manner known in the art, such as by using a conventional gate driver.

[0040] The PWM modulator 310 may be implemented in any manner known in the art. For example, in some embodiments, the PWM modulator 310 may be implemented in a manner similar to the PWM modulator 101 .

[0041] In some embodiments, processing circuits 304 and 306 may each include an integrator circuit (e.g., similar to integrator 202) and may integrate the signals from respective feedback circuits 314 and 316 with the input voltage V in For example, in some embodiments, processing circuit 306 is implemented identically to integrator 202, and processing circuit 304 is implemented similarly to integrator 202 but with an additional compensation (zero).

[0042] In some embodiments, the soft clipping control circuit 308 (using the summing circuit 302) takes the negative feedback from the signal V pwm_in It is provided back to the input of the class D amplifier 300, for example, to correct for non-linearities in the transfer function of the driver 104. The soft clipping control circuit 308 may be implemented in any manner known in the art.

[0043] In some embodiments, the negative feedback loop of Class D amplifier 300 , including feedback circuits 314 and 316 and soft clipping control circuit 308 , advantageously allows for improved performance, such as increased PSRR and THD, for example.

[0044] Figure 4A flow chart illustrating an embodiment method 400 for adjusting a PWM signal according to an embodiment of the present invention is shown.

[0045] During step 402, the PWM signal V pwm_out transition (on the rising or falling edge), the PWM signal V pwm_out is the input of the pre-conditioning circuit 312.

[0046] During step 404, the regulated PWM signal V pwm_cond Based on the PWM signal V pwm_out The switching, in turn, controls the driver circuit 104, causing the transistors 106 and 108 to switch, thus causing the voltage V out_pre For example, in some embodiments, during the transition that occurs during step 404, the signal V pwm_condP and V pwm_condN With preset delay t fix1 , for example to avoid X conduction.

[0047] During step 406, the PWM signal V pwm Is the next edge of V out_pre If the PWM signal V pwm_out The next edge of V out_pre If the switching occurs before the duty cycle is close to clipping (e.g., less than 5% or greater than 95%), and V pwm_cond The next edge of the V out_pre In some embodiments, the next edge is determined by a preset time t fix2 Add driver delay t dry delay, where the driver delay t dry The driver 104 receives the conversion signal V out_pre In some embodiments, the delay t fix1 and t fix2 are equal. In some embodiments, because V pwm_cond The next edge of the driver is based on the delay t dry is delayed, so this delay is dynamic and based on process, voltage and temperature (PVT) variations, for example. Thus, some embodiments can effectively avoid using a worst-case (eg, longer) delay to result in a worst-case PVT condition.

[0048] In some embodiments, the signal V pwm_condP and V pwm_condN In t dry Add t fix2 After that, the signal V pwm_condP and Vpwm_condN There is no preset delay between fix1 , because in some embodiments, the response time between the high-side transistor (e.g., 106) and the low-side transistor (e.g., 108) is different, and X conduction is advantageously avoided, for example, no preset delay needs to be introduced during step 408.

[0049] In some embodiments, the PWM signal V pwm_out Is the next edge of V out_pre Occurs before conversion. Based on the PWM signal V pwm_out The next edge of the transition plus the driver delay t dry Is V out_pre before the transition occurs (or whether it will occur at V out_pre occurs before the conversion).

[0050] During step 410, if the PWM signal V pwm_out The next edge is not at V out_pre occurs before the conversion, then the PWM signal V pwm_out Is the next edge of V out_pre If the PWM signal V pwm_out The next edge of the voltage V out_pre conversion occurs, then during step 412, at V pwm_condP With V pwm_condN The next edge is advanced so that it is longer between V pwm_condP and V pwm_condN The other one in the preset delay t occurs fix3 After conversion, where t fix3 Less than t fix1 In some embodiments, the delay t fix3 is not fixed, and instead it can be determined by a detection signal (e.g. V boost_on or V slow_off )Sure.

[0051] During step 410, if it is determined that the PWM signal V pwm_out The next edge of V out_pre The conversion occurs after that, then when V pwm_out When switching, the regulated PWM signal switches, and during the switching that occurs during step 416, the signal V pwm_condP and V pwm_condN With preset delay t fix1 .

[0052] In some embodiments, if the output of step 406 is "no," then steps 410 and 416 may be omitted, and step 412 is always performed.

[0053] Figures 5 to 8 1 and 2 show waveforms of signals of the class-D amplifier 300 according to an embodiment of the present invention.

[0054] Figure 5 FIG4 shows a waveform in which the duty cycle is increased to the minimum duty cycle (step 408). Figure 5 As shown in pwm_out The rising edge of 50 occurs at (step 402). At time t 51 V pwm_condN From low to high (step 404). At time t 51 After the preset time t fix1 Time t after the occurrence 52 V pwm_condP Transition from high to low (step 404).

[0055] At time t 53 V pwm_out The falling edge (next edge) of V pwm_out The falling edge (next edge) of V out_pre Conversion (at time t 55 occurs before the V pwm_condP and V pwm_condN Both at time t 56 The transition is at V pwm_condP From high to low (at time t 52 Time t after the occurrence of fix2 +t dry Happens everywhere.

[0056] like Figure 5 As shown in the figure, the reshaped V out_pre The signal has a minimum duty cycle that will be greater than that of a V out_pre The duty cycle is long (such as in Figure 5 (as shown in the figure). Figure 5 It can also be seen that due to the response time of the high-side transistor and the low-side transistor, the original (lower) duty cycle is not enough to make V out_pre Full conversion (without preconditioning).

[0057] Figure 6 The waveform of the duty cycle is shown as being reduced to the maximum duty cycle (step 408). Figure 6 As shown in pwm_out The falling edge of 60 occurs at (step 402). At time t 61 V pwm_condPFrom low to high (step 404). At time t 61 After the preset time t fix1 Time t after the occurrence 62 V pwm_condN From high to low (step 404). As shown, in some embodiments, time t fix1 It can be around 8nS. Other values ​​can also be used.

[0058] At time t 63 V pwm_out The rising edge (next edge) of V pwm_out The rising edge (next edge) of V out_pre Conversion (at time t 65 occurs before the V pwm_condP and V pwm_condN All at time t 66 The transition is at V pwm_condP Transition from low to high (at time t 62 Time t after the occurrence of fix2 +t dry .

[0059] like Figure 6 As shown in the figure, the reshaped V out_pre The signal has a maximum duty cycle that will be greater than that of a V out_pre The duty cycle should be shorter (such as in Figure 6 In Figure 6 It can also be seen that the original (lower) duty cycle is not enough to make V out_pre Full conversion (without preconditioning).

[0060] Figure 7 shows that the V pwm_out During the positive pulse period of the PWM signal V pwm_cond The pulse width of the waveform is reduced (step 412). Figure 7 As shown in pwm_out The rising edge of 70 occurs at (step 402). At time t 71 V pwm_condN From low to high (step 404). At time t 71 After the preset time t fix1 Time t after the occurrence 72 V pwm_condP Transition from high to low (step 404).

[0061] At time t 74 Vpwm_out The falling edge (next edge) of V pwm_out The falling edge (next edge) of V out_pre Conversion (at time t 73 With time t 75 ), so the output of step 406 is "No", the output of step 408 is "Yes", and therefore V pwm_condN is advanced to time t 77 The transition occurs at time t 76 V pwm_condP Preset time after conversion t fix3 In some embodiments, the detection signal (eg, V boost_on ) Make V pwm_condP At time t 76 If you then Figure 15 As illustrated in more detail in FIG. 1 , in some embodiments, V pwm_condN At time t 77 The conversion at is controlled by a latch comprising NAND gates 1518 and 1528.

[0062] like Figure 7 As shown in the figure, the reshaped V out_pre The positive pulse is shorter than the pulse without preconditioning.

[0063] Likewise Figure 7 As shown in the V pwm_condN Conversion with V pwm_condP The time between transitions (t 77 -t 76 ) is less than t fix1 , and advantageously does not cause X to turn on due to the different response times between the high-side transistor (eg, 106) and the low-side transistor (eg, 108).

[0064] Figure 8 shows that the V pwm_out During the negative pulse period of the PWM signal V pwm_cond The pulse width of the waveform is reduced (step 412). Figure 8 As shown in pwm_out The falling edge of 80 occurs at (step 402). At time t 81 V pwm_condP From low to high (step 404). At time t 81 After the preset time t fix1 Time t after the occurrence 82 V pwm_condN Transition from high to low (step 404).

[0065] At time t 84 V pwm_out The falling edge (next edge) of V pwm_out The falling edge (next edge) of V out_pre The conversion occurs, so the output of step 406 is "No", the output of step 408 is "Yes", and therefore V pwm_condP is advanced to time t 87 The transition occurs at time t 86 V pwm_condN Preset time after conversion t fix3 In some embodiments, the detection signal (eg, V slow_off ) Make V pwm_condN At time t 86 If you then Figure 15 As shown in more detail in FIG, in some embodiments, V pwm_condP At time t 87 The transition at is controlled by a latch comprising NAND gates 1518 and 1528 .

[0066] In some embodiments, for example, Figure 8 As shown in dry Determine the region of conversion. For example, in some embodiments, if V pwm_out The conversion plus the driver delay t dry In the detection signal (V boost_on ) occurs after the conversion, then V pwm_out The next edge is not at V out_pre Occurs before conversion (output of step 406 = No).

[0067] like Figure 8 As shown in the figure, the reshaped V out_pre The negative pulse is shorter than the pulse without preconditioning.

[0068] Likewise Figure 8 As shown in the V pwm_condP Conversion with V pwm_condN The time between transitions (t 87 -t 86 ) is less than t fix1 Advantageously, X is not turned on due to the difference in response time between the high-side transistor (eg, 106) and the low-side transistor (eg, 108).

[0069] Figure 9 and Figure 10 314 and 316, according to an embodiment of the present invention, when operating in open loop (without feedback circuits 308, 314 and 316), the voltage Vout_pre , without pre-regulation V out_pre , and reference V out_pre (assuming normal output stage and gate driver and no pre-regulation). Figure 9 As shown in Figure 2, when the duty cycle reaches 100%, the pre-regulated V out_pre The duty cycle of is limited (to approximately 10% duty cycle in this embodiment). Similarly, Figure 10 shows that when the duty cycle reaches 0%, the pre-regulated V out_pre The duty cycle of φ is limited (to approximately 93% duty cycle in this embodiment).

[0070] from Figure 9 and Figure 10 It can also be seen that the pre-regulated V out_pre and without pre-regulation V out_pre The duty cycle is approximately the same in the range between about 12% and about 90%.

[0071] Figure 11 1 shows simulation results comparing the power consumption of a Class D amplifier with pre-conditioning (curve 1102) and a Class D amplifier without pre-conditioning (curve 1104) according to an embodiment of the present invention. Figure 11 As shown in FIG. 4 , in some embodiments, pre-conditioning the PWM signal (e.g., by using circuit 312 and as shown in method 400) advantageously achieves power reduction (and thus V out_pre The duty cycle is close to clipping).

[0072] In some embodiments, power savings are partially due to amplifier 300 skipping short pulses when operating in closed loop. For example, in some embodiments, the duty cycle is clamped so that when the switch is close to clipping, the charge / discharge duration of LC filter 109 is fixed, which allows the feedback loop to automatically adjust the output switching frequency to a lower frequency. out Ripple may be present on the CMOS, but the switching frequency close to clipping can be removed from the audible band (moved to a higher frequency) by adjusting the clamping duty cycle level. In some embodiments, this can be achieved by sending a switch detection signal (e.g., Figure 15 V in boost_on and V slow_off ) is implemented by adding a delay. In this way, some embodiments advantageously achieve a better trade-off between power consumption and THD (e.g., Figure 11 、 Figure 13 and Figure 14 ), which may be more desirable for high frequency (HF) Class D amplifiers.

[0073] Figure 12 shows an embodiment of the present invention according to V out_pre The base-drain diode RMS current of the output power during the switching period when transistors 106 and 108 are implemented as n-type DMOS transistors.

[0074] It is well known that higher BD diode charge storage inside power DMOS used in switching applications results in higher power consumption and lower efficiency because the charge is removed during each DMOS switching cycle. Figure 12 As shown in , some embodiments exhibit lower BD diode current for the same output power when pre-regulating the PWM signal, thereby advantageously resulting in lower power consumption.

[0075] In some embodiments, reducing power consumption advantageously allows, for example, improved thermal performance of the amplifier in an integrated solution.

[0076] In some embodiments, pre-regulating PWM (eg, via method 400 ) does not result in degradation of THD performance. Figure 13 1 illustrates the post-filtered output signal V with and without pre-conditioning when the amplifier 300 operates in a closed loop according to an embodiment of the present invention. out and the pre-filtered output signal V out_pre The simulation results are shown in Figure 2. Figure 14 , shows the post-filtered output signal V with and without pre-conditioning when the amplifier 300 operates in a closed loop according to an embodiment of the present invention. out FFT simulation results.

[0077] exist Figure 13 and Figure 14 It can be seen that the non-preregulated output V out The THD with pre-regulated output V out The THD is similar to that of Figure 13 It can also be seen that the pre-regulated pre-filtered output V out_pre The switching frequency is significantly lower than the non-preregulated output V out_pre Thus, in some embodiments, a balance can be advantageously achieved between the amount of THD degradation and the amount of power savings. In some embodiments, V pwm_pre The duty cycle can be controlled by sending a detection signal to the switch (e.g. Figure 15 V in boost_on and V slow_off )Additional delay is added to adjust in order to push the ripple frequency outside the audible band.

[0078] Figure 151 shows a pre-conditioning circuit 1500 according to an embodiment of the present invention. Pre-conditioning circuit 1500 includes a pre-conditioning controller 1502, a switch state detection circuit 1506, and NAND gates 1518 and 1526. Switch state detection circuit 1506 includes comparators 1508 and 1510. Pre-conditioning circuit 312 can be implemented as pre-conditioning circuit 1500.

[0079] Figures 16 to 19 Waveforms of signals associated with pre-conditioning circuit 1500 are shown according to an embodiment of the present invention. Figure 15 Can be used with Figures 16 to 19 Common understanding. It can be seen that in some embodiments, Figures 16 to 19 Corresponding to Figures 5 to 8 .

[0080] During normal operation, the pre-regulator circuit 1500 generates a signal V pwm_condP and V pwm_condN , so that the gate drive circuit 1504 drives the transistors 106 and 108 so that the signal V out_pre Based on the signal V pwm_out Switch.

[0081] like Figure 15 As shown in , some embodiments use NAND gates 1518 and 1528 in a latching configuration to prevent X from turning on. In some embodiments, other implementations can also be used to prevent X from turning on.

[0082] As in Figure 15 As shown in FIG, the switch state detection circuit 1506 is based on the signal V out_pre Generate detection signal V boost_on and V slow_off For example, in some embodiments, comparators 1508 and 1510 may be implemented with hysteresis by applying the signal V out_pre Respectively with the threshold V th1 and V th2 are compared and are used to generate the signal V boost_on and V slow_off , where the threshold V th1 Greater than the threshold V th2 Therefore, in some embodiments, when V out_pre When transitioning from low to high, the V boost_on Before switching from high to low, V slow_off from high to low; and when V out_pre When transitioning from high to low, the V slow_off Before switching from low to high, V boost_on Transition from low to high.

[0083] In some embodiments, the threshold V th1 and Vth2 May be configurable and can be shifted (e.g. within a predetermined range).

[0084] In some embodiments, the pre-regulator controller 1502 is configured to pwm_condP and V pwm_condN causes a delay (step 408) so that when V pwm_out The duty cycle is less than 50%, and when V pwm_out The falling edge of V out_pre When a transition occurs before (for example, at V slow_off Before the falling edge of pwm_condP and V pwm_condN For example, synchronous switching, in response to a high-to-low transition of the signal V boost_on , for example, Figure 16 As shown in .

[0085] In some embodiments, the pre-regulator controller 1502 is configured to pwm_condP and V pwm_condN causes a delay (step 408) so that when V pwm_out The duty cycle is greater than 50%, and when V pwm_out The rising edge of V out_pre When a transition occurs before (for example, at V boost_on Before the rising edge of pwm_condP and V pwm_condN For example, synchronous switching, in response to a low-to-high transition of the signal V slow_off , for example, Figure 17 As shown in .

[0086] In some embodiments, pre-regulator controller 1502 is configured to cause signal V pwm_condN The conversion is advanced (step 412), so that when V pwm_out The duty cycle is less than 50%, and when V pwm_out The falling edge is not on V out_pre Before the conversion occurs, the signal V pwm_condN and V pwm_condP In response to the signal V boost_on Switching from high to low, for example, Figure 18 As shown in .

[0087] In some embodiments, pre-regulator controller 1502 is configured to cause signal V pwm_condP The conversion is advanced (step 412), so that when V pwm_out The duty cycle is greater than 50%, and when V pwm_out The rising edge of V out_pre Before the conversion occurs, the signal V pwm_condN and Vpwm_condP In response to the signal V slow_off Switching from low to high, e.g. Figure 19 As shown in .

[0088] like Figure 15 As shown in FIG, gate driver circuit 1504 can be implemented using inverting gate drivers 1520 and 1526. In some embodiments, non-inverting gate drivers can also be used instead of inverting gate drivers.

[0089] like Figures 15 to 19 As shown, in some embodiments, the pre-regulator controller 1502 uses the signal V 1512 , signal V 1516 , signal V 1530 , and signal V 1540 To drive NAND gates 1518 and 1528 to generate signal V pwm_condP and V pwm_condN .

[0090] Figure 20 The embodiment according to the present invention is shown Figure 15 Pre-regulator controller 2000. Pre-regulator controller 200 includes A-type pulse generator circuits 2002, 2006, 2014, 2042, 2048, and 2052, B-type pulse generator circuits 2032 and 2066, C-type delay circuits 2070 and 2072, D-type delay circuits 2034 and 2056, D flip-flops 1516, 1530, 2010, and 2044, AND gate 2038, OR gates 2036, 2060, and 2064, and inverters 1512, 1540, 2004, 2008, 2046, 2050, 2054, 2058, and 2062. In some embodiments, pre-regulator controller 1502 may be implemented as pre-regulator controller 2000.

[0091] During normal operation, the D flip-flop 1516 is based on V pwm_out and V boost_on Generate signal V 1516 , D flip-flop 2010 based on V pwm_out Generate signal V 1512 (e.g., via inverter 1512), D flip-flop 1530 is based on V pwm_out and V slow_off Generate signal V 1530 , and the D flip-flop 2044 is based on V pwm_out Generate signal V 1540 (eg, via inverter 1540). In some embodiments, delay circuits 2070 and 2072 are used to cause a delay t fix1 (and t fix2 ), for example, Figures 5 to 8 As shown in .

[0092] In some embodiments, D-type delay circuits 2034 and 2056 may be used as filtering logic, for example, to prevent glitches in a latch including NAND gates 1518 and 1528 .

[0093] like Figure 20 As shown in FIG, in some embodiments, D flip-flops 1516, 1530, 2010, and 2044 include a clear input to reset the flip-flops. In some embodiments, pulse generators 2002, 2006, 2014, 2042, 2048, 2052, 2032, and 2066 are used to set / reset flip-flops 2010, 1516, 2044, and 1530.

[0094] Figure 21A and Figure 21B 1 and 2. In some embodiments, each of the A-type pulse generator circuits 2002, 2006, 2014, 2042, 2048, 2052 can be implemented as the pulse generator circuit 2100.

[0095] Figure 22A and Figure 22B , respectively, illustrate a pulse generator circuit 2200 and associated waveforms according to an embodiment of the present invention. In some embodiments, each of the B-type pulse generator circuits 2032 and 2066 can be implemented as the pulse generator circuit 2200. Figure 21A and Figure 22A As shown, in some embodiments, the pulse generator circuits 2100 and 2200 may include the same delay circuit 2102 (e.g., as Figure 21A and Figure 22A As shown in , it is implemented using multiple buffers).

[0096] Figure 23A and Figure 23B 2 and 3. Delay circuit 2300 and associated waveforms according to an embodiment of the present invention are illustrated. In some embodiments, each of C-type delay circuits 2070 and 2072 can be implemented as pulse generator circuit 2300. In some embodiments, delay circuits 2070 and 2072 can be implemented using RC circuits instead.

[0097] Figure 24A and Figure 24B 2 and 3. Delay circuit 2400 and associated waveforms according to an embodiment of the present invention are respectively illustrated. In some embodiments, each of D-type delay circuits 2034 and 2056 can be implemented as delay circuit 2400.

[0098] Example embodiments of the present invention are summarized below. Other embodiments can be understood based on the overall composition of the description and claims presented herein.

[0099] Example 1. A method for shaping a pulse width modulated (PWM) signal, the method comprising: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: converting the output PWM signal using a first edge of the output PWM signal when the input PWM signal converts using a first edge of the input PWM signal; and delaying a second edge of the output PWM signal based on the first edge of the output PWM signal when the input PWM signal converts using a second edge before the first edge of the output PWM signal converts, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

[0100] Example 2. The method of Example 1, wherein delaying the second edge of the output PWM signal comprises delaying the second edge of the output PWM signal by a preset time plus a driving delay, wherein the driving delay is based on a delay of a driving circuit driving the output PWM signal.

[0101] Example 3. A method according to Example 1 or 2, wherein the drive circuit includes a high-side transistor and a low-side transistor coupled at a pre-filter node, a high-side gate driver coupled to the control terminal of the high-side transistor, and a low-side gate driver coupled to the control terminal of the low-side transistor.

[0102] Example 4. The method according to any one of Examples 1 to 3 further includes: comparing the output PWM signal with a first threshold; comparing the output PWM signal with a second threshold different from the first threshold; and when the second edge of the input PWM signal occurs before the first edge of the output PWM signal crosses the first threshold, delaying the conversion of the high-side intermediate signal and the low-side intermediate signal until the first edge of the output PWM signal crosses the second threshold, wherein generating the output PWM signal includes: generating the output PWM signal using a high-side transistor driven based on the high-side intermediate signal, and a low-side transistor driven based on the low-side intermediate signal.

[0103] Example 5. A method according to any one of Examples 1 to 4, wherein the first threshold is higher than the second threshold.

[0104] Example 6. The method of any one of Examples 1 to 5, wherein converting the high-side intermediate signal and the low-side intermediate signal comprises synchronously converting the high-side intermediate signal and the low-side intermediate signal.

[0105] Example 7. The method according to any one of Examples 1 to 6 further includes: when the input PWM signal is converted using the second edge after the first edge conversion of the output PWM signal, converting a high-side intermediate signal and a low-side intermediate signal based on the first edge conversion of the output PWM signal, wherein generating the output PWM signal includes: generating the output PWM signal using a high-side transistor driven based on the high-side intermediate signal, and a low-side transistor driven based on the low-side intermediate signal.

[0106] Example 8. The method according to any one of Examples 1 to 7 further includes: comparing the output PWM signal with a first threshold; comparing the output PWM signal with a second threshold different from the first threshold; and when the second edge of the input PWM signal occurs after the first edge of the output PWM signal crosses the first threshold, when the first edge of the output PWM signal crosses the second threshold, converting the high-side intermediate signal and the low-side intermediate signal.

[0107] Example 9. A method according to any one of Examples 1 to 8, wherein converting the output PWM signal using the first edge includes: converting the high-side intermediate signal and the low-side intermediate signal using a preset delay between the high-side intermediate signal and the low-side intermediate signal, and wherein when the second edge of the input PWM signal occurs after the first edge of the output PWM signal crosses the first threshold, converting the high-side intermediate signal and the low-side intermediate signal using a second delay time between the high-side intermediate signal and the low-side intermediate signal, the second delay time being less than the preset delay.

[0108] Example 10. A method according to any one of Examples 1 to 9, wherein the first edge of the PWM input signal is a rising edge, the second edge of the PWM input signal is a falling edge, the first edge of the PWM output signal is a rising edge, and the second edge of the PWM output signal is a falling edge.

[0109] Example 11. A method for shaping a pulse width modulated (PWM) signal, the method comprising: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal using a high-side transistor driven based on a high-side intermediate signal and a low-side transistor driven based on a low-side intermediate signal; driving the high-side intermediate signal and the low-side intermediate signal when the input PWM signal transitions with a first edge of the input PWM signal to cause the output PWM signal to transition with a first edge of the output PWM signal; and transitioning the high-side intermediate signal and the low-side intermediate signal based on the first edge of the output PWM signal to cause a second edge of the output PWM signal when the input PWM signal transitions with a second edge after the first edge of the output PWM signal transitions, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

[0110] Example 12. The method according to Example 11 further includes: when the input PWM signal is converted with the second edge before the first edge of the output PWM signal is converted, delaying the conversion of the high-side intermediate signal and the low-side intermediate signal to delay the second edge of the output PWM signal based on the first edge of the output PWM signal.

[0111] Example 13. A pulse width modulation (PWM) pre-regulation circuit, comprising: a PWM input configured to receive an input PWM signal; a high-side output and a low-side output, the high-side output and the low-side output configured to couple to control terminals of a high-side transistor and a low-side transistor, respectively; a switch detection input configured to couple to the high-side transistor and the low-side transistor to monitor an output PWM signal; and a controller configured to: when the input PWM signal transitions with a first edge of the input PWM signal, drive the high-side output and the low-side output to cause the output PWM signal to transition with the first edge of the output PWM signal; and when the input PWM signal transitions with a second edge before the first edge of the output PWM signal transitions, drive the high-side output and the low-side output based on the first edge of the output PWM signal to delay a second edge of the output PWM signal, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

[0112] Example 14. The PWM pre-regulation circuit according to Example 13 further includes a switch state detection circuit, the switch state detection circuit including: a first comparator having a first input coupled to the switch detection input and a second input configured to receive a first threshold; and a second comparator having a first input coupled to the switch detection input and a second input configured to receive a second threshold lower than the first threshold, wherein the controller is configured to determine whether the input PWM signal is converted using a second edge before the first edge of the output PWM signal is converted based on the output of the first comparator or the second comparator, and wherein the controller is configured to drive the high-side output and the low-side output based on the output of the first comparator or the second comparator to delay the second edge of the output PWM signal.

[0113] Example 15. The PWM pre-regulation circuit of Example 13 or 14 further includes: a first NAND gate having an output coupled to the high-side output and a first input coupled to the controller; and a second NAND gate having an output coupled to the low-side output and the second input of the first NAND gate, a first input coupled to the controller, and a second input coupled to the output of the first NAND gate.

[0114] Example 16. The PWM pre-regulation circuit according to any one of Examples 13 to 15 further includes: a first trigger having an input coupled to the PWM input and an output coupled to the first input of the first NAND gate; and a second trigger having a first input coupled to the output of the first trigger, a second input coupled to the switch detection input, and an output coupled to the third input of the first NAND gate.

[0115] Example 17. The PWM pre-regulation circuit according to any one of Examples 13 to 16 further includes: a switch state detection circuit, including: a first comparator having a first input coupled to the switch detection input, and a second input configured to receive a first threshold; and a second comparator having a first input coupled to the switch detection input, and a second input configured to receive a second threshold lower than the first threshold, wherein the second input of the second trigger is coupled to the switch detection input via the first comparator, and the controller further includes: a third trigger having an input coupled to the PWM input, and an output coupled to the second input of the second NAND gate; and a fourth trigger having a first input coupled to the output of the third trigger, a second input coupled to the output of the second comparator, and an output coupled to the third input of the second NAND gate.

[0116] Example 18. A PWM pre-regulation circuit according to any one of Examples 13 to 17, wherein the first flip-flop, the second flip-flop, the third flip-flop and the fourth flip-flop are D flip-flops, wherein the first input of the first flip-flop is a clock input, wherein the first input of the second flip-flop is a clock input, and the second input of the second flip-flop is a clear input, wherein the first input of the third flip-flop is a clock input, and wherein the first input of the fourth flip-flop is a clock input, and the second input of the fourth flip-flop is a clear input.

[0117] Example 19. A Class D amplifier comprising: an input terminal configured to receive an analog signal; an output terminal configured to couple to a load; an integrator circuit having a first input coupled to the input terminal and a second input coupled to the output terminal;

[0118] a pulse width modulation (PWM) modulator circuit having a first input coupled to the output of the integrator circuit, a second input configured to receive a clock signal, and an output configured to deliver a PWM signal; a pre-conditioning circuit having a first input coupled to the PWM modulator and a second input coupled to the output terminal; and an output stage having an input coupled to the output of the pre-conditioning circuit and an output coupled to the output terminal, the output stage configured to generate an output PWM signal at the output terminal based on the output of the pre-conditioning circuit, wherein the pre-conditioning circuit is configured to: cause the output PWM signal to transition with the first edge of the output PWM signal when the PWM signal transitions with the first edge of the PWM signal; and delay a second edge of the output PWM signal based on the first edge of the output PWM signal when the PWM signal transitions with the second edge before the first edge of the output PWM signal transitions with the second edge, wherein the second edge of the PWM signal is a next edge of the PWM signal after the first edge of the PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

[0119] Example 20. The Class D amplifier of Example 19, wherein the load is an audio speaker.

[0120] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments, will become apparent to those skilled in the art upon reference to this description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. A method for shaping a pulse width modulation (PWM) signal, the method comprising: Receive input PWM signal; Based on the input PWM signal, an output PWM signal is generated by: When the input PWM signal is switched using a first edge of the input PWM signal, switching the output PWM signal using a first edge of the output PWM signal; and When the input PWM signal transitions with a second edge before the first edge transitions of the output PWM signal, the second edge of the output PWM signal is delayed based on the first edge of the output PWM signal, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

2. The method of claim 1 , wherein delaying the second edge of the output PWM signal comprises: The second edge of the output PWM signal is delayed by a preset time plus a driving delay, wherein the driving delay is based on a delay of a driving circuit driving the output PWM signal.

3. The method of claim 2 , wherein the drive circuit comprises a high-side transistor and a low-side transistor coupled at a pre-filter node, a high-side gate driver coupled to a control terminal of the high-side transistor, and a low-side gate driver coupled to a control terminal of the low-side transistor.

4. The method according to claim 1, further comprising: comparing the output PWM signal with a first threshold; comparing the output PWM signal with a second threshold value different from the first threshold value; as well as When the second edge of the input PWM signal occurs before the first edge of the output PWM signal crosses the first threshold, switching the high-side intermediate signal and the low-side intermediate signal is delayed until the first edge of the output PWM signal crosses the second threshold, wherein generating the output PWM signal includes: generating the output PWM signal using a high-side transistor driven based on the high-side intermediate signal and a low-side transistor driven based on the low-side intermediate signal. The method according to claim 4 , wherein the first threshold is higher than the second threshold.

6. The method of claim 4 , wherein converting the high-side intermediate signal and the low-side intermediate signal comprises: The high-side intermediate signal and the low-side intermediate signal are converted synchronously.

7. The method according to claim 1, further comprising: When the input PWM signal is converted using the second edge after the first edge conversion of the output PWM signal, a high-side intermediate signal and a low-side intermediate signal are converted based on the first edge of the output PWM signal, wherein generating the output PWM signal includes: generating the output PWM signal using a high-side transistor driven based on the high-side intermediate signal and a low-side transistor driven based on the low-side intermediate signal.

8. The method according to claim 7, further comprising: comparing the output PWM signal with a first threshold; comparing the output PWM signal with a second threshold value different from the first threshold value; as well as When the second edge of the input PWM signal occurs after the first edge of the output PWM signal crosses the first threshold, the high-side intermediate signal and the low-side intermediate signal are switched when the first edge of the output PWM signal crosses the second threshold.

9. The method of claim 8, wherein converting the output PWM signal using the first edge comprises: The high-side intermediate signal and the low-side intermediate signal are converted with a preset delay between the high-side intermediate signal and the low-side intermediate signal, and wherein when the second edge of the input PWM signal occurs after the first edge of the output PWM signal crosses the first threshold, the high-side intermediate signal and the low-side intermediate signal are converted with a second delay time between the high-side intermediate signal and the low-side intermediate signal, the second delay time being less than the preset delay.

10. The method of claim 1, wherein the first edge of the input PWM signal is a rising edge, the second edge of the input PWM signal is a falling edge, the first edge of the output PWM signal is a rising edge, and the second edge of the output PWM signal is a falling edge.

11. A method for shaping a pulse width modulation (PWM) signal, the method comprising: Receive input PWM signal; generating an output PWM signal based on the input PWM signal using a high-side transistor driven by the high-side intermediate signal and a low-side transistor driven by the low-side intermediate signal; When the input PWM signal transitions with a first edge of the input PWM signal, driving the high-side intermediate signal and the low-side intermediate signal to cause the output PWM signal to transition with a first edge of the output PWM signal; as well as When the input PWM signal transitions with a second edge after the first edge transition of the output PWM signal, the high-side intermediate signal and the low-side intermediate signal are transitioned based on the first edge of the output PWM signal to result in a second edge of the output PWM signal, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

12. The method according to claim 11, further comprising: When the input PWM signal transitions with the second edge before the first edge transitions of the output PWM signal, transitions of the high-side intermediate signal and the low-side intermediate signal are delayed to delay the second edge of the output PWM signal based on the first edge of the output PWM signal.

13. A pulse width modulation (PWM) pre-regulation circuit, comprising: PWM input, configured to receive an input PWM signal; a high-side output and a low-side output configured to be coupled to control terminals of a high-side transistor and a low-side transistor, respectively; a switch detection input configured to be coupled to the high-side transistor and the low-side transistor to monitor an output PWM signal; as well as The controller is configured as: When the input PWM signal transitions with a first edge of the input PWM signal, driving the high-side output and the low-side output to cause the output PWM signal to transition with the first edge of the output PWM signal; as well as When the input PWM signal transitions with a second edge before the first edge transitions of the output PWM signal, the high-side output and the low-side output are driven based on the first edge of the output PWM signal to delay a second edge of the output PWM signal, wherein the second edge of the input PWM signal is a next edge of the input PWM signal after the first edge of the input PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

14. The PWM pre-regulation circuit according to claim 13, further comprising a switch state detection circuit, wherein the switch state detection circuit comprises: a first comparator having a first input coupled to the switch detection input and a second input configured to receive a first threshold; as well as a second comparator having a first input coupled to the switch detection input and a second input configured to receive a second threshold value lower than the first threshold value, wherein the controller is configured to determine whether the input PWM signal transitions with a second edge before the first edge transition of the output PWM signal based on an output of the first comparator or the second comparator, and wherein the controller is configured to drive the high-side output and the low-side output to delay the second edge of the output PWM signal based on the output of the first comparator or the second comparator.

15. The PWM pre-regulation circuit according to claim 13, further comprising: a first NAND gate having an output coupled to the high-side output and a first input coupled to the controller; as well as A second NAND gate has an output coupled to the low-side output and a second input of the first NAND gate, a first input coupled to the controller, and a second input coupled to the output of the first NAND gate.

16. The PWM pre-regulation circuit according to claim 15, further comprising: a first flip-flop having an input coupled to the PWM input and an output coupled to the first input of the first NAND gate; as well as A second flip-flop has a first input coupled to the output of the first flip-flop, a second input coupled to the switch detection input, and an output coupled to the third input of the first NAND gate.

17. The PWM pre-regulation circuit according to claim 16, further comprising: The switch state detection circuit includes: a first comparator having a first input coupled to the switch detection input and a second input configured to receive a first threshold; and a second comparator having a first input coupled to the switch detection input and a second input configured to receive a second threshold value lower than the first threshold value, wherein the second input of the second flip-flop is coupled to the switch detection input via the first comparator, the controller further comprising: a third flip-flop having an input coupled to the PWM input and an output coupled to the second input of the second NAND gate; and a fourth flip-flop having a first input coupled to the output of the third flip-flop, a second input coupled to the output of the second comparator, and an output coupled to the third input of the second NAND gate.

18. The PWM pre-regulation circuit according to claim 17, wherein the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are D flip-flops, wherein the first input of the first flip-flop is a clock input, wherein the first input of the second flip-flop is a clock input, and the second input of the second flip-flop is a clear input, wherein the first input of the third flip-flop is a clock input, and wherein the first input of the fourth flip-flop is a clock input, and the second input of the fourth flip-flop is a clear input.

19. A class D amplifier comprising: an input terminal configured to receive an analog signal; an output terminal configured to be coupled to a load; an integrator circuit having a first input coupled to the input terminal and a second input coupled to the output terminal; a pulse width modulation (PWM) modulator circuit having a first input coupled to the output of the integrator circuit, a second input configured to receive a clock signal, and an output configured to deliver a PWM signal; a pre-regulation circuit having a first input coupled to the PWM modulator and a second input coupled to the output terminal; as well as an output stage having an input coupled to the output of the pre-regulation circuit and an output coupled to the output terminal, the output stage configured to generate an output PWM signal at the output terminal based on the output of the pre-regulation circuit, wherein the pre-regulation circuit is configured to: causing the output PWM signal to transition with a first edge of the output PWM signal when the PWM signal transitions with a first edge of the PWM signal; and When the PWM signal transitions with a second edge before the first edge transitions of the output PWM signal, the second edge of the output PWM signal is delayed based on the first edge of the output PWM signal, wherein the second edge of the PWM signal is a next edge of the PWM signal after the first edge of the PWM signal, and wherein the second edge of the output PWM signal is a next edge of the output PWM signal after the first edge of the output PWM signal.

20. The Class D amplifier of claim 19, wherein the load is an audio speaker.

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