Speculative execution using page-level tracked load order queues

Abstract

Speculative execution using a page tracked load order queue includes determining that a first load instruction is directed to a determined memory region, and in response to the first load instruction being directed to the determined memory region, adding an entry to a page tracked load order queue instead of a load order queue, where the entry indicates a page address of a target of the first load instruction.

Description

Background Technology

[0001] During out-of-order execution of instructions, speculatively executed load instructions can be added to the load order queue. When an earlier load from the same thread has completed execution, the speculatively executed load can be removed from the load order queue. Further speculative execution is not permitted when the load order queue is full. Attached Figure Description

[0002] Figure 1 This is a block diagram of an exemplary processor for speculative execution using a load order queue with page-level tracing, according to some implementation schemes.

[0003] Figure 2 This is a flowchart of an exemplary method for speculative execution using a load order queue with page-level tracing, according to some implementation schemes.

[0004] Figure 3 This is a flowchart of an exemplary method for speculative execution using a load order queue with page-level tracing, according to some implementation schemes.

[0005] Figure 4 This is a flowchart of an exemplary method for speculative execution using a load order queue with page-level tracing, according to some implementation schemes.

[0006] Figure 5 This is a flowchart of an exemplary method for speculative execution using a load order queue with page-level tracing, according to some implementation schemes.

[0007] Figure 6 This is a flowchart of an exemplary method for speculative execution using a load order queue with page-level tracing, according to some implementation schemes. Detailed Implementation

[0008] In some implementations, a method for speculative execution using a load order queue of page-level tracing includes: determining a memory region identified by a first load instruction; and, in response to the memory region identified by the first load instruction, adding an entry to a load order queue of page-level tracing instead of a load order queue, wherein the entry indicates the page address of the target of the first load instruction.

[0009] In some embodiments, the method further includes determining that a second load instruction points to the determined memory region; determining that the second load instruction points to a page address identified in the entry; and updating the activity counter of the entry. In some embodiments, the method further includes determining that the second load instruction does not point to the determined memory region; and adding the entry to a load order queue based on the second load instruction. In some embodiments, the method further includes determining to remove an entry from the page-level tracked load order queue based on the state of a reordering buffer. In some embodiments, determining to remove an entry from the page-level tracked load order queue based on the state of a reordering buffer includes: decrementing the entry's activity counter based on the state of the reordering buffer; and removing the entry from the page-level tracked load order queue based on the activity counter. In some embodiments, the determined memory region is a program stack, and determining that a load instruction points to the determined memory region includes determining that a first load instruction points to a memory address relative to a stack pointer. In some embodiments, the first load instruction is associated with a first thread, and the method further includes: receiving a query from a second thread indicating a store instruction target; and initiating a pipeline flush in response to a store instruction target including a page address identified in the entry.

[0010] In some implementations, the load memory unit for speculative execution using a load order queue of page-level tracing performs the following steps: determining that a first load instruction points to the determined memory region; and in response to the first load instruction pointing to the determined memory region, adding an entry to a load order queue of page-level tracing instead of a load order queue, wherein the entry indicates the page address of the target of the first load instruction.

[0011] In some embodiments, the steps further include determining that the second load instruction points to the determined memory region; determining that the second load instruction points to the page address identified in the entry; and updating the activity counter of the entry. In some embodiments, the steps further include determining that the second load instruction does not point to the determined memory region; and adding the entry to the load order queue based on the second load instruction. In some embodiments, the steps further include determining to remove an entry from the page-level tracked load order queue based on the state of the reorder buffer. In some embodiments, determining to remove an entry from the page-level tracked load order queue based on the state of the reorder buffer includes: decrementing the entry's activity counter based on the state of the reorder buffer; and removing the entry from the page-level tracked load order queue based on the activity counter. In some embodiments, the determined memory region is a program stack, and determining that the load instruction points to the determined memory region includes determining that the first load instruction points to a memory address relative to the stack pointer. In some embodiments, the first load instruction is associated with a first thread, and the steps further include: receiving a query from a second thread indicating a store instruction target; and initiating a pipeline flush in response to a store instruction target including the page address identified in the entry.

[0012] In some implementations, a processor performing speculative execution using a page-level trace load order queue includes a load memory unit that performs the following steps: determining that a first load instruction points to the determined memory region; and in response to the first load instruction pointing to the determined memory region, adding an entry to a page-level trace load order queue instead of a load order queue, wherein the entry indicates the page address of the target of the first load instruction.

[0013] In some embodiments, the steps further include determining that the second load instruction points to the determined memory region; determining that the second load instruction points to the page address identified in the entry; and updating the activity counter of the entry. In some embodiments, the steps further include determining that the second load instruction does not point to the determined memory region; and adding the entry to the load order queue based on the second load instruction. In some embodiments, the steps further include determining to remove an entry from the page-level tracked load order queue based on the state of the reorder buffer. In some embodiments, determining to remove an entry from the page-level tracked load order queue based on the state of the reorder buffer includes: decrementing the entry's activity counter based on the state of the reorder buffer; and removing the entry from the page-level tracked load order queue based on the activity counter. In some embodiments, the determined memory region is a program stack, and determining that the load instruction points to the determined memory region includes determining that the first load instruction points to a memory address relative to the stack pointer. In some embodiments, the first load instruction is associated with a first thread, and the steps further include: receiving a query from a second thread indicating a store instruction target; and initiating a pipeline flush in response to a store instruction target including the page address identified in the entry.

[0014] In some implementations, the device for speculative execution using a page-level trace load order queue includes a processor that includes a load memory unit that performs the following steps: determining that a first load instruction points to the determined memory region; and in response to the first load instruction pointing to the determined memory region, adding an entry to a page-level trace load order queue instead of a load order queue, wherein the entry indicates the page address of the target of the first load instruction.

[0015] In some embodiments, the steps further include determining that the second load instruction points to the determined memory region; determining that the second load instruction points to the page address identified in the entry; and updating the activity counter of the entry. In some embodiments, the steps further include determining that the second load instruction does not point to the determined memory region; and adding the entry to the load order queue based on the second load instruction. In some embodiments, the steps further include determining to remove an entry from the page-level tracked load order queue based on the state of the reorder buffer. In some embodiments, determining to remove an entry from the page-level tracked load order queue based on the state of the reorder buffer includes: decrementing the entry's activity counter based on the state of the reorder buffer; and removing the entry from the page-level tracked load order queue based on the activity counter. In some embodiments, the determined memory region is a program stack, and determining that the load instruction points to the determined memory region includes determining that the first load instruction points to a memory address relative to the stack pointer. In some embodiments, the first load instruction is associated with a first thread, and the steps further include: receiving a query from a second thread indicating a store instruction target; and initiating a pipeline flush in response to a store instruction target including the page address identified in the entry.

[0016] Figure 1 This is a block diagram of a non-limiting exemplary processor 100 according to some embodiments. The exemplary processor 100 can be implemented in various computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, etc. The processor 100 includes a load-memory unit 102. The load-memory unit 102 is a dedicated execution unit (e.g., a combination of logic and / or circuitry) responsible for executing load and store instructions to generate virtual addresses for load and store operations, load data from memory, and / or store data from registers into memory.

[0017] Processor 100 executes some instructions out of order to improve performance. Therefore, load memory unit 102 speculatively executes load instructions relative to other instructions. For this purpose, load memory unit 102 maintains a load order queue 104. Load order queue 104 is a data structure that stores the speculatively executed load instructions in each entry. When all earlier loads relative to the speculatively executed loads in the load order queue 104 have been committed, an entry can be removed from the load order queue.

[0018] Load memory unit 102 can receive queries from another thread (e.g., from another processor or core via coherence interface 105) indicating a memory address that the other thread is accessing (e.g., writing to). If a memory address matches an entry in load order queue 104, a sorting violation occurs because the load might be executed incorrectly. Therefore, the execution pipeline must be flushed.

[0019] In existing solutions, all speculatively executed load instructions are added to a load order queue 104 or a similar data structure (e.g., a load memory queue, a load queue). When the load order queue 104 is full, additional load instructions cannot be speculatively executed, thus degrading performance. In contrast, the load memory unit 102 of the processor 100, which uses a load order queue with page-level tracing for speculative execution, determines whether a load instruction (e.g., a speculatively executed load instruction) points to a determined memory region. The determined memory region may include the program stack. Therefore, the load memory unit 102 determines whether a load instruction points to a memory address relative to the stack pointer stored in the stack register 106. For example, the instruction “movregX,[rsp+offset]” points to the program stack (the determined memory region) because the memory address from which data is loaded (identified as “rsp” in the instruction) is calculated by adding an offset to the stack pointer in the stack register 106. In contrast, the instruction “regX,[regBase+regIndex+offset]” does not point to the determined memory region because the memory address from which data is loaded is independent of the stack pointer.

[0020] Load instructions pointing to the program stack primarily hit the data cache 108, and are therefore processed faster than other load instructions. In many program scenarios (e.g., in highly looped or iterative code), load instructions pointing to the program stack disproportionately outnumber other load instructions, and are therefore disproportionately loaded into the load order queue 104, filling the queue and halting further speculative execution.

[0021] In response to a load instruction pointing to the identified memory region, load memory unit 102 adds an entry to the page-level tracking load order queue 110, rather than the load order queue 104. The entry indicates the page address of the target of the load instruction (e.g., the page address of the memory location of the identified memory region). The page size indicated in this entry depends on the minimum page size of the operating system being executed. Therefore, for an operating system implementing a minimum 4-kilobyte page size, each entry indicates the 4-kilobyte page address of a page in the identified memory region.

[0022] Each entry in the page-level tracing load order queue 110 also includes an activity counter that indicates the recentity of the execution of the load instruction pointing to the entry's page. For example, the activity counter may include multiple bits (e.g., two bits) initially all set to "1". When additional instructions are executed and / or submitted, the activity counter may be shifted one position to the right, as described below. For example, a two-bit activity counter set to "11" will be shifted to "01". The activity counter may later be set to "00", indicating that the entry can be removed from the page-level tracing load order queue 110.

[0023] Assuming the entry for the first load instruction is stored in the page-level trace load order queue 110, load memory unit 102 can determine that the second load instruction points to the determined memory region. If the second load instruction points to the page address identified in the entry, load memory unit 102 updates the entry's activity counter. For example, if the entry's activity counter is set to "01", the activity counter will be updated to "11". As another example, if the entry's activity counter is set to "11", the activity counter will remain at "11". Therefore, instead of adding a new entry to the page-level trace load order queue 110 for the second load instruction, the activity counter is updated. This allows multiple speculatively executed load instructions pointing to the same page address of the determined memory region to be reflected by a single entry in the page-level trace load order queue 110. Thus, more efficient memory usage is provided compared to existing solutions, where all load instructions are reflected by corresponding entries in the load order queue 104 or an equivalent data structure. If the second load instruction instead points to a page address not included in the entry of the page-level trace load order queue 110, a new entry will be created in the page-level trace load order queue for the second load instruction.

[0024] Load memory unit 102 can also determine that the received speculatively executed load instruction does not point to the determined memory region. Then, load memory unit 102 adds the entry to load order queue 104 based on the second load instruction. In other words, speculatively executed load instructions that do not point to the determined memory region cause the entry to be added to load order queue 104, while speculatively executed load instructions that point to the determined memory region cause the entry to be added or updated in the page-level trace load order queue 110.

[0025] Assume the entry for the first load instruction is stored in the page-level trace load order queue 110, and the first load instruction is associated with a first thread (e.g., executed by processor 100). Load memory unit 102 receives a query indicating the target of a store instruction from a second thread (e.g., executed by another processor or core, via coherence interface 105). If the target of the store instruction includes the page address of an entry in the page-level trace load order queue 110, an order violation is indicated. Therefore, the execution pipeline is flushed.

[0026] Load memory unit 102 determines to remove an entry from the page-level trace load order queue 110 based on the state of reorder buffer 112. Reorder buffer 112 stores instructions for speculative execution and the results of their "committed" in program order. For example, load memory unit 102 decrements (e.g., shifts) the activity counter of each entry in the page-level trace load order queue 110 for each buffer commit cycle of reorder buffer 112. A buffer commit cycle is when the number of instructions committed by reorder buffer 112 equals the number of entries in reorder buffer 112. For example, assuming reorder buffer 112 has one hundred entries, one buffer commit cycle is generated every one hundred instructions committed. When the entry's activity counter reaches "00" or another determined state, the entry can be removed from the page-level trace load order queue.

[0027] To further illustrate, Figure 2 A flowchart is provided illustrating an exemplary method for speculative execution using a load order queue with page-level tracking according to an embodiment of the present disclosure. The method includes (e.g., by load memory unit 102) determining that a first load instruction 204 (e.g., a speculatively executed load instruction) points to a determined memory region. The determined memory region may include a program stack. Therefore, the first load instruction 204 is determined to point to a memory address relative to a stack pointer stored in stack register 106. For example, the instruction “mov regX,[rsp+offset]” points to the program stack (the determined memory region) because the memory address from which data is loaded (identified as “rsp” in the instruction) is calculated by adding an offset to the stack pointer in stack register 106. In contrast, the instruction “mov regX,[regBase+regIndex+offset]” does not point to the determined memory region because the memory address from which data is loaded is independent of the stack pointer.

[0028] Figure 2The method further includes: in response to the first load instruction 204 pointing to the determined memory region, (e.g., by load memory unit 102) adding 206 an entry 208 to the page-level tracking load order queue 110 instead of the load order queue 104, wherein the entry 208 indicates the page address of the target of the first load instruction 204 (e.g., the page address of the memory location of the determined memory region). The page size indicated in the entry depends on the minimum page size of the operating system being executed. Thus, for an operating system implementing a minimum 4-kilobyte page size, each entry 208 indicates a 4-kilobyte page address of a page in the determined memory region.

[0029] Entry 208 in the page-level tracing load order queue 110 also includes an activity counter that indicates the recentity of the execution of the load instruction pointing to entry 208. For example, the activity counter may include multiple bits (e.g., two bits) initially all set to "1". When additional instructions are executed and / or committed, the activity counter may shift one position to the right. For example, a two-bit activity counter set to "11" will be shifted to "01". The activity counter may later be set to "00", indicating that the entry can be removed from the page-level tracing load order queue 110.

[0030] To further illustrate, Figure 2 A flowchart is provided illustrating an exemplary method for speculative execution using a load order queue with page-level tracing according to an embodiment of the present disclosure, the method comprising (e.g., by load memory unit 102) determining 202 that a first load instruction 204 (e.g., a load instruction for speculative execution) points to a determined memory region; and in response to the first load instruction 204 pointing to the determined memory region, (e.g., by load memory unit 102) adding 206 an entry 208 to a load order queue 110 with page-level tracing instead of load order queue 104, wherein entry 208 indicates the page address of the target of the first load instruction 204.

[0031] Figure 3 Methods and Figure 2 The difference in methods is that Figure 3 The method also includes (e.g., by load memory unit 102) determining that the second load instruction 304 points to the determined memory region (e.g., the program stack indicated by the stack pointer in stack register 106). Figure 3 Methods and Figure 2 The difference in methods also lies in, Figure 3The method also includes determining the page address identified in entry 208 that the second load instruction 304 points to. For example, load memory unit 102 determines whether the page address targeted by the second load instruction 304 results in a "hit" or match with entry 208 in the load order queue 110 of the page-level trace. Figure 3 Methods and Figure 2 The difference in methods also lies in, Figure 3 The method also includes (for example, by loading storage unit 102) updating the activity counter of entry 208 of 308.

[0032] For example, if the activity counter for entry 208 is set to "01", the activity counter will be updated to "11". As another example, if the activity counter for entry 208 is set to "11", the activity counter will remain at "11". Therefore, instead of adding a new entry to the load order queue 110 of the page-level trace for the second load instruction 304, the activity counter is updated. This allows multiple speculatively executed load instructions pointing to the same page address of the determined memory region to be reflected by a single entry 208 in the load order queue 110 of the page-level trace.

[0033] To further illustrate, Figure 4 A flowchart is provided illustrating an exemplary method for speculative execution using a load order queue 110 with page-level tracing according to an embodiment of the present disclosure. The method includes (e.g., by load memory unit 102) determining 202 that a first load instruction 204 (e.g., a load instruction for speculative execution) points to the determined memory region; and in response to the first load instruction 204 pointing to the determined memory region, (e.g., by load memory unit 102) adding 206 an entry 208 to the load order queue 110 with page-level tracing instead of the load order queue 104, wherein the entry 208 indicates the page address of the target of the first load instruction 204.

[0034] Figure 4 Methods and Figure 2 The difference in methods is that Figure 4 The method also includes (e.g., by load memory unit 102) determining that the second load instruction 404 does not point to the determined memory region (e.g., the program stack indicated by the stack pointer in stack register 106). Figure 4 Methods and Figure 2 The difference in methods is that Figure 4The method also includes adding entry 408 to load order queue 104 406 based on second load instruction 404. In other words, speculative load instructions that do not point to a determined memory region cause an entry to be added to load order queue 104, while speculative load instructions that point to a determined memory region cause an entry to be added to or updated in page-level trace load order queue 110.

[0035] To further illustrate, Figure 5 A flowchart is provided illustrating an exemplary method for speculative execution using a load order queue 110 with page-level tracing according to an embodiment of the present disclosure. The method includes (e.g., by load memory unit 102) determining 202 that a first load instruction 204 (e.g., a load instruction for speculative execution) points to the determined memory region; and in response to the first load instruction 204 pointing to the determined memory region, (e.g., by load memory unit 102) adding 206 an entry 208 to the load order queue 110 with page-level tracing instead of the load order queue 104, wherein the entry 208 indicates the page address of the target of the first load instruction 204.

[0036] Figure 5 Methods and Figure 2 The difference in methods is that Figure 5 The method also includes determining 502 entries from the page-level trace's load order queue 110 based on the state of the reorder buffer 112 (e.g., by load memory 102). The reorder buffer 112 stores instructions for speculative execution and the results of their "committed" in program order. For example, load memory 102 decrements (e.g., shifts) the activity counter of each entry in the page-level trace's load order queue 110 for each buffer commit cycle of the reorder buffer 112. A buffer commit cycle is when the number of instructions committed by the reorder buffer 112 equals the number of entries in the reorder buffer 112. For example, assuming the reorder buffer 112 has one hundred entries, one buffer commit cycle is generated every one hundred instructions committed. When the entry's activity counter reaches "00" or another determined state, the entry can be removed from the page-level trace's load order queue. Therefore, determining entry 208 based on the state of reorder buffer 112 includes decrementing the activity counter of entry 208 based on the state of reorder buffer 112 (e.g., buffer commit cycle) and removing entry 208 from the page-level tracked load order queue 110 based on the activity counter.

[0037] To further illustrate, Figure 6A flowchart is provided illustrating an exemplary method for speculative execution using a load order queue 110 with page-level tracing according to an embodiment of the present disclosure. The method includes (e.g., by load memory unit 102) determining 202 that a first load instruction 204 (e.g., a load instruction for speculative execution) points to the determined memory region; and in response to the first load instruction 204 pointing to the determined memory region, (e.g., by load memory unit 102) adding 206 an entry 208 to the load order queue 110 with page-level tracing instead of the load order queue 104, wherein the entry 208 indicates the page address of the target of the first load instruction 204.

[0038] Figure 6 Methods and Figure 2 The difference in methods is that Figure 6 The method also includes (e.g., via coherence interface 105) receiving 602 a query 604 from a second thread (e.g., executed by another processor or core) indicating a target for a stored instruction. The query corresponds to another executed or speculatively executed instruction that stores data for a target for a stored instruction (e.g., a memory address). Figure 6 Methods and Figure 2 The difference in methods also lies in, Figure 6 The method also includes initiating a 606 pipeline flush in response to a storage instruction target that includes the page address identified in entry 208. For example, loading the memory cell may determine whether the page address included in the storage instruction target matches the page address of the entry. Therefore, a sorting violation has occurred, and the execution pipeline is flushed.

[0039] In view of the foregoing description, the reader will recognize that the benefits of speculative execution using a load order queue for page-level tracing according to an embodiment of this disclosure include:

[0040] • By allowing multiple loads of the same page pointing to a defined memory region to be represented as a single entry, the storage efficiency of queued speculative load instructions is improved, thereby enhancing the performance of the computing system.

[0041] • By providing more efficient use of space in the load order queue, the likelihood of the load order queue being filled with load instructions pointing to a defined memory region is reduced, thereby preventing speculative execution from halting and improving the performance of the computing system.

[0042] Exemplary embodiments of this disclosure are described primarily in the context of a full-featured computer system for speculative execution using a load order queue with page-level tracing. However, those skilled in the art will recognize that this disclosure can also be embodied in computer program products set on a computer-readable storage medium for use with any suitable data processing system. Such computer-readable storage media can be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include disks in hard disk drives or floppy disks, optical discs for optical drives, magnetic tapes, and other media that will conceive of those skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means will be able to perform the steps of the methods of this disclosure as embodied in computer program products. Those skilled in the art will also recognize that while some of the exemplary embodiments described in this specification are directed to software installed on and executed on computer hardware, alternative embodiments implemented as firmware or hardware are also fully within the scope of this disclosure.

[0043] This disclosure can be a system, method, and / or computer program product. A computer program product may include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform aspects of this disclosure.

[0044] A computer-readable storage medium can be a tangible means capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punched cards or raised structures in grooves on which instructions are recorded, and any suitable combination of the foregoing. The computer-readable storage medium as used herein should not be construed as a transient signal, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0045] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and a wide area network / or a wireless network). The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0046] Computer-readable program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. As a standalone software package, the computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be (e.g., via the Internet using an Internet service provider) to an external computer. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by personalizing the electronic circuitry with status information from the computer-readable program instructions in order to perform various aspects of this disclosure.

[0047] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks of the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions.

[0048] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, establish means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other means to function in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0049] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which are executed on the computer, other programmable apparatus or other device, implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0050] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this respect, each block in a flowchart or block diagram may represent a module, segment, or portion comprising one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions mentioned in the blocks may occur in a different order than those shown in the drawings. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a system based on dedicated hardware that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0051] As will be understood from the foregoing description, modifications and changes can be made to various embodiments of this disclosure. The descriptions in this specification are for illustrative purposes only and should not be construed as limiting. The scope of this disclosure is limited only by the language of the appended claims.

Claims

1. A load storage unit for speculative execution using a load order queue with page-level tracing, the load storage unit being configured to perform steps including: Determine whether the first load instruction points to the determined memory region; In response to determining that the first load instruction does not point to the determined memory region, an entry is added to the load order queue; as well as In response to determining that the first load instruction points to the determined memory region, an entry is added to the load order queue of the page-level trace instead of the load order queue, wherein the entry indicates the page address of the target of the first load instruction.

2. The load storage unit of claim 1, wherein the load storage unit is further configured to perform steps including: Determine that the second load instruction points to the determined memory region; Determine that the second load instruction points to the page address identified in the entry; and Update the activity counter for the entry.

3. The load storage unit of claim 1, wherein the load storage unit is further configured to perform steps including: Determine that the second load instruction does not point to the determined memory region; and The entry is added to the loading order queue based on the second loading instruction.

4. The load storage unit of claim 1, wherein the load storage unit is further configured to perform the step of: determining, based on the state of the reorder buffer, to remove the entry from the load order queue of the page-level tracking.

5. The load memory unit of claim 4, wherein determining the removal of the entry from the page-level tracking load order queue based on the state of the reorder buffer comprises: The activity counter of the entry is decremented based on the state of the reordering buffer; as well as The entry is removed from the load order queue of the page-level tracking based on the activity counter.

6. The load memory unit of claim 1, wherein the determined memory region includes a program stack, and wherein determining that the load instruction points to the determined memory region includes determining that the first load instruction points to a memory address relative to the stack pointer.

7. The load memory unit of claim 1, wherein the first load instruction is associated with a first thread, and the load memory unit is further configured to perform steps including: Receive a query from the second thread indicating the target of the storage instruction; and A pipeline refresh is initiated in response to the storage instruction target that includes the page address identified in the entry.

8. A processor that performs speculative execution using a load order queue with page-level tracing, comprising: Load the storage unit, which is configured to perform steps including the following: Determine whether the first load instruction points to the determined memory region; In response to determining that the first load instruction does not point to the determined memory region, an entry is added to the load order queue; as well as In response to determining that the first load instruction points to the determined memory region, an entry is added to the load order queue of the page-level trace instead of the load order queue, wherein the entry indicates the page address of the target of the first load instruction.

9. The processor of claim 8, wherein the processor is further configured to perform steps including: Determine that the second load instruction points to the determined memory region; Determine that the second load instruction points to the page address identified in the entry; and Update the activity counter for the entry.

10. The processor of claim 8, wherein the processor is further configured to perform steps including: Determine that the second load instruction does not point to the determined memory region; and The entry is added to the loading order queue based on the second loading instruction.

11. The processor of claim 8, wherein the processor is further configured to perform the step of: determining, based on the state of the reorder buffer, to remove the entry from the load order queue of the page-level tracking.

12. The processor of claim 11, wherein determining to remove the entry from the page-level tracking load order queue based on the state of the reordering buffer comprises: The activity counter of the entry is decremented based on the state of the reordering buffer; as well as The entry is removed from the load order queue of the page-level tracking based on the activity counter.

13. The processor of claim 8, wherein the determined memory region includes a program stack, and wherein determining that the load instruction points to the determined memory region includes determining that the first load instruction points to a memory address relative to the stack pointer.

14. The processor of claim 8, wherein the first load instruction is associated with a first thread, and the processor is further configured to perform steps including: Receive a query from the second thread indicating the target of the storage instruction; and A pipeline refresh is initiated in response to the storage instruction target that includes the page address identified in the entry.

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