Manufacturing method of substrate with chip and substrate processing device

Abstract

A method for manufacturing a chip-carrying substrate comprises: preparing a stacked substrate comprising a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips; and separating the plurality of chips bonded to the first substrate and the second substrate from the first substrate so as to bond them to a side of a third substrate comprising a device layer.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a substrate with a chip and a substrate processing device. Background Art

[0002] FIG20 of Patent Document 1 illustrates a chip on wafer manufacturing process. In this manufacturing process, individual first memory chips are bonded to a base wafer on which a plurality of second memory chips are formed.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-46569 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] One embodiment of the present disclosure provides a technology capable of suppressing bonding defects between a chip and a substrate.

[0008] Solutions for solving problems

[0009] A method for manufacturing a chip-carrying substrate according to one embodiment of the present invention includes: preparing a stacked substrate comprising a plurality of the chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips; and separating the plurality of chips bonded to the first substrate and the second substrate from the first substrate so as to bond them to a surface of a third substrate including a device layer.

[0010] Effects of the Invention

[0011] According to one embodiment of the present disclosure, it is possible to suppress bonding defects between a chip and a substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a flowchart showing a method for manufacturing a chip-attached substrate according to one embodiment.

[0013] Figure 2 Yes Figure 1 Flowchart of the details of S1.

[0014] Figure 3 Yes Figure 1 Flowchart of the details of S6.

[0015] Figure 4A Yes Figure 1 A cross-sectional view of the midway state of S1.

[0016] Figure 4B Yes Figure 1 A cross-sectional view of the state when S1 is completed.

[0017] Figure 4C Yes Figure 1 A cross-sectional view of the state when S2 is completed.

[0018] Figure 4D Yes Figure 1 A cross-sectional view of the state when S3 is completed.

[0019] Figure 4E Yes Figure 1 A cross-sectional view of the midway state of S4.

[0020] Figure 4F Yes Figure 1 A cross-sectional view of the state when S4 is completed.

[0021] Figure 4G Yes Figure 1 A cross-sectional view of the state of S5 when it is completed.

[0022] Figure 4H Yes Figure 1 Included in the S6 Figure 3 A cross-sectional view of the state when S61 is completed.

[0023] Figure 4I Yes Figure 1 Included in the S6 Figure 3 A cross-sectional view of the state when S62 is completed.

[0024] Figure 4J Yes Figure 1 Included in the S6 Figure 3 A cross-sectional view of the S63 when completed.

[0025] Figure 4K Yes Figure 1 A cross-sectional view of the state of S7 when it is completed.

[0026] Figure 5 It is a plan view showing a substrate processing apparatus according to one embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, identical or corresponding structures are denoted by identical reference numerals, and description thereof may be omitted.

[0028] The method for manufacturing a substrate with a chip includes, for example, Figure 1 S1 to S7 shown. Figure 1 The S1 example includes Figure 2S11 to S14 shown. In addition, Figure 1 The S6 shown includes, for example, Figure 3 S61 to S63 shown.

[0029] First, in Figure 1 In S1, Figure 4A and Figure 4B As shown, the first substrate 1 is bonded to the chips 2A and 2B. Figure 1 S1 includes Figure 2 In S11 , the first substrate 1 and the chips 2A and 2B are prepared.

[0030] The first substrate 1 includes, for example, a silicon wafer 11, an absorption layer 12, and a bonding layer 13. As described later, the absorption layer 12 may also serve as the bonding layer 13. The first substrate 1 only needs to include the silicon wafer 11 and the absorption layer 12.

[0031] The absorption layer 12 is disposed between the silicon wafer 11 and the chips 2A and 2B. Figure 4H Laser beam LB2 shown here passes through silicon wafer 11 and is absorbed by absorption layer 12, as described in detail later. Absorption of laser beam LB2 by absorption layer 12 prevents it from reaching chips 2A and 2B, thereby preventing damage to chips 2A and 2B. Absorption layer 12 is, for example, a silicon oxide layer formed by thermal oxidation or CVD (Chemical Vapor Deposition).

[0032] Furthermore, the absorption layer 12 may be any layer capable of absorbing the laser beam LB2 to a degree sufficient to suppress damage to the chips 2A and 2B, and may be a silicon nitride layer or a silicon carbide nitride layer. The silicon nitride layer is formed by thermal nitridation or CVD. The silicon carbide nitride layer is formed by CVD.

[0033] like Figure 4A As shown, bonding layer 13 is disposed between absorber layer 12 and chips 2A and 2B, contacting chips 2A and 2B. Bonding layer 13 is, for example, an insulating layer such as a silicon oxide layer. Bonding layer 13 and absorber layer 12 can be made of different materials or the same material. In the latter case, absorber layer 12 can also serve as bonding layer 13.

[0034] The bonding layer 13 includes alignment marks 15 on its bonding surface 14 with the chips 2A and 2B. These alignment marks 15 are captured by a camera or the like and used to control the positions of the chips 2A and 2B. Furthermore, the position of the alignment marks 15 is not limited to the bonding surface 14 of the bonding layer 13; for example, the alignment marks 15 may also be located on the absorbent layer 12 or between the absorbent layer 12 and the bonding layer 13.

[0035] Meanwhile, chip 2A includes a silicon wafer 21A and a device layer 22A. Device layer 22A is formed on the surface of silicon wafer 21A. Device layer 22A includes semiconductor elements, circuits, terminals, etc. After forming device layer 22A, silicon wafer 21A is singulated into multiple chips 2A.

[0036] Like chip 2A, chip 2B includes a silicon wafer 21B and a device layer 22B. Device layer 22B has different functions from device layer 22A and has different thicknesses in chips 2A and 2B. After forming device layer 22B, silicon wafer 21B is singulated into multiple chips 2B.

[0037] exist Figure 1 S1 includes Figure 2 In step S12, the bonding surface 14 of the first substrate 1 is surface-modified using plasma or the like. Specifically, the SiO 2 bonds on the bonding surface 14 are cut to form dangling Si bonds, thereby making the bonding surface 14 hydrophilic.

[0038] For example, oxygen gas as a processing gas is excited in a reduced pressure atmosphere to form plasma and ionize it. The oxygen ions are irradiated onto the bonding surface 14 to modify the bonding surface 14. The processing gas is not limited to oxygen gas, and may be nitrogen gas, for example.

[0039] In the above S12, not only the bonding surface 14 of the first substrate 1 but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be surface-modified. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be surface-modified.

[0040] exist Figure 1 S1 includes Figure 2 In S13, the bonding surface 14 of the first substrate 1 is hydrophilized. For example, the first substrate 1 is held by a rotating chuck, and pure water such as DIW (deionized water) is supplied to the bonding surface 14 of the first substrate 1 that rotates along with the rotating chuck. Dangling bonds of Si on the bonding surface 14 are filled with OH groups, thereby hydrophilizing the bonding surface 14.

[0041] In the above S13, not only the bonding surface 14 of the first substrate 1 but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be hydrophilized.

[0042] exist Figure 1 S1 includes Figure 2In S14, the chips 2A and 2B are temporarily bonded one by one to the bonding surface 14 of the first substrate 1. The chips 2A and 2B are bonded to the first substrate 1 with the device layers 22A and 22B facing the first substrate 1.

[0043] The chips 2A and 2B are bonded to the first substrate 1 by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Afterwards, a heat treatment may be applied to increase the bonding strength. The heat treatment causes a dehydration reaction. Since the solids are directly bonded to each other without using a liquid adhesive, positional shifts caused by deformation of the adhesive and tilting caused by uneven thickness of the adhesive can be prevented.

[0044] Furthermore, unlike the technology disclosed herein, Patent Document 1 does not temporarily bond chips 2A and 2B to first substrate 1, but rather permanently bonds chips 2A and 2B to a third substrate 6 (described later). Therefore, bonding requires both suppressing the entry of air bubbles and foreign matter and performing highly precise position control.

[0045] When bonding the chips 2A and 2B to the third substrate 6 one by one as described in Patent Document 1, the chips 2A and 2B can be deformed one by one to prevent the entry of air bubbles during bonding. The bonding surfaces 24A and 24B of the chips 2A and 2B are deformed into downwardly convex curved surfaces, which are then gradually bonded to the third substrate 6 from the center toward the periphery, and finally return to a flat surface.

[0046] Deforming the bonding surfaces 24A and 24B of the chips 2A and 2B into downwardly convex curved surfaces involves securing the edges of the chips 2A and 2B and pressing down the centers of the chips 2A and 2B. However, due to the small size of each chip 2A and 2B, the gap between the securing position and the pressing position is narrow. Therefore, it is difficult to individually deform the chips 2A and 2B.

[0047] According to this embodiment, chips 2A and 2B are temporarily bonded to first substrate 1 and then separated from first substrate 1. Therefore, even if air bubbles are introduced when chips 2A and 2B are bonded to first substrate 1, no problem will arise. Thus, in step S14, bonding surfaces 24A and 24B of chips 2A and 2B can be bonded to bonding surface 14 of first substrate 1 in a flat state. Since chips 2A and 2B are not deformed, the accuracy of position control of chips 2A and 2B can be improved, allowing chips 2A and 2B to be accurately placed at the target position.

[0048] Furthermore, according to this embodiment, chips 2A and 2B are temporarily bonded to first substrate 1 and then separated from it. Therefore, even if particles are introduced during bonding of chips 2A and 2B to first substrate 1, no problems arise. Consequently, contamination of bonding surface 14 of first substrate 1 and bonding surfaces 24A and 24B of chips 2A and 2B can be minimized to a level that does not hinder bonding. The required cleanliness level can be reduced.

[0049] Then, in Figure 1 In S2, such as Figure 4C As shown in FIG, multiple chips 2A and 2B are thinned to make the thickness uniform. Figure 4C In FIG, the double-dashed line indicates the state immediately before S2, and the solid line indicates the state after S2 is completed. Silicon wafers 21A and 21B in chips 2A and 2B are thinned, while device layers 22A and 22B are not thinned. Thinning may include grinding or laser processing.

[0050] Then, in Figure 1 In S3, such as Figure 4D As shown, a bonding layer 3 is formed on the surfaces of chips 2A and 2B. Like bonding layer 13 of first substrate 1, bonding layer 3 is an insulating layer such as a silicon oxide layer, formed by a CVD method or the like. Chips 2A and 2B are spaced apart from each other, and the base surface of bonding layer 3 has irregularities, so the surface of bonding layer 3 also has irregularities.

[0051] Then, in Figure 1 In S4, Figure 4E and Figure 4F As shown, the surface of the bonding layer 3 is flattened. The bonding layer 3 is a silicon oxide layer or the like and has high hardness, so it takes time to flatten it by polishing such as CMP (Chemical Mechanical Polishing).

[0052] Therefore, first of all, Figure 4E As shown, laser light LB1 is irradiated onto convex portions 31 of bonding layer 3. Convex portions 31 absorb laser light LB1, changing their state from solid to gaseous, causing it to disperse, or directly dispersing in the solid phase. Alternatively, laser light LB1 can be irradiated onto concave portions 32 of bonding layer 3. As long as the irradiation intensity at concave portions 32 is lower than that at convex portions 31, the surface of bonding layer 3 can be flattened.

[0053] The irradiation point of laser beam LB1 is moved using a galvanometer scanner or an XYθ stage. The galvanometer scanner moves laser beam LB1. The XYθ stage moves first substrate 1 horizontally (in the X-axis and Y-axis directions) and rotates it about the vertical axis. An XYZθ stage can also be used in place of the XYθ stage.

[0054] Next, if Figure 4F As shown, the surface of the bonding layer 3 is further flattened by CMP, etc. Since the protrusions 31 are selectively removed before CMP, swelling remaining on the surface of the bonding layer 3 after CMP can be reduced.

[0055] Then, in Figure 1 In S5, such as Figure 4G As shown, the chips 2A and 2B are bonded to the second substrate 5. The second substrate 5 is in contact with the flattened surface of the bonding layer 3 and is bonded to the chips 2A and 2B via the bonding layer 3.

[0056] The second substrate 5 includes, for example, a silicon wafer 51 and a bonding layer 53. Like the bonding layer 13 of the first substrate 1, the bonding layer 53 is an insulating layer such as a silicon oxide layer and is formed by a CVD method or the like.

[0057] Alternatively, before bonding, surface modification and hydrophilization are performed on at least one of the bonding surface 54 of the second substrate 5 and the bonding surface 34 of the bonding layer 3. The second substrate 5 and the bonding layer 3 are bonded by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Since solids are directly bonded to each other without using a liquid adhesive, positional offsets caused by deformation of the adhesive can be prevented. In addition, the generation of tilt caused by uneven thickness of the adhesive can be prevented.

[0058] The second substrate 5 is bonded to the first substrate 1 via the bonding layer 3, with its bonding surface 54 facing downward. In other words, the substrates are bonded together. At this point, to prevent the entry of air bubbles, the bonding surface 54 of the second substrate 5 is deformed into a downwardly convex curved surface, gradually bonding from the center toward the periphery until it returns to a flat surface.

[0059] The second substrate 5 can be deformed by fixing its periphery and pressing its center downward. Compared to deforming the chips 2A and 2B individually, the gap between the fixing position and the pressing position is wider when deforming the second substrate 5, making deformation easier. This is because the substrates are bonded together.

[0060] Furthermore, the configuration of the second substrate 5 and the first substrate 1 can be reversed, and the second substrate 5 can be arranged below the first substrate 1, and the bonding surface 54 of the second substrate 5 can face upward. In this case, in order to prevent the entry of bubbles, the bonding surface 54 of the second substrate 5 is deformed into an upwardly convex curved surface, and gradually bonded from the center to the periphery, and finally restored to a flat surface.

[0061] Furthermore, to gradually bond the second substrate 5 to the first substrate 1 from the center toward the periphery, the second substrate 5 is first bent and deformed. However, the first substrate 1 can also be bent and deformed first. In this case, the substrates are also bonded together. However, from the perspective of protecting the chips 2A and 2B, it is preferable to keep the first substrate 1 flat, thereby keeping the chips 2A and 2B flat.

[0062] Then, in Figure 1 In S6, such as Figure 4H 、 Figure 4I as well as Figure 4J As shown, the chips 2A and 2B are separated from the first substrate 1. Figure 1 Included in the S6 Figure 3 In the S61, Figure 4H As shown, the laser beam LB2 forms a plurality of modified layers M on a predetermined dividing plane D, which is a plane dividing the first substrate 1 in the thickness direction. The modified layers M are formed in a dot shape, for example, at or above the focal point.

[0063] Laser beam LB2 passes through silicon wafer 11 of first substrate 1 to form modified layer M on absorption layer 12 of first substrate 1. Absorption layer 12 is positioned between silicon wafer 11 and chips 2A and 2B to absorb laser beam LB2. Laser beam LB2 rarely reaches chips 2A and 2B, thus minimizing damage to chips 2A and 2B.

[0064] Laser beam LB2 has a wavelength of, for example, 8.8 μm to 11 μm, so as to pass through silicon wafer 11 and be absorbed by absorption layer 12. The light source of laser beam LB2 is, for example, a CO2 laser (carbon dioxide laser). The wavelength of CO2 laser is approximately 9.3 μm. Laser beam LB2 is pulsed.

[0065] The formation position of the modified layer M is moved using a galvanometer scanner or an XYθ stage. The galvanometer scanner moves the laser beam LB2. The XYθ stage moves the first substrate 1 horizontally (in the X-axis and Y-axis directions) and rotates it about the vertical axis. An XYZθ stage can also be used in place of the XYθ stage.

[0066] A plurality of modified layers M are formed at intervals in the circumferential and radial directions of the first substrate 1. When the modified layers M are formed, cracks CR connecting the modified layers M to each other are also formed.

[0067] exist Figure 1 Included in the S6 Figure 3 In the S62, Figure 4IAs shown, the first substrate 1 is split with the modified layer M as the starting point. First, the upper suction cup 131 holds the first substrate 1, and the lower suction cup 132 holds the second substrate 5. However, the first substrate 1 and the second substrate 5 may be arranged in the reverse order, with the upper suction cup 131 holding the second substrate 5 and the lower suction cup 132 holding the first substrate 1. Next, when the upper suction cup 131 is raised relative to the lower suction cup 132, the crack CR propagates in a planar manner with the modified layer M as the starting point, and the first substrate 1 is split along the splitting plane D.

[0068] In the above-mentioned S62, the upper suction cup 131 may be rotated about its vertical axis simultaneously with the raising of the upper suction cup 131. This allows the first substrate 1 to be twisted and severed across the dividing surface D. Alternatively, the lower suction cup 132 may be lowered instead of, or in addition to, the raising of the upper suction cup 131. Furthermore, the lower suction cup 132 may be rotated about its vertical axis.

[0069] exist Figure 1 Included in the S6 Figure 3 The S63, such as Figure 4J As shown, residue 16 of first substrate 1 attached to chips 2A, 2B is removed by CMP or the like. Residue 16 includes a portion of absorber layer 12 and bonding layer 13. After residue 16 is removed, device layers 22A, 22B of chips 2A, 2B are exposed again.

[0070] Then, in Figure 1 In the S7, Figure 4K As shown, the chips 2A and 2B are bonded to a surface 64 of a third substrate 6 including a device layer 62 while being bonded to the second substrate 5. The third substrate 6 includes a silicon wafer 61 and a device layer 62.

[0071] The device layer 62 is formed on the surface of the silicon wafer 61. The device layer 62 includes semiconductor elements, circuits, terminals, etc., and is electrically connected to the device layers 22A and 22B of the chips 2A and 2B.

[0072] Alternatively, before bonding, at least one of the bonding surface 64 of the third substrate 6 and the bonding surfaces 24A, 24B of the chips 2A, 2B may be subjected to surface modification and hydrophilization. The third substrate 6 and the chips 2A, 2B are bonded by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Since the solids are directly bonded to each other without using a liquid adhesive, positional shifts caused by deformation of the adhesive can be prevented. In addition, tilting caused by uneven thickness of the adhesive can be prevented.

[0073] The third substrate 6 is bonded to the second substrate 5 with the chips 2A and 2B interposed therebetween, with its bonding surface 64 facing downward. In other words, the substrates are bonded together. To prevent the entry of air bubbles, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface, gradually bonding from the center toward the periphery until it returns to a flat surface.

[0074] Third substrate 6 can be deformed by fixing its periphery and pressing its center downward. Compared to deforming chips 2A and 2B individually, deformation of third substrate 6 is facilitated by the wider gap between the fixing position and the pressing position. This simplifies deformation because the substrates are bonded together.

[0075] Alternatively, the arrangement of the third substrate 6 and the second substrate 5 can be reversed, with the third substrate 6 positioned below the second substrate 5, and the bonding surface 64 of the third substrate 6 facing upward. In this case, to prevent the entry of bubbles, the bonding surface 64 of the third substrate 6 is deformed into an upwardly convex curved surface, gradually bonding from the center toward the periphery, and finally returning to a flat surface. In this case, the substrates are bonded together.

[0076] In order to gradually bond the third substrate 6 and the second substrate 5 from the center toward the periphery, the third substrate 6 is first bent and deformed, but the second substrate 5 may also be bent and deformed first. In this case as well, the substrates are bonded together.

[0077] Through the above S7, a chip-attached substrate 7 is obtained. The chip-attached substrate 7 includes a third substrate 6 and a plurality of chips 2A and 2B. The chip-attached substrate 7 also includes a second substrate 5. Alternatively, the second substrate 5 can be separated from the chips 2A and 2B. The chip-attached substrate 7 only needs to include the third substrate 6 and the chips 2A and 2B.

[0078] As described above, according to this embodiment, to obtain the chip-attached substrate 7, rather than bonding the plurality of chips 2A and 2B one by one to one surface of the third substrate 6, the plurality of chips 2A and 2B are first temporarily bonded to one surface of the first substrate 1. Because the entry of air bubbles at this stage does not pose a problem, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat. Since the chips 2A and 2B do not need to be forcibly deformed, the accuracy of positional control of the chips 2A and 2B can be improved, allowing the chips 2A and 2B to be accurately positioned at the target location.

[0079] Thereafter, the plurality of chips 2A and 2B bonded to the first substrate 1 are bonded to the surface of the second substrate 5 facing the first substrate 1. Next, the plurality of chips 2A and 2B bonded to the first substrate 1 and the second substrate 5 are separated from the first substrate 1. Next, the plurality of chips 2A and 2B separated from the first substrate 1 are bonded to a surface 64 of the third substrate 6 including the device layer 62 while still bonded to the second substrate 5.

[0080] At this time, in order to prevent the intrusion of bubbles, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface, which is slowly bonded from the center to the periphery, and finally restored to a flat surface. Compared with deforming the chips 2A and 2B one by one, it is easier to deform the third substrate 6. This is because the substrates are bonded to each other. Therefore, compared to the above-mentioned patent document 1, in which the chips 2A and 2B are permanently bonded to the third substrate 6 without temporarily bonding the chips 2A and 2B to the first substrate 1, a chip-attached substrate 7 can be obtained without the intrusion of bubbles and with good positioning accuracy.

[0081] Next, refer to Figure 5 Wait for the implementation of the instructions Figure 3 S61 and S62 of the substrate processing apparatus 100. Figure 5 In the figure, the X-axis, Y-axis, and Z-axis directions are perpendicular to each other, the X-axis and Y-axis directions are horizontal directions, and the Z-axis direction is a vertical direction. The substrate processing apparatus 100 includes a loading and unloading unit 101, a conveying unit 110, a laser processing unit 120, a dividing unit 130, and a control unit 140.

[0082] The loading and unloading section 101 has a loading section 102 for loading cassettes C. The cassettes C accommodate a plurality of sheets at intervals in the vertical direction. Figure 4G The laminated substrate 8 shown in FIG. 8 includes a plurality of chips 2A, 2B, a first substrate 1 and a second substrate 5. The laminated substrate 8 is as shown in FIG. Figure 4I As shown in FIG. 1 , the first divided body 81 and the second divided body 82 are separated by the dividing plane D. After that, the first divided body 81 and the second divided body 82 are respectively housed in the box C. The first divided body 81 includes the silicon wafer 11 and can be reused as a new first substrate 1 after being carried out of the substrate processing apparatus 100. On the other hand, the second divided body 82 includes the chips 2A and 2B and is provided to the substrate processing apparatus 100 after being carried out of the substrate processing apparatus 100. Figure 3 S63, and Figure 1 In addition, the number of the loading portion 102 and the number of the box C are not limited to Figure 5 Quantity shown.

[0083] The transport unit 110 is located adjacent to the loading / unloading unit 101, the laser processing unit 120, and the dividing unit 130, and transports the laminated substrate 8 and the like thereto. The transport unit 110 includes a holding mechanism for holding the laminated substrate 8 and the like. The holding mechanism is movable in the horizontal direction (both the X-axis and the Y-axis) and in the vertical direction, and is rotatable about the vertical axis.

[0084] The laser processing unit 120 is as follows Figure 4H As shown, a plurality of modified layers M are formed on a predetermined dividing surface D by laser light LB2, where the dividing surface D is a surface that divides the first substrate 1 in the thickness direction. The modified layer M is formed in a dot shape, for example, at or above the focal point. The laser processing unit 120 includes, for example, a workbench 121 for holding the first substrate 1, and an optical system 122 for irradiating the first substrate 1 held by the workbench 121 with the laser light LB2. The workbench 121 is, for example, an XYθ workbench or an XYZθ workbench. The optical system 122 includes, for example, a focusing lens. The focusing lens focuses the laser light LB2 toward the first substrate 1. The optical system 122 may also include a galvanometer scanner.

[0085] like Figure 4I As shown, the dividing portion 130 divides the first substrate 1 with the modified layer M as the starting point. The dividing portion 130 includes, for example, an upper suction cup 131 and a lower suction cup 132. The upper suction cup 131 holds the first substrate 1, and the lower suction cup 132 holds the second substrate 5. However, the configuration of the first substrate 1 and the second substrate 5 may be reversed up and down. Then, when the upper suction cup 131 is raised relative to the lower suction cup 132, the crack CR expands in a planar shape with the modified layer M as the starting point, and the first substrate 1 is divided through the dividing surface D. In other words, the stacked substrate 8 is divided into the first divided body 81 and the second divided body 82 through the dividing surface D. Alternatively, the upper suction cup 131 may be rotated around the vertical axis simultaneously with the raising of the upper suction cup 131. The first substrate 1 can be twisted off through the dividing surface D.

[0086] The control unit 140 is, for example, a computer. Figure 5 As shown, the control unit 140 includes a CPU (Central Processing Unit) 141 and a storage medium 142, such as a memory. The storage medium 142 stores programs for controlling various processes performed in the substrate processing apparatus 100. The control unit 140 controls the operation of the substrate processing apparatus 100 by causing the CPU 141 to execute the programs stored in the storage medium 142. The control unit 140 also includes an input interface 143 and an output interface 144. The control unit 140 receives external signals via the input interface 143 and transmits external signals via the output interface 144.

[0087] The above-mentioned program is stored in, for example, a computer-readable storage medium and is installed from the storage medium to the storage medium 142 of the control unit 140. Examples of computer-readable storage media include a hard disk (HD), a floppy disk (FD), a compact disk (CD), a magneto-optical disk (MO), and a memory card. Alternatively, the program can be downloaded from a server via a network and installed in the storage medium 142 of the control unit 140.

[0088] While embodiments of the chip-attached substrate manufacturing method and substrate processing apparatus according to the present disclosure have been described above, the present disclosure is not limited to the aforementioned embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. Such changes are naturally also within the technical scope of the present disclosure.

[0089] This application claims priority based on Japanese Patent Application No. 2019-196386 filed with the Japan Patent Office on October 29, 2019, and the entire contents of Japanese Patent Application No. 2019-196386 are cited herein.

[0090] Description of Reference Numerals

[0091] 1: First substrate; 11: Silicon wafer; 12: Absorption layer; 16: Residue; 2A, 2B: Chip; 3: Bonding layer; 5: Second substrate; 6: Third substrate; 7: Substrate with chip; 8: Stacked substrate; 100: Substrate processing device; 110: Conveying unit; 120: Laser processing unit; 130: Splitting unit; LB2: Laser beam; D: Splitting surface; M: Modified layer.

Claims

1. A method for manufacturing a substrate with a chip, comprising: preparing a laminate substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate with the plurality of chips interposed therebetween; separating the plurality of chips bonded to the first substrate and the second substrate from the first substrate so as to bond the chips to a surface of a third substrate including a device layer; as well as The plurality of chips separated from the first substrate are bonded to a surface of the third substrate including the device layer while being bonded to the second substrate.

2. The method for manufacturing a chip-attached substrate according to claim 1, wherein: Separating the plurality of chips from the first substrate includes: A plurality of modified layers are formed on a predetermined dividing surface, which is a surface for dividing the first substrate in a thickness direction, by a laser beam; and the first substrate is divided starting from the plurality of modified layers.

3. The method for manufacturing a chip-attached substrate according to claim 2, wherein: The first substrate includes a silicon wafer and an absorption layer for absorbing the laser light between the silicon wafer and the chip. The laser light passes through the silicon wafer to form the modified layer on the absorption layer.

4. The method for manufacturing a chip-attached substrate according to claim 3, wherein: The absorption layer is a silicon oxide layer.

5. The method for manufacturing a chip-attached substrate according to any one of claims 2 to 4, wherein: The wavelength of the laser light is 8.8 μm to 11 μm.

6. The method for manufacturing a chip-attached substrate according to any one of claims 2 to 4, wherein: The separation of the plurality of chips from the first substrate further includes: after the first substrate is divided by the dividing plane, removing residues of the first substrate attached to the chips.

7. A method for manufacturing a substrate with a chip, comprising: Temporarily bonding the plurality of chips one by one to one side of the first substrate; bonding the plurality of chips bonded to the first substrate to a surface of a second substrate facing the first substrate; separating the plurality of chips bonded to the first substrate and the second substrate from the first substrate; as well as The plurality of chips separated from the first substrate are bonded to a surface including a device layer of a third substrate while being bonded to the second substrate.

8. The method for manufacturing a chip-attached substrate according to claim 7, wherein: Also includes: After the plurality of chips are bonded to the first substrate and before the plurality of chips are bonded to the second substrate, the plurality of chips are thinned to make the thickness uniform.

9. The method for manufacturing a substrate with a chip according to claim 8, wherein: Also includes: After thinning the plurality of chips and before bonding the plurality of chips to the second substrate, a bonding layer for bonding the chips to the second substrate is formed on surfaces of the chips.

10. The method for manufacturing a chip-attached substrate according to claim 9, wherein: Also includes: After forming the bonding layer and before bonding the plurality of chips to the second substrate, a surface of the bonding layer that is to be in contact with the second substrate is flattened.

11. A substrate processing apparatus comprising: a conveying portion for conveying a stacked substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate with the plurality of chips interposed therebetween; a laser processing unit that forms a plurality of modified layers on a predetermined dividing surface by laser light, the dividing surface being a surface for dividing the first substrate in a thickness direction; a dividing portion for dividing the first substrate with the plurality of modified layers as a starting point to separate the plurality of chips bonded to the first substrate and the second substrate from the first substrate; as well as A control unit controls so that the plurality of chips separated from the first substrate are bonded to a surface including a device layer of a third substrate while being bonded to the second substrate.

12. The substrate processing apparatus according to claim 11, wherein: The first substrate includes a silicon wafer and an absorption layer for absorbing the laser light between the silicon wafer and the chip. The laser light passes through the silicon wafer to form the modified layer on the absorption layer.

13. The substrate processing apparatus according to claim 12, wherein: The absorption layer is a silicon oxide layer.

14. The substrate processing apparatus according to claim 12 or 13, wherein: The laser processing unit includes a carbon dioxide laser as a light source of the laser beam.

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