Chip Testing Device and Testing Method

Abstract

The present invention provides a chip testing device and a testing method. The device includes a clock module, a digital signal processing module, a control module, a communication connection circuit, a digital-to-analog converter, and a frequency doubling module. The clock module is used to generate an accurate clock signal with adjustable frequency. The control module configures the digital signal processing module to obtain digital signals with required frequencies and / or phases. The digital-to-analog converter converts the digital signals into reference signals. The frequency doubling module is electrically connected to the digital signal processing module and the chip under test respectively. The frequency doubling module adjusts the reference signals to generate high-speed jitter signals with increased jitter and tests the chip under test. The signals of the chip testing device of the present invention are obtained based on accurate clock signals, which can eliminate errors during testing, improve the accuracy of test results, and can control the frequency and / or phase of the reference signals, and can set different reference signals according to test requirements, which is convenient to use and convenient to perform tests with different requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to a chip testing device and a testing method. Background Art

[0002] With the development of semiconductor chips, the frequencies of chip input and output signals are getting higher and higher, and the requirements for the rise time and fall time of signals are also getting higher and higher. Therefore, it is necessary to use testing equipment to detect whether the functions of the chips meet the designed standards.

[0003] The jitter of a signal is an important indicator of the ability of a chip to output high-speed signals. The smaller the jitter of the output signal, the stronger the signal processing ability of the chip. The jitter of a signal will limit the maximum rate of chip pins. In chip testing, by adding jitter to the input signal of the chip through testing equipment and measuring the output signal of the chip, defective chips can be quickly detected to ensure the quality of the chips.

[0004] In the prior art, usually a noise waveform is superimposed on the input signal of the chip. The noise signal will increase the error of the output signal, making the jitter not a repetitive and predictable time jitter, resulting in inconsistent output signal quality and ineffective frequency control. Summary of the Invention

[0005] The purpose of the present invention is to provide a chip testing device and a testing method, which are used to solve the problems of high error of chip testing signals and ineffective control of testing signal frequencies.

[0006] In a first aspect, the present invention provides a chip testing device, which includes a clock module, a digital signal processing module, a control module, a communication connection circuit, a digital-to-analog converter, and a frequency doubling module; the clock module is electrically connected to the digital signal processing module, the control module is electrically connected to the digital signal processing module through the communication connection circuit, the clock module is used to generate a precise clock signal with adjustable frequency, and the clock module transmits the precise clock signal to the digital signal processing module; after receiving the precise clock signal, the digital signal processing module generates a waveform signal, and the control module controls the frequency register and / or phase register of the digital signal processing module to adjust the frequency and / or phase of the waveform signal to obtain a digital signal; the digital signal processing module is electrically connected to the digital-to-analog converter, the digital signal processing module transmits the digital signal to the digital-to-analog converter, and the digital-to-analog converter converts the digital signal into a reference signal; the frequency doubling module is respectively electrically connected to the digital-to-analog converter and the chip under test, the digital-to-analog converter transmits the reference signal to the frequency doubling module, after receiving the reference signal, the frequency doubling module adjusts the reference signal to generate a high-speed jitter signal with increased jitter, and the frequency doubling module transmits the high-speed jitter signal to the chip under test for testing.

[0007] The beneficial effects of the chip testing device of the present invention are as follows: The precise clock signal is provided by the clock module, and the digital signal processing module is controlled by the control module and the communication connection circuit. On the data information of the precise clock signal, the frequency and / or phase information input by the control module is superimposed to generate a digital signal. Then, through the action of the digital-to-analog converter, the digital signal is converted into the reference signal. After that, the reference signal is adjusted by the frequency doubling module to generate a high-speed jitter signal with increased jitter, and the high-speed jitter signal is used to test the chip under test. The high-speed jitter signal of the present application is obtained based on the precise clock signal, which ensures the accuracy of the basic data for generating the test signal, can avoid the error between the front and back test signals during testing, makes the test signal repeatable, improves the accuracy of the test result, and by configuring the digital signal processing module by the control module to adjust the precise clock signal, the frequency and / or phase of the reference signal can be controlled, and the reference signal with different frequencies and / or phases can be set according to the test requirements, which is convenient to use and convenient for testing with different requirements.

[0008] In a possible implementation, a low-pass filter is further included; the low-pass filter is electrically connected to the digital-to-analog converter and the frequency multiplication module respectively. The digital-to-analog converter transmits the reference signal to the low-pass filter, and the low-pass filter is used to filter out high-frequency signals in the reference signal, and the low-pass filter transmits the filtered reference signal to the frequency multiplication module. The beneficial effect is that: by filtering the impurity signals of the reference signal through the low-pass filter, the quality of the reference signal is improved, and the influence of high-frequency signals on the test result is reduced.

[0009] In a possible implementation, the register of the digital signal processing module is set as a frequency register, and the control module is used to adjust the frequency of the precise clock signal to obtain the reference signal. The beneficial effect is that: by setting the register of the digital signal processing module as a frequency register, conditions for frequency adjustment can be provided, which is convenient for adjusting the frequency of the precise clock signal.

[0010] In a possible implementation, the register of the digital signal processing module is set as a phase register, and the control module is used to adjust the phase of the precise clock signal to obtain the reference signal. The beneficial effect is that: by setting the register of the digital signal processing module as a phase register, conditions for phase adjustment can be provided, which is convenient for adjusting the phase of the precise clock signal.

[0011] In a possible implementation, the clock module is a clock circuit, and the clock circuit is provided with a voltage-controlled oscillator. The beneficial effect is that: by setting the clock module as a clock circuit, any operation of the generated precise clock signal is carried out in chronological order, which is convenient for eliminating errors. By setting the voltage-controlled oscillator, the accuracy and stability of the clock circuit can be improved.

[0012] In a possible implementation, the digital signal processing module is a DDS circuit. The beneficial effect is that: by setting the digital signal processing module as a DDS (Direct Digital Synthesizer, digital signal processing) circuit, the cost and power consumption can be reduced, and the conversion speed can be increased.

[0013] In a possible implementation, the DDS circuit adjusts the frequency accuracy of the precise clock signal to 0.005 to 0.02 hz, and the DDS circuit adjusts the phase accuracy of the precise clock signal to 0.011 to 0.044 degrees. The beneficial effects are as follows: By controlling and adjusting the accuracy of the frequency of the precise clock signal, the frequency of the high-speed jitter signal adjusted by the frequency multiplication module can be controlled within a certain range, which can improve the test accuracy; By controlling and adjusting the accuracy of the frequency of the precise clock signal, the phase accuracy of the high-speed jitter signal can be guaranteed, which is convenient for precise adjustment according to test requirements.

[0014] In a possible implementation, the adjustment bit accuracy of the frequency digital-to-analog converter of the digital signal processing module is 26 to 38 bits. The beneficial effects are as follows: Such a setting can ensure that the frequency accuracy of the reference signal is within a certain range.

[0015] In a possible implementation, the adjustment bit accuracy of the phase digital-to-analog converter of the digital signal processing module is 10 to 18 bits. The beneficial effects are as follows: Such a setting can ensure that the phase accuracy of the reference signal is within a certain range.

[0016] In a possible implementation, the frequency multiplication module is a transceiver (Multi-Gigabit Transceiver, MGT) of a Field Programmable Gate Array (FPGA). The beneficial effects are as follows: By setting the frequency multiplication module as an FPGA MGT, it is convenient to adjust the frequency of the reference signal during actual use and to adjust according to test requirements.

[0017] In a second aspect, the present invention provides a chip testing method, which is tested by the chip testing device in any feasible solution of the first aspect above, including the following steps:

[0018] S1. The clock module generates a precise clock signal and transmits it to the digital signal processing module;

[0019] S2. After receiving the precise clock signal, the digital signal processing module generates a waveform signal, and the control module controls the frequency register and / or the phase register of the digital signal processing module through the communication connection circuit to adjust the frequency and / or phase of the waveform signal to obtain a digital signal;

[0020] S3. The digital signal processing module transmits the digital signal to the digital-to-analog converter, the digital-to-analog converter converts the digital signal into a reference signal, and the digital-to-analog converter transmits the reference signal to the frequency multiplication module;

[0021] S4. The frequency doubling module receives the reference signal. After receiving the reference signal, the frequency doubling module adjusts the reference signal to generate a high-speed jitter signal with increased jitter, and the frequency doubling module transmits the high-speed jitter signal to the chip under test for testing.

[0022] The beneficial effect of the chip testing method of the present invention is that: by generating the precise clock signal through the clock module, the existence of errors is eliminated from the signal source, generating the waveform signal based on the precise clock signal, and controlling the frequency and / or phase of the waveform signal through the control module, the digital signal with the required frequency and / or phase and high accuracy can be obtained according to the test requirements. Then, the digital signal is converted into an available analog signal through the digital-to-analog converter, and the analog signal is the reference signal. Finally, under the action of the frequency doubling module, the frequency of the reference signal is adjusted to generate a high-speed test signal with increased jitter, so as to facilitate the subsequent testing of the quality of the chip under test through the high-speed test signal.

[0023] In a possible implementation, the digital signal processing module is a DDS circuit;

[0024] The control module controls the frequency register and / or the phase register of the digital signal processing module through the communication connection circuit to adjust the frequency and / or phase of the waveform signal to obtain the digital signal, which specifically includes:

[0025] S21. The control module configures the frequency register and / or the phase register of the DDS circuit;

[0026] S22. The control module transmits the frequency and / or phase information to the RAM of the DDS circuit;

[0027] S23. The RAM of the DDS circuit generates the digital signal according to the precise clock signal and the frequency and / or phase information.

[0028] The beneficial effect is that: by inputting the frequency and / or phase information through the control module and configuring the frequency register and / or the phase register of the DDS circuit to obtain the required digital signal, and then the specified test can be carried out on the basis of the digital signal. Description of the Drawings

[0029] Figure 1 It is a schematic structural diagram of the chip testing device in the embodiment of the present invention;

[0030] Figure 2 It is a schematic flow diagram of the chip testing method in the embodiment of the present invention.

[0031] Reference numerals in the figure:

[0032] 1. Clock module;

[0033] 2. Digital signal processing module;

[0034] 3. Control module;

[0035] 4. Communication connection circuit;

[0036] 5. Digital-to-analog converter;

[0037] 6. Low-pass filter;

[0038] 7. Frequency multiplier module;

[0039] 8. Test chip. Specific implementation manners

[0040] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0041] In the existing technology, the method for adding jitter to a signal is to superimpose a noise signal on the signal. The noise signal will increase the frequency error of the output signal, reduce the quality of the output signal, and affect the accuracy of the test.

[0042] In view of the problems existing in the existing technology, embodiments of the present invention provide a chip test device and a test method.

[0043] Figure 1 It is a schematic structural diagram of the chip test device in the embodiments of the present invention.

[0044] In some embodiments of the present invention, with reference to Figure 1, the chip testing device includes a clock module 1, a digital signal processing module 2, a control module 3, a communication connection circuit 4, a digital-to-analog converter 5, and a frequency multiplication module 7; the clock module 1 is electrically connected to the digital signal processing module 2, the control module 3 is electrically connected to the digital signal processing module 2 through the communication connection circuit 4, the clock module 1 is used to generate a precise clock signal with adjustable frequency, the clock module 1 transmits the precise clock signal to the digital signal processing module 2, after receiving the precise clock signal, the digital signal processing module 2 generates a waveform signal, and the control module 3 controls the frequency register and / or phase register of the digital signal processing module 2 to adjust the frequency and / or phase of the waveform signal to obtain a digital signal; the digital signal processing module 2 is electrically connected to the digital-to-analog converter 5, the digital signal processing module 2 transmits the digital signal to the digital-to-analog converter 5, and the digital-to-analog converter 5 converts the digital signal into a reference signal; the frequency multiplication module 7 is respectively electrically connected to the digital-to-analog converter 5 and the chip under test, the digital-to-analog converter 5 transmits the reference signal to the frequency multiplication module 7, after receiving the reference signal, the frequency multiplication module 7 adjusts the reference signal to generate a high-speed jitter signal with increased jitter, and the frequency multiplication module 7 transmits the high-speed jitter signal to the chip under test for testing.

[0045] In some embodiments, the clock module 1 is a clock circuit. The clock circuit includes a crystal oscillator clock chip and crystal capacitors, and the clock circuit outputs a working clock to the digital signal processing module 2.

[0046] In some other embodiments, the digital signal processing module 2 acquires the waveform data of the precise clock signal, and the digital signal processing module 2 obtains the waveform signal according to the waveform data.

[0047] In some other embodiments, the control module 3 is a core board. The core board is a board card integrated with chips such as a CPU, memory, and storage. The core board configures the frequency register and phase register of the digital signal processing module 2 through the communication connection circuit 4, stores the frequency and phase information of the required waveform into the digital signal processing module 2, and the digital signal processing module 2 outputs a waveform signal with the required frequency and phase according to the frequency and phase information and the precise clock signal, and then outputs the reference signal through the digital-to-analog converter 5.

[0048] In some other embodiments, the communication connection circuit 4 is a serial peripheral interface. The serial peripheral interface is a high-speed, full-duplex, synchronous communication bus.

[0049] In still some other embodiments, the frequency doubling module 7 is a transceiver (Multi-Gigabit Transceiver, MGT) of a Field Programmable Gate Array (FPGA). In some embodiments, the MGT is a multi-gigabit transceiver. Using the FPGA, the logic blocks inside the FPGA can be connected as needed, which is convenient to use and inexpensive. The reference signal output by the digital-to-analog converter 5 is sent to the FPGA, and the FPGA up-converts the reference clock, that is, up to the frequency of the test signal, and then sends the up-converted signal to the MGT circuit. The MGT circuit outputs a high-speed jitter test signal, that is, the high-speed jitter signal.

[0050] During use, the precise clock signal is generated by the clock module 1. The precise clock signal is an accurate circuit signal, which can eliminate the errors existing in the signals of the test chip 8 from the root cause. The digital signal processing module 2 is adjusted to generate the waveform signal based on the precise clock signal, and then the required frequency and phase are input through the control module 3. Under the connection of the communication connection circuit 4, the frequency and phase of the waveform signal are adjusted based on the frequency and phase information to obtain the digital signal, and then it is converted into the reference signal under the action of the digital-to-analog converter 5. Finally, the reference signal is frequency-adjusted by the frequency doubling module 7 to generate the high-speed jitter signal with increased jitter to test the test chip 8.

[0051] It is worth mentioning that the jitter results measured by the test chip 8 for test signals with different frequencies or phases are different, and the advantages and disadvantages of the chip can be inferred based on the results. Therefore, it is necessary to adjust the frequency and / or phase of the waveform signal generated by the digital signal processing module 2 through the control module 3 to obtain the reference signal for different test requirements. In addition, the frequency of the reference signal is adjusted by the frequency doubling module 7 to obtain the high-speed signal required for chip testing.

[0052] In some embodiments of the present invention, referring to Figure 1 , it further includes a low-pass filter 6; the low-pass filter 6 is electrically connected to the digital-to-analog converter 5 and the frequency doubling module 7 respectively. The digital-to-analog converter 5 transmits the reference signal to the low-pass filter 6, and the low-pass filter 6 is used to filter out the high-frequency signals in the reference signal, and the low-pass filter 6 transmits the filtered reference signal to the frequency doubling module 7.

[0053] In some other embodiments, the digital signal processing module 2 is a Direct Digital Synthesizer (DDS) circuit. The DDS circuit includes a frequency register, a phase register, an adder, and a memory.

[0054] In some embodiments of the present invention, the control module 3 configures the frequency register of the DDS circuit, stores the waveform data in the RAM of the DDS to obtain a digital signal with adjusted frequency, and outputs a reference signal with adjusted frequency through an analog-to-digital converter and a low-pass filter 6.

[0055] In some other embodiments of the present invention, the control module 3 adjusts the phase register of the DDS circuit, stores the waveform data in the RAM of the DDS to obtain a digital signal with adjusted phase, and outputs a reference signal with adjusted phase through an analog-to-digital converter and a low-pass filter 6.

[0056] In some embodiments, the core of the DDS system is a phase accumulator, which consists of an adder and a bit phase register. Each time a clock signal arrives, the phase register increases by a step size. The output of the phase register is added to the phase control word and then input to the address of the sine lookup table. The sine lookup table contains the digital amplitude information of a periodic sine wave, and each address corresponds to a phase point in the range of 0 degrees to 360 degrees of the sine wave. The lookup table maps the input address phase information into a digital quantity signal of the sine wave amplitude to obtain the digital signal. Then, under the drive of the digital-to-analog converter 5, an analog signal is output, and finally a reference signal is sent out.

[0057] In some embodiments of the present invention, referring to Figure 1 , the clock circuit is provided with a voltage-controlled oscillator.

[0058] In some specific embodiments of the present invention, the capacitance of the capacitor in the clock circuit is controlled by the voltage-controlled oscillator, thereby changing the resonant frequency of the clock circuit to ensure the stability of the circuit operating point and Q value.

[0059] In some embodiments of the present invention, referring to Figure 1 , the DDS circuit adjusts the frequency accuracy of the precise clock signal to 0.005 to 0.02 hz.

[0060] In some specific embodiments of the present invention, by setting the frequency accuracy of the precise clock signal adjusted by the DDS circuit to be between 0.005 and 0.02 hz, the frequency of the high-speed jitter signal obtained through the frequency doubling module 7 can be ensured within a certain range, ensuring the accuracy of the signal for testing the chip. For example, setting the frequency accuracy of the precise clock signal adjusted by the DDS circuit to 0.01 hz can limit the error between the actually obtained high-speed jitter signal and the theoretical value within a certain range when the frequency doubling module 7 processes the reference signal, reducing the error generated during operation.

[0061] In some embodiments of the present invention, referring to Figure 1 , the phase accuracy of the precise clock signal adjusted by the DDS circuit is 0.011 to 0.044 degrees.

[0062] In some specific embodiments of the present invention, by setting the phase accuracy of the precise clock signal adjusted by the DDS circuit to be between 0.011 and 0.044 degrees, the phase accuracy of the finally obtained high-speed jitter signal can be ensured. For example, setting the phase accuracy of the precise clock signal adjusted by the DDS circuit to 0.022 degrees.

[0063] In some embodiments of the present invention, referring to Figure 1 , the adjustment bit accuracy of the frequency digital-to-analog converter of the digital signal processing module 2 is 26 to 38 bits. The adjustment bit accuracy of the phase digital-to-analog converter of the digital signal processing module 2 is 10 to 18 bits.

[0064] In some specific embodiments of the present invention, by limiting the adjustment accuracy of the digital signal processing module 2, the error of the signal can be limited within a certain range, ensuring that the error of the result of testing the chip 8 is within a certain range. In some embodiments, the adjustment bit accuracy of the frequency digital-to-analog converter of the digital signal processing module 2 is 32 bits, and the adjustment bit accuracy of the phase digital-to-analog converter of the digital signal processing module 2 is 14 bits.

[0065] In some embodiments, if the clock frequency of the clock module 1 remains unchanged, the frequency accuracy of the DDS circuit is determined by the number of bits of the phase accumulator of the DDS circuit. During use, any frequency can be obtained by simply adjusting the number of bits of the phase accumulator.

[0066] Figure 2 It is a schematic flowchart of the chip testing method in the embodiments of the present invention.

[0067] In some embodiments of the present invention, referring to Figure 1 and Figure 2 , the chip testing method is tested through the chip testing device described in any of the above embodiments, including the following steps:

[0068] S1. The clock module 1 generates a precise clock signal and transmits it to the digital signal processing module 2;

[0069] S2. After receiving the precise clock signal, the digital signal processing module 2 generates a waveform signal. The control module 3 controls the frequency register and / or the phase register of the digital signal processing module 2 through the communication connection circuit 4 to adjust the frequency and / or the phase of the waveform signal to obtain a digital signal;

[0070] S3. The digital signal processing module 2 transmits the digital signal to the digital-to-analog converter 5. The digital-to-analog converter 5 converts the digital signal into a reference signal, and the digital-to-analog converter 5 transmits the reference signal to the frequency multiplication module 7;

[0071] S4. The frequency multiplication module 7 receives the reference signal. After receiving the reference signal, the frequency multiplication module 7 adjusts the reference signal to generate a high-speed jitter signal with increased jitter, and the frequency multiplication module 7 transmits the high-speed jitter signal to the chip under test for testing.

[0072] In some embodiments of the present invention, the digital signal processing module 2 is a DDS circuit;

[0073] The control module 3 controls the frequency register and / or the phase register of the digital signal processing module 2 through the communication connection circuit 4 to adjust the frequency and / or the phase of the waveform signal to obtain a digital signal, which specifically includes:

[0074] S21. The control module 3 configures the frequency register and / or the phase register of the DDS circuit;

[0075] S22. The control module 3 transmits the frequency and / or phase information to the RAM of the DDS circuit;

[0076] S23. The RAM of the DDS circuit generates the digital signal according to the precise clock signal and the frequency and / or phase information.

[0077] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments, and can be implemented or realized in various ways.

Claims

1. A chip testing device, characterized in that, It includes a clock module, a digital signal processing module, a control module, a communication connection circuit, a digital-to-analog converter, an FPGA, and a frequency doubling module; the frequency doubling module is the transceiver of the FPGA; The clock module is electrically connected to the digital signal processing module, and the control module is electrically connected to the digital signal processing module through the communication connection circuit. The clock module is used to generate an accurate clock signal with adjustable frequency, and the clock module transmits the accurate clock signal to the digital signal processing module; After receiving the accurate clock signal, the digital signal processing module acquires the waveform data of the accurate clock signal, obtains a waveform signal according to the waveform data, and the control module controls the frequency register and / or phase register of the digital signal processing module to adjust the frequency and / or phase of the waveform signal to obtain a digital signal; The digital signal processing module is electrically connected to the digital-to-analog converter. The digital signal processing module transmits the digital signal to the digital-to-analog converter, and the digital-to-analog converter converts the digital signal into a reference signal; The frequency doubling module is respectively electrically connected to the digital-to-analog converter and the chip under test. The digital-to-analog converter transmits the reference signal to the FPGA. After receiving the reference signal, the FPGA up-converts the reference signal to obtain an up-converted signal, and sends the up-converted signal to the frequency doubling module to generate a high-speed jitter signal with increased jitter. The frequency doubling module transmits the high-speed jitter signal to the chip under test for testing.

2. The chip testing device according to claim 1, wherein It further includes a low-pass filter; The low-pass filter is respectively electrically connected to the digital-to-analog converter and the frequency doubling module. The digital-to-analog converter transmits the reference signal to the low-pass filter. The low-pass filter is used to filter out the high-frequency signals in the reference signal, and the low-pass filter transmits the filtered reference signal to the frequency doubling module.

3. The chip testing device according to claim 1, characterized in that, The clock module is a clock circuit, and the clock circuit is provided with a voltage-controlled oscillator.

4. The chip testing device according to claim 1, characterized in that, The digital signal processing module is a DDS circuit.

5. The chip testing device according to claim 4, wherein, The DDS circuit adjusts the frequency accuracy of the accurate clock signal to 0.005 to 0.02 hz; the DDS circuit adjusts the phase accuracy of the accurate clock signal to 0.011 to 0.044 degrees.

6. The chip testing device according to claim 1, wherein, The adjustment bit accuracy of the frequency digital-to-analog converter of the digital signal processing module is 26 to 38 bits.

7. The chip testing device according to claim 1 or 6, characterized in that, The adjustment bit accuracy of the phase digital-to-analog converter of the digital signal processing module is 10 to 18 bits.

8. A chip testing method, characterized in that, Testing is performed by the chip testing device according to any one of claims 1 to 7, including the following steps: S1. The clock module generates an accurate clock signal and transmits it to the digital signal processing module; S2. After receiving the accurate clock signal, the digital signal processing module acquires the waveform data of the accurate clock signal, obtains a waveform signal according to the waveform data, and the control module controls the frequency register and / or the phase register of the digital signal processing module through the communication connection circuit to adjust the frequency and / or phase of the waveform signal to obtain a digital signal; S3. The digital signal processing module transmits the digital signal to the digital-to-analog converter, and the digital-to-analog converter converts the digital signal into a reference signal and transmits the reference signal to the frequency multiplication module; S4. The frequency multiplication module receives the reference signal, and after receiving the reference signal, the frequency multiplication module up-converts the reference signal to generate a high-speed jitter signal with increased jitter, and the frequency multiplication module transmits the high-speed jitter signal to the chip under test for testing.

9. The chip testing method according to claim 8, wherein The digital signal processing module is a DDS circuit; The control module controls the frequency register and / or the phase register of the digital signal processing module through the communication connection circuit to adjust the frequency and / or phase of the waveform signal to obtain a digital signal, specifically including: S21. The control module configures the frequency register and / or the phase register of the DDS circuit; S22. The control module transmits the frequency and / or phase information to the RAM of the DDS circuit; S23. The RAM of the DDS circuit generates the digital signal according to the precise clock signal and the frequency and / or phase information.

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