Method for managing operation of a system on chip

Abstract

The present disclosure relates to a method for managing the operation of a system on a chip. A system on a chip (SoC) includes: a system clock device configured to generate at least one system clock signal; a first region having a central processing unit; and a second region having a direct memory access (DMA) circuit, a peripheral device coupled to the DMA, and a memory containing (multiple) peripheral configuration descriptors that can be executed by the DMA circuit. In a first SoC operating mode, the system clock device delivers the system clock signal to all regions. In a second SoC operating mode, the system clock device does not deliver the system clock signal to any region. In a third SoC operating mode, the system clock device distributes the system clock signal to a portion of the second region without delivering the system clock signal to other regions, and the DMA circuit configures the peripheral device in response to the execution of the (multiple) configuration descriptors.

Description

[0001] Priority Claim

[0002] This application claims priority to French Patent Application No. 2012630 filed on December 3, 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments and examples relate to microelectronics, and more particularly to management of operation of a system on a chip (SOC), such as a microcontroller, and management of power consumption. Background Art

[0004] A system on a chip, in particular a microcontroller, comprises a number of components, in particular a central processing unit (CPU), such as a processor or microprocessor, one or more direct memory access (DMA) circuits, memory and peripherals, which may be different types of interfaces, such as supporting inter-integrated circuit (IIC) communication. 2 C) communication protocols, interfaces of the Serial Peripheral Interface (SPI) communication protocol and interfaces of the Universal Asynchronous Receiver Transmitter (UART) type. All these elements are usually connected to a system bus, for example of the Advanced Microcontroller Bus Architecture (AMBA) type.

[0005] The system on chip also includes a system clock device capable of generating a system clock signal for the system on chip.

[0006] SoC power consumption is a critical parameter, especially for battery-powered SoCs.

[0007] Typically, such a system on a chip has two operating modes, namely an operating mode called an "active" operating mode, in which the system bus and system clock are active, the central processing unit configures peripherals and the direct memory access circuit(s) perform data transfers.

[0008] The system-on-chip also has a mode called "low power" mode, in which the system bus and system clock are shut down, with limited peripheral functionality.

[0009] To save power, the system on chip may enter its low power mode and switch back to its active mode when needed, such as whenever the device needs to be reconfigured and the clock system is required by the direct memory access circuitry to perform a data transfer.

[0010] However, this switch from a low-power mode to an active mode results in an increased consumption of the central processing unit and a loss of performance, in particular in terms of bandwidth, due to the interrupt signals issued by the peripherals for delivery to the central processing unit.

[0011] Therefore, it is necessary to provide management for a system on chip, such as a microcontroller, so as to save power consumption and bandwidth of a central processing unit of the system on chip. Summary of the invention

[0012] According to one embodiment and example, it is particularly proposed to provide a third operating mode for the system on chip that is different from the first operating mode (called the "activation mode") and from the second operating mode (called the "low power" mode applicable to the entire system on chip), and this third operating mode is a local activation mode for at least one specific area of ​​the system on chip, thereby allowing other areas of the system on chip to remain in their "low power" mode.

[0013] The area to be locally "woken up" contains a direct memory access circuit (DMA), which is particularly capable of reconfiguring one or more peripheral devices of this wake-up area. In the prior art, only direct peripheral memory access circuit data transfer can be performed in "low power" mode, and peripheral device reconfiguration requires switching back to active mode.

[0014] According to one aspect, a system on chip, such as a microcontroller, is provided, comprising: a system clock device configured to generate at least one system clock signal; a first area comprising at least one central processing unit; and at least one second area comprising at least one direct memory access circuit, a peripheral device coupled to the direct memory access circuit, and a memory containing at least one configuration descriptor of the peripheral device and executable via direct memory access.

[0015] The second region is different from the first region.

[0016] In this article, the concept of region has a very general meaning.

[0017] Therefore, typically designers of microcontrollers divide the microcontroller into several domains, including, for example, a domain called the central processing unit (CPU) domain, which in turn may include, for example, direct memory access circuitry.

[0018] Also, the region may be the entire system-on-chip domain or a sub-domain of the system-on-chip domain.

[0019] Thus, if the CPU domain includes direct memory access circuitry and one or more peripheral devices in addition to a central processing unit, then the first region may be a subdomain of the CPU domain that includes the central processing unit, and the second region may be a subdomain of the CPU domain that includes the direct memory access circuitry and the peripheral device(s) coupled to the direct memory access circuitry.

[0020] Descriptors are DMA data transfer structures that are programmed into direct memory access circuit registers and are typically loaded from memory where the descriptors can be stored.

[0021] However, it is possible that the descriptors are loaded directly into registers of the direct memory access circuitry, for example when the system on chip is initialized.

[0022] For example, a descriptor defines one or more actions that may be performed by the direct memory access circuitry when the descriptor information is loaded into a register of the direct memory access circuitry.

[0023] The system on chip according to this aspect has a first operating mode in which the system clock device delivers the system clock signal to all regions. This first operating mode is therefore an active mode.

[0024] The system on chip has a second operating mode in which the system clock device does not deliver the system clock signal to any region. This second operating mode is therefore an overall "low power" mode.

[0025] The system on chip additionally has a third operating mode in which the system clock device distributes the system clock signal to at least a portion of the second region without delivering the system clock signal to other regions, and in which the direct memory access circuitry is capable of configuring the peripheral device in response to execution of the configuration descriptor.

[0026] This third operating mode is therefore a local activation mode, all other areas remaining in their "low power" mode.

[0027] Furthermore, unlike the prior art, the direct memory access circuitry is able to configure or reconfigure peripheral devices without requiring the central processing unit to "wake up" to do so.

[0028] According to one embodiment, the system on chip is configured to switch from its second operation mode to its third operation mode in the presence of a system clock signal request issued by one of the elements of the second region.

[0029] Furthermore, the system on chip is advantageously configured to switch back to its second mode of operation upon disappearance of any system clock signal request in the second region.

[0030] This also helps save energy.

[0031] According to one embodiment, the memory may contain a plurality of descriptors, each descriptor containing a request indication, the request indication being programmable and specifying for the descriptor a peripheral device capable of transmitting a request to the second region of the direct memory access circuit.

[0032] Likewise, each descriptor may contain a first trigger indication, which is programmable and indicates whether the execution of the descriptor may be triggered by a trigger signal outside the direct memory access circuit, the trigger signal originating from, for example, a peripheral device in the second area.

[0033] In addition, each descriptor may also contain a second trigger indication, which is programmable and specifies for the descriptor a peripheral device of the second region that is capable of transmitting a trigger signal that allows triggering the execution of the descriptor.

[0034] Thus, through these different indications, which can be programmed by a user, for example, depending on the application the system-on-chip has in mind, execution of complex scenarios can be provided, involving, for example, reconfiguration of peripherals and selection of peripherals, while keeping other areas of the system-on-chip in their low power modes.

[0035] The memory may also be configured to store a list of several link descriptors, which are sequentially addressable by the direct memory access circuit and respectively represent actions to be performed by the direct memory access circuit.

[0036] This list may contain the at least one reconfiguration descriptor.

[0037] Furthermore, when the memory contains several descriptors, the system clock device is configured to be in a third operation mode, distributing the system clock signal to all elements of the second area involved by the descriptor if there is a system clock signal emitted by one of the elements of the second area.

[0038] Thus, the direct memory access circuit can access all involved peripherals rather than just the one peripheral that requires the system clock signal.

[0039] By programming different indications of the request and trigger descriptors, this facilitates the development of complex implementation scenarios that can be executed locally by keeping other areas in their low power modes even when a list is present, since the direct memory access circuitry will have access to all involved elements of the second area that will have received the system clock signal without losing time.

[0040] The descriptor list may contain a selection of a peripheral request or a selection called a "memory to memory" selection (that is, a configuration in which a direct memory access circuit fetches, for example, data from a memory to store said data in one of the registers) and a trigger selection.

[0041] According to one embodiment, in the third operation mode, the direct memory access circuitry may be configured to trigger sequential execution of the linked descriptors in response to a trigger signal triggering execution of a first descriptor of the list.

[0042] The direct memory access circuit may have multiple processing channels, and in this case all descriptors may be assigned to a single channel or to several different channels.

[0043] Although a further memory separate from the memory may be provided to contain data to be written or read originating from or intended for at least one peripheral device of the second area, respectively, it may be advantageous for the memory to contain at least some of the descriptors which are also intended to contain such data to be written or read originating from or intended for at least one peripheral device of the second area, respectively.

[0044] As a non-limiting example, the second area may include at least one peripheral device, the peripheral device including I 2 Type-C interface, a device configured to deliver at least one trigger signal and possibly deliver several trigger signals periodically or non-periodically (for example but not limited to a timer, an input-output port, a comparator, a device for delivering asynchronous signals, ...).

[0045] Furthermore, the memory contains a list of link descriptors, including: a first configuration descriptor, intended to configure I in a first transmission direction (eg, in a transmitting direction); 2 C interface; the second descriptor is intended to transfer data from the memory to the I 2 C interface, and vice versa; a third configuration descriptor intended to configure I in the second transmission direction (e.g., in reception) 2 C interface; and a fourth descriptor, intended to transfer data from I according to the second transmission direction 2 C interface to the memory and vice versa.

[0046] And, the first descriptor of this list may be triggered, for example, in the presence of each trigger signal issued by the timer.

[0047] According to another aspect, a method for managing operation of a system on chip, such as a microcontroller, is provided.

[0048] The system on chip includes: a system clock device configured to generate at least one system clock signal; a first area including at least one central processing unit, such as a processor or a microprocessor; and at least one second area including at least one direct memory access circuit, a peripheral device coupled to the direct memory access circuit, and a memory containing at least one configuration descriptor of the peripheral device and executable by the direct memory access circuit.

[0049] The method according to this aspect selectively includes placing the system on chip in: a first operating mode in which the system clock device delivers the system clock signal to all regions; or a second operating mode in which the system clock device does not deliver the system clock signal to any region; or a third operating mode in which the system clock device distributes the system clock signal to at least a portion of the second region without delivering the system clock signal to other regions and wherein the direct memory access circuit configures the peripheral device in response to execution of the configuration descriptor.

[0050] According to one embodiment, the method includes switching from the second operating mode to the third operating mode in the presence of a system clock signal request issued by one of the components of the second region.

[0051] According to one embodiment, the method includes returning to the second mode of operation with the request disappearing of any system clock signal in the second region.

[0052] According to one embodiment, a memory contains a number of descriptors and the method includes programming a request indication for each descriptor, the request indication specifying for this descriptor a peripheral device capable of transmitting a request to the second region of the direct memory access circuit.

[0053] According to one embodiment, the method further comprises programming a first trigger indication for each descriptor, wherein the first trigger indication indicates whether the execution of this descriptor can be triggered by a trigger signal outside the direct memory access circuit.

[0054] According to one embodiment, the method further comprises programming a second trigger indication for each descriptor, the second trigger indication specifying for this descriptor a peripheral device of a second region capable of transmitting a trigger signal allowing to trigger the execution of the descriptor.

[0055] According to one embodiment, a method comprises storing a list of a plurality of link descriptors in a memory, the link descriptors being sequentially addressable by a direct memory access circuit and respectively representing actions to be performed by the direct memory access circuit.

[0056] The list contains, for example, the at least one reconfiguration descriptor.

[0057] According to one embodiment, the memory contains several descriptors and the method comprises, in a third operating mode, distributing a system clock signal to all elements of the second area to which the descriptors relate, in the presence of a system clock signal request issued by one of the elements of this second area.

[0058] According to one embodiment, the method includes triggering, by the direct memory access circuit in a third operating mode, sequential execution of the linked descriptors in response to a trigger signal triggering execution of a first descriptor of the list.

[0059] According to one embodiment, the direct memory access circuit has several channels and the method comprises allocating all descriptors to a single channel or to several different channels.

[0060] According to one embodiment, the method comprises storing in a memory data to be written or read, which data originate from or are intended for at least one peripheral device of the second area, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and embodiments and the accompanying drawings, which are in no way limiting, in which:

[0062] Figure 1 is a block diagram of the system on a chip;

[0063] Figure 2 is a block diagram of a direct memory access circuit;

[0064] Figure 3 is a block diagram of a memory circuit;

[0065] Figure 4 The steps of the method are shown;

[0066] Figure 5 is a block diagram of the system on a chip;

[0067] Figure 6 is a block diagram of a memory having stored descriptors;

[0068] Figure 7-Figure 8 shows the execution of actions associated with a given descriptor;

[0069] Fig. 9 is a block diagram of the system on a chip;

[0070] Fig.10 is a block diagram of a memory having stored descriptors; and

[0071] Fig.11 The execution of actions associated with the descriptors is shown. DETAILED DESCRIPTION

[0072] exist Figure 1 In the reference MCU, it means system on chip, which in this article is a microcontroller, including several areas: Z1, Z2, Z3.

[0073] The first zone Z1 contains a central processing unit (CPU) 1 , such as a processor, and other elements (E) 7 .

[0074] The second zone Z2, unlike the first zone Z1, comprises a direct memory access (DMA) circuit 2 of conventional structure and known per se, a memory (M) 3, such as a static random access memory (SRAM), and several peripheral devices (P), two of which are shown herein with reference numerals 40 and 41.

[0075] The microprocessor may also include other areas, such as a third area Z3.

[0076] As will be seen in more detail below, in this exemplary embodiment, the second zone Z2 is a specific zone that can be locally "woken up" while other zones remain in a low power mode.

[0077] The microcontroller MCU further comprises a clock generating device (C) 6 of conventional structure known per se, configured to generate a system clock signal SCLK.

[0078] This system clock signal can be delivered to the various components of the microcontroller in a controlled manner, for example by means of a clock gating unit.

[0079] The microcontroller also contains a system bus BS.

[0080] Of course, for the sake of simplicity, the microcontroller MCU may contain other elements not shown here, such as interconnection circuits known to those skilled in the art under the name "interconnect" to allow routing transactions between master devices and slave devices of the microcontroller.

[0081] Zones Z1 and Z2 can be two domains of a microcontroller or two subdomains of the same domain. Z3 can also be a domain or a subdomain of a microcontroller.

[0082] The structure of the direct memory access circuit 2 is well known to those skilled in the art, and in particular comprises (eg Figure 2 ) control logic (CL) 20, an address register (AR) 21 and several registers intended to contain data, such as in this case the indications contained in the descriptors stored in the memory 3.

[0083] These descriptors may, for example, contain a request indication which specifies for the descriptor concerned the peripheral device(s) which are able to transmit a request to the second region of the direct memory access circuit 2 .

[0084] Each descriptor may further include a first trigger indication, indicating whether the execution of the descriptor may be triggered by a trigger signal outside the direct memory access circuit.

[0085] Each descriptor may also contain a second trigger indication that specifies for this descriptor a peripheral device of a second region that is capable of transmitting a trigger signal that allows triggering execution of the descriptor.

[0086] All these instructions may be loaded from the memory 3 into the registers (R) 22 , 23 of the direct memory access circuit 2 .

[0087] All these indications are programmable, for example, by the user of the microcontroller according to the intended application and the scenario to be executed locally in the second zone Z2 while other zones of the microcontroller are in low power mode.

[0088] Among the descriptors that can be stored in the memory 3, consider one or more lists of link descriptors LLI1-LLIN, such as Figure 3 It is schematically shown in FIG.

[0089] The link descriptors of the list are sequentially addressable by the direct memory access circuit and respectively represent actions to be performed by the direct memory access circuit.

[0090] like Figure 4 It is schematically shown that the system on chip has a first operating mode MDF1 in which the system clock device delivers a system clock signal SCLK to all zones Zi.

[0091] This first operating mode is what is called “active” mode.

[0092] The system on chip furthermore has a second operating mode (or “low power” mode) in which the system clock device does not deliver the system clock signal SCLK to any zone Zi and all zones Zi are in their low power mode.

[0093] Furthermore, the system on chip includes a third operating mode MDF3, in which the system clock device distributes the system clock signal SCLK to at least a portion of the second zone Z2, and more specifically, as will be seen in more detail below, to all elements of this second zone involved in the execution of the descriptor, without delivering the system clock signal to other zones or other elements of the second zone not involved in the descriptor.

[0094] This third operating mode is therefore an active mode in the zone concerned, in this case the second zone Z2 , the other zones remaining in their low power mode.

[0095] As described above, a particularly simple way of controlling the distribution of the clock signal may consist of receiving the clock signal SCLK using a clock gating unit on the one hand and receiving a logic signal originating from a bit of a register assigned to each element of the second area on the other hand, if this bit is 1 for example, the system clock device delivers the clock signal SCLK to the element under consideration and if this bit is zero for example, the system clock device does not deliver the clock signal SCLK.

[0096] Also, the bits of this register are programmable, for example, by a user depending on the descriptor used.

[0097] like Figure 4 As shown, in the event of a request for a system clock signal SCLK from one of the elements in the second region, such as the peripheral device 40 (step ST40 ), the system on chip can switch from the second operation mode MDF2 to the third operation mode MDF3 .

[0098] As will be seen in more detail below, the system clock signal is advantageously distributed to all elements of the second region specified by the associated descriptor.

[0099] Furthermore, as shown by step ST41 , the system on chip may return to the second operation mode MDF2 based on disappearance of any system clock signal request in the second region.

[0100] Now refer to Figures 5 to 8 An example of implementation of the embodiment is shown.

[0101] exist Figure 5 In the figure, it is assumed that the second area Z2 of the microcontroller MCU includes, in addition to the direct memory access circuit 2 and the memory 3, an analog-to-digital converter (ADC) 40, a timer (T) 41 and an SPI type interface (IF) 42, which is connected to the external module MD via a bus supporting the SPI protocol.

[0102] The first zone Z1 contains the central processing unit 1 .

[0103] In this example, the analog-to-digital converter 40 is connected to the temperature sensor CPT and is configured to convert, at regular intervals, the analog data delivered by the sensor CPT.

[0104] Analog-to-digital converter 40 converts analog data into digital data at the rate of a control signal SC2 delivered periodically by timer 41, which in turn is clocked by its own clock signal and typically has a frequency lower than that of the system clock signal.

[0105] On the other hand, when the analog-to-digital converter 40 is ready to transmit data to the direct memory access circuit 2, the analog-to-digital converter must then use the system clock signal SCLK.

[0106] In this example, if Figure 6 As shown, the direct memory access circuit 2 has two processing channels CH1 and CH2. It is assumed here that the memory 3 stores a descriptor DSC1 associated with the first channel CH1 and a list of four link descriptors LLI1-LLI4 associated with the second channel CH2.

[0107] The first descriptor DSC1 relates to the transfer of digital data converted by the converter 40 to the memory 3 .

[0108] This descriptor is transferred from the memory 3 to a register of the direct memory access circuit 2 in order to define (in particular) the memory address.

[0109] The first descriptor LLI1 of the linked list processed by the second channel CH2 of the direct memory access circuit 2 is a reconfiguration descriptor that allows the threshold of the analog-to-digital converter to be increased.

[0110] More specifically, a first threshold TH1 is initially defined, for example, at 80° C. And when the curve of the value delivered by the temperature sensor CPT reaches this threshold TH1 , provision is then made to modify this first threshold TH1 to a second threshold TH2 having a value of, for example, 100° C.

[0111] Furthermore, the first descriptor LLI1 further includes a trigger indication indicating that it can be triggered.

[0112] In addition, the first descriptor includes a second trigger indication, which stipulates that the first descriptor can be triggered by the analog-to-digital converter when the first threshold TH1 is reached.

[0113] These two trigger indications are intended to be stored in the register 22 of the direct memory access circuit 2 .

[0114] And the execution of this first descriptor LLI1 is carried out by delivering the trigger signal SDL1 ( Figure 5 ) and is triggered.

[0115] The second descriptor LLI2 of this chain is the descriptor controlling the analog-to-digital converter 40 to issue an interrupt IT intended to wake up the central processing unit 1 when the curve of the analog value reaches a second threshold TH2 .

[0116] More specifically, the execution of this second descriptor LLI2 consists in writing an indication in an interrupt register of the converter 40 providing said indication to issue said interrupt IT when the threshold TH2 is reached.

[0117] The third descriptor LLI3 of this linked list is again a reconfiguration descriptor, this time aimed at reconfiguring the timer 41 so as to increase the sampling frequency of the converter 40 , that is to say to increase the delivery frequency of the signal SC2 .

[0118] Finally, the fourth descriptor of the linked list is a descriptor allowing the transfer of digital data, which have been delivered to the interface 42 by the analog-to-digital converter 40 and stored in the memory 3 , to be transmitted on the SPI bus to the external module MD.

[0119] Figure 7 and Figure 8 The execution of actions associated with the descriptor DSC1 on the channel CH1 and with the descriptors LLI1 - LLI4 on the channel CH2 is schematically described.

[0120] like Figure 7 As shown, in step ST60, once the analog data converted into digital data is ready to be transmitted to the direct memory access circuit 2 for storage in the memory 3, the analog-to-digital converter 40 issues a system clock signal SCLK request.

[0121] This clock signal SCLK is then distributed here to all elements of the second area, i.e. not only to the analog-to-digital converter 40, but also to the direct memory access circuit 2, the memory 3, the timer 41 and the interface 42, since the execution of the descriptors DSC1, LLI1, LLI2, LLI3 and LLI4 will involve all these elements.

[0122] Next, the converted digital data is transferred to the memory 3 via the direct memory access circuit 2 to the memory address contained in the address register 21 of the direct memory access circuit 2 .

[0123] As long as the value delivered by the temperature sensor does not reach the first threshold TH1 (step ST71 ) for the channel CH2 , the first descriptor LLI1 is not executed.

[0124] When the threshold TH1 is reached, the execution of the first descriptor LLI1 of the linked list is triggered by the emission of a trigger signal SDL1 (step ST72 ), which has the result of changing the threshold of the converter 40 from TH1 to TH2 (step ST73 ).

[0125] Next, in step ST74 , the second descriptor LLI2 is executed, which causes an indication to be written into the interrupt register of the converter 40 , which is intended to trigger the awakening of the central processing unit 1 by the emission of an interrupt IT, when the second threshold TH2 is reached.

[0126] Next, the third descriptor LLI3 is executed in step ST75. More specifically, the transmission frequency of the signal SC2 is changed in response to the control signal SC1. This increment value contained in the descriptor LLI3 is already stored in the register 22 of the direct memory access circuit 2.

[0127] Finally, the fourth descriptor LLI4 is executed to allow the value stored in the memory 3 to be transferred to the interface SPI42 (step ST76).

[0128] Reference now Figures 9 to 11 Another example embodiment is shown.

[0129] In this example, the second area Z2 contains a timer 45 and an I 2 C-type interface 44, which supports I 2 The bus of the C communication protocol is coupled to an external module, such as a sensor MD.

[0130] In this application example, provision is made for periodically transmitting data stored in the memory 3 to the external sensor MD and receiving data from this sensor MD to store said data in the memory 3 at the rate at which the timer 45 delivers the signal SDL2 .

[0131] In this regard, memory 3 contains a list with four link descriptors LLI10-LLI40 ( Fig.10 ).

[0132] The first descriptor of the list, LLI10, is a descriptor of the "memory to memory" type, intended to configure the interface 44 into transmit mode, setting at the same time the number of bytes to be transferred.

[0133] The second descriptor LLI20 is a descriptor of the “memory to peripheral” type, intended to transfer the number of bytes defined by the first descriptor LLI10 .

[0134] The third descriptor LLI30 is a configuration descriptor of the “memory to memory” type, intended to configure the interface 44 into reception mode, while setting the bytes to be received.

[0135] Finally, the fourth descriptor LLI40 is a descriptor of the “memory peripheral” type, intended to allow the reception of the number of bytes defined in the third descriptor LLI30 .

[0136] The timer 45 uses its own time base which is slower than the frequency of the system clock signal SCLK.

[0137] And, if Fig.11As shown, when the timer 45 periodically sends the signal SDL2 (step ST100) to the direct memory access circuit 2, this results in the triggering of the first descriptor LLI10 (step ST101).

[0138] Therefore, in step ST102 there is a request for the system clock signal SCLK issued by the direct memory access circuit 2, and therefore the system clock signal SCLK is distributed in step ST103 to all elements of the second area to which the descriptor of the chain refers, i.e. not only the direct memory access circuit 2 but also the memory 3 and I 2 C-Mount 44.

[0139] In step ST104 , the descriptor LLI10 is executed, which descriptor configures the interface 44 when transmitting.

[0140] The direct memory access circuit 2 then loads the data associated with the second descriptor LLI20, and then stops the distribution of the clock signal SCLK since there is no longer any request for the clock signal SCLK (step ST105).

[0141] When the interface 44 is ready to transfer data, there is again a request by the interface for the clock signal LCLK (step ST107), and the second descriptor LLI20 is executed (step ST106).

[0142] As shown in the loopback of the data transfer, the clock signal SCLK is allocated only for the "DMA" transfer of data (step ST107), and is not distributed between the "DMA" transfers (step ST108).

[0143] Next, when all the data have been transmitted, the third descriptor LLI30 is loaded from the memory 3 into the register of the direct memory access circuit, and the distribution of the clock signal SCLK is stopped again in step ST108 until the third descriptor LLI30 is executed in step ST109 to configure I when receiving. 2 C interface 44.

[0144] For this execution, the clock signal SCLK is distributed again in step ST110 .

[0145] And, in step ST111, when I 2 When the C interface receives data, the distribution of the signal SCLK is interrupted until the interface is ready to transfer the data to the direct memory access circuit by executing the descriptor LLI 40 in step ST112. The system clock signal SCLK is then distributed (step ST113).

[0146] Again, as shown in the loopback at the time of data reception, the clock signal SCLK is distributed only for the "DMA" transfer of data (step ST113), and is not distributed between "DMA" transfers (step ST114).

[0147] Of course, a dialog with a single sensor MD is described here. Of course, several sensors MD and multiple lists of linked descriptors similar to lists LLI10-LLI40 can be provided, which lists are executed successively in order to successively query the various sensors.

Claims

1. A system on chip, comprising: a system clock device configured to generate at least one system clock signal; The first area includes a central processing unit; a second region having an element, the element comprising: a direct memory access circuit, a peripheral device coupled to the direct memory access circuit, and a memory containing at least one configuration descriptor of the peripheral device, wherein the at least one configuration descriptor is executable by the direct memory access circuit; The system on chip comprises: a first operating mode in which the system clock device delivers the system clock signal to all zones; a second operating mode, wherein the system clock device does not deliver the system clock signal to any zone; as well as a third operating mode, wherein the system clock device distributes the system clock signal to at least part of the second region without delivering the system clock signal to other regions including the first region, and Wherein in the third operating mode the system clock device does not deliver the system clock signal to the first region having the central processing unit, the direct memory access circuit operates to configure the peripheral device in response to the execution of the at least one configuration descriptor. 2 . The system on chip according to claim 1 , configured to switch from the second operation mode to the third operation mode in the presence of a system clock signal request generated by one of the elements of the second region. 3 . The system on chip according to claim 2 , configured to switch from the third operation mode to the second operation mode when the system clock signal request from the element of the second region disappears.

4. The system on chip of claim 1 , wherein the at least one configuration descriptor in the memory comprises a plurality of descriptors, each of the plurality of descriptors containing a programmable request indication, the programmable request indication specifying, for the descriptor, the peripheral device capable of transmitting a request to the second region of the direct memory access circuit.

5. The system on chip according to claim 1, wherein the at least one configuration descriptor in the memory comprises a plurality of descriptors, each of the plurality of descriptors contains a first programmable trigger indication, and the first programmable trigger indication indicates whether the execution of the descriptor can be triggered by a trigger signal outside the direct memory access circuit.

6. The system on chip according to claim 5, wherein each of the plurality of descriptors further contains a second programmable trigger indication, the second programmable trigger indication specifying, for the descriptor, the peripheral device of the second area capable of transmitting the trigger signal, the trigger signal allowing triggering the execution of the descriptor.

7. The system on chip according to claim 1, wherein the memory is configured to store a list of a plurality of link descriptors, the plurality of link descriptors being sequentially addressable by the direct memory access circuit, and the plurality of link descriptors respectively representing actions to be performed by the direct memory access circuit.

8. The system on chip according to claim 7, wherein the list contains the at least one reconfiguration descriptor.

9. The system on chip of claim 7 , wherein the at least one configuration descriptor in the memory comprises a plurality of descriptors, each of the plurality of descriptors containing a first programmable trigger indication indicating whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit, and further wherein in the third operation mode, the direct memory access circuit is configured to trigger the sequential execution of the linked descriptors in response to the trigger signal triggering the execution of the first descriptor in the list.

10. The system on chip according to claim 1 is configured to switch from the second operation mode to the third operation mode in the presence of a system clock signal request generated by one of the elements of the second area, wherein the at least one configuration descriptor in the memory includes a plurality of descriptors, and wherein in the third operation mode, the system clock device is configured to distribute the system clock signal to all the elements of the second area involved by the plurality of descriptors in the presence of the system clock signal request issued by one of the elements of the second area.

11. The system on chip of claim 1, wherein the direct memory access circuit has a plurality of channels, and wherein the at least one configuration descriptor in the memory comprises a plurality of descriptors, and wherein the descriptors are assigned to a single channel.

12. The system on chip of claim 1, wherein the direct memory access circuit has a plurality of channels, and wherein the at least one configuration descriptor in the memory comprises a plurality of descriptors, and wherein the descriptors are assigned to a plurality of different channels.

13. The system on chip of claim 1, wherein the memory is further configured to contain data to be written or read originating from or intended for at least one peripheral device of the second region, respectively.

14. The system on chip according to claim 1, wherein the second area comprises: At least one peripheral device, including I 2 C-interface and means for delivering at least one trigger signal; and wherein the memory contains a list of link descriptors comprising: A first configuration descriptor is used to configure the I in the first transmission direction. 2 C interface; a second descriptor, for transmitting data from the memory to the I according to the first transmission direction; 2 C interface, or transfer the data from the I 2 C interface to transmit to the memory; The third configuration descriptor is used to configure the I in the second transmission direction. 2 C interface; as well as A fourth descriptor is used to transfer data from the I 2 C interface to the memory, or the data is transmitted from the memory to the I 2 C interface, the first descriptor of the list can be triggered in the presence of each trigger signal issued by the means for delivering.

15. A method for managing operation of a system on chip, the system on chip comprising: a system clock device configured to generate at least one system clock signal; a first region comprising a central processing unit; and at least one second region having elements comprising at least one direct memory access circuit, a peripheral device coupled to the direct memory access circuit, and a memory containing at least one configuration descriptor of the peripheral device executable by the direct memory access circuit, wherein the method comprises: selectively placing the system on chip into a first operating mode in which the system clock device delivers the system clock signal to all regions; selectively placing the system on chip into a second operating mode in which the system clock device does not deliver the system clock signal to any region; as well as selectively placing the system on chip into a third operating mode, wherein the system clock device distributes the system clock signal to at least a portion of the second region without delivering the system clock signal to other regions including the first region, and Wherein in the third operating mode the system clock device does not deliver the system clock signal to the first region having the central processing unit, the direct memory access circuit operates to configure the peripheral device in response to the execution of the at least one configuration descriptor.

16. The method according to claim 15, further comprising: In the presence of a system clock signal request generated by one of the elements of the second region, switching is performed from the second operation mode to the third operation mode.

17. The method according to claim 16, further comprising: When the system clock signal request from the element in the second region disappears, switching is performed from the third operation mode to the second operation mode.

18. The method of claim 15, wherein the at least one configuration descriptor in the memory comprises a plurality of descriptors, and the method comprises: A programmable request indication is contained for each of the plurality of descriptors, the programmable request indication specifying, for the descriptor, the peripheral device capable of transmitting a request to the second region of the direct memory access circuitry.

19. The method of claim 15, wherein the at least one configuration descriptor in the memory comprises a plurality of descriptors, the method further comprising: A first programmable trigger indication is programmed for each of the plurality of descriptors, the first programmable trigger indication indicating whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit.

20. The method of claim 19, further comprising programming a second programmable trigger indication, the second programmable trigger indication specifying, for the descriptor, the peripheral device of the second region capable of transmitting the trigger signal, the trigger signal enabling triggering of the execution of the descriptor.

21. The method of claim 15, further comprising: A list of a plurality of link descriptors is stored in the memory, the plurality of link descriptors are sequentially addressable by the direct memory access circuit, and the plurality of link descriptors respectively represent actions to be performed by the direct memory access circuit.

22. The method of claim 21, wherein the list contains the at least one reconfiguration descriptor.

23. The method of claim 21, wherein the at least one configuration descriptor in the memory comprises a plurality of descriptors, the method further comprising: programming a first programmable trigger indication for each of the plurality of descriptors, the first programmable trigger indication indicating whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit; as well as In the third mode of operation, the sequential execution of the linked descriptors is triggered by the direct memory access circuitry in response to the trigger signal triggering the execution of a first descriptor in the list.

24. The method of claim 15, further comprising: switching from the second operating mode to the third operating mode in the presence of a system clock signal request generated by one of the elements of the second region; storing a plurality of descriptors in the memory; as well as In the third operation mode, and in the presence of a system clock signal request generated by one of the elements of the second region, the system clock signal is distributed to all of the elements in the second region referred to by the descriptor.

25. The method of claim 15, wherein the direct memory access circuit has a plurality of channels, and the method further comprises: All of said descriptors are assigned to a single channel.

26. The method of claim 15, wherein the direct memory access circuit has a plurality of channels, and the method further comprises: All of the descriptors are assigned to several different channels.

27. The method of claim 15, further comprising: Data to be written or read, respectively originating from or intended for at least one peripheral device of the second area, are stored in the memory.

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