Verification method, electronic device, and storage medium

Abstract

The present disclosure provides a verification method, electronic device, and storage medium. The verification method includes: providing multiple chipsets, wherein the interconnect modules of the chipsets include at least one of a physical layer, a link layer, and a network layer; selecting a first chipset from the multiple chipsets; selecting a second chipset from the multiple chipsets, wherein the second chipset includes a selected interconnect layer, and the selected interconnect layer is one of a physical layer and a link layer; selecting a first interconnect module from at least one interconnect module in the first chipset; selecting one of the physical layer and the link layer of the first interconnect module as a target interconnect layer; interconnecting the first interconnect module and the selected interconnect layer, thereby providing a verification path in the selected interconnect layer, so that the target interconnect layer transmits verification stimulus or verification output to verify the first chipset. The verification method adopts layered modeling verification, which can reduce the scale of the verification platform and speed up simulation.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a verification method, an electronic device, and a storage medium. Background Art

[0002] System-on-Chip (SoC) is also known as a system on a chip. With the advancement of process technology, a large SoC has been broken down into different chipsets, for example, based on functionality. These chipsets are fabricated as independent dies using different process flows, and then packaged together to form a system-on-chip. The importance of interconnection between different chipsets has gradually become apparent, and with the advancement of interconnection technology, interconnection verification has become increasingly important. However, the large size of a chipset and the slow simulation speed, coupled with the fact that different products have different chipset combinations and verification must cover these diverse product combinations, have made verification of inter-chipset interactions increasingly complex and difficult. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a verification method, comprising: providing multiple chipsets, wherein each of the multiple chipsets includes at least one interconnection module, and each of the at least one interconnection module includes at least one of a physical layer, a link layer, and a network layer; selecting a first chipset from the multiple chipsets, wherein the first chipset is a chipset to be tested; selecting a second chipset from the multiple chipsets, wherein the interconnection module of the second chipset includes a selected interconnection layer, and the selected interconnection layer is configured as one of a physical layer and a link layer of the interconnection module of the second chipset; selecting a first interconnection module from at least one interconnection module in the first chipset; selecting one of the physical layer and the link layer of the first interconnection module as a target interconnection layer; interconnecting the first interconnection module of the first chipset and the selected interconnection layer of the second chipset, thereby providing a verification path for the selected interconnection layer of the second chipset to transmit a verification stimulus or a verification output to verify the first chipset.

[0004] For example, a verification method provided by at least one embodiment of the present disclosure also includes: using a verification system to provide the verification stimulus to the target interconnect layer through a selected interconnect layer in the second chipset and receiving the verification output from the target interconnect layer, or using a verification system to receive the verification stimulus from the target interconnect layer through a selected interconnect layer in the second chipset and providing the verification output to the target interconnect layer.

[0005] For example, in a verification method provided in at least one embodiment of the present disclosure, the verification system includes a universal verification module.

[0006] For example, in a verification method provided by at least one embodiment of the present disclosure, the selected interconnection layer of the second chipset is directly interconnected with the verification system.

[0007] For example, in a verification method provided by at least one embodiment of the present disclosure, selecting one of the physical layer and the link layer of the first interconnection module as the target interconnection layer includes: selecting the link layer of the first interconnection module as the target interconnection layer.

[0008] For example, in a verification method provided by at least one embodiment of the present disclosure, interconnecting the first interconnection module of the first chipset and the selected interconnection layer of the second chipset includes: in response to the selected interconnection layer of the second chipset being a link layer, directly interconnecting the link layer of the second chipset with the link layer of the first interconnection module, and disconnecting the link layer of the first interconnection module from the physical layer of the first interconnection module.

[0009] For example, in a verification method provided by at least one embodiment of the present disclosure, the link layer of the second chipset is directly interconnected with the verification system.

[0010] For example, in a verification method provided by at least one embodiment of the present disclosure, selecting one of the physical layer and the link layer of the first interconnection module as the target interconnection layer includes: selecting the physical layer of the first interconnection module as the target interconnection layer.

[0011] For example, in a verification method provided by at least one embodiment of the present disclosure, the first interconnection module of the first chipset and the selected interconnection layer of the second chipset are interconnected, including: in response to the selected interconnection layer of the second chipset being the physical layer, the second chipset includes a physical layer and the physical layer of the second chipset is directly interconnected with the physical layer of the first interconnection module and the verification system, respectively; in response to the selected interconnection layer of the second chipset being the link layer, the second chipset includes a physical layer and a link layer, and the second chipset also includes a physical layer, the physical layer of the second chipset is interconnected with the link layer of the second chipset, and the physical layer of the second chipset is directly interconnected with the physical layer of the first interconnection module.

[0012] For example, in a verification method provided by at least one embodiment of the present disclosure, in response to the second chipset selecting the interconnection layer as the physical layer, the physical layer of the second chipset is directly interconnected with the verification system; in response to the second chipset selecting the interconnection layer as the link layer, the link layer of the second chipset is directly interconnected with the verification system.

[0013] For example, in a verification method provided by at least one embodiment of the present disclosure, a verification system is used to provide the verification stimulus to the target interconnect layer through the selection interconnect layer in the second chipset and receive the verification output from the target interconnect layer, including: the verification system sends the verification stimulus to the selection interconnect layer; the selection interconnect layer provides the verification stimulus to the target interconnect layer, and transmits the verification stimulus through the network layer of the first chipset, so that the first chipset obtains the corresponding verification output according to the verification stimulus; the network layer of the first chipset obtains the verification output and sends the verification output to the selection interconnect layer through the target interconnect layer; the verification system receives the verification output from the selection interconnect layer.

[0014] For example, in a verification method provided by at least one embodiment of the present disclosure, a verification system is used to receive the verification stimulus from the target interconnect layer through the selected interconnect layer in the second chipset and provide the verification output to the target interconnect layer, including: transmitting the verification stimulus provided by the first chipset to the target interconnect layer through the network layer of the first chipset; the target interconnect layer sends the verification stimulus to the selected interconnect layer, and the verification system receives the verification stimulus from the selected interconnect layer to obtain a corresponding verification output; the selected interconnect layer obtains the verification output from the verification system and sends the verification output to the target interconnect layer; the target interconnect layer receives the verification output and transmits the verification output through the network layer of the first chipset

[0015] For example, in a verification method provided by at least one embodiment of the present disclosure, selecting a second chipset from the multiple chipsets includes: selecting at least one opposite chipset configured to be interconnected with the first chipset from the multiple chipsets; and selecting the second chipset from the at least one opposite chipset.

[0016] For example, a verification method provided by at least one embodiment of the present disclosure also includes: selecting at least one third chipset from the at least one opposite chipset; selecting a second interconnection module from the at least one interconnection module in the first chipset; and interconnecting the physical layer of the second interconnection module of the first chipset with the physical layer of the corresponding third chipset in the at least one third chipset.

[0017] For example, a verification method provided by at least one embodiment of the present disclosure further includes: in response to the at least one third chipset including a plurality of third chipsets, serially interconnecting each of the at least one third chipset.

[0018] For example, in a verification method provided by at least one embodiment of the present disclosure, the second chipset and the first chipset are heterogeneous chipsets, and the third chipset and the first chipset are homogeneous chipsets.

[0019] At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the verification method as described in any one of the above items is implemented.

[0020] At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the verification method as described in any of the above examples is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic diagram of interconnection between two chipsets;

[0023] Figure 2 A flowchart of a verification method provided in some embodiments of the present disclosure;

[0024] Figure 3 A schematic diagram of verification between two chipsets in which a target interconnection layer is a link layer and a selected interconnection layer is a link layer is provided for some embodiments of the present disclosure;

[0025] Figure 4 A schematic diagram of verification between two chipsets in which a target interconnection layer is a physical layer and a selected interconnection layer is a physical layer is provided in some embodiments of the present disclosure;

[0026] Figure 5 A schematic diagram of verification between two chipsets in which the target interconnection layer is a physical layer and the selected interconnection layer is a link layer is provided for some embodiments of the present disclosure;

[0027] Figure 6 Some embodiments of the present disclosure provide Figure 2 Flowchart about step S3;

[0028] Figure 7 A flowchart of a verification method provided in some other embodiments of the present disclosure;

[0029] Figure 8 A schematic diagram of verification between three chipsets in which a target interconnection layer is a link layer and a selected interconnection layer is a link layer is provided for some embodiments of the present disclosure;

[0030] Figure 9 A schematic diagram of verification between three chipsets in which the target interconnection layer is the physical layer and the selected interconnection layer is the link layer is provided for some embodiments of the present disclosure; and

[0031] Figure 10 A block diagram of an electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined in this manner in the embodiments of the present disclosure.

[0034] The words "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Similarly, words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0035] In the embodiments of the present disclosure, flow charts are used to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps do not necessarily need to be performed in precise order. Instead, the various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or more steps can be removed from these processes.

[0036] The inventors of this disclosure discovered that different chipsets are combined to meet different product requirements, and different product solutions require different verification platforms. For example, for a product with two chipsets, two real chipsets are instantiated for interconnection verification; for a product with four chipsets, four real chipsets are instantiated for interconnection verification, and so on.

[0037] For example, Figure 1 As shown, two chipsets that need to be interconnected are designated chipset 001 and chipset 002. Chipset 001 and chipset 002 can communicate with each other and serve as peer chipsets. The interconnection module of chipset 001 includes a physical layer 101, a link layer 102, and a network layer 103, which are interconnected in sequence. The interconnection module of chipset 002 also includes a physical layer 201, a link layer 202, and a network layer 203, which are interconnected in sequence.

[0038] The physical layer in the network protocol layering provides a virtual bit pipe for transmitting bit streams (bit sequences) between any pair of nodes connected by a physical communication channel. At the transmitting end, it converts the received bit stream into a signal suitable for transmission over the physical channel, and at the receiving end, it restores the signal back to the transmitted bit stream. The physical layer provides only raw digital bit stream transmission services and does not provide error protection. For example, the physical layer can be considered the first layer. For example, physical communication channels include but are not limited to twisted pair cables, coaxial cables, optical cables, and radio channels.

[0039] In the network protocol layering, above the network layer are also the transport layer, session layer, presentation layer and application layer, which will not be described in detail here.

[0040] The link layer of the network protocol layer is responsible for the transmission of data blocks (frames) and performs necessary synchronization control, error control, and flow control. Because of the services of the data link layer, the layers above the data link layer can assume that the transmission on the link is error-free. For example, the link layer can be referred to as layer 2, and the link layer can be referred to as the layer above the physical layer.

[0041] The network layer of the network protocol layer lies between the transport layer and the data link layer. Building on the data link layer's function of transmitting data frames between two adjacent nodes, it further manages data communications within the network, transmitting data from the source to the destination via several intermediate nodes, providing the transport layer with the most basic end-to-end data transmission services. For example, the network layer can be considered the third layer, and the network layer can be considered the upper layer of the link layer.

[0042] For example, Figure 1As shown, the link layer of any one of chipset 001 and chipset 002 receives data provided by the upper network layer, and provides it to the lower physical layer after corresponding processing. The physical layer transmits the data to the physical layer of the opposite chipset after corresponding processing. In the opposite chipset, the data is then processed in sequence by the physical layer, link layer and network layer to realize the interconnection and communication between chipset 001 and chipset 002.

[0043] The inventors of the present disclosure have discovered that the following problems exist in the method for verifying the above-mentioned chipset: First, for the same chipset, many combinations need to be verified, and the verification platform is large; second, if a real chipset is used, the verification platform is large, the simulation speed is slow, and the time consumption is long; third, for the interconnection of heterogeneous chipsets, due to the different development cycles between different chipsets, there may not be suitable chipsets for interconnection, which is not conducive to the interconnection verification of the chipsets.

[0044] In this regard, at least one embodiment of the present disclosure provides a verification method, including: providing multiple chipsets, wherein each of the multiple chipsets includes at least one interconnection module, and each of the at least one interconnection module includes at least one of a physical layer, a link layer, and a network layer; selecting a first chipset from the multiple chipsets, the first chipset being the chipset to be tested; selecting a second chipset from the multiple chipsets, wherein the interconnection module of the second chipset includes a selected interconnection layer, and the selected interconnection layer is configured as one of the physical layer and the link layer of the interconnection module of the second chipset; selecting a first interconnection module from at least one interconnection module in the first chipset; selecting one of the physical layer and the link layer of the first interconnection module as a target interconnection layer; interconnecting the first interconnection module of the first chipset and the selected interconnection layer of the second chipset, thereby providing a verification path by the selected interconnection layer in the second chipset, so that the target interconnection layer of the first chipset transmits verification stimulus or verification output to verify the first chipset.

[0045] The above-mentioned embodiments of the present disclosure adopt hierarchical modeling verification for different functions of the chipset. According to different interconnection levels, at least part of the interconnection module of the chipset on the opposite side of the chipset under test (for example, part of the RTL (Register Transfer Level) code, such as RTL code used only to implement the network layer, link layer or physical layer) is modeled to interconnect with the chipset under test. This not only achieves the purpose of verifying different functions, but also can use the code of part of the interconnection level of the opposite side chipset without waiting for the completion of the overall verification of the opposite side chipset, thereby solving the problem caused by the development cycle of different chipsets during the verification process.

[0046] The verification method of the above-mentioned embodiment of the present disclosure can also use targeted RTL codes for different verification scenarios or verification targets, so that the scale of the verification platform is greatly reduced and the simulation speed can be greatly accelerated.

[0047] Figure 2 A flowchart of a verification method provided in some embodiments of the present disclosure.

[0048] For example, Figure 2 As shown, at least one embodiment of the present disclosure provides a verification method including steps S1 to S6.

[0049] Step S1: provide a plurality of chipsets, wherein each of the plurality of chipsets comprises at least one interconnection module, and each of the at least one interconnection module of each chipset comprises at least one of a physical layer, a link layer, and a network layer.

[0050] Step S2: Select a first chipset from a plurality of chipsets, where the first chipset is the chipset to be tested.

[0051] Step S3: Select a second chipset from the plurality of chipsets, wherein the interconnection module of the second chipset includes a selected interconnection layer, and the selected interconnection layer is configured as one of a physical layer and a link layer of the interconnection module of the second chipset.

[0052] Step S4: Select a first interconnection module from at least one interconnection module in the first chipset.

[0053] Step S5: Select one of the physical layer and the link layer of the first interconnection module as the target interconnection layer.

[0054] Step S6: interconnecting the first interconnection module of the first chipset and the selected interconnection layer of the second chipset, whereby the selected interconnection layer in the second chipset provides a verification path, so that the target interconnection layer of the first chipset transmits verification stimulus or verification output to verify the first chipset.

[0055] At least one embodiment of the present disclosure utilizes layered modeling and verification for different chipset functions. Modeling at least a portion of the interconnect modules of the chipset under test based on different interconnection layers allows interconnection with the chipset under test. This not only achieves verification of different functions, but also allows the use of code for a portion of the interconnection layers of the chipset without waiting for the complete verification of the chipset, thereby resolving issues associated with the development cycles of different chipsets during verification. The verification method of the embodiments of the present disclosure also utilizes targeted code for different functions, significantly reducing the scale of the verification platform and significantly accelerating simulation speed.

[0056] In some examples, the verification method of embodiments of the present disclosure further includes the following steps or processes: using the verification system to provide verification stimulus to a target interconnect layer or receive verification output from the target interconnect layer via a selected interconnect layer in the second chipset. In this way, embodiments of the present disclosure can implement verification for different verification scenarios by combining the verification system with the aforementioned multiple chipsets.

[0057] In some examples, verification system comprises universal verification module, and for example universal verification module is UVM (Universal Verification Methodology) verification module.For example, this UVM verification module is a verification platform development framework with System Verilog class library as main body, can utilize its reusable component to build the functional verification environment with standardized hierarchy and interface, i.e. UVM environment. The UVM verification environment stipulates the basic class (i.e. reusable component) among the UVM, for example, sequencer (Sequencer), monitor (Monitor) etc. and communication interface. Verifier can expand the class that oneself needs on the basis of basic class, and then connects the communication interface of each class with the communication statement of UVM standard.

[0058] It should be noted that, in the present disclosure, since the specific composition of the verification system and how to perform verification using the verification system are not limited, they are not described in detail here.

[0059] At least one embodiment of the present disclosure utilizes the UVM verification system to implement verification, which has high reusability, and the verification method is flexible, easy to use, and efficient.

[0060] Figure 3 A schematic diagram of verification between two chipsets, where the target interconnection layer is a link layer and the selected interconnection layer is a link layer, is provided for some embodiments of the present disclosure. Figure 4 A schematic diagram of verification between two chipsets, where the target interconnect layer is a physical layer and the selected interconnect layer is a physical layer, is provided for some embodiments of the present disclosure. Figure 5 A schematic diagram of verification between two chipsets, where the target interconnection layer is the physical layer and the selected interconnection layer is the link layer, is provided for some embodiments of the present disclosure.

[0061] In some examples, for step S1, the number of at least one interconnection module included in each chipset is equal to the number of peer chipsets for which the chipset under test is to undergo interconnection verification. For example, the number of interconnection modules included in a chipset may be one, such as Figure 3 The chipset 1100 is shown as an interconnection module 1110. For another example, the chipset may include multiple interconnection modules, such as 2 or more. Figure 8The chipset 4100 shown (see below) has two interconnection modules, an interconnection module 4110 and an interconnection module 4120. This is merely exemplary and does not limit the embodiments of the present disclosure, and the present disclosure is not limited thereto.

[0062] It should be noted that, in each embodiment of the present disclosure, the peer chipset may not only refer to a chipset directly interconnected with a chipset to be tested, for example, Figure 3 The chipset 1100 corresponds to the opposite chipset 1200, Figure 4 The chipset 2100 corresponds to the opposite chipset 2200, Figure 5 The chipset 3100 corresponds to the opposite chipset 3200, as described below. Figure 8 (See below) The chipset 4100 corresponds to the opposite chipset 4400 and Figure 9 The opposite chipset 5400 corresponding to the chipset 5100 (see below) may also represent a chipset indirectly interconnected with a chipset under test, such as another chipset (not shown) connected to the chipset under test via at least one intermediate chipset.

[0063] For example, in step S1, the interconnection modules of some chipsets in the plurality of chipsets may include three layers: the physical layer, the link layer, and the network layer. Figure 4 The interconnection module 2110 of the chipset 2100 (first chipset) shown includes a physical layer 2111, a link layer 2112, and a network layer 2113. Figure 5 The interconnection module 3110 of the illustrated chipset 3100 (first chipset) includes a physical layer 3111 , a link layer 3112 , and a network layer 3113 .

[0064] For another example, in step S1, the interconnection modules of some chipsets in the plurality of chipsets may also include one of the physical layer, the link layer and the network layer, such as Figure 3 The interconnection module 1210 of the chipset 1200 (ie, the second chipset) shown includes a link layer 1212, or as shown in FIG. Figure 4 The interconnection module 2210 of the chipset 2200 (ie, the second chipset) shown includes a physical layer 2211 .

[0065] For another example, in step S1, the interconnection modules of some chipsets in the plurality of chipsets may further include two of the physical layer, the link layer, and the network layer, such as Figure 5 The interconnection module 3210 of the chipset 3200 (second chipset) shown includes a physical layer 3211 and a link layer 3212 .

[0066] Therefore, the embodiments of the present disclosure are not limited to this, and targeted hierarchical codes can be selected for different verification targets, which will not be described in detail here.

[0067] In some examples, for step S2, the first chipset is an RTL module to be verified, which may also be referred to as a device under test (DUT), for example Figure 3 The chipset 1100 shown, Figure 4 The chipset 2100 shown, Figure 5 The chipset 3100 shown, Figure 8 The chipset 4100 and Figure 9 Chipset 5100 shown.

[0068] In some examples, for step S3, the second chipset is a counterpart chipset to the first chipset to be tested during the verification process, for example Figure 3 The chipset 1200 shown, Figure 4 The chipset 2200 and Figure 5 The chipset 3200 is shown. The second chipset selects a transmission layer according to different verification goals, and hierarchical modeling is performed on the second chipset. A layer required for verification is selected from the multiple interconnection layers obtained by the hierarchical modeling. The selected layer (e.g., the corresponding RTL code) is then used to implement verification of the relevant functions of the first chipset. At this time, at least some components of the second chipset other than the selected layer may be temporarily ignored.

[0069] In some examples, the interconnection module of the second chipset may include at least some layers of the physical layer, link layer, and network layer. For example, the interconnection module of the second chipset includes the link layer (for example, there is no at least some other layers of the physical layer, network layer, etc.), or the interconnection module of the second chipset includes the physical layer and the link layer (for example, there is no at least some other layers of the network layer, etc.). This can be adjusted accordingly according to different verification goals in actual applications, and the embodiments of the present disclosure are not limited to this.

[0070] In some examples, for step S3, the second chipset and the first chipset may be heterogeneous chipsets or homogeneous chipsets.

[0071] In some examples, in step S3, the selected interconnect layer of the second chipset may be a link layer. In other examples, in step S3, the selected interconnect layer of the second chipset may also be a physical layer. This is merely exemplary and not a limitation of the present disclosure, and may be adjusted accordingly based on different verification objectives.

[0072] In some examples, for step S4, the first interconnection module selected from the first chipset is one of the interconnection modules in the first chipset used for interconnection verification with the second chipset. Figure 3In the example, the interconnection module 1110 is used to verify the interconnection with the chipset 1200. Figure 4 In the example, the interconnection module 2110 is used to verify the interconnection with the chipset 2200. Figure 5 In the example, the interconnection module 3110 is used for interconnection verification with the chipset 3200 in the chipset 3100, that is, the interconnection module 1110, the interconnection module 2110, and the interconnection module 3110 are respectively the first interconnection modules in the corresponding examples.

[0073] In some examples, for step S5, selecting one of the physical layer and the link layer of the first interconnect module as the target interconnect layer includes: selecting the link layer of the first interconnect module as the target interconnect layer. For example, when the target interconnect layer of the first chipset is the link layer of the first interconnect module, the selected interconnect layer of the second chipset is the link layer, such as Figure 3 shown.

[0074] In other examples, for step S5, selecting one of the physical layer and the link layer of the first interconnect module as the target interconnect layer includes: selecting the physical layer of the first interconnect module as the target interconnect layer. For example, when the target interconnect layer of the first chipset is the physical layer of the first interconnect module, the selected interconnect layer of the second chipset can be the physical layer, such as Figure 4 As shown. For another example, when the target interconnection layer of the first chipset is the physical layer of the first interconnection module, the selected interconnection layer of the second chipset may also be the link layer, as shown in FIG. Figure 5 shown.

[0075] Therefore, at least some embodiments of the present disclosure select different layers of the chipset under test to model different functions to verify different functions, simplifying the complexity of the verification environment, greatly improving the simulation speed, and saving verification time. Figure 3 For example, the embodiment of the present disclosure can realize the verification of the functions of the link layer and the upper layer of the link layer. Figure 4 or Figure 5 For example, the embodiments of the present disclosure can realize the verification of the functions of the physical layer and the layers above the physical layer.

[0076] It should be noted that the embodiments of the present disclosure do not limit the hierarchical modules included in the interconnection modules of each chipset. This can be adjusted according to different protocol layers, such as the seven layers of the OSI reference model or the five-layer model of the Internet or other models. The embodiments of the present disclosure are not exhaustive or detailed here.

[0077] It should also be noted that the chipset and / or interconnection module shown in the drawings of the embodiments of the present disclosure is only a simple schematic diagram and does not limit the chipset and interconnection module itself. For example, the first chipset may also include a master / slave device connected to the interconnection module and / or a higher-level module in the interconnection module. Since this is not the focus of the description of the embodiments of the present disclosure, it will not be repeated here.

[0078] In this disclosure, a "target interconnect layer" refers to a layer in a first interconnect module of a first chipset that is directly interconnected with an interconnect module of a second chipset, thereby enabling verification of the functionality of the corresponding layer. In this disclosure, a "selected interconnect layer" refers to a layer selected from the interconnect module of the second chipset, based on the corresponding target interconnect layer, for direct interconnection with the verification system.

[0079] For example, in Figure 3 In the example, the first chipset is chipset 1100, and the first interconnection module of the first chipset is interconnection module 1110. The second chipset is chipset 1200, and chipset 1200 includes interconnection module 1210. Interconnection module 1110 of chipset 1100 includes physical layer 1111, link layer 1112, and network layer 1113. Interconnection module 1210 of chipset 1200 includes link layer 1212. The target interconnection layer of interconnection module 1110 of chipset 1100 is link layer 1112, and the selected interconnection layer of interconnection module 1210 of chipset 1200 is link layer 1212.

[0080] For example, Figure 3 As shown, for step S6, interconnecting the first interconnection module of the first chipset and the selected interconnection layer of the second chipset includes the following process or steps: directly interconnecting the link layer 1212 of the chipset 1200 with the link layer 1112 of the interconnection module 1110, and disconnecting the link layer 1112 of the interconnection module 1110 from the physical layer 1111 of the interconnection module 1110. Thus, the link layer 1212 in the chipset 1200 provides a verification path, so that the link layer 1112 of the chipset 1100 transmits a verification stimulus or a verification output to verify the chipset 1100. For example, in Figure 3 In the example shown in FIG, the link layer 1212 of the chipset 1200 is directly interconnected with the verification system 1300 .

[0081] Thus, the embodiment of the present disclosure uses the link layer 1112 of the chipset 1100 as the target interconnection layer, which can verify the functions of the link layer and the layers above the link layer. In addition, by disconnecting the link layer 1112 from the physical layer 1111 and directly interconnecting the link layer 1212 with the link layer 1112, data transmission during the verification process is faster, which speeds up the verification process. When the interconnection module 1210 of the chipset 1200 in the embodiment of the present disclosure includes the link layer, the amount of modeling code is small, which can simplify the complexity of the verification environment, improve the simulation speed, and save verification time.

[0082] In some examples, for Figure 3 The link layer 1212 of the chipset 1200 in the example provides a verification path, including: when the chipset 1100 acts as a receiver, the link layer 1212 of the chipset 1200 provides verification stimulus to the link layer 1112 of the chipset 1100 and the link layer 1212 of the chipset 1200 receives the verification output sent by the link layer 1112 of the chipset 1100.

[0083] For example, when the chipset 1100 acts as the receiver, a verification stimulus is sent to the link layer 1212 of the chipset 1200 through the verification system 1300. The link layer 1212 provides the verification stimulus to the link layer 1112 of the chipset 1100 and transmits it to the network layer 1113 of the chipset 1100. The chipset 1100 performs corresponding processing based on the verification stimulus and provides a corresponding verification output (for example, it can also be called an acknowledgement signal or a response signal). The verification output will be provided to the network layer 1113 of the chipset 1100 and transmitted to the link layer 1112 of the chipset 1100. The link layer 1212 of the chipset 1200 receives the verification output from the link layer 1112 of the chipset 1100 and sends it to the verification system 1300 to obtain a verification result, thereby realizing the verification of the chipset 1100.

[0084] It should be noted that for Figure 3 The link layer 1212 of the chipset 1200 in the example provides a verification path. The embodiments of the present disclosure are not limited to the case where the chipset 1100 acts as a receiver, but may also include a case where the chipset 1100 acts as a sender.

[0085] For example, when the chipset 1100 acts as a sender, the link layer 1212 of the chipset 1200 receives the verification stimulus sent by the link layer 1112 of the chipset 1100 and provides the link layer 1212 of the chipset 1200 with a verification output.

[0086] For example, when chipset 1100 acts as the sender, the verification stimulus provided by chipset 1100 is transmitted to link layer 1112 of chipset 1100 via network layer 1113 of chipset 1100. Link layer 1112 of chipset 1100 sends the verification stimulus to link layer 1212 of chipset 1200. Verification system 1300 then receives the verification stimulus from link layer 1212 of chipset 1200 and obtains a corresponding verification output based on the verification stimulus. Link layer 1212 of chipset 1200 obtains the verification output from verification system 1300 and sends the verification output to link layer 1112 of chipset 1100. Link layer 1112 of chipset 1100 receives the verification output sent by link layer 1212 of chipset 1200 and transmits the verification output through network layer 1113 of chipset 1100 to implement verification of chipset 1100.

[0087] It should be noted that, since the specific composition of the verification system and the details of how to perform verification using the verification system are not the focus of the embodiments of the present disclosure, the embodiments of the present disclosure will no longer elaborate on the specific verification process.

[0088] For example, in Figure 4 In the example, the first chipset is chipset 2100, and the first interconnection module of the first chipset is interconnection module 2110. The second chipset is chipset 2200, and chipset 2200 includes interconnection module 2210. Interconnection module 2110 of chipset 2100 includes a physical layer 2111, a link layer 2112, and a network layer 2113. Interconnection module 2210 of chipset 2200 includes physical layer 2211. The target interconnection layer of interconnection module 2110 of chipset 2100 is physical layer 2111, and the selected interconnection layer of interconnection module 2210 of chipset 2200 is physical layer 2211.

[0089] For example, Figure 4 As shown, for step S6, interconnecting the first interconnection module of the first chipset and the selected interconnection layer of the second chipset includes the following process or steps: directly interconnecting the physical layer 2211 of the chipset 2200 with the physical layer 2111 of the interconnection module 2110. Thus, the physical layer 211 in the chipset 2200 provides a verification path, so that the physical layer 2111 of the chipset 2100 transmits verification stimulus or verification output to verify the chipset 2100. For example, Figure 4 In the example shown in FIG, the physical layer 2211 of the chipset 2200 is directly interconnected with the verification system 2300 .

[0090] Thus, the embodiments of the present disclosure use the physical layer 2111 of the chipset 2100 as the target interconnect layer, enabling verification of the physical layer and the functions of layers above it. When the interconnect module 2210 of the chipset 2200 in the embodiments of the present disclosure includes the physical layer, the modeling code size is reduced, simplifying the complexity of the verification environment, improving simulation speed, and saving verification time.

[0091] In some examples, for Figure 4 The physical layer 2211 of the chipset 2200 in the example provides a verification path, including: when the chipset 2100 acts as a receiver, the physical layer 2211 of the chipset 2200 provides verification stimulus to the physical layer 2111 of the chipset 2100 or the physical layer 2211 of the chipset 2200 receives the verification output sent by the physical layer 2111 of the chipset 2100.

[0092] It should be noted that for Figure 4 In the example, the chipset 2100 as the receiver and the chipset 2100 as the sender can be verified by referring to the above related Figure 3 The description of the example is not repeated here.

[0093] For example, in Figure 5 In the example, the first chipset is chipset 3100, and the first interconnection module of the first chipset is interconnection module 3110. The second chipset, which serves as (one of) the opposite chipsets, is chipset 3200, and chipset 3200 includes interconnection module 3210. Interconnection module 3110 of chipset 3100 includes a physical layer 3111, a link layer 3112, and a network layer 3113. Interconnection module 3210 of chipset 3200 includes a physical layer 3211 and a link layer 3212. The target interconnection layer of interconnection module 3110 of chipset 3100 is physical layer 3111, and the selected interconnection layer of interconnection module 3210 of chipset 3200 is link layer 3212. For example, chipset 3100 and chipset 3200 may be components of the same system-on-chip.

[0094] For example, Figure 5 As shown, for step S6, interconnecting the first interconnection module of the first chipset and the selected interconnection layer of the second chipset includes the following processes or steps: interconnecting the physical layer 3211 of the chipset 3200 with the link layer 3212 of the chipset 3200, and directly interconnecting the physical layer 3211 of the chipset 3200 with the physical layer 3111 of the interconnection module 3110 of the chipset 3100. Thus, the link layer 3212 in the chipset 3200 provides a verification path, so that the link layer 3112 of the chipset 3100 transmits a verification stimulus or a verification output to verify the chipset 3100. For example, in Figure 5 In the example shown in FIG, the link layer 3212 of the chipset 3200 is directly interconnected with the verification system 3300 .

[0095] Thus, the embodiments of the present disclosure use the physical layer 3111 of chipset 3100 as the target interconnect layer, enabling verification of the physical layer and the functions of layers above it. In the case where the interconnect module 3210 of chipset 3200 in the embodiments of the present disclosure includes both the physical layer and the link layer, the modeling code size is reduced, simplifying the complexity of the verification environment, improving simulation speed, and saving verification time.

[0096] In some examples, for Figure 5 The link layer 3212 of the chipset 3200 in the example provides a verification path, including: when the chipset 3100 acts as a receiver, the link layer 3212 of the chipset 3200 provides verification stimulus to the physical layer 3111 of the chipset 3100 through the physical layer 3211, or the link layer 3212 of the chipset 3200 receives the verification output sent by the physical layer 3111 of the chipset 3100 through the physical layer 3211.

[0097] It should be noted that for Figure 5 The verification of the chipset 3100 as a receiver and the chipset 3100 as a sender in the example can be referred to above. Figure 3 The description of the example is not repeated here.

[0098] Figure 6 Some embodiments of the present disclosure provide Figure 2 Flowchart about step S3 in FIG.

[0099] For example, Figure 6 As shown, an example of step S3 includes step S31 and step S32.

[0100] Step S31: Select at least one opposite chipset configured to be interconnected with the first chipset from a plurality of chipsets.

[0101] Step S32: Select a second chipset from at least one opposite chipset.

[0102] Therefore, the embodiments of the present disclosure are applicable to interconnection verification between any number of chipsets, and can perform hierarchical modeling according to different verification targets to verify functions at different levels, with good portability and universality.

[0103] For example, in step S31, the number of the opposite end chipset may be one, such as the second chipset, and the verification method can implement the interconnection verification between the two chipsets. For another example, in step S31, the number of the opposite end chipset may be multiple, such as the second chipset is one of the multiple opposite end chipsets, and the verification method can implement the interconnection verification between more than three chipsets, such as the following Figure 8 and Figure 9shown.

[0104] It should be noted that the embodiment of the present disclosure does not limit the number of opposite-end chipsets corresponding to the first chipset, and can be freely adjusted according to actual conditions, which will not be elaborated here.

[0105] Figure 7 A flowchart of a verification method provided in some other embodiments of the present disclosure. Figure 8 A schematic diagram of verification between three chipsets in which a target interconnection layer is a link layer and a selected interconnection layer is a link layer is provided for some embodiments of the present disclosure. Figure 9 A schematic diagram of verification between three chipsets, in which the target interconnection layer is the physical layer and the selected interconnection layer is the link layer, is provided for some embodiments of the present disclosure.

[0106] For example, Figure 7 As shown, the verification method provided by some embodiments of the present disclosure may also include steps S71 to S73.

[0107] Step S71: Select at least one third chipset from at least one opposite-end chipset.

[0108] Step S72: Select a second interconnection module from at least one interconnection module in the first chipset.

[0109] Step S73: interconnect the physical layer of the second interconnection module of the first chipset with the physical layer of a corresponding third chipset in at least one third chipset.

[0110] Therefore, the above-mentioned embodiments of the present disclosure are not only applicable to the interconnection verification between two chipsets, but also applicable to the interconnection verification between three or more chipsets, which can cover more verification scenarios and provide more comprehensive verification.

[0111] In the above embodiment of the present disclosure, the third chipset is different from the second chipset. For example, in step S71, the number of the third chipset may be one, for example Figure 8 The chipset 4400 and Figure 9 For example, if there are multiple chipsets, the verification method can verify the interconnection between the three chipsets. For another example, if there are multiple chipsets, the verification method can verify the interconnection between four or more chipsets. It should be noted that the embodiments of the present disclosure do not limit the number of third chipsets and can be freely adjusted according to actual circumstances. This will not be further elaborated here.

[0112] For example, in step S72, when the number of interconnection modules in the first chipset is greater than or equal to 2, the interconnection modules of the first chipset include, in addition to the first interconnection module, another interconnection module for performing interconnection verification with other chipsets (e.g., a third chipset), namely, a second interconnection module. Figure 8 In the embodiment shown, the second interconnection module is the interconnection module 4410 and the third chipset corresponding to the interconnection module 4410 is the chipset 4400. Figure 9 In the illustrated embodiment, the second interconnection module is the interconnection module 5410 and the third chipset corresponding to the interconnection module 5410 is the chipset 5400 .

[0113] In some examples, the second chipset and the first chipset are heterogeneous chipsets, and the third chipset and the first chipset are homogeneous chipsets. Figure 8 The chipset 4200 and the chipset 4100 are heterogeneous chipsets, and the chipset 4400 and the chipset 4100 are homogeneous chipsets. Figure 9 As shown, chipset 5200 and chipset 5100 are heterogeneous chipsets, and chipset 5400 and chipset 5100 are homogeneous chipsets. In other examples, the second chipset and the first chipset are heterogeneous chipsets, and the third chipset and the first chipset are heterogeneous chipsets. In this way, embodiments of the present disclosure can implement interconnection verification between more than three chipsets, covering more verification scenarios and facilitating faster simulation speeds.

[0114] In some examples, when the at least one third chipset includes multiple third chipsets, each of the at least one third chipset can be serially interconnected. In this way, the above-described embodiments of the present disclosure can implement interconnection verification between a large number of chipsets, covering more verification scenarios and achieving faster simulation speeds. Of course, this is for illustrative purposes only and is not intended to be a limitation of the present disclosure.

[0115] It should be noted that for the interconnection verification between three chipsets or the interconnection verification between more chipsets, the present disclosure is not limited to the examples described above. For example, the verification scheme of physical layer or link layer modeling can be flexibly used for heterogeneous or homogeneous chipsets, which will not be repeated here.

[0116] For example, in Figure 8In the example, the first chipset is chipset 4100, the first interconnection module of the first chipset is interconnection module 4110, and the second interconnection module of the first chipset is interconnection module 4120. The second chipset, which is (one of) the opposite chipset, is chipset 4200, and chipset 4200 includes interconnection module 4210. Interconnection module 4110 of chipset 4100 includes a physical layer 4111, a link layer 4112, and a network layer 4113. Interconnection module 4120 of chipset 4100 includes a physical layer 4121, a link layer 4122, and a network layer 4113. Interconnection module 4210 of chipset 4200 includes link layer 4212. The target interconnection layer of interconnection module 4110 of chipset 4100 is link layer 4112, and the selected interconnection layer of interconnection module 4210 of chipset 4200 is link layer 4212. The third chipset is chipset 4400 . The interconnection module 4410 of chipset 4400 includes a physical layer 4411 , a link layer 4412 , and a network layer 4413 .

[0117] For example, in Figure 8 In the example of FIG, the physical layer 4121 of the interconnection module 4120 of the chipset 4100 is interconnected with the physical layer 4411 of the interconnection module 4410 of the chipset 4400. Figure 8 In the example of , the link layer 4212 of the chipset 4200 is directly interconnected with the link layer 4112 of the interconnection module 4110, and the link layer 4112 of the interconnection module 4110 is disconnected from the physical layer 4111 of the interconnection module 4110. Figure 8 In the example shown in FIG, the link layer 4212 of the chipset 4200 is directly interconnected with the verification system 4300 .

[0118] For example, Figure 8 As shown, chipset 4200 and chipset 4100 are heterogeneous chipsets, and chipset 4400 and chipset 4100 are homogeneous chipsets. Chipset 4400 and chipset 4100, which are homogeneous chipsets, use complete RTL interconnection, and chipset 4200, which is a heterogeneous chipset with chipset 4100, uses link layer 4212 to interconnect with chipset 4100, and interacts verification system 4300 with link layer 4212 of chipset 4200, thereby realizing verification of chipset 4100.

[0119] Therefore, the present disclosure Figure 8In this example, link layer 4112 of chipset 4100 is used as the target interconnection layer, which can also verify the functions of the link layer and the layers above the link layer. In addition, by disconnecting link layer 4112 from physical layer 4111 and directly interconnecting link layer 4212 with link layer 4112, data transmission during the verification process is faster, accelerating verification speed. When interconnection module 4210 of chipset 4200 in the embodiment of the present disclosure includes a link layer, the amount of modeling code is relatively small, which can simplify the complexity of the verification environment, improve simulation speed, and save verification time.

[0120] For example, in Figure 9 In the example, the first chipset is chipset 5100, the first interconnection module of the first chipset is interconnection module 5110, and the second interconnection module of the first chipset is interconnection module 5120. The second chipset is chipset 5200, and chipset 5200 includes interconnection module 5210. Interconnection module 5110 of chipset 5100 includes a physical layer 5111, a link layer 5112, and a network layer 5113. Interconnection module 5120 of chipset 5100 includes a physical layer 5121, a link layer 5122, and a network layer 5113. Interconnection module 5210 of chipset 5200 includes a link layer 5212 and a physical layer 5211. The target interconnection layer of interconnection module 5110 of chipset 5100 is physical layer 5111, and the selected interconnection layer of interconnection module 5210 of chipset 5200 is link layer 5212. The third chipset is chipset 5400 . The interconnection module 5410 of chipset 5400 includes a physical layer 5411 , a link layer 5412 , and a network layer 5413 .

[0121] For example, in Figure 9 In the example of FIG, the physical layer 5121 of the interconnection module 5120 of the chipset 5100 is interconnected with the physical layer 5411 of the interconnection module 5410 of the chipset 5400. Figure 9 In the example of , the physical layer 5211 of the chipset 5200 is interconnected with the link layer 5212 of the chipset 5200, and the physical layer 5211 of the chipset 5200 is directly interconnected with the physical layer 5111 of the interconnection module 5110 of the chipset 5100. Figure 9 In the example shown in FIG, the link layer 5212 of the chipset 5200 is directly interconnected with the verification system 5300 .

[0122] For example, Figure 9As shown, chipset 5200 and chipset 5100 are heterogeneous chipsets, and chipset 5400 and chipset 5100 are homogeneous chipsets. Chipset 5400 and chipset 5100, which are homogeneous chipsets, are interconnected using a complete design, and chipset 5200, which is a heterogeneous chipset with chipset 5100, uses link layer 5212 and physical layer 5211 to achieve interconnection with chipset 5100, and interacts verification system 5300 with link layer 5212 of chipset 5200, thereby achieving verification of chipset 5100.

[0123] Therefore, the present disclosure Figure 9 In this example, the physical layer 5111 of chipset 5100 is used as the target interconnect layer, enabling verification of the physical layer and the functions of layers above it. In the case where the interconnect module 5210 of chipset 5200 in the disclosed embodiment includes both the physical layer and the link layer, the modeling code size is reduced, simplifying the complexity of the verification environment, improving simulation speed, and saving verification time.

[0124] It should be noted that for the verification between three chipsets whose target interconnection layer is the physical layer and whose selected interconnection layer is the link layer, not only can Figure 9 In the example, the interconnection module 5210 of the chipset 5200 is designed to include a physical layer and a link layer. Alternatively, the interconnection module 5210 of the chipset 5200 may be designed to include only a physical layer and the physical layer of the interconnection module 5210 is directly connected to the verification system to implement verification of the physical layer and the functions of the layers above the physical layer. For details, please refer to the above-mentioned Figure 5 The description of the example is not repeated here.

[0125] As previously mentioned, the verification methods provided in some embodiments of the present disclosure can use partial models of the peer chipset (e.g., RTL models) to model at different transmission layers to verify functions at different layers. This can simplify the complexity of the verification environment, increase simulation speed, and save verification time. For example, for different architectures and verification platforms, one or a combination of layered modeling methods can be used. For example, modeling can be performed at different layers such as the physical layer and the link layer to achieve the purpose of verifying different functions. The scale of the verification platform can be significantly reduced, and the simulation speed can be greatly accelerated.

[0126] Figure 10 This is a structural diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device 600 includes a processor 610 and a memory 620, wherein a computer program is stored on the memory 620. When the computer program is executed by the processor 610, the verification method of at least some embodiments of the present disclosure is implemented.

[0127] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as laptop computers, tablet computers, etc., and fixed terminals such as desktop computers, etc. Figure 10 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0128] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. When the computer program is executed by a processor, the verification method of the embodiment of the present disclosure is performed.

[0129] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In embodiments of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or device. In embodiments of the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0130] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0131] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 600 can be referred to the above description of the verification method, which will not be repeated here.

[0132] There are a few points to note:

[0133] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0134] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0135] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A verification method, comprising: Providing a plurality of chipsets, wherein each of the plurality of chipsets comprises at least one interconnection module, and each of the at least one interconnection module comprises at least one of a physical layer, a link layer, and a network layer; Selecting a first chipset from the plurality of chipsets, where the first chipset is a chipset to be tested; selecting a second chipset from the plurality of chipsets, wherein the interconnect module of the second chipset includes a selected interconnect layer, and the selected interconnect layer is configured as one of a physical layer and a link layer of the interconnect module of the second chipset; selecting a first interconnection module from at least one interconnection module in the first chipset; selecting one of the physical layer and the link layer of the first interconnection module as a target interconnection layer; interconnecting a first interconnect module of the first chipset and a selected interconnect layer of the second chipset, whereby the selected interconnect layer in the second chipset provides a verification path such that the target interconnect layer of the first chipset transmits a verification stimulus or a verification output to verify the first chipset; The verification method further comprises: providing the verification stimulus to the target interconnect layer and receiving the verification output from the target interconnect layer using a verification system through a selected interconnect layer in the second chipset, or, receiving, using a verification system, the verification stimulus from the target interconnect layer through a selected interconnect layer in the second chipset and providing the verification output to the target interconnect layer; The selected interconnection layer of the second chipset is directly interconnected with the verification system.

2. The verification method according to claim 1, wherein: The verification system includes a universal verification module.

3. The verification method according to claim 1, wherein: Selecting one of the physical layer and the link layer of the first interconnection module as the target interconnection layer includes: The link layer of the first interconnection module is selected as the target interconnection layer.

4. The verification method according to claim 3, wherein: Interconnecting the first interconnection module of the first chipset and the selection interconnection layer of the second chipset, comprising: In response to the selected interconnect layer of the second chipset being the link layer, the link layer of the second chipset is directly interconnected with the link layer of the first interconnect module, and the link layer of the first interconnect module is disconnected from the physical layer of the first interconnect module.

5. The verification method according to claim 1, wherein: Selecting one of the physical layer and the link layer of the first interconnection module as the target interconnection layer includes: The physical layer of the first interconnect module is selected as the target interconnect layer.

6. The verification method according to claim 5, wherein: Interconnecting the first interconnection module of the first chipset and the selection interconnection layer of the second chipset, comprising: In response to the selected interconnect layer of the second chipset being a physical layer, the second chipset includes a physical layer and directly interconnects the physical layer of the second chipset with the physical layer of the first interconnect module; In response to the selected interconnection layer of the second chipset being the link layer, the second chipset includes a physical layer and a link layer, and the physical layer of the second chipset is interconnected with the link layer of the second chipset and the physical layer of the second chipset is directly interconnected with the physical layer of the first interconnection module.

7. The verification method according to claim 1, wherein: Providing the verification stimulus to the target interconnect layer through a selected interconnect layer in the second chipset and receiving the verification output from the target interconnect layer using a verification system includes: The verification system sends the verification stimulus to the selected interconnect layer; The selected interconnect layer provides the verification stimulus to the target interconnect layer, and transmits the verification stimulus through the network layer of the first chipset, so that the first chipset obtains a corresponding verification output according to the verification stimulus; The network layer of the first chipset obtains the verification output and sends the verification output to the selected interconnection layer through the target interconnection layer; The verification system receives the verification output from the select interconnect layer.

8. The verification method according to claim 1, wherein: Receiving the verification stimulus from the target interconnect layer through a selected interconnect layer in the second chipset using a verification system and providing the verification output to the target interconnect layer includes: transmitting the verification stimulus provided by the first chipset to the target interconnection layer through the network layer of the first chipset; The target interconnect layer sends the verification stimulus to the selected interconnect layer, and the verification system receives the verification stimulus from the selected interconnect layer to obtain a corresponding verification output; The selected interconnect layer obtains the verification output from the verification system and sends the verification output to the target interconnect layer; The target interconnect layer receives the verification output and transmits the verification output through a network layer of the first chipset.

9. The verification method according to any one of claims 1 to 8, wherein: Selecting a second chipset from the plurality of chipsets comprises: Selecting at least one opposite-end chipset from the plurality of chipsets, configured to be interconnected with the first chipset; The second chipset is selected from the at least one peer chipset.

10. The verification method according to claim 9, further comprising: Selecting at least one third chipset from the at least one peer chipset; selecting a second interconnection module from at least one interconnection module in the first chipset; The physical layer of the second interconnection module of the first chipset is interconnected with the physical layer of a corresponding third chipset of the at least one third chipset.

11. The verification method according to claim 10, further comprising: In response to the at least one third chipset comprising a plurality of third chipsets, each of the at least one third chipset is serially interconnected.

12. The verification method according to claim 10, wherein: The second chipset and the first chipset are heterogeneous chipsets, and the third chipset and the first chipset are homogeneous chipsets.

13. An electronic device comprising: processor and memory, Wherein, a computer program is stored in the memory, and when the computer program is executed by the processor, the verification method according to any one of claims 1 to 12 is implemented.

14. A computer-readable storage medium, wherein: The storage medium stores a computer program, and when the computer program is executed by the processor, the verification method according to any one of claims 1 to 12 is implemented.

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