Session-based storage operations

Abstract

This application is directed to session-based memory operations. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the association of the logical address with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for the logical address.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 113,999, filed by Ambula et al. on December 7, 2020, entitled “SESSION-BASED MEMORY OPERATION,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to session-based memory operations. Background Art

[0004] Memory systems, such as those comprising memory devices, are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to a logical 1 or a logical 0. In some instances, a single memory cell can support more than two possible states, either of which can be stored. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to the corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0006] A method is described. The method is executable by a memory system and may include determining that a logical block address targeted by a read command is associated with a first table indicating a first set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied a timing criterion; writing the first table to a cache based at least in part on the logical block address being associated with the first set of logical block addresses; and writing a second set of logical block addresses including logical block addresses from the first set of logical block addresses indicated by the first table to the cache based at least in part on the first table and a second table indicating a second set of logical block addresses and corresponding physical block addresses.

[0007] A method is described. The method may be performed by a memory system and may include receiving a write command that targets a logical block address; determining that the logical block address is associated with a table that indicates a set of logical block addresses that were each previously targeted by one or more write commands, the receipt of the one or more write commands satisfying a timing criterion; and updating the table to indicate that the set of logical block addresses includes the logical block address based at least in part on the receipt of the write command satisfying the timing criterion relative to a previous write command associated with the set of logical block addresses.

[0008] A device is described. The device may include a memory system including a cache; and a controller coupled to the memory system and configured to cause the device to: determine that a logical block address targeted by a read command is associated with a first table indicating a first set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied a timing criterion; write the first table to the cache based at least in part on the logical block address being associated with the first set of logical block addresses; and write a second set of logical block addresses including logical block addresses from the first set of logical block addresses indicated by the first table to the cache based at least in part on the first table, a second table indicating a second set of logical block addresses and corresponding physical block addresses. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting session-based memory operations according to examples disclosed herein is described.

[0010] Figure 2 An example of a table supporting session-based memory operations according to examples disclosed herein is described.

[0011] Figure 3 An example of a process flow supporting session-based memory operations according to examples disclosed herein is described.

[0012] Figure 4An example of a process flow supporting session-based memory operations according to examples disclosed herein is described.

[0013] Figure 5 An example of a table supporting session-based memory operations according to examples disclosed herein is described.

[0014] Figure 6 An example of a process flow supporting session-based memory operations according to examples disclosed herein is described.

[0015] Figure 7 An example of a process flow supporting session-based memory operations according to examples disclosed herein is described.

[0016] Figure 8 A block diagram illustrating a memory system supporting session-based memory operations according to aspects of the present disclosure is shown.

[0017] Figure 9 and 10 A flowchart illustrating one or more methods of supporting session-based memory operations according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0018] A memory system may receive logical addresses from a host system and translate those logical addresses into physical addresses associated with memory cells of memory devices within the memory system. For example, the memory system may receive commands (e.g., access commands) targeting one or more logical block addresses (LBAs) and translate those LBAs into physical block addresses (PBAs) that can be used to locate memory cells for the access operations indicated by the access commands. To perform logical address translation, the memory system may use a logical-to-physical (L2P) block address table, or "L2P table," that maps LBAs to corresponding PBAs. The memory system may store multiple L2P tables (e.g., in long-term memory) and, upon receiving an associated access command, selectively load one or more of the L2P tables into a cache (e.g., for faster access). However, waiting for an associated access command before loading an L2P table into the cache can increase address translation latency, which can adversely affect system performance, among other drawbacks.

[0019] According to the techniques described herein, a memory system can reduce address translation latency by using one or more session tables to predictively load an L2P table into a cache memory before receiving one or more associated access commands. In a first example, a session table can define a set of numerically contiguous LBAs that can (e.g., are likely to) be accessed sequentially by a host device. In a second example, a session table can define a set of LBAs that are likely to be accessed and also provide PBAs corresponding to those LBAs (e.g., the session table can be an L2P session table). As used herein, a set can include one or more elements unless otherwise specified as including two or more elements.

[0020] Initially referring to Figure 1 Features of the present disclosure are described in the context of the systems and devices described. Figure 2-7 Features of the present disclosure are described in the context of the tables and process flows described. Figure 8-10 The device diagrams and flow diagrams of the described session-based storage operations further illustrate and describe these and other features of the present disclosure.

[0021] Figure 1 is an example of a system 100 supporting session-based memory operations according to examples disclosed herein. The system 100 includes a host system 105 coupled to a memory system 110 (also referred to as a memory device).

[0022] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0023] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes memory and processing devices.

[0024] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but it should be understood that the host system 105 can be coupled to any number of memory systems 110 .

[0025] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a UFS interface, an eMMC interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled with the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110 or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled with the memory system controller 115).

[0026] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, where memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0027] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations, which can generally be referred to as access operations, at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. And in some cases, the memory system controller 115 can exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0028] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0029] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0030] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, when reading from or writing to the memory device 130, the data may be stored in the local memory 120, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0031] although Figure 1 The example of the memory system 110 in FIG. 1 has been described as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130, to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may in some cases be performed instead by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include random access memory (RAM) memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0033] In some examples, memory devices 130 may each include a local controller 135 (e.g., on the same die or within the same package) that may perform operations on one or more memory cells of memory device 130. Local controller 135 may operate in conjunction with memory system controller 115 or may perform one or more functions attributed herein to memory system controller 115.

[0034] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0035] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) if each is configured to store two bits of information, a triple-level cell (TLC) if each is configured to store three bits of information, a quad-level cell (QLC) if each is configured to store four bits of information, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density than an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0036] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more restrictions, such as the same operation being performed on memory cells within different pages 175 having the same page address within a respective plane 165 (e.g., involving command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0037] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0038] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0039] The system 100 may include any number of non-transitory computer-readable media that support session-based memory operations. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, when executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0041] The system 100 may include any number of non-transitory computer-readable media that support session-based memory operations. For example, the host system 105, the memory system 110, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, when executed by the host system 105 (e.g., by the host system controller 106), by the memory system 110 (e.g., by the memory system controller 115), or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0042] To access information in memory device 130, host system 105 may communicate one or more access commands to memory system 110 for execution. Host system 105 may use a set of logical addresses for the access commands, while memory system 110 may use a set of physical addresses for executing the access commands. For example, host system 105 may use logical block addresses (LBAs) while the memory system may use physical block addresses (PBAs). Each logical block address and each physical block address may be associated with the same granularity of data (e.g., 4kB), and multiple physical block addresses may exist for each page 175. Therefore, a physical block address may refer to the location of a set of memory cells within page 175 and should not be confused with the address of block 170.

[0043] The memory system 110 may translate logical addresses into physical addresses to properly execute access commands from the host system 105. To perform address translation, the memory system 110 may use logical-to-physical (L2P) tables, each of which may indicate a set of logical addresses and their corresponding physical block addresses. In some examples, the logical addresses in the L2P tables may be numerically consecutive (e.g., each L2P table may provide a physical address mapping for a numerically consecutive set of logical addresses).

[0044] The L2P table used by memory system 110 may be stored in one or more of memory devices 130 (e.g., due to the size of the L2P table). To avoid accessing memory device 130 each time memory system 110 uses the L2P table for address translation, memory system 110 may move the L2P table from memory device 130 to another location, such as a cache memory, such as cache 180, which may have a faster access time than the memory in memory device 130.

[0045] If the memory system 110 receives an access command that targets a logical address of an L2P table in the cache 180, a cache hit is said to have occurred, and the memory system 110 may perform address translation using the L2P table in the cache 180. If the memory system 110 receives an access command that targets a logical address of an L2P table that is not in the cache 180, a cache miss is said to have occurred, and the memory system 110 may retrieve the L2P table from the memory device 130 and load the L2P table into the cache 180 before address translation can occur. Because retrieving the L2P table from the memory device 130 takes more time than accessing an L2P table that is already in the cache 180, increasing the cache hit rate may reduce the latency of the system 100.

[0046] According to the techniques described herein, the memory system 110 can increase cache hit rates and, therefore, reduce system latency by loading a predicted L2P table into the cache 180 before receiving one or more associated access commands (e.g., access commands targeting logical addresses in the L2P table). The memory system 110 can predict the L2P table using a session table that indicates a set of logical addresses that are likely to be accessed sequentially based on how the logical addresses were previously written (e.g., based on a write pattern).

[0047] Figure 2 An example of a table 200 supporting session-based memory operations according to examples disclosed herein is illustrated. Table 200 may be maintained by a memory system, such as memory system 110, and may include a tracking table 205 and a session table 210. Tracking table 205 may be used to monitor one or more commands received from a host system, such as access commands (e.g., write commands), and populate session table 210. Session table 210 may indicate logical addresses written during different sessions and may be used by the memory system to predictively load an L2P table into a cache for one or more read operations. By predictively loading the L2P table, the memory system may reduce address translation latency and thereby improve system performance, among other advantages.

[0048] In other scenarios, when data from a file spans logical addresses in multiple L2P tables, using session table 210 can be advantageous. Rather than waiting for read commands that target logical addresses in the L2P tables individually, the memory system can load the L2P tables into the cache immediately after receiving the first read command that targets the logical addresses of session entries in session table 210. Thus, session table 210 can be used to preemptively load the L2P tables for logical addresses before receiving read commands that target those addresses. Figure 3 The use of the session table 210 during a read operation is described in more detail. Figure 4 Constructing session table 210 is described in more detail using tracking table 205. A table may also be referred to as an array or other suitable terminology.

[0049] Session table 210 may include entries for multiple sessions (e.g., session 0 through session n), one entry for each session. Each entry in session table 210 may have a reference LBA field and a size field that together indicate a numerically contiguous set of logical addresses contained in that session (or "covered by that session"). In other words, the reference LBA (or "starting LBA") may be the LBA from which the remaining LBAs in the session are derived. For example, if each LBA is associated with data of a common granularity (e.g., 4kB), then the range of LBAs in a given session (or "covered by a session") can be determined by the reference LBA and the data size associated with the session (as given by the size field). By way of illustration, if session 0 has a reference LBA of LBA0 and a size s0 of 40kB, then the range of LBAs in session 0 can be determined as LBA0 through LBA9. Of course, other granularities of LBAs and PBAs are contemplated.

[0050] As mentioned, the tracking table 205 (as one example of a way to organize this tracking information) can be used to track access commands (e.g., write commands) received from the host system and populate the session table 210. Thus, the tracking table 205 can be updated at a given cadence, such as whenever the memory system receives a write command, as described with respect to Figure 4 Further description.

[0051] Tracking table 205 can allow the memory system to selectively construct sessions that are large enough to have a meaningful impact on latency. Thus, tracking table 205 can contain an entry for each potential or ongoing session and can be organized in a manner similar to session table 210. For example, the reference LBA and data size associated with a potential or ongoing session (as given by the reference LBA field and the size field, respectively) can indicate a numerically contiguous set of logical addresses involved in the potential or ongoing session. Additionally, each tracking entry can have an associated timestamp (e.g., given by the timestamp field) that can be used to determine when to stop tracking the session. When the size of a tracking entry (e.g., the size of a potential or ongoing session) meets a threshold size, the memory system can use the information in tracking table 205 to create a new session or update an existing session in session table 210.

[0052] Thus, tracking table 205 may be used to maintain session table 210, which in turn may be used by the memory system to predictively load the L2P table into cache during read operations, thereby increasing cache hit rates and reducing system latency.

[0053] Figure 3 An example of a process flow 300 for supporting session-based storage operations according to examples disclosed herein is illustrated. The process flow 300 may be performed by, for example, referring to Figure 1The memory system 110 described herein may implement the process flow 300 so that the memory system may use a session table (e.g., a reference table) during a read operation. Figure 2 210) to predictively load one or more L2P tables into, for example, a cache. Aspects of process flow 300 may be implemented by a controller and other components. Additionally or alternatively, aspects of process flow 300 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to memory system 110). For example, the instructions, when executed by a controller (e.g., memory system controller 115), may cause the controller to perform the operations of process flow 300. Although the description of Figure 3 The description focuses on read commands and related aspects, but other alternative implementations are also within the scope of this description and disclosure.

[0054] At 305, a first read command targeting a first logical address can be received. For example, the memory system can receive a read command targeting (e.g., indicating, associated with) logical block address x ("LBAx"). In some examples, the logical address can be one of a plurality of logical addresses targeted by the first read command (e.g., the read command can indicate a numerically contiguous set of logical addresses given by a reference logical address and a data size).

[0055] At 310, a session table associated with the logical address may be determined. For example, the memory system may determine a session table that includes a session associated with LBAx. The memory system may determine the session table based on LBAx being included in a logical address range covered by a session in the session table. At 315, the session table may be retrieved from memory and loaded into a cache (e.g., transferred to the cache, written to the cache, stored in the cache). For example, the memory system may retrieve (e.g., read, retrieve, obtain) a session table associated with LBAx and load the session table into the cache. The session associated with LBAx may cover a logical address range that includes logical block address y ("LBAy").

[0056] At 320, an L2P table associated with the logical address covered by the session can be determined based on loading the session table into the cache. For example, the memory system can determine an L2P table associated with the logical address covered by the session associated with LBAx.

[0057] At 325, the L2P table associated with LBAx may be loaded into a cache. For example, the memory system may retrieve the L2P table from memory and load the L2P table into the cache. Loading information, such as an L2P table, into a memory, such as a cache, may refer to writing, storing, or otherwise placing the information in the memory. The cache may also be referred to as memory, cache memory, temporary memory, local memory, buffer, or other suitable terminology. In some examples, the cache is an SRAM cache. In some examples, the cache comprises an SLC.

[0058] At 330, address translation can be performed on LBAx.For example, the memory system can use the L2P table for LBAx (which is in the cache) to determine the physical block address associated with LBAx.

[0059] At 335, the L2P table associated with LBAy (determined at 320) may be loaded into the cache based on LBAy being included in the same session as LBAx. For example, the memory system may retrieve the L2P table associated with LBAy from memory and load the L2P table into the cache. Although described as being loaded at different times, which may occur when the cache is limited to storing a single L2P table at a time, in some examples, the L2P tables for LBAx and LBAy may be in a manner such that both L2P tables are in the cache simultaneously or during overlapping time periods. For example, the L2P table for LBAy may also be loaded into the cache at 325 (instead of at 335) or in a manner such that the L2P tables for LBAx and LBAy coexist in the cache for a duration.

[0060] At 340, a second read command targeting a second logical address may be received. For example, the memory system may receive a read command targeting LBAy, which may be associated with a different L2P table than LBAx. Because the L2P table for LBAy is already ready in the cache when the read command for LBAy is received, LBAy may be translated without the delay associated with retrieving the L2P table for LBAy from memory.

[0061] At 345, address translation can be performed on LBAy. For example, the memory system can use the L2P table for LBAy to determine the physical block address associated with LBAy. After determining the physical block addresses for LBAx and LBAy, one or more read operations can be performed at 350. For example, the memory system can use the physical block addresses to perform the one or more read operations according to the first read command and the second read command.

[0062] Thus, process flow 300 can support predictive loading of one or more L2P tables into, for example, a cache using a session table during a read operation, which can reduce system latency. Alternative embodiments of process flow 300 can be implemented in which some operations are performed in an order different from that described, in parallel, or not performed at all. In some cases, the operations may include additional features not described below, or additional operations may be added. Furthermore, certain operations may be performed multiple times, or certain combinations of operations may be repeated or looped.

[0063] In some examples, the memory system may implement a follow-up technique for loading session tables into the cache. For example, the memory system may associate a first session table with a second table so that when the first session table is loaded into the cache, the second table is also loaded into the cache (e.g., simultaneously with or after the first table). The association between the session tables may be based on the read patterns of the session tables. For example, if the memory system determines that the second session table is constantly or frequently accessed after the first session table is accessed, the memory system may associate the first session table with the second session table. By loading multiple session tables at once, or identifying multiple session tables for loading, the memory system may further increase cache hit rates and thereby reduce system latency.

[0064] In some examples, the memory system may implement fast read techniques for certain session tables. For example, the memory system may identify frequently accessed session tables (e.g., session tables associated with frequently read data) and store these frequently accessed session tables in low-latency memory. For example, the memory system may store the frequently accessed session tables in a memory with lower latency than the memory used to store the remaining session tables. By doing so, the memory system can further reduce the latency associated with retrieving and loading the frequently accessed session tables, which can further reduce address translation latency. Additionally or alternatively, the memory system may load the frequently accessed session tables into a cache with lower latency than the cache used for the remaining session tables. By doing so, the memory system can reduce the latency associated with accessing the frequently accessed session tables during translation operations.

[0065] Figure 4 An example of a process flow 400 for supporting session-based memory operations according to examples disclosed herein is illustrated. The process flow 400 may be performed by, for example, referring to Figure 1 The memory system 110 described herein may implement the process flow 400 to construct a memory system such as a reference Figure 2 The session table 210 described herein may be used to predictively load one or more L2P tables into, for example, a cache during a read operation, as described with reference to FIG. Figure 3As described above, aspects of process flow 400 may be implemented by a controller and other components. Additionally or alternatively, aspects of process flow 400 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to memory system 110). For example, when executed by a controller (e.g., memory system controller 115), the instructions may cause the controller to perform the operations of process flow 400.

[0066] The right branch of process flow 400 may represent actions performed by the memory system when the starting logical block address for a write command is numerically contiguous with the logical address range indicated by (covered by, or associated with) a tracking table entry. Generally speaking, if a write command is received for numerically contiguous logical addresses according to a time criterion, the tracking table entry may be updated; and, for example, if the tracking table entry meets a size threshold, the corresponding session table entry may be updated.

[0067] The left branch of process flow 400 may represent actions performed by the memory system when the starting logical block address for a write command is included in a logical address range indicated by a tracking table entry (or not covered by any tracking table entry). Generally speaking, if a write command is received for a logical address within the range according to a timing criterion and the size of the tracking table entry is modified, the tracking table entry may be updated; for example, if the tracking table entry meets a size threshold, the corresponding session table entry may be updated.

[0068] At 405, a write command targeting a logical address can be received. For example, the memory system can receive a write command targeting a logical block address x ("LBAx"). In some examples, the logical address can be a starting address of a set of numerically contiguous logical addresses that are the targets of the write command (e.g., the write command can indicate a starting address LBAx and a data size that together indicate a set of LBAs to write to).

[0069] At 410, a determination may be made as to whether the logical address is numerically contiguous with the numerically last logical block address in any of the entries in the tracking table, such as the tracking table 205. For example, the memory system 410 may determine whether LBAx is numerically contiguous with the numerically last logical block address in any of the entries in the tracking table. If, at 410, it is determined that LBAx is numerically contiguous with the numerically last logical block address in the entry of the tracking table, the memory system may proceed to 415. If, at 410, it is determined that LBAx is not numerically contiguous with the numerically last logical block address in the entry of the tracking table, the memory system may proceed to 450.

[0070] At 415, it may be determined whether receipt of the write command satisfies a timing criterion (e.g., one or more criteria). For example, the memory system may determine whether the write command was received within a threshold time (e.g., y ms) from the most recent write command associated with the tracking table entry. The memory system may determine whether the timing criterion is satisfied based on a timestamp of the write command received at 405. For example, the memory system may determine whether the timing criterion has been satisfied based on a difference between the timestamp of the write command received at 405 and the timestamp of the most recent write command associated with the tracking table entry. Other suitable terms may also be used to refer to the timing criterion (e.g., timing criterion, timing parameter, timing threshold, etc.).

[0071] If, at 415, it is determined that receipt of the write command satisfies the timing criteria, the memory system may proceed to 420. If, at 415, it is determined that receipt of the write command does not satisfy the timing criteria, the memory system may proceed to 440 and close the tracking table entry. Closing the tracking table entry may involve removing or clearing values ​​in fields of the tracking table entry (e.g., to zeros).

[0072] At 420, the tracking table entry can be updated. For example, the memory system can update the tracking table entry based on satisfying a time threshold. Updating the tracking table entry can include updating a timestamp field of the tracking table entry to reflect the timestamp of the write command received at 405. Updating the tracking table entry can also include updating a size field of the tracking table entry by adding the data size associated with the write command to the existing value in the size field. For example, if the size field of the tracking table entry indicates a value of 36 kB and the data size associated with the write command is 4 kB, the size field of the tracking table entry can be updated to indicate 40 kB. As mentioned, the LBA range covered by the tracking table entry can be indicated by the reference LBA and data size associated with the entry.

[0073] In some examples, updating the tracking table entry may include updating the Reference LBA field to reflect the numerically last LBA targeted by the write command (which may be LBAx or another LBA determined based on the LBAx and data size associated with the write command). Alternatively, the Reference LBA field may remain the same (depending on the calculation direction for the range LBA).

[0074] At 425, a determination may be made as to whether the tracking table entry is associated with an existing session or a new session. For example, the memory system may determine whether LBAx is numerically contiguous with the numerically last logical block address of the session in a session table, such as session table 210. If LBAx is numerically contiguous with the numerically last logical block address of the session in the session table, the memory system may determine that the tracking table entry is associated with the existing session. If LBAx is not numerically contiguous with the numerically last logical block address of the session in the session table, the memory system may determine that the tracking table entry is associated with a new session.

[0075] If, at 425, it is determined that the tracking table entry is associated with an existing session, the memory system may proceed to 445 and update the existing session. Updating the existing session may include updating one or more fields associated with the session entry in the session table. For example, the memory system may update the size field of the session table entry by adding the data size associated with the write command to the existing value in the size field. In some examples, the memory system may also update the reference LBA field of the session table entry to reflect the numerically last LBA targeted by the write command (which may be LBAx or another LBA determined based on the LBAx and data size associated with the write command). Alternatively, the reference LBA field may remain the same (depending on the calculation direction used for the LBA range).

[0076] If, at 425 , it is determined that the tracking table entry is associated with a new session, the memory system may proceed to 430 .

[0077] At 430, it may be determined whether the updated size of the tracking table entry satisfies a size threshold. For example, the memory system may determine whether the size of the tracking table entry (as given by the size field) is greater than a threshold size, such as 3MB.

[0078] If at 430, it is determined that the size of the tracking table entry meets the size threshold, the memory system can proceed to 435 and create a new session table entry for the new session. The new session table entry can indicate the reference logical block address for the session and the size of the data associated with the session. If at 430, it is determined that the size of the tracking table entry does not meet the size threshold, the memory system waits for the next write command.

[0079] Referring now to the decision at 410 , the memory system may proceed to 450 upon determining that LBAx is not numerically contiguous with the numerically last logical block address overwritten by an entry of the tracking table.

[0080] At 450, a determination can be made as to whether the logical address is within a range of logical addresses covered by entries in the tracking table. For example, the memory system can determine whether LBAx is included in a range of logical block addresses covered by any of the entries in the tracking table. By way of illustration, if LBAx is LBA0, LBA1, LBA2, or LBA3, then LBAx can be considered to be included in the range of logical block addresses LBA0 to LBA4.

[0081] If at 450 , it is determined that LBAx is not included in the range of entries in the tracking table, the memory system may proceed to 475 and create a new tracking table entry covering LBAx.

[0082] If, at 450, it is determined that LBAx is included in the range of entries in the tracking table, the memory system may proceed to 455. At 455, it may be determined whether the receipt of the write command meets a time criterion. For example, the memory system may determine whether the write command was received within y ms of the most recent write command associated with the tracking table entry. The memory system may determine whether the time criterion is met based on the timestamp of the write command received at 405. For example, the memory system may determine whether the time criterion is met based on the difference between the timestamp of the write command received at 405 and the timestamp of the most recent write command associated with the tracking table entry.

[0083] If at 455 , it is determined that receipt of the write command does not satisfy the time threshold, the memory system may proceed to 480 and close the tracking table entry that overwrites LBAx.

[0084] If, at 455, it is determined that receipt of the write command satisfies the timing criteria, the memory system may proceed to 460. At 460, the tracking table entry having the logical address range that includes LBAx may be updated based on the timing criteria being met. For example, the memory system may update the timestamp field for the tracking table entry to reflect the timestamp of the write command received at 405. In some cases, the memory system may also update the size field for the tracking table entry. For example, if the data size associated with the write command for LBAx indicates a set of one or more logical addresses that overlaps with and extends beyond the numerically last logical address of the tracking table entry, the memory system may update the tracking table entry to reflect a new logical address range that includes the original range plus the set of one or more logical addresses. The memory system may update the tracking table entry by updating the size field so that the size field and the reference LBA together indicate the new logical address range. As an illustration, if the tracking table entry has an original range of LBA0 to LBA4, LBAx is LAB2, and the data size associated with the write command indicates LBA2 to LBA7, the size field of the tracking table entry can be updated (e.g., from 20kB to 32kB) to indicate LBA0 to LBA7.

[0085] At 465, it may be determined whether the size of the tracking table entry satisfies a size threshold. For example, the memory system may determine whether the size of the tracking table entry (as given by the size field) is greater than a threshold size (eg, 3MB).

[0086] If at 465, it is determined that the size of the tracking table entry does not meet the size threshold, then the memory system may wait for the next write command.

[0087] If, at 465, it is determined that the size of the tracking table entry meets the size threshold, the memory system may proceed to 470 and create a new session table entry for the new session or update an existing session associated with the tracking table entry. Creating a new session table entry may include populating a size field and a reference LBA field with values ​​associated with the entry. Updating an existing session table entry may include updating the values ​​of the size field and / or reference LBA field for the existing session table entry.

[0088] Thus, a memory system can implement process flow 400 to construct a session table that can be used to predictively load one or more L2P tables into, for example, a cache during a read operation. Alternative embodiments of process flow 400 can be implemented in which some operations are performed in an order different from that described, in parallel, or not performed at all. In some cases, the operations may include additional features not described below, or additional operations may be added. Furthermore, certain operations may be performed multiple times, or certain combinations of operations may be repeated or looped.

[0089] Figure 5 An example of a table 500 that supports session-based memory operations according to examples disclosed herein is illustrated. Table 500 may be maintained by a memory system, such as memory system 110, and may include multiple L2P session tables 505. L2P session tables 505 may be used by the memory system in place of an L2P table and may allow the memory system to load the L2P session table into a cache for translation of discontinuous logical addresses, which may improve system performance. In some examples, table 500 may include one or more sessionless L2P tables, such as those described with respect to FIG. Figure 7 Describe in more detail.

[0090] The L2P session table 505 may be different from other L2P tables (e.g., Figures 1 to 4 L2P session table 505 is organized in a manner similar to those L2P tables described herein. For example, rather than providing physical block addresses for a numerically contiguous set of physical block addresses, each L2P session table 505 may provide physical block addresses for a set of physical block addresses in the same session. Thus, the logical block addresses contained in an L2P session table may or may not be contiguous. For example, L2P session table 0 may indicate physical block addresses for LBA3, LBA22, LBA7, and so on. Like the other L2P tables, L2P session table 505 may be stored in memory as described herein and loaded into cache for address translation during read operations.

[0091] In other scenarios, the use of session table 505 can be advantageous when data from a file is stored in memory cells associated with non-contiguous logical block addresses. For example, the memory cells storing a first data set (or first "segment") for a file may have non-contiguous logical addresses relative to the logical addresses of the memory cells storing a second data set (or second "segment") for the file. Rather than waiting for a read command targeting a logical address for a different segment, the memory system can load the L2P session table 505 for the file into the cache immediately after receiving the first read command targeting the logical address of L2P session table 505. Because the L2P table has the physical bank addresses for the other logical addresses in the session, the memory system can perform address translation for the file without loading an additional L2P table, thereby saving resources and reducing latency.

[0092] References in this article Figure 6 The use of the L2P session table 505 during a read operation is described in more detail. Figure 7 The construction of the L2P session table 505 is described in more detail.

[0093] Figure 6An example of a process flow 600 and a master table 605 for supporting session-based memory operations according to examples disclosed herein is illustrated. The process flow 600 may be referenced by, for example, Figure 1 The memory system 110 described herein may implement the process flow 600 so that the memory system may use the L2P session table (e.g., referenced to the L2P session table) during a read operation. Figure 5 The L2P session table 505 described herein effectively performs address translation. Aspects of process flow 600 may be implemented by a controller as well as other components. Additionally or alternatively, aspects of process flow 600 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to memory system 110). For example, the instructions, when executed by a controller (e.g., memory system controller 115), may cause the controller to perform the operations of process flow 600. Although the Figure 6 The description focuses on read commands and related aspects, but other alternative implementations are also within the scope of this description and disclosure.

[0094] At 610, a first read command targeting a first logical address may be received. For example, the memory system may receive a read command targeting logical block address x ("LBAx"). At 615, an L2P session table associated with the logical address may be determined. For example, the memory system may determine an L2P session table associated with LBAx. For example, the memory system may determine that L2P session table 3 is associated with LBAx. The memory system may determine the session table based on associating LBAx with an identifier (ID) of the session table. In some examples, the session table ID is derived from a range of logical block addresses covered by the session table. For example, a hash function may be used to derive the session table ID from the range of logical block addresses.

[0095] At 620, the logical address of the L2P session table may be determined. For example, the memory system may determine the logical address for L2P session table 3. At 625, the physical address for the L2P session table may be determined based on the logical address of the L2P session table. For example, the memory system may determine the physical address of L2P session table 3. The memory system may determine the physical address from master table 605, which may contain the physical addresses of the L2P session tables. The physical addresses may be arranged such that the logical addresses associated with the physical addresses increase sequentially (numerically, exponentially) starting from the physical address of L2P session table 0. Therefore, to determine the physical address of the L2P session table, the memory system may use an offset indicating the appropriate entry of master table 605. For example, to determine the physical address for L2P session table 3, the memory system may use offset 645, which may be equal to three, referring to the fourth entry of master table 605, which may contain the physical address for L2P session table 3.

[0096] At 630, the L2P session table can be loaded into a cache for the memory system. For example, the memory system can load L2P session table 3 into the cache. The memory system can locate the L2P session table in the memory based on the physical address determined at 625. At 635, a second read command targeting a second logical address can be received. For example, the memory system can receive a read command targeting logical block address y ("LBAy"). The L2P session table (e.g., L2P session table 0) can include physical addresses for LBAx and LBAy, and so on. Thus, the memory system can be ready to translate LBAy even before receiving a write command targeting LBAy.

[0097] In some examples, the host system may request read operations for two different concurrent activities (e.g., read commands for one activity may be interleaved with read commands for another activity). In such scenarios, the memory system may load multiple L2P sessions (e.g., one L2P session for each activity) into the cache. For example, in addition to loading L2P session table 0 into the cache, the memory system may also load L2P session table 10 into the cache, where L2P session table 0 and L2P session table 10 are associated with different activities.

[0098] At 640, address translation for LBAx and LBAy can be performed. For example, the memory system can use L2P session table 0 to determine the physical block addresses associated with LBAx and LBAy, respectively. After determining the physical block addresses, one or more read operations can be performed at 645. For example, the memory system can use the physical block addresses to perform the one or more read operations according to the first read command and the second read command.

[0099] Thus, process flow 600 can support efficient address translation using the L2P session table during read operations. Alternative embodiments of process flow 600 can be implemented in which some operations are performed in an order different from that described, in parallel, or not performed at all. In some cases, the operations may include additional features not described below, or additional operations may be added. Furthermore, certain operations may be performed multiple times, or certain combinations of operations may be repeated or looped.

[0100] Figure 7 An example of a process flow 700 for supporting session-based memory operations according to examples disclosed herein is illustrated. The process flow 700 may be performed by, for example, referring to Figure 1 The memory system 110 described herein may implement the process flow 700 to construct an L2P session table, such as with reference to FIG. Figure 5The L2P session table 505 described above can be used to efficiently perform address translation during read operations, as shown in FIG. Figure 6 700. Aspects of process flow 700 may be implemented by a controller and other components. Additionally or alternatively, aspects of process flow 700 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to memory system 110). For example, when executed by a controller (e.g., memory system controller 115), the instructions may cause the controller to perform the operations of process flow 700.

[0101] At 705, a write command targeting a logical address can be received. For example, the memory system can receive a write command targeting a logical block address x ("LBAx"). At 710, a physical address associated with the logical address can be determined. For example, the memory system can determine the logical address associated with LBAx.

[0102] At 715, it may be determined whether receipt of the write command satisfies a time criterion. For example, the memory system may determine whether the write command was received within a threshold duration (e.g., y ms) from the most recent write command associated with the L2P session table. The memory system may determine whether the time criterion is satisfied based on a timestamp of the write command received at 705. For example, the memory system may determine whether the time criterion has been satisfied based on a difference between a timestamp of the write command received at 705 and a timestamp of the most recent write command associated with the L2P session table.

[0103] If, at 715, it is determined that receipt of the write command satisfies the time criteria, the memory system may proceed to 720. At 720, the physical address and the logical address may be added to the current L2P session table based on the time criteria being met. For example, the memory system may update L2P session table 0 to include LBAx and the physical address associated with LBAx.

[0104] If, at 715, it is determined that receipt of the write command does not meet the timing criteria, the memory system may proceed to 725. At 725, the current L2P session table may be closed based on not meeting the timing criteria. Closing the L2P session table may include storing the L2P session table in memory. At 730, the logical address may be added to a sessionless L2P table or a new L2P session table may be started. The sessionless L2P table may include physical address mappings for logical addresses not associated with a session (e.g., logical addresses for which a write command was not received according to the timing criteria). Thus, the memory system may add LBAx and its corresponding physical block address to the sessionless L2P table. If another (e.g., a second) write command is received according to the timing criteria, the memory system may start a new L2P session table that includes LBAx and the logical address targeted by the second write command.

[0105] Due to the temporal criteria, host activity (e.g., video encoding) or files can be distributed among different L2P session tables. For example, a first data segment of a file can be associated with a first L2P session table, and a second data segment of the file can be associated with a second L2P session table. The memory system can compensate for fragmented files using the following techniques described herein (e.g., the memory system can follow the associated L2P session table for loading into the cache).

[0106] Thus, a memory system can implement process flow 700 to construct an L2P session table that can be used to efficiently perform address translation during read operations. Alternative embodiments of process flow 700 can be implemented in which some operations are performed in an order different from that described, in parallel, or not performed at all. In some cases, the operations may include additional features not described below, or additional operations may be added. Furthermore, certain operations may be performed multiple times, or certain combinations of operations may be repeated or looped.

[0107] In some examples, the memory system may construct an L2P session table based on session information from the host system (as opposed to a time-based basis). For example, the host system may indicate to the memory system when to start a session and when to stop a session.

[0108] Figure 8 A block diagram 800 illustrates a memory system 805 that supports session-based memory operations according to examples disclosed herein. The memory system 805 may be a reference Figures 1 to 7 Memory system 805 may include session logic 810, cache logic 815, interface circuitry 820, follower logic 825, translation logic 830, memory logic 835, size comparator 840, and timing logic 845. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0109] The session logic 810 may determine that the logical block address targeted by the read command is associated with a first table indicating a first set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied the timing criteria. In some cases, the first set of logical block addresses includes numerically consecutive logical block addresses. In some examples, the session logic 810 may determine that the logical block address is associated with a table indicating a set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied the timing criteria.

[0110] In some examples, the session logic 810 may update the table to indicate that the set of logical block addresses includes the logical block addresses based on receipt of the write command satisfying timing criteria relative to a previous write command associated with the set of logical block addresses.

[0111] In some instances, the session logic 810 may write one or more values ​​in the first table based on each of the logical block addresses in the first set of logical block addresses being targeted by a write command received within a threshold duration relative to a previous write command, wherein the previous write command is associated with numerically consecutive logical block addresses in the first set of logical block addresses.

[0112] In some examples, the session logic 810 may, based on expiration of a threshold amount of time, update the second table to indicate that the set of logical block addresses includes the logical block address.

[0113] In some examples, the session logic 810 may determine that the logical block address is numerically consecutive to the last logical block address of the set of logical block addresses indicated by the table.

[0114] In some examples, session logic 810 may determine that the second set of logical block addresses numerically overlaps with the set of logical block addresses.

[0115] In some cases, the timing criteria specify a threshold duration between receipt of a write command targeting a first logical block address and receipt of a second write command targeting a second logical block that is numerically consecutive to the first logical block address.

[0116] In some cases, the logical block address set includes numerically consecutive logical block addresses. In some cases, the table indicates the physical block addresses corresponding to the logical block address set.

[0117] The cache logic 815 may write the first table to the cache based on the logical block address being associated with the first set of logical block addresses.

[0118] In some instances, the cache logic 815 may write a second logical block address set including logical block addresses from the first logical block address set indicated by the first table to the cache based on the first table and a second table indicating the second logical block address set and corresponding physical block addresses.

[0119] In some instances, the cache logic 815 may write a third logical block address set including logical block addresses from the first logical block address set indicated by the first table to the cache based on the first table, a third table indicating the third logical block address set and corresponding physical block addresses.

[0120] In some examples, the cache logic 815 may write the third table to the cache based on determining that the first table is associated with the third table.

[0121] In some examples, cache logic 815 may write the table to a cache of the memory system based on the read command and the logical block address being included in the table.

[0122] In some instances, the cache logic 815 may write the second logical block address set including logical block addresses from the logical block address set indicated by the table to the cache based on a second table indicating the second logical block address set and corresponding physical block addresses.

[0123] Interface circuitry 820 may receive a write command targeting a logical block address.

[0124] In some examples, the interface circuitry 820 may receive a second read command for the second logical block address after loading a third table into the cache, the third table indicating physical block addresses corresponding to the second logical block address.

[0125] In some examples, interface circuitry 820 may receive a read command targeting a logical block address.

[0126] The follow logic 825 may determine that the first table is associated with a third table indicating a third set of logical block addresses that were each previously targeted by one or more write operations according to the timing criteria.

[0127] The translation logic 830 may determine a physical block address associated with the logical block address based on the second table.

[0128] In some examples, translation logic 830 may determine a physical block address associated with a logical block address based on a mapping provided by a table.

[0129] The memory logic 835 may perform a read operation on the set of memory cells associated with the physical block address.

[0130] In some examples, the memory logic 835 may perform a read operation on a set of memory cells associated with a physical block address.

[0131] The size comparator 840 may determine that the set of logical block addresses is associated with a data size that satisfies a size threshold, wherein the table is updated based on the data size that satisfies the size threshold.

[0132] The timing logic 845 may determine that a threshold amount of time has expired since the write command was received.

[0133] Figure 9 Flowchart showing one or more methods 900 for supporting session-based memory operations according to aspects of the present disclosure. The operations of the method 900 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory system or components thereof as described herein. Figure 8 The memory system described herein performs the functions described herein. In some examples, the memory system may execute instruction sets to control functional elements of the memory system to perform the functions described herein. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the functions described herein.

[0134] At 905, the method may include determining that the logical block address targeted by the read command is associated with a first table indicating a first set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied a timing criterion. The operations of 905 may be performed according to the methods described herein. In some examples, the operation may be performed by reference to Figure 8 The described session logic performs aspects of the operations of 905 .

[0135] At 910, the method may include writing a first table to a cache memory based on the logical block address being associated with the first set of logical block addresses. The operations of 910 may be performed according to the methods described herein. In some examples, the first table may be written to the cache memory based on the logical block address being associated with the first set of logical block addresses. Figure 8 The described cache logic performs aspects of the operations of 910 .

[0136] At 915, the method may include writing a second set of logical block addresses including logical block addresses from the first set of logical block addresses indicated by the first table to the cache based on the first table and a second table indicating the second set of logical block addresses and corresponding physical block addresses. The operation of 915 may be performed according to the methods described herein. In some examples, the reference Figure 8 The described cache logic performs aspects of the operations of 915 .

[0137] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include operations, features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for: determining that a logical block address targeted by a read command is associated with a first table indicating a first set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied a timing criterion; writing the first table to a cache based on the logical block address being associated with the first set of logical block addresses; and writing a second set of logical block addresses including logical block addresses from the first set of logical block addresses indicated by the first table to the cache based on the first table, a second table indicating a second set of logical block addresses and corresponding physical block addresses.

[0138] In some examples of the method 900 and apparatus described herein, the first set of logical block addresses includes numerically consecutive logical block addresses.

[0139] In some examples of the method 900 and apparatus described herein, the timing criteria specify a threshold duration between receipt of a write command targeting a first logical block address and receipt of a second write command targeting a second logical block that is numerically consecutive to the first logical block address.

[0140] Some instances of the method 900 and apparatus described herein may further include operations, features, means, or instructions for writing, based on the first table, a third table indicating a third set of logical block addresses and corresponding physical block addresses, a third set of logical block addresses including logical block addresses from the first set of logical block addresses indicated by the first table to the cache.

[0141] Some instances of the method 900 and apparatus described herein may further include operations, features, means, or instructions for receiving a second read command for a second logical block address after loading a third table into the cache, the third table indicating a physical block address corresponding to the second logical block address.

[0142] Some instances of the method 900 and apparatus described herein may further include operations, features, means, or instructions for writing one or more values ​​in the first table based on each of the logical block addresses in the first set of logical block addresses being targeted by a write command received within a threshold duration relative to a previous write command, the previous write command being associated with numerically consecutive logical block addresses in the first set of logical block addresses.

[0143] Some instances of the method 900 and apparatus described herein may further include operations, features, means, or instructions for determining that a first table may be associated with a third table indicating a third set of logical block addresses, each of which was previously the target of one or more write operations according to timing criteria; and based on determining that the first table may be associated with the third table, writing the third table to a cache.

[0144] Some examples of the method 900 and apparatus described herein may additionally include operations, features, means, or instructions for: determining a physical block address associated with the logical block address based on the second table; and performing a read operation on the set of memory cells associated with the physical block address.

[0145] Figure 10 1000 is a flowchart illustrating one or more methods 1000 for supporting session-based memory operations according to aspects of the present disclosure. The operations of the method 1000 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 1000 may be implemented by a memory system or components thereof as described herein. Figure 8 The memory system described herein performs the functions described herein. In some examples, the memory system may execute instruction sets to control functional elements of the memory system to perform the functions described herein. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the functions described herein.

[0146] At 1005, the method may include receiving a write command targeting a logical block address. The operations of 1005 may be performed according to the methods described herein. In some examples, the write command may be performed by reference to Figure 8 The described interface circuitry performs aspects of the operations of 1005 .

[0147] At 1010, the method may include determining that a logical block address is associated with a table indicating a set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied a timing criterion. The operations of 1010 may be performed according to the methods described herein. In some examples, the operation may be performed by reference to Figure 8 The described session logic performs aspects of the operations of 1010 .

[0148] At 1015, the method may include updating the table to indicate that the logical block address set includes the logical block address based on the receipt of the write command satisfying the timing criteria relative to the previous write command associated with the logical block address set. The operation of 1015 may be performed according to the methods described herein. In some examples, the table may be updated as described in reference to Figure 8 Aspects of the operations of session logic execution 1015 are described.

[0149] In some examples, an apparatus as described herein may perform one or more methods, such as method 1000. The apparatus may include operations, features, means, or instructions (e.g., instructions executable by a processor stored on a non-transitory computer-readable medium) for: receiving a write command that targets a logical block address; determining that the logical block address is associated with a table that indicates a set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied a timing criterion; and updating the table to indicate that the set of logical block addresses includes the logical block address based on the receipt of the write command satisfying the timing criterion relative to a previous write command associated with the set of logical block addresses.

[0150] In some examples of the method 1000 and apparatus described herein, the set of logical block addresses includes numerically consecutive logical block addresses.

[0151] Some instances of the method 1000 and apparatus described herein may include features, means, or instructions (e.g., instructions executable by a processor stored on a non-transitory computer-readable medium) for determining that a set of logical block addresses may be associated with a data size that satisfies a size threshold, wherein a table may be updated based on the size that satisfies the size threshold.

[0152] Some instances of the method 1000 and apparatus described herein may further include operations, features, means, or instructions for determining that a threshold amount of time may have expired from receipt of the write command; and based on the expiration of the threshold amount of time, updating the second table to indicate that the set of logical block addresses includes the logical block address.

[0153] In some instances of the method 1000 and apparatus described herein, determining that a logical block address may be associated with a table may include operations, features, means, or instructions for determining that the logical block address may be numerically consecutive to a last logical block address of the set of logical block addresses indicated by the table.

[0154] In some examples of the method 1000 and apparatus described herein, the logical block address may be included in a second set of logical block addresses targeted by the write command, and wherein determining that the logical block address may be associated with the set of logical block addresses may include an operation, feature, means, or instruction for determining that the second set of logical block addresses numerically overlaps with the set of logical block addresses.

[0155] Some instances of the method 1000 and apparatus described herein may further include operations, features, means, or instructions for: receiving a read command targeting the logical block address; and writing the table to a cache of the memory system based on the read command and the inclusion of the logical block address in the table.

[0156] Some instances of the method 1000 and apparatus described herein may further include operations, features, means, or instructions for writing, based on the table, a second table indicating a second set of logical block addresses and corresponding physical block addresses, the second set of logical block addresses including logical block addresses from the set of logical block addresses indicated by the table to the cache.

[0157] Some instances of the method 1000 and apparatus described herein may further include operations, features, means, or instructions for determining a physical block address associated with the logical block address based on a mapping provided by the table; and performing a read operation on a set of memory cells associated with the physical block address.

[0158] In some examples of the method 1000 and apparatus described herein, the table indicates physical block addresses corresponding to the set of logical block addresses.

[0159] In some examples, a device may implement the techniques described herein. The device may include a memory system including a cache memory; and a controller coupled to the memory system and configured to cause the device to: determine that a logical block address targeted by a read command is associated with a first table indicating a first set of logical block addresses that were each previously targeted by one or more write commands, the receipt of which satisfied a timing criterion; write the first table to the cache memory based at least in part on the logical block address being associated with the first set of logical block addresses; and write a second set of logical block addresses including logical block addresses from the first set of logical block addresses indicated by the first table to the cache memory based at least in part on the first table, a second table indicating a second set of logical block addresses and corresponding physical block addresses.

[0160] In some instances of the apparatus, the first set of logical block addresses includes numerically consecutive logical block addresses. In some instances of the apparatus, the timing criteria specify a threshold duration between receipt of a write command targeting a first logical block address and receipt of a second write command targeting a second logical block that is numerically consecutive to the first logical block address.

[0161] In some instances of the device, the controller is further configured to cause the device to: write the third logical block address set including logical block addresses from the first logical block address set indicated by the first table to the cache based at least in part on the first table, a third table indicating the third logical block address set and corresponding physical block addresses.

[0162] In some examples of the device, the controller is further configured to cause the device to receive a second read command for the second logical block address after loading a third table into the cache, the third table indicating a physical block address corresponding to the second logical block address.

[0163] In some instances of the device, the controller is further configured to cause the device to: write one or more values ​​in the first table based at least in part on each of the logical block addresses in the first set of logical block addresses being targeted by a write command received within a threshold duration relative to a previous write command, the previous write command being associated with numerically consecutive logical block addresses in the first set of logical block addresses.

[0164] In some instances of the device, the controller is further configured to cause the device to: determine that the first table is associated with a third table indicating a third set of logical block addresses, each of which was previously the target of one or more write operations according to the timing criteria; and write the third table to the cache based at least in part on determining that the first table is associated with the third table.

[0165] It should be noted that the methods described herein describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are possible. Additionally, portions from two or more of the methods described may be combined.

[0166] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signaling as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have various bit widths.

[0167] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0168] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via the conductive paths, to a closed-circuit relationship between the components, in which signals are able to communicate between the components via the conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via the conductive paths that previously did not permit signal flow.

[0169] The term "isolation" refers to a relationship between components where signals cannot flow between them. Components are isolated from one another if an open circuit exists between them. For example, components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller separates two components, it implements a change that prevents signals from flowing between them using the conductive path that previously allowed signal flow.

[0170] As used herein, the term "substantially" means that the modified characteristic (such as a verb or adjective modified by the term substantially) is not necessarily absolute but is close enough to obtain the advantage of the characteristic.

[0171] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0172] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "switched on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0173] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "superior" to other examples. The detailed description includes specific details to provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0174] In the accompanying drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0175] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0176] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0177] As used herein, "or," as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of"), included in the claims, indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based, at least in part, on."

[0178] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method performed by a memory system, comprising: determining that a logical block address targeted by the read command is associated with a session table, the session table comprising a starting logical block address and a size, the starting logical block address and the size together indicating a first set of logical block addresses for a write session, wherein write commands targeting the first set of logical block addresses each satisfy a timing criterion; writing the session table to a cache based at least in part on the logical block address being included in the first set of logical block addresses for the write session; and An address mapping table is written to the cache based at least in part on writing the session table to the cache, the address mapping table indicating a mapping between physical block addresses and a second set of logical block addresses, wherein the address mapping table is written to the cache based at least in part on the second set of logical block addresses including at least some logical block addresses from the first set of logical block addresses indicated by the session table. 2 . The method of claim 1 , wherein the first set of logical block addresses comprises numerically consecutive logical block addresses.

3. The method of claim 2, wherein the timing criteria specifies a threshold duration between receipt of a write command targeting a first logical block address and receipt of a second write command targeting a second logical block that is numerically consecutive to the first logical block address.

4. The method of claim 1 , further comprising: The third logical block address set including logical block addresses from the first logical block address set indicated by the session table is written to the cache based at least in part on the session table, a second address mapping table indicating a third logical block address set and corresponding physical block addresses.

5. The method of claim 4, further comprising: After loading the second address mapping table into the cache, a second read command for a second logical block address is received, the second address mapping table indicating a physical block address corresponding to the second logical block address.

6. The method of claim 1 , further comprising: The starting logical block address and the size are written to the session table based at least in part on the write commands targeting the first set of logical block addresses each being received within a threshold duration relative to a previous write command associated with numerically consecutive logical block addresses in the first set of logical block addresses.

7. The method of claim 1 , further comprising: determining that the session table is associated with a second session table indicating a third set of logical block addresses that were each previously targeted for one or more write operations according to the timing criteria; and Based at least in part on determining that the session table is associated with the second session table, the second session table is written to the cache.

8. The method of claim 1 , further comprising: determining a physical block address associated with the logical block address based at least in part on the address mapping table; and A read operation is performed on the set of memory cells associated with the physical block address.

9. A method performed by a memory system, comprising: receiving a write command targeting a logical block address; determining that the logical block address is associated with a table comprising a starting logical block address and a size, the starting logical block address and the size together indicating a set of logical block addresses for a write session, wherein write commands targeting the set of logical block addresses each satisfy a timing criterion; and Based at least in part on the logical block address being numerically consecutive to the numerically last logical block address in the table and at least in part on receipt of the write command satisfying the timing criteria relative to a previous write command associated with the set of logical block addresses, the starting logical block address or the size associated with the table is updated to indicate that the set of logical block addresses includes the logical block address.

10. The method of claim 9, wherein the set of logical block addresses comprises numerically consecutive logical block addresses.

11. The method of claim 9, further comprising: A determination is made that the set of logical block addresses is associated with a data size that satisfies a size threshold, wherein the table is updated based at least in part on the data size satisfying the size threshold.

12. The method of claim 9, further comprising: determining that a threshold amount of time has expired since receiving the write command; and Based at least in part on the expiration of the threshold amount of time, a second table is updated to indicate that the set of logical block addresses includes the logical block address.

13. The method of claim 9, wherein determining that the logical block address is associated with the table comprises: The logical block address is determined to be numerically consecutive to the numerically last logical block address of the set of logical block addresses indicated by the table.

14. The method of claim 9 , wherein the logical block address is included in a second set of logical block addresses targeted by the write command, and wherein determining that the logical block address is associated with the set of logical block addresses comprises: It is determined that the second logical block address set overlaps with the logical block address set in terms of value.

15. The method of claim 9, further comprising: receiving a read command targeting the logical block address; and Based at least in part on the read command and the inclusion of the logical block address in the table, the table is written to a cache of the memory system.

16. The method of claim 15, further comprising: Based at least in part on the table, a second table indicating a second set of logical block addresses and corresponding physical block addresses, writing the second set of logical block addresses including logical block addresses from the set of logical block addresses indicated by the table to the cache.

17. The method of claim 15, further comprising: determining a physical block address associated with the logical block address based at least in part on a mapping provided by the table; and A read operation is performed on the set of memory cells associated with the physical block address.

18. An apparatus comprising: a memory system including a cache memory; and a controller coupled to the memory system and configured to cause the device to: determining that a logical block address targeted by the read command is associated with a session table, the session table comprising a starting logical block address and a size, the starting logical block address and the size together indicating a first set of logical block addresses for a write session, wherein write commands targeting the first set of logical block addresses each satisfy a timing criterion; writing the session table to a cache based at least in part on the logical block address being included in the first set of logical block addresses; and An address mapping table is written to the cache based at least in part on writing the session table to the cache, the address mapping table indicating a mapping between physical block addresses and a second set of logical block addresses, wherein the address mapping table is written to the cache based at least in part on the second set of logical block addresses including at least some logical block addresses from the first set of logical block addresses indicated by the session table.

19. The apparatus of claim 18, wherein the first set of logical block addresses comprises numerically consecutive logical block addresses.

20. The apparatus of claim 18, wherein the timing criteria specifies a threshold duration between receipt of a write command targeting a first logical block address and receipt of a second write command targeting a second logical block that is numerically consecutive to the first logical block address.

21. The apparatus of claim 18, wherein the controller is further configured to cause the apparatus to: The third logical block address set including logical block addresses from the first logical block address set indicated by the session table is written to the cache based at least in part on the session table, a second address mapping table indicating a third logical block address set and corresponding physical block addresses.

22. The apparatus of claim 21 , wherein the controller is further configured to cause the apparatus to: After loading the second address mapping table into the cache, a second read command for a second logical block address is received, the second address mapping table indicating a physical block address corresponding to the second logical block address.

23. The apparatus of claim 18, wherein the controller is further configured to cause the apparatus to: The starting logical block address and the size are written to the session table based at least in part on the write commands targeting the first set of logical block addresses each being received within a threshold duration relative to a previous write command associated with numerically consecutive logical block addresses in the first set of logical block addresses.

24. The apparatus of claim 18, wherein the controller is further configured to cause the apparatus to: determining that the session table is associated with a second session table indicating a third set of logical block addresses that were each previously targeted for one or more write operations according to the timing criteria; and Based at least in part on determining that the session table is associated with the second session table, the second session table is written to the cache.

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