Temperature compensation of unselected sub-block inhibition bias for mitigating erasure interference

Abstract

The invention is entitled "Temperature Compensation of Unselected Sub-Block Inhibit Bias for Mitigating Erase Disturb." The invention provides a memory device and method of operation. The device includes a block having memory cells connected to word lines and arranged in strings and divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The device has a temperature measurement circuit configured to detect an ambient temperature of the device. A control circuit is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuit applies an erase voltage to each of the strings while applying a word line erase voltage to the word line associated with a selected one of the first sub-block and the second sub-block to facilitate erasing and applying the word line inhibit voltage to the word line associated with a non-selected one of the first sub-block and the second sub-block to prevent erasing in the erase operation.

Description

TECHNICAL FIELD

[0001] This application relates to non-volatile memory devices and operations of non-volatile memory devices. BACKGROUND

[0002] This section provides background information related to the technical field of the disclosure and as such is not necessarily prior art.

[0003] Semiconductor memory is used in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.

[0004] Some non-volatile memory utilizes a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between a source region and a drain region. A control gate is disposed above and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor turns on to allow conduction between its source and drain is controlled by the charge level on the floating gate.

[0005] Some non-volatile memory utilizes a charge-trapping layer to store information. One such example has an oxide-nitride-oxide (ONO) region, where the nitride (e.g., SiN) serves as a charge-trapping layer to store information. When such a memory cell is programmed, an electron is stored in the charge-trapping layer.

[0006] Non-volatile memory can have a 2D architecture or a 3D architecture. Ultra-high density storage devices have been adopted using 3D stacked memory structures with strings of memory cells. One such storage device is sometimes referred to as a Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductor layers and insulator layers. The conductor layers can serve as word lines. Memory holes are drilled in the layers to simultaneously define many memory layers. NAND strings are then formed by filling the memory holes with appropriate materials. Straight NAND strings extend in one memory hole, while pipe or U-shaped NAND strings (P-BiCS) include a pair of vertical columns of memory cells extending in two memory holes and joined by a pipe connection. The pipe connection can be made of undoped polysilicon. A back gate can surround the pipe connection to control conduction of the pipe connection. The control gates of the memory cells are provided by the conductor layers.

[0007] Before programming certain non-volatile memory devices, such as NAND flash memory devices, memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gate. For others, the erase operation removes electrons from the charge trapping layer.

[0008] During the operation of a non-volatile memory device, reading, writing, and erasing data in one memory cell or storage unit typically interferes with data stored in other memory cells. One source of this interference is field-effect coupling between adjacent floating gates. Summary of the Invention

[0009] This section provides a general overview of the disclosure and is not a full disclosure of its entire scope or all its features and advantages.

[0010] The purpose of this disclosure is to provide a memory device and a method for operating the memory device that solves and overcomes the above-mentioned disadvantages.

[0011] Therefore, one aspect of this disclosure is to provide an apparatus comprising a block having memory cells connected to word lines and arranged in a string. The block is divided into a first sub-block and a second sub-block, each configured to be erased as a whole in an erase operation. The apparatus also includes a temperature measurement circuit configured to detect the ambient temperature of the apparatus. A control circuit is coupled to the word lines, the strings, and the temperature measurement circuit, and is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuit is further configured to apply an erase voltage to each string in the string, while simultaneously applying a word line erase voltage to the word line associated with a selected one of the first sub-block and the second sub-block to facilitate the erasure of the memory cell in the erase operation. Furthermore, the control circuit is configured to apply a word line inhibit voltage to the word line associated with an unselected one of the first sub-block and the second sub-block to prevent the erasure of the memory cell in the erase operation.

[0012] According to another aspect of the disclosure, a controller in communication with a memory device is provided, the memory device including a block of memory cells connected to word lines and arranged into strings. The block is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The controller is in communication with a temperature measurement circuit configured to detect an ambient temperature of the memory device. The controller is configured to determine a word line inhibit voltage based on the ambient temperature. The controller is further configured to instruct the memory device to apply an erase voltage to each of the strings while applying a word line erase voltage to the word line associated with a selected one of the first sub-block and the second sub-block to facilitate erasure of the memory cells in the erase operation. Additionally, the controller is configured to instruct the memory device to apply the word line inhibit voltage to the word line associated with a non-selected one of the first sub-block and the second sub-block to prevent erasure of the memory cells in the erase operation.

[0013] According to an additional aspect of the disclosure, a method of operating a memory device is provided. The memory device includes a block of memory cells connected to word lines and arranged into strings. The block is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The memory device further includes a temperature measurement circuit configured to detect an ambient temperature of the memory device. The method includes the step of determining a word line inhibit voltage based on the ambient temperature. The method continues with the steps of applying an erase voltage to each of the strings while applying a word line erase voltage to the word line associated with a selected one of the first sub-block and the second sub-block to facilitate erasure of the memory cells and applying the word line inhibit voltage to the word line associated with a non-selected one of the first sub-block and the second sub-block to prevent erasure of the memory cells in the erase operation.

[0014] Additional areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0015] The drawings described herein are for illustrative purposes only of selected embodiments and are not intended to limit the scope of the present disclosure.

[0016] FIG. 1A is a top view of a NAND string according to aspects of the disclosure;

[0017] FIG. 1B is a top view of a NAND string according to aspects of the disclosure FIG. 1A is an equivalent circuit diagram of the NAND string of

[0018] FIG. 2 is a top view of a NAND string according to aspects of the disclosureFIG. 1A a cross-sectional view of a NAND string of the array 400;

[0019] FIG. 3 depicts a portion of one of the blocks of the array 400 in accordance with aspects of the present disclosure; FIG. 1A-2 three example NAND strings as shown;

[0020] FIG. 4 is a block diagram of the array 400 of NAND flash memory cells including FIG. 3 BLK0 and additional blocks BLK1 and BLK2 in accordance with aspects of the present disclosure;

[0021] FIG. 5A is a block diagram of one embodiment of a sense block of the array 400 in accordance with aspects of the present disclosure;

[0022] FIG. 5B is a block diagram of a non-volatile memory system including FIG. 4 the array 400 in accordance with aspects of the present disclosure;

[0023] FIG. 6A depicts an example cross-sectional view of a portion of one of the blocks of the array 400 in accordance with aspects of the present disclosure; FIG. 4

[0024] FIG. 6B depicts a plot of memory hole diameters in a stack of the array 400 in accordance with aspects of the present disclosure; FIG. 6A

[0025] FIG. 7A depicts an example of a fully programmed block BLK0 in accordance with aspects of the present disclosure;

[0026] FIG. 7B depicts an example of a partially programmed block BLKa having a programmed source-side neighbor sub-block SBLK0a and an erased non-source-side neighbor sub-block SBLKla in accordance with aspects of the present disclosure;

[0027] FIG. 7C depicts another example of a partially programmed block BLKb having a programmed source-side neighbor sub-block SBLKOb and an erased non-source-side neighbor sub-block SBLKlb in accordance with aspects of the present disclosure;

[0028] FIG. 7D depicts another example of a partially programmed block BLKc having a programmed source-side neighbor sub-block SBLK0c, a programmed non-source-side neighbor sub-block SBLKlc, and an erased non-source-side neighbor sub-block SBLK2c in accordance with aspects of the present disclosure;

[0029] FIG. 8A ​​An exemplary threshold voltage distribution of a memory cell array is shown when each memory cell stores two bits of data in four physical states, in accordance with aspects of the present disclosure;

[0030] FIG. 8B An example erase operation is depicted, in accordance with aspects of the present disclosure;

[0031] FIG. 8C A flowchart of a process to perform an erase operation in 3D NAND, in accordance with aspects of the present disclosure;

[0032] FIG. 9A-9B An arrangement of sub-blocks of a block can result in erase disturbance in a forbidden erase one sub-block during erasing another sub-block is shown, in accordance with aspects of the present disclosure;

[0033] FIG. 10A-10C Hole generation based on gate induced drain leakage (GIDL) can be prevented during a double side, source side, and drain side erase operation is shown, in accordance with aspects of the present disclosure;

[0034] FIG. 11 When a forbidden or unselected sub-block is strongly forbidden, the erase speed of a selected sub-block is reduced, while there is less erase disturbance on the unselected or forbidden sub-block, and when a forbidden or unselected sub-block is weakly forbidden, the erase speed of a selected sub-block is improved, while there is more or worse erase disturbance on the unselected or forbidden sub-block is shown, in accordance with aspects of the present disclosure;

[0035] FIG. 12 An erase disturbance of an unselected sub-block during a double side erase operation at both high and low temperatures is shown, in accordance with aspects of the present disclosure;

[0036] FIG. 13A And FIG. 13B An erase top tail during a double side erase and source side erase operation at both high and low temperatures to show a comparison of erase speed of a selected sub-block is shown, in accordance with aspects of the present disclosure;

[0037] FIG. 14A A plot of word line inhibit voltage at various temperatures of negligible erase disturbance of an example memory device is shown, in accordance with aspects of the present disclosure;

[0038] FIG. 14B A table stored in a memory cell is shown, in accordance with aspects of the present disclosure, the table configured to store one or more factors for determining a word line inhibit voltage based on an ambient temperature;

[0039] FIG. 15 Steps of a method of operating a memory device are shown, in accordance with aspects of the present disclosure; and

[0040] FIG. 16Simulation results of a memory device that selects a word line inhibit voltage based on ambient temperature are shown in accordance with aspects of the disclosure. DETAILED DESCRIPTION

[0041] In the following description, details are set forth to provide an understanding of the disclosure. In some instances, certain circuitry, structures, and techniques have not been described in detail or have been omitted so as not to obscure the disclosure.

[0042] In general, the present disclosure relates to non-volatile memory devices of the type that are well suited for many applications. The non-volatile memory devices and associated methods of operation of the present disclosure will be described in connection with one or more example embodiments. However, the specific example embodiments disclosed are merely exemplary of the disclosure and are not intended to limit the concepts, features, advantages, and objects of the present disclosure. Specifically, example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. Those skilled in the art will recognize that the specific details are not required in order to practice the present disclosure and that example embodiments can be practiced with a variety of different specific details. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail in order to avoid obscuring the present disclosure.

[0043] In some memory devices or apparatuses, memory cells are joined to one another, such as in NAND strings in a block or sub-block. Each NAND string includes a plurality of memory cells connected in series between one or more drain-side SG transistors (SGD transistors) located on a drain side of the NAND string connected to a bit line and one or more source-side SG transistors (SGS transistors) located on a source side of the NAND string connected to a source line. In addition, the memory cells can be arranged with a common control gate line (e.g., word line) that serves as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells can be connected in other types of strings, and can also be connected in other ways.

[0044] In 3D memory structures, memory cells can be arranged in vertical strings in a stack, where the stack includes alternating conductive layers and dielectric layers. The conductive layers serve as word lines connected to the memory cells. The memory cells can include data memory cells that are eligible to store user data, and dummy memory cells or non-data memory cells that are not eligible to store user data.

[0045] Each memory cell can be associated with a data state in accordance with write data in a program command. Based on the data state of that memory cell, the memory cell will remain in an erased state or be programmed to a programmed data state. For example, in a one-bit-per-cell memory device, there are two data states, including an erased state and a programmed state. In a two-bit-per-cell memory device, there are four data states, including an erased state and three higher data states, referred to as A, B, and C data states (see FIG. 8A ). In a three-bit-per-cell memory device, there are eight data states, including an erased state and seven higher data states, referred to as A, B, C, D, E, F, and G data states. In a four-bit-per-cell memory device, there are sixteen data states, including an erased state and fifteen higher data states.

[0046] Prior to programming certain non-volatile memory devices, the memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gate of an erased memory cell. Alternatively, the erase operation removes electrons from the charge-trapping layer. A memory cell that has not been erased is typically prohibited from being erased.

[0047] When sub-blocks are arranged vertically in a stack (e.g., one or more sub-blocks are arranged vertically on top of another sub-block), erasing one sub-block can cause erase disturb in another sub-block that is prohibited from being erased. Moreover, during an erase operation, the holes necessary to erase one sub-block (e.g., GIDL-based hole generation or holes provided by PWELL, rather than GIDL-based hole generation) can be blocked by a prohibited-erase sub-block. As a result, when the prohibited or unselected sub-blocks are strongly prohibited, the erase speed of the selected sub-block (the sub-block being erased) is reduced; however, there is typically less erase disturb on the unselected or prohibited sub-blocks. In contrast, when the prohibited or unselected sub-blocks are weakly prohibited, the erase speed of the selected sub-block (the sub-block being erased) is improved, while there is more or worse erase disturb on the unselected or prohibited sub-blocks. These effects can also be influenced by the temperature of the memory cells.

[0048] The technology disclosed herein can be applied to 3D NAND, but is not necessarily limited thereto. A NAND flash memory structure can arrange a plurality of transistors in series between two select gates. The series of transistors and select gates can be referred to as a NAND string. FIG. 1A is a top view showing one NAND string. FIG. 1B is its equivalent circuit. FIG. 1A and FIG. 1BThe depicted NAND string includes four transistors 100, 102, 104, 106 in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to a bit line 126. Select gate 122 connects the NAND string to a source line 128. Select gate 120 is controlled by applying an appropriate voltage to control gate 120CG. Select gate 122 is controlled by applying an appropriate voltage to control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. Transistor 100 has a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. Transistor 104 includes a control gate 104CG and a floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WLl, and control gate 106CG is connected to word line WLO. In one embodiment, transistors 100, 102, 104, and 106 are each a memory cell. In other embodiments, a memory cell can include multiple transistors or can be different than depicted. Select gate 120 is connected to select line SGD. Select gate 122 is connected to select line SGS.

[0049] FIG. 2 A cross-sectional view of one embodiment of the above-described NAND string is provided. FIG. 2A 2D NAND string formed in a substrate. The transistors of the NAND string are formed in a p-well region 140. The p-well region in turn can be within an n-well region 142 of a p-type substrate 144. Each transistor includes a stacked gate structure consisting of a control gate (100CG, 102CG, 104CG, and 106CG) and a floating gate (100FG, 102FG, 104FG, and 106FG). The floating gate is formed on the surface of the p-well on top of an oxide or other dielectric film. The control gate is above the floating gate, with a polysilicon interlayer separating the control gate and the floating gate. The control gates of the memory cells (100, 102, 104, and 106) form a word line. N+ doped layers 130, 132, 134, 136, and 138 are shared between adjacent cells, whereby the cells are connected in series to each other to form a NAND string. These N+ doped layers form the source and drain of each cell. For example, N+ doped layer 130 serves as the drain of transistor 122 and the source of transistor 106, N+ doped layer 132 serves as the drain of transistor 106 and the source of transistor 104, N+ doped layer 134 serves as the drain of transistor 104 and the source of transistor 102, N+ doped layer 136 serves as the drain of transistor 102 and the source of transistor 100, and N+ doped layer 138 serves as the drain of transistor 100 and the source of transistor 120. N+ doped layer 126 is connected to a bit line of the NAND string, while N+ doped layer 128 is connected to a common source line of a plurality of NAND strings.

[0050] Note that although FIG. 1A-2 Four memory cells in a NAND string are shown, but the use of four transistors is provided as an example only. NAND strings used with the techniques described herein can have fewer than four memory cells or more than four memory cells. For example, some NAND strings will include 8, 16, 32, 64, or more memory cells.

[0051] Each memory cell can store data represented in analog or digital form. When storing one bit of digital data, the range of possible threshold voltages of the memory cell can be divided into two ranges, which are assigned the logical data "1" and "0". In one example of a NAND type flash memory, the voltage threshold can be negative after the memory cell is erased and is defined as a logical "1". After a program operation, the threshold voltage is positive and is defined as a logical "0". When the threshold voltage is negative and a read is attempted by applying 0V to the control gate, the memory cell will turn on to indicate that a logical one is being stored. When the threshold voltage is positive and a read operation is attempted by applying 0V to the control gate, the memory cell will not turn on, which indicates that a logical zero is stored.

[0052] Memory cells can also store multiple states, storing multiple bits of digital data. When multiple data states are stored, the threshold voltage window is divided into multiple states. For example, if four states are used, there will be four threshold voltage ranges assigned to data values "11", "10", "01", and "00". In one example of NAND type memory, the threshold voltage after an erase operation is negative and is defined as "11". Positive threshold voltages are used for the "10", "01", and "00" states. In some implementations, a Gray code assignment is used to assign data values (e.g., logical states) to threshold voltage ranges such that if the threshold voltage of a floating gate is erroneously shifted to its adjacent physical state, only one bit will be affected. The specific relationship between data programmed into a memory cell and the threshold voltage range of the memory cell depends on the data encoding scheme employed by the memory cell.

[0053] In addition to NAND flash memory, other types of non-volatile memory can also be used with the present technology.

[0054] Another type of memory cell, for example, that can be used in a flash EEPROM system utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above the memory cell channel. This cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. The stored charge then changes the threshold voltage of the portion of the channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A split gate configuration can provide a similar cell, where a doped polysilicon gate extends over part of the memory cell channel to form a separate select transistor.

[0055] In another approach, two bits are stored in each NROM cell, with the ONO dielectric extending over the channel between the source and drain diffusions. Charges for one data bit are positioned in the dielectric adjacent to the drain, and charges for the other data bit are positioned in the dielectric adjacent to the source. Multi-state data storage is obtained by reading the binary states of the spatially separate charge storage regions within the dielectric.

[0056] FIG. 3 A block BLK0 in the memory is depicted as including a number of memory cells, such as FIG. 1A-2Three example NAND strings are shown. BLKO includes a plurality of NAND strings NSO, NSl, NS2,... and respective bit lines, e.g., BLO, BLl, BL2,... BLKO includes a set of non-volatile storage elements. Each NAND string is connected at one end to a select gate drain (SGD) transistor, and the control gates of the SGD transistors are connected via a common SGD line. The NAND strings are connected at their other end to a select gate source (SGS) transistor, which in turn is connected to a common source line (SL). A plurality of word lines WLO-WL63 extend between the SGS transistors and the SGD transistors. WLO is an edge word line adjacent to the source side (SS) of the block, and WL63 is an edge word line adjacent to the drain side (DS) of the block.

[0057] Example NAND string NSO includes storage elements 301,..., 302-306,..., 307 having respective control gates CG63,... CG32-CG28,... CGO, and includes SGS transistor 308 having control gate CGsgs and SGD transistor 300 having control gate CGsgd. Another example NAND string NSl includes storage elements 311,..., 312-316,..., 317, SGS transistor 318, and SGD transistor 310. Another example NAND string NS2 includes storage elements 321,..., 322-326,..., 327, SGS transistor 328, and SGD transistor 320. NAND strings NSO, NS2,... are even, and NAND strings NSl, NS3 (not shown),... are odd. Similarly, bit lines BLO, BL2,... are even, and NAND strings BLl, BL3 (not shown),... are odd. The storage elements can store user data and / or non-user data.

[0058] FIG. 4 is an array 400 of NAND flash memory cells including FIG. 3 BLKO and additional blocks BLKl and BLK2. Along each column, a bit line (BL) is coupled to the drain terminals of the drain select gates of the NAND strings. Along each row of NAND strings, a source line (SL) can connect (e.g., at SEO of NSO) all of the source terminals of the source select gates of the NAND strings.

[0059] The array of storage elements is divided into a number of blocks (e.g., BLK0-BLK2) of storage elements, where each block includes a set of one or more NAND strings in communication with a common set of word lines, SGS lines, and SGD lines. Each NAND string is also in communication with a respective bit line. For example, BLK0 includes NAND strings NS0, NS1,..., which are in communication with BL0, BL1,..., BLn-1, respectively, and with WL0-WL63, SGS, and SGD. BLK1 includes NAND strings NSa0, NSa1,..., NSan-1, which are in communication with BL0, BL1,..., BLn-1, respectively, and with WL0a-WL63a, SGSa, and SGDa. BLK2 includes NAND strings NSb0, NSb1,..., NSbn-1, which are in communication with BL0, BL1,..., BLn-1, respectively, and with WL0b-WL63b, SGSb, and SGDb.

[0060] It is common for flash EEPROM systems that a block is the erase unit. That is, each block contains the minimum number of storage elements that are erased together. Each block is typically divided into a number of pages. A page is the minimum unit of programming. Data for one or more pages is typically stored in a row of storage elements. For example, a row typically contains several interleaved pages, or it can constitute one page. All storage elements of a page are read or programmed together. In addition, a page can store user data from one or more sectors. A sector is a logical concept used by the host as a convenient unit of user data; it typically does not contain overhead data that is specific to the controller. Overhead data can include error correction codes (ECCs) that have been computed from the user data of a sector. A portion of the controller (described below) computes the ECCs when data is programmed into the array, and also checks it when data is read from the array. Alternatively, the ECCs and / or other overhead data are stored in a different page or even a different block than the user data to which they belong.

[0061] A sector of user data is typically 512 bytes, corresponding to the size of a sector in a disk drive. Overhead data is typically an additional 16 to 20 bytes. A number of pages form a block, from 8 pages, for example, up to 32 pages, 64 pages, or more. In some embodiments, a row of NAND strings includes a block.

[0062] In one embodiment, memory cells are erased by raising the p-well to an erase voltage (e.g., 15V to 20V) for a sufficient period of time and grounding or applying a low bias (e.g., 1V) to the word lines of the selected block while the source lines and bit lines are floating. Due to capacitive cross-coupling (“cross” denotes coupling from adjacent storage elements), the bit lines, select lines, and common source are also raised to a significant portion of the erase voltage. Thus, a strong electric field is applied to the tunnel oxide layer of the selected memory cells, and as electrons from the floating gate are emitted to the substrate side, the data of the selected memory cells is erased. As the electrons transfer from the floating gate to the p-well region, the threshold voltage of the selected cells is lowered. Erasing can be performed on the entire memory array, individual blocks, or another unit of cells. In one embodiment, 3D NAND is erased using a different technique. 3D NAND is discussed further below.

[0063] FIG. 5A is a block diagram depicting one embodiment of a sense block 500. A single sense block 500 is divided into a core portion (referred to as a sense module 580) and a common portion 590. In one embodiment, there is a separate sense module 580 for each bit line and one common portion 590 for a group of multiple sense modules 580. In one example, a sense block 500 will include one common portion 590 and eight sense modules 580. Each sense module in the group will communicate with the associated common portion via a data bus 572.

[0064] A sense module 580 includes sense circuitry 571 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. The sense module 580 also includes a bit line latch 582 that is used to set the voltage condition on the connected bit line. For example, a predetermined state in the latch in the bit line latch 582 will cause the connected bit line to be pulled to a state that designates program inhibit (e.g., 1.5V to 3V). As an example, flag = 0 can inhibit programming, while flag = 1 does not inhibit programming.

[0065] The common portion 590 includes a processor 592, three sets of example data latches 594, and an I / O interface 598 coupled between the three sets of data latches 594 and the data bus 521. One set of data latches can be provided for each sense module, and each set can be provided with data latches identified by DL1, DL2, and DL3. The use of data latches is discussed further below.

[0066] The processor 592 performs computations. For example, one of its functions is to determine the data stored in the sensed storage elements and store the determined data in the set of data latches. At least some of the set of data latches (e.g., 594) are used to store data bits determined by the processor 592 during a read operation. At least some of the set of data latches are also used to store data bits imported from the data bus 521 during a program operation. The imported data bits represent write data intended to be programmed into the memory. The I / O interface 598 provides an interface between the data latches 594-697 and the data bus 521

[0067] In one embodiment, at the start of a program operation, data is stored in DL1 and DL2 latches. For example, lower page data can be stored in DL1 and upper page data can be stored in DL2. In one embodiment, lower page data read from a memory cell during an IDL is stored in the DL1 latch. DL3 can be used to store a verify status, such as a lockout status during programming. For example, when the Vt of a memory cell has been verified to its target level, the DL3 latch can be set to indicate the target level so that further programming of the memory cell can be inhibited. Note that this describes programming of two bits per memory cell. In one embodiment, during a read operation, the DL1 and DL2 latches are used to store the two bits read from a memory cell. Note that there can be more than two bits per memory cell. There can be one additional latch per additional bit to be stored per memory cell.

[0068] During a read or other sense operation, the state machine 512 controls the application of different control gate voltages to the addressed storage elements. As it steps through the various control gate voltages corresponding to the various memory states supported by the memory, the sense module 580 can trip at one of these voltages and output a digit line signal via bus 572 from the sense module 580 to the processor 592. At this point the processor 592 determines the resulting memory state by considering the sense module's trip event and information about the control gate voltage being applied from the state machine via input line 593. It then calculates the binary encoding for the memory state and stores the resulting data bits into the data latches (e.g., 594). In another embodiment of the core portion, the bit line latches 582 serve as latches for latching the output of the sense module 580 as well as bit line latches as described above.

[0069] Some implementations can include multiple processors 592. In one embodiment, each processor 592 will include an output line (not depicted) so that each output line is wired or wired together. In some embodiments, the output line is inverted before being connected to the line or line. This configuration enables a quick determination of when the programming process is complete during the program verify process because the receiving line or state machine can determine when all programmed bits have reached the desired level. For example, when each bit reaches its required level, the logical zero for that bit will be sent to the line or line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sense modules, the state machine needs to read the line or line eight times, or add logic to the processor 592 to accumulate the results of the associated bit lines so that the state machine only needs to read the line or line once. Similarly, by properly selecting the logic levels, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0070] During programming or verification, the data to be programmed is stored in the data latch sets 594-597 from the data bus 521. Under the control of the state machine, the programming operation includes a series of programming voltage pulses applied to the control gate of the addressed storage elements. Each programming pulse is followed by a read back (verify) to determine if the storage elements have been programmed to the desired memory state. The processor 592 monitors the read back memory state relative to the desired memory state. When the two are in agreement, the processor 592 sets the bit line latch 582 so as to cause the bit line to be pulled to a state that specifies program inhibit. This inhibits the storage elements coupled to the bit line from further programming even if a programming pulse appears at their control gate. In other embodiments, the processor initially loads the bit line latch 582 and the sense circuitry sets it to the inhibit value during the verify process.

[0071] In one embodiment, each set of data latches stacks 594-597 contains a stack of data latches corresponding to the sense module 580. In one embodiment, each sense module 580 has three data latches. All of the DL1 and DL2 data latches corresponding to a read / write block of storage elements can be connected together to form a block shift register so that a block of data can be input or output by serial transfer.

[0072] In one embodiment, one purpose of the DL1 and DL2 latches is to store the data to be programmed into the storage elements. For example, the storage elements can store two bits for each storage element. In one embodiment, the lower page data is initially stored into the DL1 latches and the upper page data is initially stored into the DL2 latches.

[0073] In one embodiment, the storage elements store three bits per storage element. In this case, there can be an additional data latch (not depicted in FIG. 5A ) for initially storing the third data bit to be programmed into the storage element. In one embodiment, the storage elements store four bits per storage element, where there can be two additional data latches (not depicted in FIG. 5A ) for initially storing the third and fourth data bits to be programmed into the storage element. The storage elements can store more than four bits per storage element, in which case there can be one data latch per bit.

[0074] Additional information regarding read operations and sense amplifiers can be found in (1) U.S. Patent No. 7,196,931, "Non-Volatile Memory and Method with Reduced Source Line Bias Errors"; (2) U.S. Patent No. 7,023,736, "Non-Volatile Memory and Method with Improved Sensing"; (3) U.S. Patent No. 7,046,568, "Memory Sensing Circuit and Method for Low Voltage Operation"; (4) U.S. Patent No. 7,196,928, "Compensating for Coupling during Read Operations of Non-Volatile Memory"; and (5) U.S. Patent No. 7,327,619, "Reference Sense Amplifier for Non-Volatile Memory". All five of the immediately above-listed patent documents are incorporated herein by reference in their entirety.

[0075] FIG. 5B is comprised of FIG. 4FIG. 1 illustrates a block diagram of a non-volatile memory system of an array 400. The memory array 400 can include a 2D architecture or a 3D architecture. One example of a 3D architecture is a BiCS architecture. A 3D architecture can include 3D vertical NAND strings. The memory cells in a 3D vertical NAND string can include an ONO layer for storing information. This information can be stored in a charge-trapping layer, such as but not limited to SiN. Note that an ONO layer can be used to store information for 2D and 2D NAND as well as other architectures. Thus, a floating gate can be used to store information, but is not required.

[0076] According to one embodiment of the present technology, a non-volatile memory system includes a memory device 596 having read / write circuits for reading and programming pages of memory cells in parallel. The memory device 596 includes one or more memory dies 598. The memory die 598 includes a two-dimensional array of memory cells 400, a control circuit 510, and read / write circuits 565. The memory array 400 is addressable by word lines via a row decoder 530 and by bit lines via a column decoder 560. The read / write circuits 565 include a plurality of sense blocks 500 and allow a page of memory cells to be read or programmed in parallel. Typically, a controller 550 is included in the same memory device 596 (e.g., removable memory card) as the one or more memory dies 598. Commands and data are transferred between the host 570 and the controller 550 via lines 520 and between the controller and the one or more memory dies 598 via lines 518.

[0077] The control circuit 510 cooperates with the read / write circuits 565 to perform memory operations on the memory array 400. The control circuit 510 includes a state machine 512, memory 513, an on-chip address decoder 514, a temperature measurement circuit 515, and a power control module 516. The state machine 512 provides chip-level control of memory operations. The memory 513 can store raw write data, modified write data, and status bits for use by the state machine 512. The on-chip address decoder 514 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by the decoders 530 and 560. The temperature measurement circuit 515 can be used to record an ambient temperature of the memory device 596 periodically to provide a temperature history that can also be stored in the memory 513, for example. An example implementation uses a temperature sensitive band gap current. The power control module 516 controls the power and voltages supplied to the word lines and bit lines during memory operations. In another approach, a dual row / column decoder and read / write circuits are used. The control circuit can be viewed as including one or more of the components 510, 512, 513, 514, 515, 516, 530, 550, 560, 565, for example.

[0078] FIG. 6A depictedFIG. 3 An example cross-sectional view of a portion of a block. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (or word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers (or word lines) WLD1, WLD2, WLD3, and WLD4. The dielectric layers are labeled DL0 to DL19. Furthermore, regions comprising NAND strings NS1 and NS2 are depicted within the stack. Each NAND string encompasses a memory via 618 or 619, which is filled with material forming memory cells adjacent to the word lines.

[0079] The stack 610 includes a substrate 611, an insulating film 612 on the substrate, and a portion of a source line SL. SL1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack. Metal-filled slots 617 and 620 may be provided periodically across the stack as interconnects extending through the stack, such as to connect the source line to a line above the stack. The slots may be used during word line formation and subsequently filled with metal. A portion of a bit line BL0 is also depicted. A conductive via 621 connects the drain terminal 615 to BL0.

[0080] In one method, a block of memory cells comprises a stack of alternating control gates and dielectric layers, and the memory cells are arranged in vertically extending memory vias within the stack.

[0081] FIG. 6B Depicting FIG. 6A A graph showing the diameter of memory holes / pillars in a stack. The vertical axis is parallel to... FIG. 6A The stack alignment is shown, and the width (wMH), such as diameter, of the pillars formed by the material in memory holes 618 and 619 is depicted. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25 to 30 is common. The memory holes may have a circular cross-section. Due to the etching process, the width of the memory holes and the resulting pillars can vary along the length of the holes. Typically, the diameter gradually decreases from the top to the bottom of the memory hole. FIG. 6B (Solid lines in the diagram). That is, the memory aperture is tapered, narrowing at the bottom of the stack. In some cases, there is a slight narrowing at the top of the aperture near the select gate, causing the diameter of the memory aperture to widen slightly before gradually decreasing from its top to its bottom (long dashed lines). For example, in this example, the memory aperture width is largest at level WL9 in the stack. The memory aperture width is slightly smaller at level WL10 and gradually decreases from level WL8 to WL0.

[0082] Due to the non-uniformity of the diameters of the memory holes and the resulting pillars, the programming and erasing speeds of the memory cells can vary based on their position along the memory hole. With a relatively small diameter at the bottom of the memory hole, the electric field across the tunnel oxide is relatively strong, resulting in higher programming and erasing speeds for memory cells in word lines adjacent to the relatively small diameter portion of the memory hole.

[0083] In another possible implementation, indicated by the short dashed line, the stack is fabricated as two layers (also...). FIG. 9A and FIG. 9B (As shown in the diagram). The lower or bottom layer is formed first with corresponding memory holes. Then, the top or upper layer is formed with corresponding memory holes that align with the memory holes in the bottom layer. Each memory hole is tapered, forming a double-tapered memory hole, in which the width increases, then decreases and increases again, moving from the bottom to the top of the stack.

[0084] FIG. 7A An example of a fully programmed block BLK0 is depicted. In this example, block BLK0 (corresponding to...) FIG. 3 and FIG. 4 The NAND string NS0 has 64 word lines (WL0 to WL63), and each of them is programmed. A programmed word line can be defined as a word line in which at least a specified number of memory elements are programmed. The example NAND string NS0 includes one memory element for each word line, including memory elements 700, ..., 714 in WL0, ..., WL63 respectively.

[0085] FIG. 7B An example of a partially programmed block BLKa is depicted, which has a programmed source-side adjacent sub-block SBLK0a and an erased non-source-side adjacent sub-block SBLK1a. The sub-block can be an appropriate subset of the block. Therefore, a sub-block can include a subset of multiple word lines of the block. In one approach, the sub-block includes contiguous (adjacent) word lines. In another approach, the sub-block includes non-contiguous (non-adjacent) word lines. For example, the sub-block can include an odd number of word lines instead of an even number, or an even number of word lines instead of an odd number. A source-side adjacent sub-block can be a sub-block adjacent to the source-side SS (SBLK0a) of the block. FIG. 3 Adjacent sub-blocks, for example, can extend from WL0 to the source and drain sides of the block (DS). FIG. 3 The word lines between ) . Alternatively, the source-side adjacent sub-blocks may only include WL0, for example, such as FIG. 7B As depicted. In this example, the programmed subblock SBLK0a includes WL0 as the programmed word line, and the erased subblock SBLK1a includes WL1 through WL63 as the erased word lines. Generally, partially programmed blocks have some but not all of the programmed word lines.

[0086] Example storage elements 700, 702,..., 714 of NS0 are in WL0, WL1,..., WL63, respectively.

[0087] Non-source-side-adjacent subset SBLKla includes non-volatile storage elements 714 adjacent the drain side of the block.

[0088] FIG. 7C Another example of a partially programmed block BLKb is depicted, having a programmed source-side-adjacent sub-block SBLKOb and an erased non-source-side-adjacent sub-block SBLKlb. In this example, SBLKOb includes WL0 through WL5 as programmed word lines, and SBLKlb includes WL6 through WL63 as erased word lines.

[0089] Example storage elements 700,..., 706, 708,..., 714 of a NAND string are in WL0,... WL5, WL6,..., WL63, respectively.

[0090] FIG. 7D Another example of a partially programmed block BLKc is depicted, having a programmed source-side-adjacent sub-block SBLK0c, a programmed non-source-side-adjacent sub-block SBLKlc, and an erased non-source-side-adjacent sub-block SBLK2c.

[0091] In this example, the first programmed sub-block (which is a source-side-adjacent sub-block) SBLK0c includes WL0 as a programmed word line, the second programmed sub-block (which is not a source-side-adjacent sub-block) SBLKlc includes WL1 through WL31 as programmed word lines, and the erased drain-side-adjacent sub-block (which is not a source-side-adjacent sub-block) SBLK2c includes WL32 through WL63 as erased word lines. SBLKlc is a non-source-side-adjacent sub-block and a non-drain-side-adjacent sub-block. SBLKlc is thus intermediate the source-side-adjacent sub-blocks and the drain-side-adjacent sub-blocks. The drain-side-adjacent sub-blocks can be sub-blocks adjacent the drain side DS of the block, e.g., the sub-blocks can extend from WL63 to a word line located between the source side and the drain side of the block, or the drain-side-adjacent sub-blocks can include only WL63 (or other drain-side edge word line), e.g. FIG. 3 ) of the block, or the drain-side-adjacent sub-blocks can include only WL63 (or other drain-side edge word line), e.g.

[0092] Example storage elements 700, 702,..., 710, 712,..., 714 of a NAND string are in WL0, WL1,... WL31, WL32,..., WL63, respectively.

[0093] While FIG. 7A-7DEach of the examples in FIG. 8A shows a programmed sub-block on the source side and an erased sub-block on the drain side, but it should be understood that there is no such constraint during sub-block operation. Any sub-block can be independently erased and programmed at any time. Thus, for example, there can be a scenario where source side-adjacent sub-blocks or word lines are erased and drain side sub-blocks (i.e., non-source side-adjacent sub-blocks) are programmed.

[0094] After a successful program operation, the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells. FIG. 8A An exemplary threshold voltage distribution for a memory cell array is shown when each memory cell stores two bits of data in four physical states. Distribution 800 represents a distribution of threshold voltages for cells in an erased state (storing "11"), which can have negative threshold voltage levels. Distribution 802 represents a distribution of threshold voltages for cells in a first programmed state ("A"), storing "10". Distribution 804 represents a distribution of threshold voltages for cells in a second programmed state ("B"), storing "00". Distribution 806 represents a distribution of threshold voltages for cells in a third programmed state ("C"), storing "01".

[0095] When programming the memory cells, they can be verified using verify reference levels Vva, Vvb, and Vvc, which verify the A to C states, respectively. When reading the memory cells, a read reference level Vra can be used to determine whether the memory cell is in the A state distribution or higher. Likewise, Vrb and Vrc are read reference levels for the B and C states, respectively.

[0096] Note that when the memory cells are initially erased, they can be erased using an erase verify level Vev, resulting in an initial erase distribution 801. Later programming of other states can cause the upper tail of the erase distribution to shift. Some of the final erase distribution 800 can be above the A state read level (higher than Vth).

[0097] Of course, if the memory is operated in more than four physical states, there will be multiple threshold voltage distributions equal to the number of states within the defined voltage threshold window of the memory cells. Further, although a particular bit pattern has been assigned to each of the distributions or physical states, different bit patterns can be assigned.

[0098] In one embodiment, memory cells are erased by raising the p-well to an erase voltage (e.g., 20 volts) and grounding or applying 0 volts to the word lines of the selected block while the source lines and bit lines are floating. Due to capacitive coupling, the unselected word lines (e.g., those in the unselected, non-erasing block), bit lines, select lines, and common source lines also rise to a high positive potential (e.g., 20V). As a result, a strong electric field is applied to the tunnel oxide layer of the memory cells of the selected block, and as electrons of the floating gates are emitted to the substrate, the data of the selected memory cells is erased. Erasing refers to reducing the threshold voltage of a memory cell by transferring electrons out of its charge storage region (e.g., floating gate or charge trapping layer). For devices with floating gates, as enough electrons are transferred from the floating gate to the p-well region, the threshold voltage of the selected cell becomes negative. Once the threshold voltage reaches a predetermined sufficiently low value, the memory cell can be considered erased, and the erase process is considered complete or successful. Thus, erasing a memory cell refers to reducing the threshold voltage of the memory cell, and does not imply its complete or successful erasure. Erasing can be performed on the entire memory array, one or more blocks of the array, or another unit of cells. The erase voltage signal Vsense is typically applied as a series of erase voltage pulses, with an erase verify operation performed between each pulse. If the cells of the unit being erased are not verified as erased after an erase voltage pulse is applied, another erase voltage pulse can be applied to the p-well region. In some embodiments, the peak value of the erase voltage is increased for each subsequent pulse (e.g., from 16V to 20V in increments of 1V).

[0099] FIG. 8B An example erase operation is depicted. Steps include: initialize Verase, 870; apply erase pulse, 872; perform erase verify test, 874; pass erase verify test?, 876; Verase < Verase_max?, 878; increment Verase, 880; erase operation successful end, 882; and erase operation failed, 884. In one approach, Verase is the voltage level applied to the substrate of a block to pull electrons out of the floating gates of the storage elements, thereby reducing the Vth of the storage elements. Performing an erase verify test can include applying a voltage Vev to multiple word lines in the block at the same time. The erase verify test can be performed at the same time for storage elements associated with all bit lines, even bit lines, or odd bit lines.

[0100] At decision step 876, if the sensed storage elements have reached an erased state (e.g., their Vth is below Vev such that the sensed storage elements and their corresponding NAND strings are in a conductive state), then the erase verify test is passed.

[0101] If decision step 876 is true, the erase operation successfully ends (step 882). If decision step 876 is false, Verase is incremented and additional erase pulses are applied if Verase has not reached a maximum level Verase max. If decision step 876 is false and Verase has exceeded the maximum level (e.g., decision step 878 is false), the erase operation fails at step 884.

[0102] In one embodiment, in a 2D NAND memory device, the p-well substrate is biased at a high voltage to erase the storage elements. Note that the NAND strings are typically formed in the substrate such that by applying an erase voltage to the substrate while, for example, grounding the control gates, the memory cells can be erased.

[0103] One method of erasing in a 3D stacked non-volatile memory device is to generate gate-induced drain leakage (GIDL) current to charge the channel, raise the channel potential to the erase voltage, and maintain this channel potential during the erase. In one method, the memory device includes a NAND string having a drain-side select gate (SGD) transistor at one end and a source-side select gate (SGS) transistor at the other end.

[0104] FIG. 8C is a flowchart of one embodiment of a process to perform an erase operation in a 3D NAND. Generally, the erase operation can include multiple erase verify iterations that are performed until a verify condition is met, at which time the erase operation ends. Optionally, one or more additional erase voltages can be applied after passing verification. In one method, the memory device includes a NAND string having a drain-side select gate (SGD) transistor at one end and a source-side select gate (SGS) transistor at the other end (see FIG. 3 ). The erase can be a "single-side erase" or a "double-side erase." When an erase voltage is applied to the bit line in a single-side erase or to the bit line and source line in a double-side erase, the select gate transistor generates a sufficient amount of gate-induced drain leakage (GIDL) current to charge the floating body (channel) of the NAND string. The GIDL increases in proportion to the drain-to-gate voltage (Vdg) of the select gate transistor.

[0105] Step 816 sets the state = erase for the storage elements on the selected NAND string that are in the selected block.

[0106] Step 818 sets the state = inhibit for the storage elements in the unselected blocks.

[0107] Step 821 initializes the erase voltage (Verase) to a starting value.

[0108] Step 822 charges the channels of the 3D NAND string by applying an erase voltage to the string, setting the state = erase for each memory element's control gate voltage to facilitate erasing, and floating or setting the state = inhibit for each memory element's control gate voltage to prevent erasing. For example, a control gate voltage at a relatively high level (e.g., 10V to 15V) prevents erasing by creating a small potential difference across the tunneling layer.

[0109] A control gate voltage equal to or slightly above, for example, 0V facilitates erasing by creating a large potential difference across the tunneling layer between the channel and the control gate, which facilitates further tunneling.

[0110] Step 823 performs an erase verify test on the memory elements in the selected block (on the selected NAND string). The erase verify test can be performed simultaneously on different memory elements on the string. For example, this can involve applying a common erase verify control gate voltage (Vv erase) to the control gate of each memory element in the selected block while detecting the current through the string.

[0111] If the current of the string is above a reference current (indicating that the string is conducting), then the erase verify test passes.

[0112] If the selected NAND string passes the erase verify test, then step 824 sets the state = inhibit. If the selected NAND string fails the erase verify test, then the erase state = erase is continued.

[0113] Decision step 826 determines whether Verase is at Verase max. If the answer is "yes," then the erase operation is unsuccessfully ended at step 827. If the answer is "no," then Verase is incrementally increased at step 828, and another iteration is performed at step 822.

[0114] As previously mentioned, when sub-blocks are arranged to have abutting (adjacent) word lines such that the sub-blocks are arranged vertically in a stack (e.g., one or more sub-blocks are arranged on top of another sub-block), such as described in FIG. 7B Erasing one sub-block can cause erase disturb in another sub-block that is inhibited from erasing. For example, in FIG. 9AIn the case of the first sub-block SB0 associated with the lower tier of the stack (i.e., the first sub-block SB0 is a source side neighbor sub-block) is disposed below the second sub-block SB1 associated with the upper tier of the stack (i.e., the second sub-block SB1 is a drain side neighbor sub-block). During an erase operation of the first sub-block SB0, an erase voltage VERA is applied to the substrate or channel of the block. At the same time, the word lines corresponding to the first sub-block SB0 (the selected one of the first block SB0 and the second block SB1) have a word line erase voltage VERA WL LI (e.g., 0.5 volts) applied to them to facilitate erasure of the memory cells connected to the word lines corresponding to the first sub-block SB0. At the same time, the word lines corresponding to the second sub-block SB1 (the unselected one of the first block SB0 and the second block SB1) have a word line inhibit voltage UERA SBM SB1 applied to them to prevent erasure of the memory cells connected to the word lines corresponding to the second sub-block SB1. However, during the erase operation, the second sub-block SB1 experiences erase disturb. Similarly, during an erase operation of the second sub-block SB1 in FIG. 9B In the case of the first sub-block SB0 associated with the lower tier of the stack (i.e., the first sub-block SB0 is a source side neighbor sub-block) is disposed below the second sub-block SB1 associated with the upper tier of the stack (i.e., the second sub-block SB1 is a drain side neighbor sub-block). During an erase operation of the first sub-block SB0, an erase voltage VERA is applied to the substrate or channel of the block. At the same time, the word lines corresponding to the first sub-block SB0 (the selected one of the first block SB0 and the second block SB1) have a word line erase voltage VERA WL LI (e.g., 0.5 volts) applied to them to facilitate erasure of the memory cells connected to the word lines corresponding to the first sub-block SB0. At the same time, the word lines corresponding to the second sub-block SB1 (the unselected one of the first block SB0 and the second block SB1) have a word line inhibit voltage UERA SBM SB1 applied to them to prevent erasure of the memory cells connected to the word lines corresponding to the second sub-block SB1. However, during the erase operation, the second sub-block SB1 experiences erase disturb. Similarly, during an erase operation of the second sub-block SB1 in FIG. 9A In the case of the first sub-block SB0 associated with the lower tier of the stack (i.e., the first sub-block SB0 is a source side neighbor sub-block) is disposed below the second sub-block SB1 associated with the upper tier of the stack (i.e., the second sub-block SB1 is a drain side neighbor sub-block). During an erase operation of the first sub-block SB0, an erase voltage VERA is applied to the substrate or channel of the block. At the same time, the word lines corresponding to the first sub-block SB0 (the selected one of the first block SB0 and the second block SB1) have a word line erase voltage VERA WL LI (e.g., 0.5 volts) applied to them to facilitate erasure of the memory cells connected to the word lines corresponding to the first sub-block SB0. At the same time, the word lines corresponding to the second sub-block SB1 (the unselected one of the first block SB0 and the second block SB1) have a word line inhibit voltage UERA SBM SB1 applied to them to prevent erasure of the memory cells connected to the word lines corresponding to the second sub-block SB1. However, during the erase operation, the second sub-block SB1 experiences erase disturb. Similarly, during an erase operation of the second sub-block SB1 in FIG. 9B In the case of the first sub-block SB0 associated with the lower tier of the stack (i.e., the first sub-block SB0 is a source side neighbor sub-block) is disposed below the second sub-block SB1 associated with the upper tier of the stack (i.e., the second sub-block SB1 is a drain side neighbor sub-block). During an erase operation of the first sub-block SB0, an erase voltage VERA is applied to the substrate or channel of the block. At the same time, the word lines corresponding to the first sub-block SB0 (the selected one of the first block SB0 and the second block SB1) have a word line erase voltage VERA WL LI (e.g., 0.5 volts) applied to them to facilitate erasure of the memory cells connected to the word lines corresponding to the first sub-block SB0. At the same time, the word lines corresponding to the second sub-block SB1 (the unselected one of the first block SB0 and the second block SB1) have a word line inhibit voltage UERA SBM SB1 applied to them to prevent erasure of the memory cells connected to the word lines corresponding to the second sub-block SB1. However, during the erase operation, the second sub-block SB1 experiences erase disturb. Similarly, during an erase operation of the second sub-block SB1 in

[0115] Reference is made to FIG. 10A When the erase operation is a "double side erase," for both the case where the first sub-block SB0 is erased and the second sub-block SB1 is inhibited from erasure, and the case where the second sub-block SB1 is erased and the first sub-block SB0 is strongly inhibited from erasure (i.e., the word line inhibit voltage UERA SBM SB1 applied on the word lines corresponding to the first sub-block SB0 is a higher related voltage, or closer to the erase voltage), gate induced drain leakage (GIDL) based hole generation is prevented. As FIG. 10BAs shown, when the erase operation is a source-side erase operation and the first sub-block SB0 is a source-side neighboring sub-block, the hole generation required to erase the first sub-block SB0 is not prevented by the strong inhibition of the second sub-block SB1. However, when the erase operation is a source-side erase operation and the second sub-block SB1 is a drain-side neighboring sub-block, the hole generation required to erase the second sub-block SB1 is prevented by the strong inhibition of the first sub-block SB0. Similarly, as shown in FIG. 10C the erase operation is a drain-side erase operation and the second sub-block SB1 is a drain-side neighboring sub-block, the hole generation required to erase the second sub-block SB1 is not prevented by the strong inhibition of the first sub-block SB0. However, when the erase operation is a drain-side erase operation and the first sub-block SB0 is a source-side neighboring sub-block, the hole generation required to erase the first sub-block SB0 is prevented by the strong inhibition of the second sub-block SB1. In other words, there are scenarios (those enclosed by the dashed lines shown) in which the inhibited sub-block is in the path of hole transport. FIG. 10A-10C

[0116] Thus, as shown in FIG. 11 the best case, when the inhibited or unselected sub-block is strongly inhibited (i.e., the word line inhibition voltage UERA_SBM_SB1 applied on the word line corresponding to the first sub-block SB0 is a relatively high voltage), the erase speed of the selected sub-block (the sub-block being erased) is reduced, while there is less erase disturbance on the unselected or inhibited sub-block. In contrast, still referring to FIG. 11 , when the inhibited or unselected sub-block is weakly inhibited (i.e., the word line inhibition voltage UERA_SBM_SB1 applied on the word line corresponding to the first sub-block SB0 is a lower relative voltage), the erase speed of the selected sub-block (the sub-block being erased) is improved, while there is more or worse erase disturbance on the unselected or inhibited sub-block. Thus, it is desirable to find the optimal word line inhibition voltage to reduce the erase disturbance of the unselected or inhibited sub-block, while not degrading the erase speed of the selected sub-block.

[0117] FIG. 12 erase disturbance of the unselected sub-blocks during a double-side erase operation at both high temperature (HT) and low temperature (LT) is shown. More specifically, the word line inhibition voltage used is the erase voltage VERA minus 6.8 volts, and the threshold voltage Vt distribution of the memory cells of the first sub-block SB0 (shown in the lower portion of FIG. 12 ) and the second sub-block SB1 (shown in the upper portion of FIG. 12 ​The threshold voltage Vt of the memory cells (shown in the upper part) is illustrated at high temperatures (e.g., 85 degrees Celsius) and low temperatures (e.g., -30 degrees Celsius). As shown, at high temperatures, as the second subblock SB1 undergoes an increasing number of erase operation cycles, the programming state of the memory cells in the first subblock SB0 shifts toward the erase state (i.e., experiences erase interference). However, at low temperatures, as the second subblock SB1 undergoes an increasing number of erase operation cycles, the programming state of the memory cells in the first subblock SB0 does not shift significantly. Therefore, even a weaker inhibit bias applied to the word line associated with the first subblock SB0 (e.g., the word line inhibit voltage used is the erase voltage VERA minus 6.8 volts) causes significant erase interference on the first subblock SB0 at high temperatures. From these results, it can be concluded that erase interference is highly temperature-dependent, and the erase interference experienced by inhibited or unselected subblocks (e.g., the first subblock SB0) is more severe at high temperatures than at low temperatures.

[0118] FIG. 13A and FIG. 13B A comparison of the threshold voltage Vt distribution of memory cells in a sub-block that is in an erased state with a relatively high threshold voltage is shown to illustrate a two-sided erase operation of a selected sub-block (e.g., the first sub-block SB1) at both high and low temperatures. FIG. 13A ) and source-side erase operation ( FIG. 13B The erase speed during the erase operation. More specifically, without using a word line disable voltage (i.e., no disable) for the unselected sub-block, the average threshold voltage Vt of the memory cells in the selected sub-block after the erase operation is plotted against various erase voltages VERA. The word line disable voltage used is equal to the erase voltage VERA of the unselected sub-block, and the word line disable voltage used is the erase voltage VERA of the unselected sub-block minus 6.8 volts. The average threshold voltage Vt of the memory cells in the selected sub-block after the erase operation is... FIG. 13A and FIG. 13B The left side is shown as being for high temperatures (e.g., 85 degrees Celsius) and... FIG. 13A and FIG. 13B The right side is shown for low temperatures (e.g., -30 degrees Celsius). As shown, for double-sided erasure at high temperatures (…),… FIG. 13A ) and source-side erase operation ( FIG. 13B), the average threshold voltage Vt of the memory cells of the selected sub-block does not change significantly after an erase operation at each word line inhibit voltage (no inhibit, word line inhibit voltage = VERA, and word line inhibit voltage = VERA - 6.8v). In contrast, there is a significant change in the average threshold voltage Vt of the memory cells of the selected sub-block after an erase operation when the word line inhibit voltage = VERA compared to no inhibit or word line inhibit voltage = VERA - 6.8V. In more detail, at low temperatures, for both a double-sided erase operation ( FIG. 13A ) and a source-side erase operation ( FIG. 13B ), the average threshold voltage Vt of the memory cells of the selected sub-block is higher after an erase operation. This increase in the average threshold voltage Vt of the memory cells of the selected sub-block after an erase operation indicates a slower erase speed. Thus, for a double-sided erase operation, for example, the erase of the second sub-block SB1 is slowed when the first sub-block SB0 word line is strongly inhibited (word line inhibit voltage = VERA); however, the erase speed of the second sub-block SB1 is comparable to the full block erase speed (e.g., the entire block including both the first sub-block SB0 and the second sub-block SB1) when the first sub-block SB0 word line is more weakly inhibited (word line inhibit voltage = VERA - 6.8v). Thus, strong inhibition of the unselected sub-block (e.g., word line inhibit voltage = VERA) only significantly impacts the erase speed at low temperatures.

[0119] Accordingly, there is provided an improved memory device (e.g., the memory device 596 in FIG. 3 ) including a block (e.g., BLK0 in FIG. 5B ) having storage elements or memory cells (e.g., storage elements 301,..., 302-306,..., 307 in FIG. 3 ) connected to word lines (e.g., WL0 to WL63 in FIG. 3 ) and arranged into strings (e.g., strings NS0, NS1,..., NSn-1 in FIG. 3 ). The block is divided into a first sub-block SB0 and a second sub-block SB1 (see, e.g., FIG. 9A-9B ), each sub-block configured to be erased as a whole in an erase operation. The device also includes a temperature measurement circuit 515 (see, e.g., FIG. 5B). In addition, the apparatus includes control circuitry (e.g., components 510, 512, 513, 514, 515, 516, 530, 550, 560, 565) coupled to the word lines and strings and the temperature measurement circuit 515. The control circuitry is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuitry is also configured to apply an erase voltage to each string while applying a word line erase voltage to the word lines associated with a selected one of the first sub-block SB0 and the second sub-block SB0 to facilitate erasing of the memory cells and applying a word line inhibit voltage to the word lines associated with a non-selected one of the first sub-block SB0 and the second sub-block SB0 to prevent erasing of the memory cells in the erase operation. In more detail, the word line inhibit voltage is selected based on the ambient temperature to minimize erase disturb effects experienced by the memory cells in the non-selected one of the first sub-block and the second sub-block and to optimize the speed of the erase operation of the memory cells in the selected one of the first sub-block SB0 and the second sub-block SB1. According to an aspect, the word line erase voltage is approximately 0.5 volts and the erase voltage is in a range of approximately 16 volts to approximately 22 volts. While the apparatus is discussed as including only two sub-blocks SB0, SB1, it should be understood that the apparatus can alternatively include more than two sub-blocks (i.e., the operations of the apparatus and methods discussed herein are scalable to “n” sub-blocks).

[0120] Referring back to FIG. 6A and FIG. 6B and as discussed above, the word lines overlap one another in the stack and each string includes a memory hole that extends vertically through the stack. The memory hole has a plurality of layers including a lower layer and an upper layer that are vertically aligned with one another in the stack. Thus, according to an aspect, the lower layer includes a first sub-block SB0 of memory cells and the upper layer includes a second sub-block SB1 of memory cells. However, other arrangements of the word lines and layers are contemplated, including stacks having more than two layers.

[0121] As discussed above, the erase operation can be a “single-sided erase” or a “double-sided erase”. Thus, the erase operation is selectable from a group consisting of a double-sided erase operation, a source side erase operation, and a drain side erase operation. Likewise, each string is coupled to a bit line on a drain side of each string and a source line on a source side of each string (e.g., FIG. 6Asource line during the source side erase operation. For example, when the erase voltage is applied to the source line, GIDL-based hole generation is initiated under the SGS region, and the holes will be transported into the channel and raise the channel potential to the erase voltage level. Further, the control circuit is configured to apply the erase voltage to both the bit line and the source line of each string associated with the selected one of the first sub-block SB0 and the second sub-block SB1 during the double side erase operation. In each type of erase operation, it is advantageous to select the word line inhibit voltage based on the ambient temperature to minimize the erase disturb effects experienced by the memory cells of the unselected one of the first sub-block and the second sub-block, and to optimize the speed of the erase operation of the memory cells of the selected one of the first sub-block and the second sub-block.

[0122] Accordingly, the control circuit is further configured to utilize the first word line inhibit voltage as the word line inhibit voltage in response to the temperature measurement circuit detecting that the ambient temperature is a high temperature (e.g., 85 degrees Celsius). The control circuit is further configured to utilize the second word line inhibit voltage as the word line inhibit voltage in response to the temperature measurement circuit detecting that the ambient temperature is a low temperature (e.g., -30 degrees Celsius) that is lower than the high temperature. According to an aspect, the second word line inhibit voltage is less than the first word line inhibit voltage. Thus, for example, by applying a stronger or higher word line inhibit voltage (e.g., VERA) on the unselected sub-block at a high temperature (e.g., 85 degrees Celsius), thereby reducing the erase disturb on the unselected sub-block without reducing the erase speed. In addition, by applying a weaker or lower word line inhibit voltage (e.g., VERA - 6.8 volts) on the unselected sub-block at a low temperature (e.g., -30 degrees Celsius), thereby eliminating the erase speed reduction on the unselected sub-block while there is only negligible erase disturb on the unselected sub-block.

[0123] FIG. 14A A plot of word line inhibit voltage at various temperatures for negligible erase disturb for an example memory device is shown. As FIG. 14B As best shown, the device can also include a table 1400 stored in the memory cells. The table 1400 is configured to store one or more factors used by the control circuit to determine the word line inhibit voltage based on the ambient temperature. FIG. 14B The rightmost column of the table defines FIG. 14A the slope of the plot / line as shown. For example, such a slope can be selected prior to manufacturing the memory device (no slope or a slope of zero would indicate that any temperature compensation of the word line inhibit voltage is disabled).

[0124] Referring now to FIG. 15 A method of operating a memory device is also provided. As described above, the memory device includes a block having memory cells connected to word lines and arranged in strings. The block is divided into a first sub-block SBO and a second sub-block SBl that are each configured to be erased as a whole under an erase operation. The memory device includes a temperature measurement circuit 515 configured to detect an ambient temperature of the memory device. Accordingly, the method includes a step 1500 of determining a word line inhibit voltage based on the ambient temperature. The method continues with a step 1502 of applying an erase voltage to each string while applying a word line erase voltage to word lines associated with a selected one of the first sub-block SBO and the second sub-block SBO to facilitate erasure of the memory cells and applying a word line inhibit voltage to word lines associated with a non-selected one of the first sub-block SBO and the second sub-block SBO to prevent erasure of the memory cells in the erase operation. Again, the word line inhibit voltage is selected to minimize erase disturb effects experienced by the memory cells of the non-selected one of the first sub-block SBO and the second sub-block SBl and to optimize a speed of the erase operation of the memory cells of the selected one of the first sub-block SBO and the second sub-block SBl.

[0125] As discussed, the word lines of the memory device can overlap one another in a stack and each string includes a memory hole extending vertically through the stack. Each string can also have a plurality of tiers including a lower tier and an upper tier vertically aligned with one another in the stack. For example, the lower tier can include the first sub-block SBO of memory cells and the upper tier can include the second sub-block SBl of memory cells. Additionally, the erase operation can be selected from a group consisting of a double-sided erase operation, a source-side erase operation, and a drain-side erase operation and each string is coupled to a bit line on a drain side of each string and a source line on a source side of each string. Accordingly, the method also includes a step of applying the erase voltage to the bit line of each string associated with a selected one of the first sub-block SBO and the second sub-block SBl during a drain-side erase operation. The method can also include a step of applying the erase voltage to the source line of each string associated with the selected one of the first sub-block SBO and the second sub-block SBl during a source-side erase operation. Additionally, the method can include a step of applying the erase voltage to both the bit line and the source line of each string associated with the selected one of the first sub-block SBO and the second sub-block SBl during a double-sided erase operation.

[0126] The method may further include the step of using a first word line disable voltage as a word line disable voltage in response to the temperature measuring circuit 515 detecting that the ambient temperature is high (e.g., 85 degrees Celsius). Additionally, the method may include the step of using a second word line disable voltage as a word line disable voltage in response to the temperature measuring circuit 515 detecting that the ambient temperature is low (e.g., -30 degrees Celsius). The second word line disable voltage may be less than the first word line disable voltage. As discussed above, Table ( FIG. 14B This can be stored in a memory cell. The table can be configured to store one or more factors used to determine the word line disable voltage based on ambient temperature.

[0127] FIG. 16 Simulation results for a memory device with a word line disable voltage selected based on ambient temperature are shown. Specifically, at both high (e.g., 85 degrees Celsius) and low (e.g., -30 degrees Celsius) temperatures, unselected sub-blocks experience significantly less erase interference during erase operations. The first sub-block SB0 is shown as disabled using a word line disable voltage, which is... FIG. 16 The erase voltage VERA on the left or the erase voltage VERA minus 6.8 volts (i.e., SB0 victim). Similarly, the second sub-block SB1 is shown as being disabled using a word line disable voltage, which is FIG. 16 The erase voltage VERA on the right or the erase voltage VERA minus 6.8 volts (i.e., SB1victim). First sub-block SB0 (in FIG. 16 The threshold voltage Vt distribution of the memory cell (shown in the lower part) and the second sub-block SB1 (in FIG. 16 The threshold voltage Vt distribution of the memory cells (shown in the upper part) confirms that negligible erase interference can be achieved by using a disable bias or word line disable voltage based on ambient temperature. Therefore, the memory device and method described herein minimize the erase interference effects experienced by memory cells in either the first subblock SB0 or ​​the second subblock SB1, and optimize the speed of erase operations on memory cells in either the first subblock SB0 or ​​the second subblock SB1.

[0128] Obviously, changes may be made to what is described and shown herein without departing from the scope defined in the appended claims. The foregoing description of embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or limiting of this disclosure. Various elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable where applicable and can be used in selected embodiments, even if not specifically shown or described. The same applies to many other aspects. Such variations should not be considered as departing from this disclosure, and all such modifications are intended to be included within the scope of this disclosure.

[0129] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" can be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having," are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order

[0130] When an element or layer is referred to as being "on," "engaged to," "connected to," or "coupled to" another element or layer, it can be directly on, engaged, connected, or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0131] Although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms, when used herein do not necessarily connote a sequential or chronological order, unless explicitly stated otherwise. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

[0132] For purposes of the description hereinafter, spatial terms, such as “inner,” “outer,” “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like can be used with reference to a device's features or elements as illustrated in the figures. Unless otherwise indicated, spatial terms are intended to refer to the device as it is oriented in a viewing direction of the figures. For example, if the device in the figures were turned over, a component described as “below” or “beneath” other components would then be oriented “above” the other components. Thus, the example term “below” can encompass both an above and below orientation. The device can be oriented in other ways (rotated 90 degrees, or at other orientations) and spatially relative terms used herein are interpreted accordingly.

Claims

1. An apparatus comprising: a block comprising memory cells connected to word lines and arranged in strings, the block divided into first and second sub-blocks each configured to be erased as a whole in an erase operation, wherein the word lines overlap one another in a stack, and each of the strings comprises a memory hole extending vertically through the stack and having a plurality of layers, the plurality of layers comprising a lower layer and an upper layer vertically aligned with one another in the stack, and the lower layer comprises the first sub-block of the memory cells and the upper layer comprises the second sub-block of the memory cells, and the erase operation is selected from the group consisting of a double-sided erase operation, a source-side erase operation, and a drain-side erase operation, and each of the strings is coupled to a bit line on a drain side of each of the strings and a source line on a source side of each of the strings; a temperature measurement circuit configured to detect an ambient temperature of the apparatus; and a control circuit coupled to the word lines and the strings and the temperature measurement circuit and configured to: determine a word line inhibit voltage based on the ambient temperature, apply an erase voltage to each of the strings while applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to facilitate erasure of the memory cells in the erase operation and applying the word line inhibit voltage to the word lines associated with a non-selected one of the first and second sub-blocks to prevent erasure of the memory cells in the erase operation; apply the erase voltage to the bit lines of each of the strings associated with the selected one of the first and second sub-blocks during the drain-side erase operation, apply the erase voltage to the source lines of each of the strings associated with the selected one of the first and second sub-blocks during the source-side erase operation, and apply the erase voltage to both the bit lines and the source lines of each of the strings associated with the selected one of the first and second sub-blocks during the double-sided erase operation.

2. The apparatus of claim 1, wherein the control circuit is further configured to: utilize a first word line inhibit voltage as the word line inhibit voltage in response to the temperature measurement circuit detecting that the ambient temperature is a high temperature, and utilize a second word line inhibit voltage as the word line inhibit voltage in response to the temperature measurement circuit detecting that the ambient temperature is a low temperature less than the high temperature, wherein the second word line inhibit voltage is less than the first word line inhibit voltage.

3. The apparatus of claim 1, further comprising a table stored in the memory cells, the table configured to store one or more factors used by the control circuit to determine the word line inhibit voltage based on the ambient temperature. ​ 4. The apparatus of claim 1, wherein the word line inhibit voltage is selected to minimize erase disturb effects experienced by the memory cells of the unselected one of the first sub-block and the second sub-block and to optimize speed of the erase operation of the memory cells of the selected one of the first sub-block and the second sub-block.

5. The apparatus of claim 1, wherein the word line erase voltage is 0.5 volts and the erase voltage is in a range of 16 volts to 22 volts.

6. A controller in communication with a memory device, the memory device comprising a block, the block comprising memory cells connected to word lines and arranged in strings, the block divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation, the controller in communication with a temperature measurement circuit configured to detect an ambient temperature of the memory device, the word lines overlapping one another in a stack, and each of the strings comprising a memory hole extending vertically through the stack and having a plurality of layers, the plurality of layers comprising a lower layer and an upper layer vertically aligned with one another in the stack, and the lower layer comprising the first sub-block of the memory cells and the upper layer comprising the second sub-block of the memory cells, the erase operation selected from a group consisting of a double-sided erase operation, a source-side erase operation, and a drain-side erase operation, and each of the strings coupled to a bit line on a drain side of each of the strings and a source line on a source side of each of the strings, the controller configured to: determine a word line inhibit voltage based on the ambient temperature; instruct the memory device to apply an erase voltage to each of the strings while applying a word line erase voltage to the word lines associated with a selected one of the first sub-block and the second sub-block to facilitate erasure of the memory cells in the erase operation and applying the word line inhibit voltage to the word lines associated with an unselected one of the first sub-block and the second sub-block to prevent erasure of the memory cells in the erase operation; instruct the memory device to apply the erase voltage to the bit lines of each of the strings associated with the selected one of the first sub-block and the second sub-block during the drain-side erase operation; instruct the memory device to apply the erase voltage to the source lines of each of the strings associated with the selected one of the first sub-block and the second sub-block during the source-side erase operation; and instruct the memory device to apply the erase voltage to both the bit lines and the source lines of each of the strings associated with the selected one of the first sub-block and the second sub-block during the double-sided erase operation.

7. The controller of claim 6, wherein the controller is further configured to: utilize a first word line inhibit voltage as the word line inhibit voltage in response to the temperature measurement circuit detecting that the ambient temperature is a high temperature; and utilize a second word line inhibit voltage as the word line inhibit voltage in response to the temperature measurement circuit detecting that the ambient temperature is a low temperature. in response to the temperature measurement circuit detecting that the ambient temperature is a low temperature that is less than the high temperature, utilizing a second word line inhibit voltage as the word line inhibit voltage, wherein the second word line inhibit voltage is less than the first word line inhibit voltage.

8. The controller of claim 6, wherein the memory device further comprises a table stored in the memory cells, the table configured to store one or more factors used by the controller to determine the word line inhibit voltage based on the ambient temperature.

9. The controller of claim 6, wherein the word line inhibit voltage is selected to minimize erase disturb effects experienced by the memory cells of the unselected one of the first sub-block and the second sub-block, and to optimize speed of the erase operation for the memory cells of the selected one of the first sub-block and the second sub-block.

10. The controller of claim 6, wherein the word line erase voltage is 0.5 volts, and the erase voltage is in a range of 16 volts to 22 volts.

11. A method of operating a memory device comprising a block, the block comprising memory cells connected to word lines and arranged into strings, the block divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation, the memory device comprising a temperature measurement circuit configured to detect an ambient temperature of the memory device, the word lines overlapping one another in a stack, and each of the strings comprising a memory hole extending vertically through the stack and having a plurality of layers, the plurality of layers comprising a lower layer and an upper layer vertically aligned with one another in the stack, and the lower layer comprising the first sub-block of the memory cells and the upper layer comprising the second sub-block of the memory cells, the erase operation selected from a group consisting of a double-sided erase operation, a source-side erase operation, and a drain-side erase operation, and each of the strings coupled to a bit line on a drain side of each of the strings and a source line on a source side of each of the strings, the method comprising the steps of: determining a word line inhibit voltage based on the ambient temperature; applying an erase voltage to each of the strings while applying a word line erase voltage to the word lines associated with a selected one of the first sub-block and the second sub-block to facilitate erasing of the memory cells, and the word line inhibit voltage to the word lines associated with an unselected one of the first sub-block and the second sub-block to prevent erasing of the memory cells in the erase operation; during the drain-side erase operation, applying the erase voltage to the bit lines of each of the strings associated with the selected one of the first sub-block and the second sub-block; during the source-side erase operation, applying the erase voltage to the source lines of each of the strings associated with the selected one of the first sub-block and the second sub-block; and ​ During the double-sided erase operation, the erase voltage is applied to both the bit lines and the source lines of each of the strings associated with the selected one of the first sub-block and the second sub-block.

12. The method of claim 11, wherein the method further comprises the steps of: in response to the temperature measurement circuit detecting that the ambient temperature is a high temperature, utilizing a first word line inhibit voltage as the word line inhibit voltage; and in response to the temperature measurement circuit detecting that the ambient temperature is a low temperature that is less than the high temperature, utilizing a second word line inhibit voltage as the word line inhibit voltage, wherein the second word line inhibit voltage is less than the first word line inhibit voltage.

13. The method of claim 11, the method further comprising a table stored in the memory unit, the table configured to store one or more factors for determining the word line inhibit voltage based on the ambient temperature.

14. The method of claim 11, wherein the word line inhibit voltage is selected to minimize an erase disturb effect experienced by the memory cells of the non-selected one of the first sub-block and the second sub-block, and to optimize a speed of the erase operation of the memory cells of the selected one of the first sub-block and the second sub-block.

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