Transistor gate structure and method of forming the same

Abstract

The present application relates to transistor gate structures and methods of forming the same. In one embodiment, a device includes a first nanostructure; a second nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric including a dielectric material; and a gate electrode including a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric material of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 atomic percent metal; and a fill layer on the work function tuning layer.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically to transistor gate structures and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a transistor gate structure is provided, the transistor gate structure comprising: a first nanostructure; a second nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric comprising a dielectric material; and a gate electrode comprising: a work function tuning layer on the gate dielectric, the work function tuning layer comprising a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric material of the gate dielectric completely filling the region between the first nanostructure and the second nanostructure, the pure work function metal having a metal composition of greater than 95% atomic percentage; and a filling layer on the work function tuning layer.

[0005] According to another aspect of this disclosure, a transistor gate structure is provided, the transistor gate structure comprising: a channel region on a substrate; a gate dielectric layer on the channel region; a work function metal on the gate dielectric layer, the work function metal having a first concentration of impurities, the impurities including quasi-metals or non-metals; an adhered metal on the work function metal, the adhered metal having a second concentration of impurities, the second concentration being greater than the first concentration; and a filler metal on the adhered metal, the filler metal being different from the work function metal, the filler metal having a third concentration of impurities, the second concentration being greater than the third concentration.

[0006] According to another aspect of this disclosure, a method for forming a transistor gate structure is provided, the method comprising: forming a first nanostructure and a second nanostructure on a substrate; forming a gate dielectric layer having a first portion surrounding the first nanostructure and a second portion surrounding the second nanostructure; depositing a pure work function metal on the gate dielectric layer, the pure work function metal extending continuously between the first portion and the second portion of the gate dielectric layer; and depositing a pure filler metal on the pure work function metal. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanostructured FET) is shown in a three-dimensional view according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A and Figure 19B This is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0010] Figure 20A , Figure 20B , Figure 21A and Figure 21BThis is a view of a nanostructured FET according to some other embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover devices in use or operation in orientations other than those shown in the accompanying drawings. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0013] According to various embodiments, the transistor gate structure forms an active function tuning layer, which is formed of one or more pure work function metals. This pure work function metal(s) can be deposited using one of several deposition processes, and optionally a purification process can be performed to increase the purity of the metal in the work function tuning layer. Devices having a work function tuning layer formed of one or more pure work function metals have a work function close to the bandgap edge of the metal(s), thereby allowing for a lower threshold voltage of the device. Furthermore, the work function tuning layer formed of one or more pure work function metals has low resistance. Device performance can therefore be improved.

[0014] Embodiments of dies incorporating nanostructured FETs (field effect transistors) have been described in a specific context. However, various embodiments may be applied to dies incorporating other types of transistors (e.g., fin field effect transistors, planar transistors, etc.) instead of or in combination with nanostructured FETs.

[0015] Figure 1Examples of nanostructured FETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments are shown. Figure 1 This is a 3D view, in which some features of the nanostructure FET are omitted for clarity. Nanostructure FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), etc.

[0016] The nanostructured FET includes nanostructures 66 (e.g., nanosheets, nanowires, etc.) on a substrate 50 (e.g., a semiconductor substrate) above fins 62, wherein the nanostructures 66 serve as channel regions for the nanostructured FET. The nanostructures 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 70 (e.g., shallow trench isolation (STI) regions) are disposed between adjacent fins 62, and the fins 62 may protrude above the isolation regions 70 between adjacent isolation regions 70. Although the isolation regions 70 are described / illustrated as independent of the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fins 62 is illustrated as a single continuous material with respect to the substrate 50, the bottom portion of the fins 62 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 62 refers to the portion extending above the isolation regions 70 between adjacent isolation regions 70.

[0017] Gate dielectric 122 is located above the top surface of fin 62 and along the top, sidewalls, and bottom surface of nanostructure 66. Gate electrode 124 is located above gate dielectric 122. Epitaxial source / drain regions 98 are disposed on fin 62, on opposite sides of gate dielectric 122 and gate electrode 124. These epitaxial source / drain regions 98 can be shared between fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, for example, by joining these epitaxial source / drain regions 98 through epitaxial growth, or by coupling these epitaxial source / drain regions 98 to the same source / drain contact.

[0018] Figure 1Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 124 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 98 of the nanostructure FET. Cross section B-B' is along the longitudinal axis of the nanostructure 66 and in a direction, for example, the current flow direction between the epitaxial source / drain regions 98 of the nanostructure FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 98 of the nanostructure FET. These reference cross sections are referenced in subsequent figures for clarity.

[0019] Some of the embodiments discussed herein are discussed in the context of forming nanostructured FETs using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices (e.g., planar FETs) or in fin field-effect transistors (FinFETs). For example, a FinFET may include fins on a substrate, where these fins serve as the channel region of the FinFET. Similarly, a planar FET may include a substrate, where a portion of the substrate serves as the channel region of the planar FET.

[0020] Figures 2 to 19B This is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 It is a 3D view, showing the relationship with Figure 1 A similar 3D view. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A It shows Figure 1 The reference section A-A' shown is different in that it shows two fins. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B and Figure 19B It shows Figure 1 The reference section B-B' is shown in the figure. Figure 9C and Figure 9D It shows Figure 1 The reference section C-C' shown is different in that it shows two fins.

[0021] exist Figure 2 The diagram provides a substrate 50 for forming a nanostructured FET. The substrate 50 can be a semiconductor substrate (e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc.), which can be doped (e.g., doped with p-type or n-type impurities) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0022] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices such as N-type metal-oxide-semiconductor (NMOS) transistors, for example, n-type nanostructure FETs, and the p-type region 50P can be used to form p-type devices such as P-type metal-oxide-semiconductor (PMOS) transistors, for example, p-type nanostructure FETs. The n-type region 50N can be physically independent of the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0023] The substrate 50 can be lightly doped with p-type or n-type impurities. Anti-punch-through (APT) implantation can be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, impurities can be implanted into the substrate 50. The conductivity type of the impurity can be opposite to the conductivity type of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region can extend below the source / drain regions in the nanostructured FET. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region can be approximately 10. 18 cm -3 To about 10 19 cm -3 Within the range.

[0024] A multilayer stack 52 is formed on the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. Each semiconductor material can be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three first semiconductor layers 54 and three second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56.

[0025] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 is removed, and the second semiconductor layer 56 is patterned to form channel regions for a nanostructured FET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity (compared to etching the second semiconductor layer 56), such as silicon-germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0026] In another embodiment (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for a nanostructured FET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 will be patterned to form a channel region for a nanostructured FET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si). x Ge 1-xThe second semiconductor material of the second semiconductor layer 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. The first and second semiconductor materials can have high etch selectivity relative to each other, such that the first semiconductor layer 54 can be removed without removing the second semiconductor layer 56 in the n-type region 50N, and the second semiconductor layer 56 can be removed without removing the first semiconductor layer 54 in the p-type region 50P.

[0027] Each layer of the multilayer stack 52 can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE) and deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each layer can have a small thickness, for example, in the range of about 5 nm to about 30 nm. In some embodiments, some layers (e.g., the second semiconductor layer 56) are formed to be thinner than other layers (e.g., the first semiconductor layer 54). For example, in an embodiment where the first semiconductor layer 54 is a sacrificial layer (or dummy layer) and the second semiconductor layer 56 is patterned to form the channel region for a nanostructured FET in an n-type region 50N and a p-type region 50P, the first semiconductor layer 54 can have a first thickness T1 and the second semiconductor layer 56 can have a second thickness T2, wherein the second thickness T2 is about 30% to about 60% smaller than the first thickness T1. Forming the second semiconductor layer 56 to a smaller thickness allows the channel region to be formed at a greater density.

[0028] exist Figure 3 In this process, trenches are patterned in substrate 50 and multilayer stack 52 to form fins 62, a first nanostructure 64, and a second nanostructure 66. Fins 62 are semiconductor strips patterned in substrate 50. The first nanostructure 64 and the second nanostructure 66 comprise the remainder of the first semiconductor layer 54 and the remainder of the second semiconductor layer 56, respectively. The trenches can be patterned using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0029] Fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, fins 62 and nanostructures 64, 66 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have smaller spacing, for example, than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can subsequently be used as masks to pattern fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on nanostructures 64, 66.

[0030] The widths of fins 62 and nanostructures 64, 66 can each range from about 8 nm to about 40 nm. In the illustrated embodiment, fins 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, fins 62 and nanostructures 64, 66 in one region (e.g., n-type region 50N) are wider or narrower than those in another region (e.g., p-type region 50P).

[0031] exist Figure 4 In this embodiment, STI regions 70 are formed on substrate 50 and between adjacent fins 62. The STI regions 70 are arranged to surround at least a portion of the fins 62, such that at least a portion of the nanostructures 64, 66 protrudes from between adjacent STI regions 70. In the illustrated embodiment, the top surface of the STI region 70 is coplanar with the top surface of the fin 62 (within process variations). In some embodiments, the top surface of the STI region 70 is higher or lower than the top surface of the fin 62. The STI regions 70 separate features of adjacent devices.

[0032] The STI regions 70 can be formed by any suitable method. For example, an insulating material can be formed on the substrate 50 and the nanostructures 64, 66 and between adjacent fins 62. The insulating material can be an oxide, such as silicon oxide, a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by a chemical vapor deposition (CVD) process (e.g., high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof). Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66. Although the individual STI regions 70 are illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64, 66. Subsequently, a filler material, such as those previously described, can be formed on top of the lining.

[0033] Then, a removal process is applied to the insulating material to remove excess insulating material on the nanostructures 64, 66. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back processes, combinations thereof, can be used. In embodiments where the mask remains on the nanostructures 64, 66, the planarization process can expose or remove the mask. After the planarization process, the top surface of the insulating material is coplanar with the top surface of the mask (if present) or the nanostructures 64, 66 (within the range of process variations). Thus, the top surface of the mask (if present) or the nanostructures 64, 66 is exposed through the insulating material. In the illustrated embodiment, no mask is retained on the nanostructures 64, 66. The insulating material is then recessed to form the STI region 70. The insulating material is recessed such that at least a portion of the nanostructures 64, 66 protrudes between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 70 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI region 70 can be formed into a flat, convex, and / or concave shape through appropriate etching. Acceptable etching processes can be used to recess the insulating material, such as material-selective etching processes for the insulating material (e.g., selectively etching the STI region 70 at a faster rate than etching the material for fins 62 and nanostructures 64, 66). For example, oxide removal can be performed using diluted hydrofluoric acid (dHF).

[0034] The processes described above are merely one example of how the fins 62 and nanostructures 64, 66 can be formed. In some embodiments, the fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64, 66. The epitaxial structure may include the alternating semiconductor materials described previously, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing the epitaxial structure, the material to be epitaxially grown can be in-situ doped during growth, which can avoid prior and / or subsequent implantation; however, in-situ doping and implantation doping can also be used together.

[0035] Furthermore, suitable wells (not shown separately) may be formed in the substrate 50, fins 62, and / or nanostructures 64, 66. The conductivity type of the well may be opposite to the conductivity type of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well may be formed in the n-type region 50N, and an n-type well may be formed in the p-type region 50P. In some embodiments, either a p-type well or an n-type well may be formed in both the n-type region 50N and the p-type region 50P.

[0036] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using a mask such as a photoresist (not shown separately). For example, a photoresist can be formed over the fins 62, nanostructures 64, 66, and STI region 70 in the n-type region 50N. The photoresist can be patterned to expose the p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted in the region at a concentration of about 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0037] After or before implantation into the p-type region 50P, a mask, such as a photoresist (not shown separately), is formed over the fins 62, nanostructures 64, 66, and STI region 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurity implantation into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region, at a concentration of approximately 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0038] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments of epitaxial growth of fins 62 and / or nanostructures 64, 66, the grown material can be in-situ doped during growth, which avoids implantation; however, in-situ doping and implantation doping can also be used together.

[0039] exist Figure 5In this process, a dummy dielectric layer 72 is formed on fins 62 and nanostructures 64 and 66. The dummy dielectric layer 72 can be formed from dielectric materials such as silicon oxide, silicon nitride, or combinations thereof, which can be deposited or thermally grown using acceptable techniques. A dummy gate layer 74 is formed on the dummy dielectric layer 72, and a mask layer 76 is formed on the dummy gate layer 74. The dummy gate layer 74 can be deposited on the dummy dielectric layer 72 and then planarized, for example, by CMP. The mask layer 76 can be deposited on the dummy gate layer 74. The dummy gate layer 74 can be formed from conductive or non-conductive materials, such as amorphous silicon, polycrystalline silicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline SiGe), metals, metal nitrides, metal silicides, metal oxides, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 74 can be formed of one or more materials with high etch selectivity (compared to etch insulating materials such as STI region 70 and / or dummy dielectric layer 72). The mask layer 76 can be formed of a dielectric material such as silicon nitride or silicon oxynitride. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the fins 62, nanostructures 64, 66, and STI region 70, such that the dummy dielectric layer 72 is over the STI region 70 and extends between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and nanostructures 64, 66.

[0040] exist Figure 6 In this process, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 is then transferred to dummy gate layer 74 using any acceptable etching technique to form dummy gate 84. The pattern of mask 86 may optionally be further transferred to dummy dielectric layer 72 using acceptable etching techniques to form dummy dielectric 82. Dummy gate 84 covers portions of nanostructures 64, 66, which will be exposed in subsequent processing to form channel regions. Specifically, dummy gate 84 extends along portions of nanostructures 66, which will be patterned to form channel regions 68. The pattern of mask 86 can be used to physically separate adjacent dummy gates 84. Furthermore, the longitudinal direction of dummy gate 84 may be substantially perpendicular to the longitudinal direction of fin 62 (within process variations). Mask 86 may optionally be removed after patterning, for example, by acceptable etching techniques.

[0041] Figures 7A to 19B Various additional steps in manufacturing the embodiment device are shown. Figures 7A to 19BFeatures in either the n-type region 50N or the p-type region 50P are shown. For example, the structure shown can be applied to both the n-type region 50N and the p-type region 50P. Differences (if any) in the structure of the n-type region 50N and the p-type region 50P are described in the text corresponding to each figure.

[0042] exist Figure 7A and Figure 7B In this embodiment, gate spacers 90 are formed on nanostructures 64 and 66, on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacers 90 can be formed by conformally depositing one or more dielectric materials and subsequently etching that dielectric material(s). Acceptable dielectric materials include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, each gate spacer 90 includes multiple layers, such as a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layer 90A and the second spacer layer 90B are made of silicon carbonitride (e.g., SiO2). x N y C 1-x-y The first spacer layer 90A may be formed from a silicon carbonitride composition similar to or different from that of the second spacer layer 90B. An acceptable etching process, such as dry etching, wet etching, or a combination thereof, may be performed to pattern the dielectric material(s). The etching may be anisotropic. The dielectric material(s) may have portions remaining on the sidewalls of the dummy gate 84 during etching (thus forming the gate spacer 90). As will be described in more detail later, the dielectric material(s) may also have portions remaining on the sidewalls of the fins 62 and / or nanostructures 64, 66 during etching (thus forming the fin spacer 92, see...). Figure 9C and Figure 9D After etching, the fin spacer 92 / gate spacer 90 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0043] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments for different device types, similar to the implantation previously described for wells, a mask such as a photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist (not shown separately) can be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity described above, and the p-type impurity can be any p-type impurity described above. During implantation, the channel region 68 remains covered by the dummy gate 84, ensuring that the channel region 68 is essentially free of impurities implanted to form the LDD region. The impurity concentration in the LDD region can be approximately 10. 15 cm -3 To about 10 19 cm -3 Within the specified range. Annealing can be used to repair damage to the injected material and activate injected impurities.

[0044] Note that the previous disclosures generally described the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and so on. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0045] exist Figure 8A and Figure 8BIn the illustrated embodiment, source / drain recesses 94 are formed in nanostructures 64, 66. In this embodiment, the source / drain recesses 94 extend through nanostructures 64, 66 and into fin 62. The source / drain recesses 94 may also extend into substrate 50. In various embodiments, the source / drain recesses 94 may extend to the top surface of substrate 50 without etching substrate 50; the fin 62 may be etched such that the bottom surface of the source / drain recesses 94 is arranged below the top surface of STI region 70; and so on. The source / drain recesses 94 can be formed by etching nanostructures 64, 66 using anisotropic etching processes (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc.). During the etching process used to form the source / drain recesses 94, gate spacer 90 and dummy gate 84 jointly mask portions of fin 62 and / or nanostructures 64, 66. A single etching process can be used to etch each of the nanostructures 64 and 66, or multiple etching processes can be used to etch the nanostructures 64 and 66. A time-controlled etching process can be used to stop the etching of the source / drain recess 94 after it has reached the desired depth.

[0046] Optionally, internal spacers 96 are formed on the sidewalls of the remaining portion of the first nanostructure 64 (e.g., those sidewalls exposed by the source / drain recesses 94). As will be described in more detail later, source / drain regions are then formed in the source / drain recesses 94, and the first nanostructure 64 is subsequently replaced by a corresponding gate structure. The internal spacers 96 act as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 96 can be used to substantially prevent subsequent etching processes (e.g., etching processes for the subsequent removal of the first nanostructure 64) from damaging the subsequently formed source / drain regions.

[0047] As an example of forming the internal spacer 96, the source / drain recesses 94 can be extended laterally. Specifically, portions of the sidewalls of the first nanostructure 64 exposed by the source / drain recesses 94 can be recessed. Although the sidewalls of the first nanostructure 64 are illustrated as straight, these sidewalls can be concave or convex. The sidewalls can be recessed by an acceptable etching process, such as an etching process selective for the material of the first nanostructure 64 (e.g., selectively etching the material of the first nanostructure 64 at a faster rate than etching the material of the second nanostructure 66). The etching can be isotropic. For example, when the second nanostructure 66 is formed of silicon and the first nanostructure 64 is formed of silicon-germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process can be a dry etching using a fluorine-based gas (e.g., hydrogen fluoride (HF) gas). In some embodiments, the same etching process can be performed sequentially to form the source / drain recesses 94 and to recess the sidewalls of the first nanostructure 64. The internal spacer 96 can then be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material can be silicon nitride or silicon oxynitride, however any suitable material can be used, such as a low dielectric constant (low-k) material with a k-value less than about 3.5. The insulating material can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. Although the outer sidewalls of the internal spacer 96 are illustrated as flush with the sidewalls of the gate spacer 90, the outer sidewalls of the internal spacer 96 can extend beyond or recess from the sidewalls of the gate spacer 90. In other words, the internal spacer 96 can fill, completely fill, or overfill the sidewall recesses. Furthermore, although the sidewalls of the inner spacer 96 are shown as straight, the sidewalls of the inner spacer 96 may be concave or convex.

[0048] exist Figure 9A and Figure 9BIn this process, epitaxial source / drain regions 98 are formed in the source / drain recesses 94. The epitaxial source / drain regions 98 are formed in the source / drain recesses 94 such that each dummy gate 84 (and its corresponding channel region 68) is arranged between corresponding adjacent pairs of epitaxial source / drain regions 98. In some embodiments, gate spacers 90 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84 by an appropriate lateral distance, and internal spacers 96 are used to separate the epitaxial source / drain regions 98 from the first nanostructure 64 by an appropriate lateral distance, such that the epitaxial source / drain regions 98 are not short-circuited with the gate of the subsequently formed nanostructure FET. The material of the epitaxial source / drain regions 98 can be selected to apply stress in the corresponding channel regions 68, thereby improving performance.

[0049] The epitaxial source / drain region 98 in the n-type region 50N can be formed by masking the p-type region 50P. The epitaxial source / drain region 98 in the n-type region 50N is then epitaxially grown in the source / drain recess 94 in the n-type region 50N. The epitaxial source / drain region 98 can include any acceptable material suitable for an n-type device. For example, the epitaxial source / drain region 98 in the n-type region 50N can include a material that applies tensile strain to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 98 in the n-type region 50N may be referred to as the "n-type source / drain region". The surface of the epitaxial source / drain region 98 in the n-type region 50N may protrude above the surfaces of the corresponding fins 62 and nanostructures 64, 66, and may have small facets.

[0050] The epitaxial source / drain region 98 in the p-type region 50P can be formed by masking the n-type region 50N. The epitaxial source / drain region 98 in the p-type region 50P is then epitaxially grown in the source / drain recess 94 in the p-type region 50P. The epitaxial source / drain region 98 can include any acceptable material suitable for a p-type device. For example, the epitaxial source / drain region 98 in the p-type region 50P can include a material that applies compressive strain to the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 98 in the p-type region 50P may be referred to as the "p-type source / drain region". The surface of the epitaxial source / drain region 98 in the p-type region 50P may protrude above the surfaces of the corresponding fins 62 and nanostructures 64, 66, and may have small facets.

[0051] Epitaxial source / drain regions 98, nanostructures 64, 66, and / or fins 62 can be implanted with impurities to form source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The impurity concentration in the source / drain regions can be approximately 10. 19cm -3 To about 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any impurities previously described. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0052] As a result of the epitaxial process used to form the epitaxial source / drain region 98, the upper surface of the epitaxial source / drain region has small planes that extend laterally outward beyond the sidewalls of the fins 62 and nanostructures 64, 66. In some embodiments, such as Figure 9C As shown, these small planes cause adjacent epitaxial source / drain regions 98 to merge. In some embodiments, such as Figure 9D As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 98 remain separated. In the illustrated embodiment, the spacer etching for forming the gate spacer 90 is adjusted to also form fin spacers 92 on the sidewalls of fins 62 and / or nanostructures 64, 66. The fin spacers 92 are formed to cover portions of the sidewalls of fins 62 and / or nanostructures 64, 66 that extend above the STI region 70, thereby blocking epitaxial growth. In another embodiment, the spacer etching for forming the gate spacer 90 is adjusted not to form fin spacers, so as to allow the epitaxial source / drain regions 98 to extend to the surface of the STI region 70.

[0053] The epitaxial source / drain region 98 may include one or more semiconductor material layers. For example, each epitaxial source / drain region 98 may include a liner layer 98A, a main layer 98B, and a finishing layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 98. Each of the liner layer 98A, the main layer 98B, and the finishing layer 98C may be formed of different semiconductor materials and may be doped with different impurity concentrations. In some embodiments, the liner layer 98A may have a lower impurity concentration than the main layer 98B, and the finishing layer 98C may have a higher impurity concentration than the liner layer 98A but a lower impurity concentration than the main layer 98B. In an embodiment where the epitaxial source / drain region 98 includes three semiconductor material layers, a liner layer 98A may be grown in the source / drain recess 94, a main layer 98B may be grown on the liner layer 98A, and a trimming layer 98C may be grown on the main layer 98B.

[0054] exist Figure 10A and Figure 10BIn this configuration, a first-layer dielectric (ILD) 104 is deposited over the epitaxial source / drain region 98, gate spacer 90, mask 86 (if present), or dummy gate 84. The first ILD 104 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phospho-silicate gases (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0055] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain region 98, the gate spacer 90, and the mask 86 (if present) or the dummy gate 84. The CESL 102 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which have high etch selectivity (compared to etching the first ILD 104). The CESL 102 can be formed by any suitable method, such as CVD, ALD, etc.

[0056] exist Figure 11A and Figure 11B In this process, a removal process is performed to make the top surface of the first ILD 104 flush with the top surface of the mask 86 (if present) or the dummy gate 84. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84 and portions of the gate spacer 90 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the gate spacer 90, the first ILD 104, CESL 102, and the mask 86 (if present) or the dummy gate 84 are coplanar (within the range of process variations). Therefore, the top surface of the mask 86 (if present) or the dummy gate 84 is exposed through the first ILD 104. In the illustrated embodiment, the mask 86 is retained, and the planarization process makes the top surface of the first ILD 104 flush with the top surface of the mask 86.

[0057] exist Figure 12A and Figure 12BIn the etching process, the mask 86 (if present) and the dummy gate 84 are removed to form the recess 106. A portion of the dummy dielectric 82 in the recess 106 is also removed. In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 84 at a faster rate than for the first ILD 104 or the gate spacer 90. During removal, the dummy dielectric 82 may serve as an etch stop layer while the dummy gate 84 is etched. The dummy dielectric 82 is then removed. Each recess 106 exposes and / or covers a portion of the channel region 68. A portion of the second nanostructure 66 serving as the channel region 68 is disposed between an adjacent pair of epitaxial source / drain regions 98.

[0058] The remaining portion of the first nanostructure 64 is then removed to extend the recess 106, thereby forming an opening 108 in the region 50I between the second nanostructures 66. The remaining portion of the first nanostructure 64 can be removed by an acceptable etching process that selectively etches the material of the first nanostructure 64 at a rate faster than that for the material of the second nanostructure 66. The etching can be isotropic. For example, when the first nanostructure 64 is formed of silicon-germanium and the second nanostructure 66 is formed of silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the second nanostructure 66. Figures 14A to 16B As shown more clearly in (described in more detail later), the remainder of the second nanostructure 66 may have rounded corners.

[0059] exist Figure 13A and Figure 13B In the recess 106, a gate dielectric layer 112 is formed. A gate electrode layer 114 is formed on the gate dielectric layer 112. The gate dielectric layer 112 and the gate electrode layer 114 are layers used to replace the gate, and each layer encloses all (e.g., four) sides of the second nanostructure 66.

[0060] A gate dielectric layer 112 is disposed on the sidewalls and / or top surface of the fin 62; on the top surface, sidewalls, and bottom surface of the second nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric layer 112 may also be formed on the top surface of the gate spacer 90 and the first ILD 104. The gate dielectric layer 112 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric layer 112 may include dielectric materials with a k-value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although in Figure 13A and Figure 13B The diagram shows a single-layer gate dielectric layer 112, but as will be described in more detail later, the gate dielectric layer 112 may include an interface layer and a main layer.

[0061] The gate electrode layer 114 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Although in Figure 13A and Figure 13B The diagram shows a single gate electrode layer 114, but as will be described in more detail later, the gate electrode layer 114 may include any number of work function tuning layers, any number of adhesive layers, and filler materials.

[0062] The formation of the gate dielectric layer 112 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 112 in each region is formed of the same material, and the formation of the gate electrode layer 114 can occur simultaneously, such that the gate electrode layer 114 in each region is formed of the same material. In some embodiments, the gate dielectric layer 112 in each region can be formed by different processes, such that these gate dielectric layers 112 can be different materials and / or have different numbers of layers, and / or the gate electrode layer 114 in each region can be formed by different processes, such that these gate electrode layers 114 can be different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions. In the following description, at least a portion of the gate electrode layer 114 in the n-type region 50N and at least a portion of the gate electrode layer 114 in the p-type region 50P are formed separately.

[0063] Figures 14A to 16B The process of forming a gate dielectric layer 112 and a gate electrode layer 114 for replacing the gate in the recess 106 is shown. Figure 14A , Figure 15A and Figure 16A It shows Figure 13A Features in region 50A. Figure 14B , Figure 15B and Figure 16B It shows Figure 13B The features in region 50B are described. The replacement gate layer comprises one or more work function tuning layers, all formed of pure work function metals. Pure work function metals are work function tuning materials formed of pure metals. Specifically, pure work function metals have a composition comprising one or more metallic elements and substantially free of quasi-metallic and non-metallic elements. Pure work function metals may have a composition of more than 95% atomic percentage (95 at.%) of metal and less than 5% atomic percentage (5 at.%) of quasi-metallic / non-metallic elements. The work function tuning layer formed of pure metals may be referred to as a "pure work function metal layer". The pure work function metal layer is primarily composed of metallic elements. Devices with one or more pure work function metal layers have a work function close to the band edge of the metal(s), thereby allowing for a reduction in the device's threshold voltage. Furthermore, the one or more pure work function metal layers have low resistance. Device performance can therefore be improved.

[0064] exist Figure 14A and Figure 14B In the second nanostructure 66, a gate dielectric layer 112 is formed in the recess 106. The gate dielectric layer 112 can be formed by methods including molecular-beam deposition (MBD), ALD, PECVD, etc. The gate dielectric layer 112 surrounds all (e.g., four) sides of the second nanostructure 66. After the gate dielectric layer 112 is formed, portions of the opening 108 remain in the region 50I between the second nanostructures 66. The gate dielectric layer 112 is multilayered, including a first gate dielectric layer 112A (e.g., an interface layer) and a second gate dielectric layer 112B (e.g., a high-k dielectric layer) above the first gate dielectric layer 112A. The first gate dielectric layer 112A may be formed of silicon oxide, and the second gate dielectric layer 112B may be formed of hafnium oxide.

[0065] exist Figure 15A and 15B In this embodiment, a work function tuning layer 114A is formed on the gate dielectric layer 112. The work function tuning layer 114A is formed of a pure work function metal (e.g., aluminum, titanium, tungsten, nickel, cobalt, ruthenium, their alloys, their multilayers, etc.), which can be conformally deposited by CVD, ALD, PECVD, PEALD, PVD, etc. The pure work function metal can be any acceptable metal selected to tune the work function of the device to a desired amount when applied to the device to be formed. In the illustrated embodiment, the work function tuning layer 114A is a single, continuous layer of pure work function metal. In other embodiments (hereinafter referred to as...) Figures 20A-21B(As described below), the work function tuning layer 114A is a multilayer pure work function metal. In some embodiments, the work function tuning layer 114A is composed of aluminum, titanium, hafnium, or alloys thereof, and has less than 5% atomic percentage (5 at.%) nitrogen and / or carbon. Forming the work function tuning layer 114A from a pure work function metal allows it to have a lower resistance than work function tuning layers formed from materials including quasi-metallic / nonmetallic materials (e.g., work function tuning layers formed from metal nitrides (e.g., titanium nitride, tantalum nitride, etc.) or metal carbides (e.g., titanium carbide, titanium aluminum carbide, etc.). Different work function tuning layers 114A can be formed in each of regions 50N and 50P by different processes, such that the work function tuning layer 114A can be of different materials and / or have different numbers of layers.

[0066] The work function tuning layer 114A in the n-type region 50N can be formed by masking the p-type region 50P. Then, the work function tuning layer 114A in the n-type region 50N is deposited in the recess 106 in the n-type region 50N. The work function tuning layer 114A in the n-type region 50N can comprise any acceptable pure work function metal suitable for an n-type device. For example, the work function tuning layer 114A in the n-type region 50N can be formed from titanium, aluminum, hafnium, etc.

[0067] The work function tuning layer 114A in the p-type region 50P can be formed by masking the n-type region 50N. Then, the work function tuning layer 114A in the p-type region 50P is deposited in the recess 106 in the p-type region 50P. The work function tuning layer 114A in the p-type region 50P can include any acceptable pure work function metal suitable for a p-type device. For example, the work function tuning layer 114A in the p-type region 50P can be formed of tungsten, nickel, platinum, etc.

[0068] The work function tuning layer 114A fills the remainder of the region 50I between the second nanostructures 66 (e.g., fills the opening 108, see...). Figures 14A-14B Specifically, the work function tuning layer 114A is deposited on the gate dielectric layer 112 until it is thick enough to be merged and bonded together. The thickness of the work function tuning layer 114A can be approximately... up to approximately Within the range. In some embodiments, interface 118 is formed by contact between adjacent portions of work function tuning layer 114A (e.g., those around the second nanostructure 66). Because work function tuning layer 114A is formed of pure work function metal, opening 108 is therefore filled with pure metal and is substantially free of quasi-metallic / non-metallic elements.

[0069] In some embodiments, the work function tuning layer 114A is deposited by CVD. Specifically, the work function tuning layer 114A can be formed by placing a substrate 50 in a deposition chamber and dispensing one or more metal-containing precursors into the deposition chamber to allow the metal-containing precursors to flow over the gate dielectric layer 112. The metal-containing precursors include any precursors for the material used in the work function tuning layer 114A. When the work function tuning layer 114A comprises aluminum, the one or more metal-containing precursors may include aluminum-containing precursors such as aluminum chloride (AlCl3), trimethylaluminum (Al2Me6), etc. When the work function tuning layer 114A comprises titanium, the one or more metal-containing precursors may include titanium-containing precursors such as titanium chloride (TiCl4), tetrakis(dimethylamino)titanium (TDMAT). When the work function tuning layer 114A includes hafnium, the metal-containing precursor may include hafnium-containing precursors such as hafnium chloride (HfCl4) or tetrakis(dimethylamino)hafnium (TDMAHf). During the CVD process, the metal is dissociated from one or more metal-containing precursors to form the material of the work function tuning layer 114A. The one or more metal-containing precursors are held in the deposition chamber until the work function tuning layer 114A is formed to the desired thickness (as previously described). The CVD process can be performed at temperatures ranging from about 20°C to about 750°C and pressures ranging from about 0.1 Torr to about 500 Torr, for example, by maintaining the deposition chamber at temperatures and pressures within this range. Performing the CVD process with parameters within these ranges allows the work function tuning layer 114A to be formed to the desired purity. Performing CVD processes with parameters outside these ranges may not allow the work function tuned layer 114A to form with the desired purity.

[0070] In some embodiments, the work function tuning layer 114A is deposited by ALD. Specifically, the work function tuning layer 114A can be formed by placing a substrate 50 in a deposition chamber and cyclically dispensing different source precursors into the deposition chamber. The source precursors include one or more metal-containing precursors previously described and one or more precursors of a material that reacts with the one or more metal-containing precursors to form the work function tuning layer 114A. An ALD cycle is performed by sequentially dispensing each source precursor, wherein each ALD cycle results in the deposition of an atomic layer (sometimes referred to as a monolayer) of the material of the work function tuning layer 114A. The ALD cycle is repeated multiple times until the work function tuning layer 114A is formed to the desired thickness (as previously described). The ALD process can be performed at temperatures from about 20°C to about 750°C and pressures from about 0.1 Torr to about 500 Torr, for example, by maintaining the deposition chamber at temperatures and pressures within this range. Performing the ALD process with parameters within these ranges allows the work function tuning layer 114A to be formed to the desired purity. Performing the ALD process with parameters outside these ranges may not allow the work function tuned layer 114A to form with the desired purity.

[0071] In some embodiments, the work function tuned layer 114A is deposited using a plasma-enhanced deposition process such as PECVD or PEALD. Specifically, the work function tuned layer 114A can be formed by performing a CVD or ALD process similar to that previously described during plasma generation. Plasma can be generated by flowing a gas source into the deposition chamber and exciting the gas source into a plasma state using a plasma generator. The gas source includes a carrier gas (e.g., hydrogen, helium, neon, argon, krypton, xenon, radon, etc.) and the precursors described above. The gas source can flow into the deposition chamber at a rate ranging from about 100 sccm to about 8000 sccm. The plasma generator can be a capacitively coupled plasma (CCP) generator, an inductively coupled plasma (ICP) generator, a remote plasma generator, etc. The plasma generator generates radio frequency (RF) power to excite the gas source into a plasma state. The plasma generation power can be in the range of about 50 watts to about 5000 watts. Performing the plasma-enhanced deposition process with parameters within these ranges allows the work function tuned layer 114A to form with the desired purity. Performing the plasma-enhanced deposition process with parameters outside these ranges may not allow the work function tuned layer 114A to form with the desired purity.

[0072] In some embodiments, the work function tuning layer 114A is deposited by PVD. Specifically, the work function tuning layer 114A can be formed by placing a substrate 50 under a metal target in a deposition chamber and bombarding the target with ions. The target comprises the material of the work function tuning layer 114A, and bombarding the target results in sputtering of material (e.g., metal atoms) from the target. The target can be bombarded with ions by flowing a gas source into the deposition chamber and exciting the gas source into a plasma state using a plasma generator. The gas source includes an ion source gas (e.g., hydrogen, helium, neon, argon, krypton, xenon, radon, etc.). The gas source can flow into the deposition chamber at a rate of about 10 sccm to about 8000 sccm. The plasma generator can be a capacitively coupled plasma (CCP) generator, an inductively coupled plasma (ICP) generator, a remote plasma generator, etc. Radio frequency (RF) power is applied to the target by a plasma generator to activate the ion source gas into a plasma state. The target is then bombarded with ionized gas molecules from the plasma, causing metal atoms to sputter from the target, resulting in the deposition of the work function tuned layer 114A. Each cycle of the applied RF power includes a bombardment cycle (in which the target is bombarded with ions) and a scavenging cycle (in which electrons are attracted to the target to remove ion buildup). The plasma generation power can range from approximately 50 watts to approximately 5000 watts. The PVD process can be performed at temperatures from approximately 20°C to approximately 750°C and for approximately 10... -7 The process is carried out at pressures of approximately 500 Torr, for example, by maintaining the deposition chamber at a temperature and pressure within this range. Performing the PVD process with parameters within these ranges allows the work function tuned layer 114A to form with the desired purity. Performing the PVD process with parameters outside these ranges may not allow the work function tuned layer 114A to form with the desired purity.

[0073] Optionally, forming the work function tuning layer 114A includes purifying the material of the work function tuning layer 114A through a purification process 120. The purification process 120 reduces the concentration of one or more non-metallic elements (e.g., quasi-metallic / non-metallic) in the material of the work function tuning layer 114A, thereby increasing the concentration of one or more metallic elements in the material of the work function tuning layer 114A. In some embodiments, if the initially deposited material of the work function tuning layer 114A does not have the desired purity, the purification process 120 is performed until the material of the work function tuning layer 114A has the desired purity. For example, the material of the work function tuning layer 114A may have a quasi-metallic / non-metallic composition greater than 5% atomic percentage (5 at.%) before the purification process 120, and may have a quasi-metallic / non-metallic composition less than 5% atomic percentage (5 at.%) after the purification process 120.

[0074] In some embodiments, the purification process 120 is a heat treatment. The heat treatment can be performed by annealing the work function tuning layer 114A. Annealing the work function tuning layer 114A causes non-metallic atoms (e.g., quasi-metallic / non-metallic) to degas from the material of the work function tuning layer 114A. Annealing can be performed in a temperature range of about 25°C to about 1000°C.

[0075] In some embodiments, purification process 120 is plasma treatment. Plasma treatment can be performed by bombarding the work function tuned layer 114A with ions within a chamber. Bombarding the work function tuned layer 114A with ions causes nonmetallic atoms (e.g., quasi-metallic / nonmetallic) to be sputtered from the material of the work function tuned layer 114A. The work function tuned layer 114A can be bombarded with ions by introducing a gas source into the chamber and exciting the gas source into a plasma state using a plasma generator. The gas source includes ion source gases (e.g., hydrogen, helium, neon, argon, krypton, xenon, radon, etc.). The gas source can flow into the chamber at a rate ranging from about 100 sccm to about 8000 sccm. The plasma generator can be a capacitively coupled plasma (CCP) generator, an inductively coupled plasma (ICP) generator, a remote plasma generator, etc. Radio frequency (RF) power is applied to the work function tuned layer 114A by a plasma generator to activate the ion source gas into a plasma state. The ionized gas molecules from the plasma bombard the work function tuned layer 114A, causing non-metallic atoms (e.g., quasi-metallic / non-metallic) to be sputtered from the material of the work function tuned layer 114A. Each cycle of the applied RF power includes a bombardment cycle (in which the work function tuned layer 114A is bombarded by ions) and a scavenging cycle (in which electrons are attracted to the work function tuned layer 114A to remove ion buildup on the work function tuned layer 114). The plasma generation power can range from approximately 50 watts to approximately 5000 watts.

[0076] In some embodiments, purification treatment 120 is a chemical treatment. Chemical treatment can be performed by exposing the work function tuning layer 114A to a reducing chemical capable of reducing the material of the work function tuning layer 114A. Reduction of the work function tuning layer 114A can eliminate non-metallic atoms (e.g., quasi-metallic / non-metallic) from the material of the work function tuning layer 114A. The reducing chemical can be a metal hydride (e.g., aluminum hydride, sodium hydride, lithium hydride, etc.), hydrogen, etc., and can be gaseous, liquid, or solid. Reduction can be carried out in a temperature range of about 25°C to about 1000°C.

[0077] exist Figure 16A and Figure 16BIn this process, the remaining portion of the gate electrode layer 114 is deposited to fill the remaining portion of the recess 106. Specifically, a filling layer 114C is deposited on the work function tuning layer 114A. Optionally, an adhesion layer 114B is formed between the filling layer 114C and the work function tuning layer 114A. After formation, the gate electrode layer 114 includes the work function tuning layer 114A, the adhesion layer 114B, and the filling layer 114C.

[0078] The adhesion layer 114B can be conformally deposited on the work function tuning layer 114A. The adhesion layer 114B can be formed of a conductive material such as titanium nitride, tantalum nitride, titanium carbide, or tantalum carbide, which can be deposited by CVD, ALD, PECVD, PVD, etc. In some embodiments, the adhesion layer 114B is formed of an impure adhesion metal (such as a metal nitride or metal carbide), and is therefore not a pure metal. The adhesion layer 114B can alternatively be referred to as an adhesive layer and improves the adhesion between the work function tuning layer 114A and the filler layer 114C.

[0079] The filler layer 114C may be conformally deposited on the adhesion layer 114B. In some embodiments, the filler layer 114C may be formed of a conductive material such as cobalt, ruthenium, aluminum, tungsten, or combinations thereof, which may be deposited by CVD, ALD, PECVD, PVD, etc. In some embodiments, the filler layer 114C may be formed of a pure filler metal that is substantially free of quasi-metallic / non-metallic elements. The filler layer 114C may be formed of one or more metals selected from the same set of candidate metals used for the work function tuning layer 114A, which may be formed using methods selected from the same set of candidate methods used for forming the work function tuning layer 114A. In some embodiments, the pure filler metal of the filler layer 114C may be different from the work function metal of the work function tuning layer 114A. The filler layer 114C fills the remainder of the recess 106.

[0080] Region 50I between the second nanostructures 66 is completely filled with one or more dielectric materials of the gate dielectric layer 112 and a pure work function metal of the work function tuning layer 114A. No adhesion layer 114B (if present) and filling layer 114C are formed in region 50I between the second nanostructures 66, such that region 50I is free of adhesion layer 114B and filling layer 114C. Instead, portions of the gate dielectric layer 112 are wrapped around the second nanostructures 66, and portions of the work function tuning layer 114A between the second nanostructures 66 extend continuously between these portions of the gate dielectric layer 112. Because the work function tuning layer 114A is formed of a pure work function metal, portions of the gate electrode layer 114 in region 50I (e.g., between the second nanostructures 66) comprise metal and are substantially free of quasi-metallic / non-metallic materials.

[0081] As described above, the work function tuning layer 114A and the filler layer 114C can be formed of pure metals, while the adhesion layer 114B can be formed of impure metals. In such an embodiment, the material of the adhesion layer 114B has a higher concentration of impurities (e.g., quasi-metallic / non-metallic) compared to the materials of the work function tuning layer 114A and the filler layer 114C. For example, the adhesion layer 114B can be formed of metal nitrides or metal carbides, while the work function tuning layer 114A and the filler layer 114C are substantially free of nitrogen and / or carbon.

[0082] exist Figure 17A and Figure 17B In this process, a removal process is performed to remove excess material from the gate dielectric layer 112 and the gate electrode layer 114 (these excess portions are above the top surfaces of the first ILD 104 and the gate spacer 90), thereby forming the gate dielectric 122 and the gate electrode 124. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., may be utilized. The gate dielectric layer 112 has a portion remaining in the recess 106 when planarized (thus forming the gate dielectric 122). The gate electrode layer 114 has a portion remaining in the recess 106 when planarized (thus forming the gate electrode 124). Gate spacer 90; CESL 102; first ILD 104; gate dielectric 122 (e.g., first gate dielectric layer 112A and second gate dielectric layer 112B, see Figure 16A and Figure 16B ); and gate electrode 124 (e.g., work function tuning layer 114A, adhesion layer 114B (if present) and fill layer 114C, see Figure 16A and Figure 16B The top surfaces of the gate dielectric 122 and gate electrode 124 are coplanar (within the range of process variations). The gate dielectric 122 and gate electrode 124 form the replacement gate of the resulting nanoFET. Each pair of corresponding gate dielectric 122 and gate electrode 124 can be collectively referred to as a “gate structure”. These gate structures each extend along the top surface, sidewalls, and bottom surface of the channel region 68 of the second nanostructure 66.

[0083] exist Figure 18A and Figure 18B In this configuration, the second ILD 134 is deposited over the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. In some embodiments, the second ILD 134 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 134 is formed of a dielectric material such as PSG, BSG, BPSG, or USG, which can be deposited by any suitable method such as CVD or PECVD.

[0084] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. The ESL 132 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has high etch selectivity (compared to etching the second ILD 134).

[0085] exist Figure 19A and Figure 19B In this configuration, a gate contact 142 and a source / drain contact 144 are formed to respectively connect the gate electrode 124 and the epitaxial source / drain region 98. The gate contact 142 is physically and electrically coupled to the gate electrode 124. The source / drain contact 144 is physically and electrically coupled to the epitaxial source / drain region 98.

[0086] As an example of forming the gate contact 142 and the source / drain contact 144, the opening for the gate contact 142 is formed through the second ILD 134 and ESL 132, and the opening for the source / drain contact 144 is formed through the second ILD 134, ESL 132, the first ILD 104, and CESL 102. These openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately), such as a diffusion barrier layer or an adhesion layer, and a conductive material are formed in these openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., CMP) may be performed to remove excess material from the surface of the second ILD 134. The remaining liner and conductive material form the gate contact 142 and the source / drain contact 144 in the openings. The gate contact 142 and the source / drain contact 144 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 142 and the source / drain contact 144 can be formed in different cross sections to avoid short circuits.

[0087] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 98 and the source / drain contact 144. The metal-semiconductor alloy region 146 may be: a silicide region formed of metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide silicon region formed of both metal silicides and metal germanides. The metal-semiconductor alloy region 146 can be formed before one or more materials of the source / drain contact 144 by depositing metal in the opening for the source / drain contact 144 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 98 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process (e.g., ALD, CVD, PVD, etc.). After the thermal annealing process, a cleaning process (e.g., wet cleaning) can be performed to remove any residual metal from the openings for the source / drain contacts 144, for example, from the surface of the metal-semiconductor alloy region 146. One or more materials of the source / drain contacts 144 can then be formed on the metal-semiconductor alloy region 146.

[0088] Figures 20A-21B This is a view of a nanostructured FET according to some other embodiments. These embodiments are similar to those for... Figures 14A-16B The described embodiments differ in that the work function tuning layer 114A is a multilayer pure work function metal. In some embodiments, the work function tuning layer 114A is a two-layer pure work function metal, including a first work function metal sublayer 114A1 and a second work function metal sublayer 114A2 on the first work function metal sublayer 114A1, such as... Figure 20A and Figure 20B As shown. In some embodiments, the work function tuning layer 114A is a three-layer pure work function metal, similar to a two-layer structure but also including a third work function metal sublayer 114A3 on top of the second work function metal sublayer 114A2. Figure 21A and Figure 21B As shown. Each sublayer is a single, continuous layer of metals with different pure work functions. For example, the first work function metal sublayer 114A1 could be aluminum, the second work function metal sublayer 114A2 could be titanium, and the third work function metal sublayer 114A3 (if present) could be hafnium.

[0089] When the work function tuning layer 114A is a multilayer pure work function metal, sublayers of pure work function metal are deposited such that the topmost sublayer of the work function tuning layer 114A (e.g., the third work function metal sublayer 114A3 (if present) or the second work function metal sublayer 114A2) merges and bonds together. For example, the thickness of the topmost sublayer of the work function tuning layer 114A can be thicker than each of the lower sublayers of the work function tuning layer 114A (e.g., the second work function metal sublayer 114A2 and / or the first work function metal sublayer 114A1), which prevents the lower sublayers from merging.

[0090] In some embodiments, the sublayers of the work function tuning layer 114A have a difficult-to-distinguish interface comprising an alloy of the metals in each layer. Continuing with the example where the first work function metal sublayer 114A1 is aluminum, the second work function metal sublayer 114A2 is titanium, and the third work function metal sublayer 114A3 (if present) is hafnium, the interface between work function metal sublayers 114A1 and 114A2 can be a difficult-to-distinguish interface comprising an aluminum-titanium alloy, and the interface between work function metal sublayers 114A2 and 114A3 (if present) can be a difficult-to-distinguish interface comprising a titanium-hafnium alloy.

[0091] In some embodiments, the sublayers of the work function tuning layer 114A have identifiable interfaces that are substantially free of alloys of the metals in each layer. Continuing with the example where the first work function metal sublayer 114A1 is aluminum, the second work function metal sublayer 114A2 is titanium, and the third work function metal sublayer 114A3 is hafnium (if present), the interface between work function metal sublayers 114A1 and 114A2 can be an identifiable interface of aluminum and titanium, and the interface between work function metal sublayers 114A2 and 114A3 (if present) can be an identifiable interface of titanium and hafnium.

[0092] The embodiments offer various advantages. Performing the deposition process described herein allows the work function tuning layer 114A to be formed from one or more pure work function metals. Performing purification treatment 120 allows for increased purity of the metal in the work function tuning layer 114A. Forming the gate electrode 124 with the work function tuning layer 114A of one or more pure work function metals allows the resulting device to have a work function close to the bandgap edge of the metal, thereby reducing the threshold voltage of the resulting device. Furthermore, the work function tuning layer 114A formed from one or more pure work function metals has low resistance. Device performance can therefore be improved.

[0093] In one embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric surrounding the first and second nanostructures, the gate dielectric comprising a dielectric material; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer comprising a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric material of the gate dielectric completely filling a region between the first and second nanostructures, the pure work function metal having a metal composition of greater than 95% atomic percentage; an adhesion layer on the work function tuning layer; and a filling layer on the adhesion layer. In some embodiments of the device, the work function tuning layer is a single layer of pure work function metal. In some embodiments of the device, the work function tuning layer is a multilayer of pure work function metal. In some embodiments of the device, each metal of the pure work function metal has an interface containing an alloy of the corresponding metal. In some embodiments of the device, each metal of the pure work function metal has an interface not containing an alloy of the corresponding metal. In some embodiments of the device, the adhesion layer comprises an impure metal, and the filler layer comprises a filler metal, wherein the impure metal of the adhesion layer has a greater concentration of quasi-metals and non-metals than the filler metal of the filler layer and the pure work function metal of the work function tuning layer. In some embodiments of the device, the filler metal is tungsten, the impure metal is a metal nitride or a metal carbide, and the pure work function metal is pure aluminum, pure titanium, or pure hafnium.

[0094] In one embodiment, a device includes: a channel region on a substrate; a gate dielectric layer on the channel region; a work function metal on the gate dielectric layer, the work function metal having a first concentration of impurities, the impurities including quasi-metals or nonmetals; an adhered metal on the work function metal, the adhered metal having a second concentration of impurities, the second concentration being greater than the first concentration; and a filler metal on the adhered metal, the filler metal being different from the work function metal, the filler metal having a third concentration of impurities, the second concentration being greater than the third concentration. In some embodiments of the device, the impurities are nitrogen or carbon. In some embodiments of the device, both the first concentration and the third concentration are less than 5% atomic percentage.

[0095] In one embodiment, a method includes: forming a first nanostructure and a second nanostructure on a substrate; forming a gate dielectric layer having a first portion surrounding the first nanostructure and a second portion surrounding the second nanostructure; depositing a pure work function metal on the gate dielectric layer, the pure work function metal extending continuously between the first portion and the second portion of the gate dielectric layer; depositing an impure adherent metal on the pure work function metal; and depositing a pure filler metal on the impure adherent metal. In some embodiments of the method, depositing the pure work function metal includes: placing the substrate in a chamber; and allowing a precursor comprising the pure work function metal to flow over the gate dielectric layer, the precursor being maintained at a temperature of 20°C to 750°C and a pressure of 0.1 Torr to 500 Torr during the flow. In some embodiments of the method, depositing a pure work function metal includes: placing a substrate in a chamber; and performing a cycle comprising: flowing a first precursor comprising a pure work function metal onto a gate dielectric layer; and flowing a second precursor onto the gate dielectric layer, the second precursor reacting with the first precursor to deposit the pure work function metal, wherein the chamber is maintained at a temperature of 20°C to 750°C and a pressure of 0.1 Torr to 500 Torr during the cycle; and repeating the cycle multiple times. In some embodiments of the method, depositing a pure work function metal includes: placing a substrate under a target comprising a pure work function metal; and bombarding the target with ions, wherein during bombardment, the pure work function metal is sputtered from the target onto the gate dielectric layer. In some embodiments, the method further includes: applying a purification treatment to the pure work function metal, the purification treatment reducing the concentration of impurities in the pure work function metal, the impurities including quasi-metals or nonmetals. In some embodiments of the method, applying the purification treatment includes: annealing the pure work function metal. In some embodiments of the method, the purification process includes: generating plasma; and bombarding the pure work function metal with ions from the plasma. In some embodiments of the method, the purification process includes: exposing the pure work function metal to a reducing chemical comprising hydrogen or a metal hydride. In some embodiments of the method, the impure adhering metal has a higher concentration of impurities than the pure work function metal, including metalloids or nonmetals. In some embodiments of the method, the impure adhering metal is a metal nitride or a metal carbide, and the pure work function metal is pure aluminum, pure titanium, or pure hafnium.

[0096] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0097] Example 1. A transistor gate structure comprising: a first nanostructure; a second nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric comprising a dielectric material; and a gate electrode comprising: a work function tuning layer on the gate dielectric, the work function tuning layer comprising a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric material of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a metal composition of greater than 95% atomic percentage; and a filling layer on the work function tuning layer.

[0098] Example 2. The transistor gate structure according to Example 1, wherein the work function tuning layer is a single layer of the pure work function metal.

[0099] Example 3. The transistor gate structure according to Example 1, wherein the work function tuning layer is a multilayer pure work function metal.

[0100] Example 4. The transistor gate structure according to Example 3, wherein each of the pure work function metals has an interface of an alloy containing the corresponding metal.

[0101] Example 5. The transistor gate structure according to Example 3, wherein each of the pure work function metals has an interface of an alloy that does not contain the corresponding metal.

[0102] Example 6. The transistor gate structure according to Example 1, wherein the gate electrode further includes an adhesion layer located between the work function tuning layer and the fill layer, the adhesion layer comprising an impure metal, and the fill layer comprising a fill metal, the impure metal of the adhesion layer having a greater quasi-metal and non-metal concentration than the fill metal of the fill layer and the pure work function metal of the work function tuning layer.

[0103] Example 7. The transistor gate structure according to Example 6, wherein the filler metal is tungsten, the impure metal is a metal nitride or a metal carbide, and the pure work function metal is pure aluminum, pure titanium, or pure hafnium.

[0104] Example 8. A transistor gate structure comprising: a channel region on a substrate; a gate dielectric layer on the channel region; a work function metal on the gate dielectric layer, the work function metal having a first concentration of impurities, the impurities comprising quasi-metals or nonmetals; an adhered metal on the work function metal, the adhered metal having a second concentration of the impurities, the second concentration being greater than the first concentration; and a fill metal on the adhered metal, the fill metal being different from the work function metal, the fill metal having a third concentration of the impurities, the second concentration being greater than the third concentration.

[0105] Example 9. The transistor gate structure according to Example 8, wherein the impurity is nitrogen or carbon.

[0106] Example 10. The transistor gate structure according to Example 8, wherein both the first concentration and the third concentration are less than 5% atomic percentage.

[0107] Example 11. A method of forming a transistor gate structure, comprising: forming a first nanostructure and a second nanostructure on a substrate; forming a gate dielectric layer having a first portion surrounding the first nanostructure and a second portion surrounding the second nanostructure; depositing a pure work function metal on the gate dielectric layer, the pure work function metal extending continuously between the first portion and the second portion of the gate dielectric layer; and depositing a pure filler metal on the pure work function metal.

[0108] Example 12. The method according to Example 11, wherein depositing the pure work function metal comprises: placing the substrate in a chamber; and allowing a precursor comprising the pure work function metal to flow over the gate dielectric layer, the precursor comprising the pure work function metal, wherein during the flow, the chamber is maintained at a temperature of 20°C to 750°C and a pressure of 0.1 Torr to 500 Torr.

[0109] Example 13. The method according to Example 11, wherein depositing the pure work function metal comprises: placing the substrate in a chamber; performing a cycle comprising: flowing a first precursor on the gate dielectric layer, the first precursor comprising the pure work function metal; and flowing a second precursor on the gate dielectric layer, the second precursor reacting with the first precursor to deposit the pure work function metal, wherein during the cycle, the chamber is maintained at a temperature of 20°C to 750°C and a pressure of 0.1 Torr to 500 Torr; and repeating the cycle multiple times.

[0110] Example 14. The method according to Example 11, wherein depositing the pure work function metal comprises: placing the substrate below a target containing the pure work function metal; and bombarding the target with ions, during which the pure work function metal is sputtered from the target onto the gate dielectric layer.

[0111] Example 15. The method according to Example 11 further includes: applying a purification treatment to the pure work function metal, the purification treatment reducing the concentration of impurities in the pure work function metal, the impurities including quasi-metals or non-metals.

[0112] Example 16. The method according to Example 15, wherein applying the purification process includes annealing the pure work function metal.

[0113] Example 17. The method according to Example 15, wherein applying the purification process comprises: generating plasma; and bombarding the pure work function metal with ions from the plasma.

[0114] Example 18. The method according to Example 15, wherein applying the purification process comprises: exposing the pure work function metal to a reducing chemical comprising hydrogen or a metal hydride.

[0115] Example 19. The method according to Example 11 further includes depositing an impure adhering metal between the work function metal and the pure filler metal, wherein the impure adhering metal has a higher concentration of impurities than the pure work function metal, the impurities including quasi-metals or non-metals.

[0116] Example 20. The method according to Example 19, wherein the impure adhering metal is a metal nitride or a metal carbide, and the pure work function metal is pure aluminum, pure titanium, or pure hafnium.

Claims

1. A transistor gate structure, comprising: First nanostructure; Second nanostructure; A gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric comprising a dielectric material; as well as Gate electrode, including: The work function tuning layer on the gate dielectric comprises multiple layers of pure work function metals, the upper layer of pure work function metals having a greater thickness than the lower layer of pure work function metals, the multiple layers of pure work function metals of the work function tuning layer and the dielectric material of the gate dielectric completely filling the region between the first nanostructure and the second nanostructure, and the multiple layers of pure work function metals having a metal composition of greater than 95% atomic percentage; as well as A filling layer on the work function tuning layer.

2. The transistor gate structure according to claim 1, wherein, Each metal in the multilayer pure work function metal has an interface containing an alloy of the corresponding metal.

3. The transistor gate structure according to claim 1, wherein, Each metal in the multilayer pure work function metal has an interface of an alloy that does not contain the corresponding metal.

4. The transistor gate structure according to claim 1, wherein, The gate electrode further includes an adhesion layer located between the work function tuning layer and the fill layer. The adhesion layer includes an impure metal, and the fill layer includes a fill metal. The impure metal in the adhesion layer has a greater concentration of quasi-metals and non-metals than the fill metal in the fill layer and the multilayer pure work function metals in the work function tuning layer.

5. The transistor gate structure according to claim 4, wherein, The filler metal is tungsten, the impure metal is a metal nitride or a metal carbide, and the multilayer pure work function metal includes pure aluminum, pure titanium or pure hafnium.

6. A transistor gate structure, comprising: The channel region on the substrate; A gate dielectric layer in the channel region; A first work function metal on the gate dielectric layer, the first work function metal having a first concentration of impurities, the impurities including quasi-metals or non-metals; A second work function metal on the first work function metal, the second work function metal being different from the first work function metal, the second work function metal having a greater thickness than the first work function metal, and the second work function metal having a second concentration of the impurities; Adhesive metal on the second work function metal, the adhesive metal having a third concentration of the impurities, the third concentration being greater than the first concentration and the second concentration; as well as The filler metal on the adhered metal has a fourth concentration of the impurities, the third concentration being greater than the fourth concentration.

7. The transistor gate structure according to claim 6, wherein, The impurity is nitrogen or carbon.

8. The transistor gate structure according to claim 6, wherein, Both the first concentration and the fourth concentration are less than 5% atomic percentage.

9. A method for forming a transistor gate structure, comprising: A first nanostructure and a second nanostructure are formed on a substrate; A gate dielectric layer is formed, the gate dielectric layer having a first portion surrounding the first nanostructure and a second portion surrounding the second nanostructure; A first pure work function metal is deposited on the gate dielectric layer. A second pure work function metal is deposited on the first pure work function metal, the second pure work function metal having a greater thickness than the first pure work function metal, and the first pure work function metal and the second pure work function metal completely fill the region between the first portion of the gate dielectric layer and the second portion of the gate dielectric layer. as well as Deposit pure filler metal on the second pure work function metal.

10. The method according to claim 9, wherein, Depositing the first pure work function metal includes: The substrate is placed in the chamber; and A precursor comprising the first pure work function metal is flowed over the gate dielectric layer, and during this flow, the chamber is maintained at a temperature of 20°C to 750°C and a pressure of 0.1 Torr to 500 Torr.

11. The method according to claim 9, wherein, Depositing the first pure work function metal includes: The substrate is placed in the chamber; Execute a loop, which includes: The first precursor, comprising the first work function metal, is allowed to flow on the gate dielectric layer; and A second precursor is allowed to flow on the gate dielectric layer, reacting with the first precursor to deposit the first pure work function metal. During this cycle, the chamber is maintained at a temperature of 20°C to 750°C and a pressure of 0.1 Torr to 500 Torr. Repeat the loop multiple times.

12. The method according to claim 9, wherein, Depositing the first pure work function metal includes: The substrate is placed below the target containing the first pure work function metal; and The target is bombarded with ions, during which the first pure work function metal is sputtered from the target onto the gate dielectric layer.

13. The method of claim 9, further comprising: The first pure work function metal is subjected to a purification treatment, which reduces the concentration of impurities in the first pure work function metal, the impurities including quasi-metals or non-metals.

14. The method according to claim 13, wherein, The purification process described above includes: Anneal the first metal with a pure work function.

15. The method according to claim 13, wherein, The purification process described above includes: Generate plasma; and The first work function metal is bombarded with ions from the plasma.

16. The method according to claim 13, wherein, The purification process described above includes: The first pure work function metal is exposed to a reducing chemical, which contains hydrogen or a metal hydride.

17. The method of claim 9, further comprising depositing an impure adhering metal between the second pure work function metal and the pure filler metal, wherein, The impure adhering metal has a higher concentration of impurities than the first pure work function metal, and the impurities include quasi-metals or non-metals.

18. The method according to claim 17, wherein, The impure adhering metal is a metal nitride or a metal carbide, and the first pure work function metal is pure aluminum, pure titanium, or pure hafnium.

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