Parallel competing main power supply system for high-speed optical fiber communication loop reconstruction and its control method

Abstract

The present invention relates to a power supply system and a control method thereof, and in particular to a parallel competing master power supply system for high-speed optical fiber communication loop reconstruction and a control method thereof. The purpose of the present invention is to solve the technical problem that the existing parallel power supply system theoretically requires that the output phase and voltage amplitude of all parallel modules are completely consistent, but in practice is limited by hardware differences and control methods, resulting in difficult implementation. A parallel power supply system for high-speed optical fiber communication loop reconstruction and a control method thereof are provided. The parallel competing master power supply system and the control method thereof adopt a parallel competing master power supply system with arbitrary master-slave switching, which improves the stability and continuous output capacity of the parallel power supply operation; reconstructs a digital-analog hybrid control loop, taking into account the stability and high performance characteristics of analog control and the flexibility, convenience and high efficiency characteristics of digital control; adopts the low latency of the high-speed optical fiber communication network, narrows the difference between the master and slave outputs, and reduces the adverse effects caused by the master-slave output phase difference.

Description

Technical Field

[0001] The present invention relates to a power supply system and a control method thereof, and in particular to a parallel competing main power supply system for high-speed optical fiber communication loop reconstruction and a control method thereof. Background Art

[0002] AC output power systems such as inverters and UPS are widely used in the current power electronics field. Output paralleling technology facilitates this widespread application, enabling modularization of AC power systems, improving reliability and scalability. In theory, AC output paralleling requires that the output phase and voltage amplitude of all parallel modules be identical. However, in practice, this is difficult to achieve due to hardware differences and control methods. Software or hardware methods can be used to minimize the amplitude and phase errors between the outputs of parallel modules, thus reducing the difficulty of paralleling.

[0003] Currently, the most common approach is to use a digital controller to perform calculations entirely, generating PWM signals to control the inverter circuit and achieve AC output. While fully digital control offers advantages such as high efficiency, compact size, and flexible algorithms, it also provides a more convenient control solution for AC output parallel connection. However, it also has drawbacks such as increased development difficulty, susceptibility to electromagnetic interference, and loss of control performance due to digital-to-analog conversion errors. While fully analog control offers excellent loop performance and is suitable for single-module control, it is somewhat challenging to achieve parallel connection and cannot meet the requirements of ultra-high power demands and system parallel connection designs. Summary of the Invention

[0004] The purpose of the present invention is to solve the problem that the existing parallel power supply system theoretically requires that the output phase and voltage amplitude of all parallel modules are completely consistent, but in practice it is difficult to achieve due to hardware differences and control methods. The amplitude and phase errors between the outputs of each parallel module can only be reduced by software or hardware means to reduce the difficulty of parallel connection. If full digital control is used, the development is difficult and is easily affected by electromagnetic interference and digital-to-analog conversion errors, resulting in loss of control performance. If full analog control is used, it cannot meet the technical problems of ultra-high power requirements and system parallel design requirements. A parallel power supply system with high-speed fiber-optic communication loop reconstruction and a control method thereof are provided.

[0005] To solve the above technical problems, the present invention provides the following technical solutions:

[0006] The present invention provides a parallel competitive main power supply system for high-speed optical fiber communication loop reconstruction, which is special in that it includes an optical fiber communication network and N AC power supplies; 2≤N≤6;

[0007] The optical fiber communication network includes N communication terminals, each of which corresponds to N AC power supplies. Two optical fibers, one for receiving and one for transmitting, are used to maintain real-time communication between every two communication terminals.

[0008] Furthermore, each AC power supply includes a front-stage uncontrolled rectifier unit and a rear-stage single-phase inverter unit.

[0009] Furthermore, the uncontrolled rectifier unit includes a bus soft start unit, a grid-side transformer, at least one diode rectifier bridge and a DC bus LC filter unit connected in sequence;

[0010] The busbar soft start unit is used to slowly raise the inlet voltage of the grid-side transformer to the same level as the grid voltage;

[0011] The diode rectifier bridge is used to convert the AC input into a DC voltage with ripple;

[0012] The DC bus LC filter unit is used to eliminate the ripple of the DC voltage with ripples to obtain a stable DC bus Udc.

[0013] Furthermore, the single-phase inverter unit includes a control unit, output busbars respectively connected to the control units, and three pairs of IGBT switch groups and output LC filter units constituting a single-phase inverter topology structure;

[0014] The output LC filter unit is used to convert the square wave voltage transmitted from the IGBT switch group into a sinusoidal AC voltage;

[0015] The control unit is used to perform closed-loop control calculations by sampling the input feedback of the bus soft-start unit, the inductor current feedback of the output LC filter unit, and the output voltage feedback of the output bus, and output PWM control signals for each of the three phases to control the single-phase inverter unit to chop the output bus, thereby achieving single-machine AC output of the AC power supply;

[0016] The control unit adopts a parallel competition logic system to ensure that each AC power supply has the same output mode, and any number of AC power supplies have the ability to output in parallel. When any one or more AC power supplies fail, the system will automatically exit parallel operation without affecting the normal operation of other AC power supplies.

[0017] Furthermore, the diode rectifier bridge includes three diode rectifier bridges connected in series, and the first and last two diode rectifier bridges each have an output terminal connected to the DC bus LC filter unit.

[0018] Furthermore, the control unit includes a master control loop and a slave control loop;

[0019] The host control loop includes DSP, FPGA, AD sampling, analog voltage control loop, DA, analog current control loop and PWM;

[0020] DSP is used to calculate the AC voltage effective value loop output using the proportional integral PI control method;

[0021] FPGA is used to calculate the digital voltage sinusoidal reference based on the AC voltage RMS loop output;

[0022] DA is used to convert the digital voltage sinusoidal reference into an analog signal and transmit it to the analog voltage control loop reference input terminal;

[0023] The analog voltage control loop is used to perform analog proportional P control calculation on the analog signal;

[0024] AD sampling is used to collect the analog voltage control loop output signal and convert it into a digital signal and send it to DA;

[0025] DA is used to convert digital signals into analog signals as given signals for the analog current control loop;

[0026] At the same time, the digital signal obtained by AD sampling and conversion is sent to the communicating slave through optical fiber;

[0027] The analog current control loop is used to calculate the analog signal using the given signal and compare it with the triangle wave signal to obtain the PWM control signal;

[0028] The slave control loop has the same structure as the master control loop.

[0029] Furthermore, the AC power supply can operate independently at full load.

[0030] The present invention also provides a control method for a parallel competing main power supply system based on the reconstruction of the high-speed optical fiber communication loop, which is special in that it includes the following steps:

[0031] 1) The AC power supply of the smallest unit is used as the host, and the DSP of the host control loop uses the proportional integral PI control method to calculate the AC voltage effective value loop output; the FPGA calculates the digital voltage sine given according to the AC voltage effective value loop output; the DA converts the digital voltage sine given into an analog signal and transmits it to the given input of the analog voltage control loop; the analog voltage control loop performs analog proportional P control calculation on the analog signal; the AD samples and collects the signal at the output of the analog voltage control loop and converts it into a digital signal and sends it to the DA, which converts the digital signal into an analog signal as the given signal of the analog current control loop; at the same time, the digital signal obtained by the AD sampling conversion is sent to the communicating slave through the optical fiber; the analog current control loop uses the given signal to calculate the analog signal and compares it with the triangular wave signal to obtain the PWM control signal; when selecting the host here, the rule of using the smallest unit in operation as the host is adopted. Of course, other rules can also be used, as long as one can be selected each time a host is selected.

[0032] 2) The slave control loop converts the digital signal obtained from the master control loop into an analog signal via the slave DA, and transmits it to the given input of the slave analog current control loop. The analog current control loop calculates and compares it with the triangle wave signal to obtain a PWM control signal, thereby achieving consistency in the master and slave outputs of the parallel power supply. At the same time, the slave's own effective value loop and analog voltage control loop continue to run and sample, and the input of the slave's own effective value loop also comes from the digital signal of the master;

[0033] 3) Each AC power supply receives the machine number and operating status of other AC power supplies through optical fiber communication. If the main AC power supply stops or fails, the remaining AC power supplies enter the master competition logic, and the AC power supply with the smallest remaining number becomes the master. The master position is changed, and the given value of the analog current control loop is also synchronously switched to the current master data.

[0034] Furthermore, in step 1), the trigger signal of the AD sampling precedes the trigger signal of the optical fiber communication transmission module by a time equal to the total time used for AD sampling and conversion, and the AD sampling sends the data out through the optical fiber immediately after the data conversion is completed;

[0035] In steps 1) and 2), the trigger signal of the DA is issued when the optical fiber analysis module completely analyzes and updates a frame of data, so that the DA converts the digital signal into an analog signal immediately after receiving it;

[0036] In steps 1) and 2), the analog voltage control loop and the analog current control loop are both analog proportional P control. A total of three sets of control parameters are designed for different output frequency modes. The mode switching is performed by controlling the electronic switch using an FPGA control signal. The three modes correspond to the startup phase, normal operation phase, and post-fault restart phase of the load operated by the AC power supply, respectively.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] 1. The parallel competing main power supply system and control method for high-speed optical fiber communication loop reconstruction provided by the present invention adopts a parallel competing main power supply system with arbitrary master-slave switching, which improves the stability and continuous output capacity of the parallel power supply operation, and will not cause the entire power supply system to shut down due to a failure of a certain AC power supply.

[0039] 2. The parallel competing main power supply system and control method for reconstructing the high-speed optical fiber communication loop provided by the present invention combine the characteristics of digital and analog control, reconstruct the digital-analog hybrid control loop, and take into account the stability and high performance characteristics of analog control and the flexibility, convenience and high efficiency characteristics of digital control.

[0040] 3. The parallel competing master power supply system and control method for high-speed fiber-optic communication loop reconstruction provided by the present invention adopt the low latency of the high-speed fiber-optic communication network, narrow the difference between the master and slave outputs, reduce the adverse effects of the master-slave output difference, enhance the anti-interference ability of communication, reduce the difficulty of parallel operation, and improve the performance of the parallel system. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of the connection of a parallel main power supply system for reconstructing a high-speed optical fiber communication loop according to the present invention;

[0042] Figure 2 This is a block diagram of a single-machine (single AC power supply) parallel main power supply system for reconstructing a high-speed optical fiber communication loop according to the present invention;

[0043] Figure 3 A block diagram of a digital-analog hybrid control loop of a control unit of a parallel competing main power supply system for reconstructing a high-speed optical fiber communication loop according to the present invention; DETAILED DESCRIPTION

[0044] The present invention will be further described below in conjunction with the accompanying drawings.

[0045] A parallel competing main power supply system for high-speed optical fiber communication loop reconstruction, such as Figure 1 As shown, it includes a low-latency, high-speed optical fiber communication network and N AC power supplies; the AC power supply can independently operate a 500KW load, 2≤N≤6, and preferably N=6; the optical fiber communication network includes N communication terminals, and the N communication terminals correspond one to one with the N AC power supplies. Two optical fibers, one for receiving and one for transmitting, are used between each two communication terminals to maintain real-time communication, so that each running terminal maintains real-time communication with other running terminals and knows the operating status and output data of other terminals, thereby forming an interwoven communication network with a maximum power of 3MW.

[0046] like Figure 2As shown, each AC power supply includes a front-stage 18-pulse uncontrolled rectifier unit and a rear-stage single-phase inverter unit. The uncontrolled rectifier unit includes a bus soft-start unit, a grid-side transformer, three series-connected diode rectifier bridges (uncontrolled rectifier bridges), and a DC bus LC filter unit. The bus soft-start unit is used to slowly raise the grid-side transformer input voltage to the same level as the grid voltage; the diode rectifier is used to convert the AC input into a rippled DC voltage; and the DC bus LC filter unit is used to eliminate the ripple of the rippled DC voltage to achieve a stable DC bus Udc. The single-phase inverter unit includes a control unit, output buses connected to the control unit, and three pairs of IGBT switch groups and output LC filter units forming a single-phase inverter topology (i.e., three IGBT switch groups and three output LC filter units corresponding to the three IGBT switch groups). The output LC filter unit is used to convert the square wave voltage transmitted from the IGBT switch group into a sinusoidal AC voltage. The control unit is used to perform closed-loop control calculations by sampling the input feedback of the bus soft-start unit, the inductor current feedback of the output LC filter unit, and the output voltage feedback of the output bus, and output PWM control signals for each of the three phases to control the single-phase inverter unit to chop the output bus, thereby achieving single-unit AC output of the AC power supply. The control unit adopts a parallel competition logic system combining digital control and analog control to ensure that each AC power supply has the same output mode, and any number of AC power supplies have the ability to output in parallel. In the event of a failure of any one or more AC power supplies, the control unit automatically exits parallel operation without affecting the normal operation of the other AC power supplies. The diode rectifier bridge comprises three diode rectifier bridges connected in series in sequence, and the first and last two diode rectifier bridges each have an output terminal connected to a DC bus LC filter unit.

[0047] like Figure 3 As shown, the control unit includes a host control loop and a slave control loop; the host control loop includes DSP, FPGA, AD sampling, analog voltage control loop, DA, analog current control loop and PWM; DSP is used to calculate the AC voltage effective value loop output using the proportional integral PI control method; FPGA is used to calculate the digital voltage sine given according to the AC voltage effective value loop output; DA is used to convert the digital voltage sine given into an analog signal and transmit it to the given input end of the analog voltage control loop; the analog voltage control loop is used to perform analog proportional P control calculation on the analog signal; AD sampling is used to collect the analog voltage control loop output end signal and convert it into a digital signal and send it to the DA; DA is used to convert the digital signal into an analog signal as the given signal of the analog current control loop; at the same time, the digital signal obtained by AD sampling conversion is sent to the communicating slave through optical fiber; the analog current control loop is used to use the given signal to calculate the analog signal and compare it with the triangular wave signal to obtain the PWM control signal; the structure of the slave control loop is the same as that of the host control loop.

[0048] The control method (parallel master logic) of the parallel master power system for high-speed optical fiber communication loop reconstruction includes the following steps:

[0049] 1) The AC power supply of the smallest unit is used as the host. The DSP of the host control loop uses the proportional-integral (PI) control method to calculate the AC voltage RMS loop output. The FPGA calculates the digital voltage sinusoidal reference based on the AC voltage RMS loop output. The DA converts the digital voltage sinusoidal reference into an analog signal and transmits it to the reference input of the analog voltage control loop. The analog voltage control loop performs analog proportional P control calculations on the analog signal. The AD samples and collects the signal at the output of the analog voltage control loop and converts it into a digital signal and sends it to the DA. The DA converts the digital signal into an analog signal as the reference signal for the analog current control loop. At the same time, the digital signal obtained by the AD sampling conversion is sent to the communicating slave via optical fiber. The analog current control loop uses the reference signal to calculate the analog signal and compares it with the triangular wave signal to obtain the PWM control signal.

[0050] 2) The slave control loop converts the digital signal obtained from the master control loop into an analog signal via the slave DA, and transmits it to the given input of the slave analog current control loop. The analog current control loop calculates and compares it with the triangle wave signal to obtain a PWM control signal, thereby achieving consistency in the master and slave outputs of the parallel power supply. At the same time, the slave's own effective value loop and analog voltage control loop continue to run and sample, and the input of the slave's own effective value loop also comes from the digital signal of the master;

[0051] 3) Each AC power supply receives the machine number and operating status of other AC power supplies through optical fiber communication. If the master machine stops or fails, the remaining operating AC power supplies will enter the master competition logic. In a very short time, the AC power supply with the smallest remaining machine number will become the master, changing the master position. At the same time, the given value of the analog current control loop is also synchronously switched to the current master data, thereby achieving smooth and seamless master-slave switching.

[0052] In step 1), the trigger signal of the AD sampling precedes the trigger signal of the optical fiber communication sending module by a time equal to the total time used for AD sampling and conversion. After the AD sampling completes the data conversion, it is immediately sent out through the optical fiber.

[0053] In steps 1) and 2), the DA trigger signal is issued when the optical fiber analysis module completely analyzes and updates a frame of data, so that the DA immediately converts the digital signal into an analog signal after receiving it, to ensure that the data delay is minimized and the parallel effect is optimized under this solution.

[0054] In steps 1) and 2), the analog voltage control loop and the analog current control loop are both analog proportional P control. A total of three sets of control parameters are designed for different output frequency modes. The mode switching is performed by controlling the electronic switch using an FPGA control signal. The three modes correspond to the startup phase, normal operation phase, and post-fault restart phase of the load operated by the AC power supply, respectively.

[0055] The host control loop utilizes a DSP RMS loop as the outermost loop for proportional-integral control, an analog voltage control loop as the middle loop for proportional control, and an analog current control loop as the innermost loop for proportional control, forming a triple-nested digital-analog hybrid control system. This completely disassembles the traditional digital control loop, reconstructing a "digital-analog-digital-analog" hybrid control loop. This provides an entry point for master-slave parallel control while maintaining control performance.

[0056] When the AC power supply operates as a slave, its effective value control output comes from the same position data as the master control loop. The slave analog voltage control loop continues to run and sample but does not use its data. This ensures that the analog voltage control loop output of the slave is not much different from that of the master, and there will be no major impact when switching between the master and slave states.

[0057] The aforementioned high-speed fiber-optic communication loop-reconstructed parallel master power supply system and its control method utilizes high-speed fiber-optic communication for parallel communication. Combining the efficiency, flexibility, and convenience of digital control with the stability and high performance of analog control, the system reconstructs the master control loop for digital-analog hybrid control and the slave control loop using the low latency of high-speed fiber-optic communication. Parallel master logic is designed to implement a parallel power supply system with arbitrary master-slave switching, achieving consistency in the master-slave output of the parallel power supply. An FPGA-based high-speed fiber-optic communication network is a key component of this system's implementation. The parallel loop reconstruction method breaks with the original control strategy, interweaving digital and analog control to reconstruct a more stable control loop. The parallel master logic system design enables arbitrary parallel operation and rapid, seamless master-slave switching. The present invention utilizes the strong anti-interference performance of optical fiber communication to increase its communication rate, reduce parallel synchronization delay, and improve parallel performance. The adopted digital-analog hybrid control strategy takes into account the convenience of digital control and the high stability and low loss characteristics of analog control. These designs enable the present invention to have many advantages such as low communication delay, strong anti-interference ability, easy parallelization, small master-slave phase difference, strong load capacity, high output stability, and strong system robustness.

[0058] The slave control loop begins with the conversion of the analog voltage control loop output sampled by the master AD into a digital signal. This signal is then transmitted via low-latency, high-speed fiber-optic communications and then, in the slave FPGA, is converted into a given signal for the analog current control loop via DA, thus achieving output consistency between the master and slave parallel power supplies. The slave's own RMS loop and analog voltage control loop continue to operate, with the RMS loop output also derived from the master data. This minimizes the difference between the slave's analog voltage control loop output and the master's. This prevents excessive impact during master-slave switching, which could cause a cascading power supply failure and shutdown. It also minimizes the adverse effects of different analog current control loop settings when switching from a slave to a master.

[0059] The specific working process is as follows:

[0060] During startup, the bus soft-start unit slowly raises the inlet voltage of the grid-side transformer to the same level as the grid, and the bus soft-start unit is cut out. During this process, the secondary side of the grid-side transformer also slowly changes and rises. The AC input is converted into a DC voltage with ripples through three diode rectifier bridges connected in series, and then connected to the DC bus LC filter unit to eliminate its ripples to obtain a stable DC bus Udc, which is provided to the single-phase inverter unit. The control unit performs closed-loop control through output voltage feedback and inductor current feedback to calculate and output the PWM control signals of each phase to control the IGBT switch group of the single-phase inverter topology structure to chop the output bus, and then the square wave voltage is converted into the designed sinusoidal AC voltage through the output LC filter unit of each phase. At this point, the single-machine AC output is completed.

[0061] An important prerequisite for the above control scheme to effectively eliminate the master-slave difference is a communication system that can efficiently transmit data information. At the same time, considering the safety, reliability and stability of system operation, a parallel master competition logic system is designed to ensure that this power supply system can automatically switch to the remaining power supplies and operate normally with load when any whole machine fails and exits parallel operation.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. For ordinary professional and technical personnel in this field, the specific technical solutions recorded in the aforementioned embodiments can be modified, or some of the technical features therein can be replaced by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.

Claims

1. A control method for a parallel competitive main power supply system with a high-speed optical fiber communication loop reconstruction, based on the parallel competitive main power supply system with a high-speed optical fiber communication loop reconstruction, comprising an optical fiber communication network and N AC power supplies; 2≤N≤6; the optical fiber communication network comprises N communication terminals, each of which corresponds to the N AC power supplies in a one-to-one manner, and two optical fibers, one for receiving and one for transmitting, are used between each two communication terminals to maintain real-time communication; each AC power supply comprises a front-stage uncontrolled rectifier unit and a rear-stage single-phase inverter unit; the uncontrolled rectifier unit comprises a busbar soft-phase inverter unit connected in sequence; The single-phase inverter unit comprises a control unit, an output bus connected to the control unit, and three pairs of IGBT switch groups and an output LC filter unit forming a single-phase inverter topology structure; the output LC filter unit is used to eliminate the ripple of the DC voltage with ripples, and the output LC filter unit is used to eliminate the ripple of the DC voltage with ripples to obtain a stable DC bus Udc; the single-phase inverter unit comprises a control unit, an output bus connected to the control unit, and three pairs of IGBT switch groups and an output LC filter unit forming a single-phase inverter topology structure; the output LC The filter unit is used to convert the square wave voltage transmitted from the IGBT switch group into a sinusoidal AC voltage; the control unit is used to perform closed-loop control calculation by sampling the input feedback of the bus soft start unit, the inductor current feedback of the output LC filter unit, and the output voltage feedback of the output bus, and output the PWM control signal of each of the three phases to control the single-phase inverter unit to chop the output bus to achieve the single-machine AC output of the AC power supply; the control unit adopts a parallel competition logic system to make each AC power supply have the same output mode, and any multiple AC power supplies have the ability to output in parallel, and any one or When multiple AC power supplies fail, they automatically exit parallel operation without affecting the normal operation of other AC power supplies; the diode rectifier bridge includes three diode rectifier bridges connected in series, and the first and last two diode rectifier bridges each have an output terminal connected to a DC bus LC filter unit; the control unit includes a host control loop and a slave control loop; the host control loop includes DSP, FPGA, AD sampling, analog voltage control loop, DA, analog current control loop and PWM; the slave control loop has the same structure as the host control loop; the AC power supply can operate independently at full load; it is characterized in that The following steps are involved: 1) The AC power supply of the smallest unit is used as the host. The DSP of the host control loop uses the proportional-integral (PI) control method to calculate the AC voltage RMS loop output. The FPGA calculates the digital voltage sinusoidal reference based on the AC voltage RMS loop output. The DA converts the digital voltage sinusoidal reference into an analog signal and transmits it to the reference input of the analog voltage control loop. The analog voltage control loop performs analog proportional P control calculations on the analog signal. The AD samples and collects the signal at the output of the analog voltage control loop and converts it into a digital signal and sends it to the DA. The DA converts the digital signal into an analog signal as the reference signal for the analog current control loop. At the same time, the digital signal obtained by the AD sampling conversion is sent to the communicating slave via optical fiber. The analog current control loop uses the reference signal to calculate the analog signal and compares it with the triangular wave signal to obtain the PWM control signal. 2) The slave control loop converts the digital signal obtained from the master control loop into an analog signal via the slave DA, and transmits it to the given input of the slave analog current control loop. The analog current control loop calculates and compares it with the triangle wave signal to obtain a PWM control signal, thereby achieving consistency in the master and slave outputs of the parallel power supply. At the same time, the slave's own effective value loop and analog voltage control loop continue to run and sample, and the input of the slave's own effective value loop also comes from the digital signal of the master; 3) Each AC power supply receives the machine number and operating status of other AC power supplies through optical fiber communication. If the main AC power supply stops or fails, the remaining AC power supplies enter the master competition logic, and the AC power supply with the smallest remaining number becomes the master. The master position is changed, and the given value of the analog current control loop is also synchronously switched to the current master data.

2. The control method for a parallel competing main power supply system for high-speed optical fiber communication loop reconstruction according to claim 1, characterized in that: In step 1), the trigger signal of the AD sampling precedes the trigger signal of the optical fiber communication transmission module by a time equal to the total time used for AD sampling and conversion. The AD sampling sends the data out through the optical fiber immediately after the data conversion is completed; In steps 1) and 2), the trigger signal of the DA is issued when the optical fiber analysis module completely analyzes and updates a frame of data, so that the DA converts the digital signal into an analog signal immediately after receiving it; In steps 1) and 2), the analog voltage control loop and the analog current control loop are both analog proportional P control. A total of three sets of control parameters are designed for different output frequency modes. The mode switching is performed by controlling the electronic switch using an FPGA control signal. The three modes correspond to the startup phase, normal operation phase, and post-fault restart phase of the load operated by the AC power supply, respectively.

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