A digital-analog hybrid low-power automatic gain control amplifier

Abstract

A kind of digital-analog hybrid low-power automatic gain control amplifier, its remarkable feature is low power consumption.The system is mainly composed of ultra-low power 4bit programmable operational amplifier, peak detection circuit, dynamic comparator, latch and Verilog RTL control module.The input signal is passed through 4bit low-power programmable operational amplifier and then passed through peak detection circuit, and the peak of the circuit is compared with dynamic comparator, the output result of comparator is output to latch, and the output of latch is input to Verilog RTL control module.Digital module outputs different control code to control the preceding ultra-low power programmable operational amplifier, so that the gain increases or decreases until the gain reaches between the two reference voltages previously input to dynamic comparator, VREF1 and VREF2.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication, in particular to a digital-analog hybrid low-power automatic gain control amplifier. BACKGROUND

[0002] Automatic gain control amplifier has a wide range of applications. In the field of communication, automatic gain control amplifier is generally located in the low-pass filter after the level, the analog-to-digital converter before the level in order to offset the fading phenomenon caused by radio signal loss problem, its role is to reduce the output signal amplitude in a small range of input signal amplitude variation, so as to provide the appropriate input for the circuit module of the latter. For weak input signal, automatic gain control amplifier increases the amplification, so that the output signal meets the quantization requirements of ADC; for larger input signal, the gain of automatic gain control amplifier is reduced to negative gain to reduce the amplitude of the signal. In addition, automatic gain control amplifier is also widely used in wired communication, hard disk reading, radar, laser and other systems.

[0003] However, with the continuous progress of science and technology, the continuous upgrading of consumption, the traditional automatic gain control amplifier can not meet the performance requirements of today's chip. The feature size of CMOS process is continuously reduced, and the feature cutoff frequency of the device is continuously improved. The high integration, low power consumption and low cost of automatic gain control amplifier under new process are the research hotspots today. SUMMARY

[0004] To solve the above technical problems, the present application provides a digital-analog hybrid low-power automatic gain control amplifier, which has the advantages of low power consumption.

[0005] To achieve the above technical purpose, the technical scheme adopted is: a digital-analog hybrid low-power automatic gain control amplifier, comprising an ultra-low power 4bit programmable operational amplifier, a peak detection circuit, a dynamic comparator, a latch and a Verilog RTL control module. The signal is sent to the peak detection circuit through the ultra-low power 4bit programmable operational amplifier. The peak detection circuit detects the highest value of the signal and sends it to the dynamic comparator. The dynamic comparator has two preset reference voltages VREF1 and VREF2. The peak voltage is compared with the reference voltages VREF1 and VREF2. The results of the comparator are sent to the latch and stored, and a two-bit binary code is output. The Verilog RTL control module increases or decreases the gain of the ultra-low power 4bit programmable operational amplifier according to the two-bit binary code.

[0006] Further, the ultra-low power consumption 4-bit programmable operational amplifier comprises a full-transistor switch matrix, a first operational amplifier OPAl and an equivalent resistor; the full-transistor switch matrix has four total control switches S0, S1, S2 and S3 controlled by a two-bit binary code according to a Verilog RTL control module, an output OUT of the full-transistor switch matrix is connected with an output of the first operational amplifier OPAl, an input IN of the full-transistor switch matrix is connected with a negative terminal of the first operational amplifier OPAl, a positive terminal of the first operational amplifier OPAl is connected with an external power supply, a BIAS terminal of the full-transistor switch matrix is connected with one end of the equivalent resistor, and the other end of the equivalent resistor is a signal input terminal.

[0007] Further, the equivalent resistor is an NMOS transistor or a PMOS transistor, a gate of the NMOS transistor or the PMOS transistor is connected with the BIAS terminal, a source of the NMOS transistor or the PMOS transistor is connected with the signal input terminal, and a drain of the NMOS transistor or the PMOS transistor is connected with the negative terminal of the first operational amplifier OPAl.

[0008] Further, the full-transistor switch matrix comprises transistors M1-M16, switches SW1-SW15, total control switches S0, S1, S2 and S3.

[0009] The gates of the transistors M1-M16 are connected to the bias voltage BIAS, the input VIN is connected to the source of the transistor M1, the source of the transistor M2 is connected to the 0 terminal of the switch SW8 and the drain of the transistor M1, the drain of the transistor M2 is connected to the source of the transistor M3 and the 1 terminal of the switch SW8, the drain of the transistor M3 is connected to the source of the transistor M4 and the 0 terminal of the switch SW7, the drain of the transistor M4 is connected to the source of the transistor M5 and the 1 terminal of the switch SW7, the drain of the transistor M5 is connected to the source of the transistor M6 and the 0 terminal of the switch SW6, the drain of the transistor M6 is connected to the source of the transistor M7 and the 1 terminal of the switch SW6, the drain of the transistor M7 is connected to the source of the transistor M8 and the 0 terminal of the switch SW5, the drain of the transistor M8 is connected to the source of the transistor M9 and the 1 terminal of the switch SW5, the drain of the transistor M9 is connected to the source of the transistor M10 and the 0 terminal of the switch SW4, the drain of the transistor M10 is connected to the source of the transistor M11 and the 1 terminal of the switch SW4, the drain of the transistor M11 is connected to the source of the transistor M12 and the 0 terminal of the switch SW3, the drain of the transistor M12 is connected to the source of the transistor M13 and the 1 terminal of the switch SW3, the drain of the transistor M13 is connected to the source of the transistor M14 and the 0 terminal of the switch SW2, the drain of the transistor M14 is connected to the source of the transistor M15 and the 1 terminal of the switch SW2, the drain of the transistor M15 is connected to the source of the transistor M16 and the 0 terminal of the switch SW1, the drain of the transistor M16 is connected to the 1 terminal of the switch SW1;

[0010] The single terminal of the switch SW8 is connected to the 0 terminal of the switch SW12, the single terminal of the switch SW7 is connected to the 1 terminal of the switch SW12, the single terminal of the switch SW6 is connected to the 0 terminal of the switch SW11, the single terminal of the switch SW5 is connected to the 1 terminal of the switch SW11, the single terminal of the switch SW4 is connected to the 0 terminal of the switch SW10, the single terminal of the switch SW3 is connected to the 1 terminal of the switch SW10, the single terminal of the switch SW2 is connected to the 0 terminal of the switch SW9, the single terminal of the switch SW1 is connected to the 1 terminal of the switch SW9, the single terminal of the switch SW12 is connected to the 0 terminal of the switch SW14, the single terminal of the switch SW11 is connected to the 1 terminal of the switch SW14, the single terminal of the switch SW10 is connected to the 0 terminal of the switch SW13, the single terminal of the switch SW9 is connected to the 1 terminal of the switch SW13, the single terminal of the switch SW14 is connected to the 0 terminal of the switch SW15, the single terminal of the switch SW13 is connected to the 1 terminal of the switch SW15, and the output terminal of the switch SW15 is connected to the OUT terminal.

[0011] The total control switch S0 is connected with the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 and SW8; the total control switch S1 is connected with the switches SW9, SW10, SW11 and SW12; the total control switch S2 is connected with the switches SW13 and SW14; and the total control switch S1 is connected with the control switch SW15.

[0012] Further, the peak detection circuit comprises a second operational amplifier OPA2, a transistor and a capacitor, the transistor is an NMOS transistor or a PMOS transistor, the positive terminal of the second operational amplifier OPA2 is connected with the output of the ultra-low power 4-bit programmable operational amplifier, the output terminal of the second operational amplifier OPA2 is connected with the gate of the transistor, and the source of the transistor is connected with the negative terminal of the second operational amplifier OPA2, the capacitor and the output terminal of the peak detection circuit respectively.

[0013] Further, the specific method for adjusting the gain of the ultra-low power 4-bit programmable operational amplifier according to the two-bit binary code by the Verilog RTL control module is as follows: the reference voltage VREF2 is greater than the reference voltage VREF1, the latch stores and outputs the two-bit binary code 00, 01 and 11 of the output of the comparator; the Verilog RTL module receives the two-bit binary code and outputs the control code COTROL_CODE, the control code COTROL_CODE is a four-bit binary code and has an initial value;

[0014] When the peak voltage is lower than the reference voltage VREF1, the output of the latch is 00, at this time, the value of the control code COTROL_CODE is increased by 1, when the peak voltage is higher than VREF2, the output of the latch is 11, and the output value of the control code COTROL_CODE is decreased by 1, when the peak voltage is between the reference voltages VREF2 and VREF2, the output of the latch is 01, and the output value of the control code COTROL_CODE is unchanged.

[0015] The Verilog RTL module has four control code ports, each port outputs a control code, and the control codes from high to low are connected with the total control switches S3, S2, S1 and S0 in sequence, according to the value of each control code, the total control switches S3, S2, S1 and S0 control the connection of the switches connected with the corresponding value terminals, and the gain is added or subtracted.

[0016] The present application has the following beneficial effects:

[0017] 1. The application proposes an ultra-low power 4bit programmable operational amplifier, a peak detection circuit, a dynamic comparator, a latch and a Verilog RTL module. Compared with a conventional digital-controlled automatic gain control operational amplifier, the application does not need an additional analog-to-digital converter module for signal conversion. In addition, the application adopts a dynamic comparator, which has lower power consumption than a conventional static comparator. Therefore, the application has higher integration and lower power consumption.

[0018] 2. The application proposes a new type of ultra-low power 4bit programmable operational amplifier. The amplifier uses MOS transistors in the linear region to replace the conventional resistance array, which reduces the overall power consumption of the circuit and reduces the heat loss caused by the resistance. At the same time, when the layout of the integrated circuit is designed, the layout area is greatly reduced, and the cost of tape-out is saved.

[0019] 3. Through the improvement of the programmable operational amplifier, the complexity of the Verilog RTL control module is greatly improved. The benefits are that the number of digital transistors in the Verilog RTL control module is reduced, which can reduce the overall power consumption and layout area of the digital module, and has higher integration. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is the overall structure diagram of the application;

[0021] Figure 2 is the structure diagram of the prior art operational amplifier;

[0022] Figure 3 is the structure diagram of the ultra-low power 4bit programmable operational amplifier of the application;

[0023] Figure 4 is Figure 3 is the schematic diagram of the deep linear region of the transistor;

[0024] Figure 5 is Figure 3 is the structure diagram of the full-transistor switch matrix;

[0025] Figure 6 is the peak detection circuit diagram of the application;

[0026] Figure 7 is the conventional parallel resistance switch array diagram;

[0027] Figure 8 is the gain addition and subtraction state transition diagram of the application;

[0028] Figure 9 is the Verilog RTL control module flowchart;

[0029] Figure 10 is the circuit simulation diagram of the application;

[0030] Figure 11 The peak detection circuit simulation diagram of the present application. DETAILED DESCRIPTION

[0031] As Figure 1 shown, a digital-analog hybrid low-power automatic gain control amplifier includes an ultra-low-power 4bit programmable operational amplifier, a peak detection circuit, a dynamic comparator, a latch and a Verilog RTL control module, a signal is transmitted to the peak detection circuit through the ultra-low-power 4bit programmable operational amplifier, the peak detection circuit detects the highest value of the signal and sends it to the dynamic comparator, the dynamic comparator has two preset reference voltages VREF1 and VREF2, the peak voltage is compared with the reference voltages VREF1 and VREF2, the result of the comparator is sent to the latch and stored, and a two-bit binary code is output, and the Verilog RTL control module adds or subtracts the gain of the ultra-low-power 4bit programmable operational amplifier according to the two-bit binary code.

[0032] As Figure 3 shown, the ultra-low-power 4bit programmable operational amplifier includes a full-transistor switch matrix, a first operational amplifier OPA1 and an equivalent resistance; the full-transistor switch matrix has four total control switches S0, S1, S2 and S3 controlled by the Verilog RTL control module according to the two-bit binary code, instead of a traditional parallel resistance switch array as Figure 7 shown, the output OUT of the full-transistor switch matrix is connected with the output of the first operational amplifier OPA1, the input IN of the full-transistor switch matrix is connected with the negative terminal of the first operational amplifier OPA1, the positive terminal of the first operational amplifier OPA1 is connected with an external power supply, the BIAS terminal of the full-transistor switch matrix is connected with one end of the equivalent resistance, and the other end of the equivalent resistance is a signal input terminal.

[0033] The equivalent resistance is an NMOS transistor or a PMOS transistor, the gate of the NMOS transistor or the PMOS transistor is connected with the BIAS terminal, the source of the NMOS transistor or the PMOS transistor is connected with the signal input terminal, and the drain of the NMOS transistor or the PMOS transistor is connected with the negative terminal of the first operational amplifier OPA1.

[0034] As Figure 5 shown, the full-transistor switch matrix includes transistors M1-M16, switches SW1-SW15, total control switches S0, S1, S2 and S3.

[0035] The gates of the transistors M1-M16 are connected to the bias voltage BIAS, the input VIN is connected to the source of the transistor M1, the source of the transistor M2 is connected to the 0 terminal of the switch SW8 and the drain of the transistor M1, the drain of the transistor M2 is connected to the source of the transistor M3 and the 1 terminal of the switch SW8, the drain of the transistor M3 is connected to the source of the transistor M4 and the 0 terminal of the switch SW7, the drain of the transistor M4 is connected to the source of the transistor M5 and the 1 terminal of the switch SW7, the drain of the transistor M5 is connected to the source of the transistor M6 and the 0 terminal of the switch SW6, the drain of the transistor M6 is connected to the source of the transistor M7 and the 1 terminal of the switch SW6, the drain of the transistor M7 is connected to the source of the transistor M8 and the 0 terminal of the switch SW5, the drain of the transistor M8 is connected to the source of the transistor M9 and the 1 terminal of the switch SW5, the drain of the transistor M9 is connected to the source of the transistor M10 and the 0 terminal of the switch SW4, the drain of the transistor M10 is connected to the source of the transistor M11 and the 1 terminal of the switch SW4, the drain of the transistor M11 is connected to the source of the transistor M12 and the 0 terminal of the switch SW3, the drain of the transistor M12 is connected to the source of the transistor M13 and the 1 terminal of the switch SW3, the drain of the transistor M13 is connected to the source of the transistor M14 and the 0 terminal of the switch SW2, the drain of the transistor M14 is connected to the source of the transistor M15 and the 1 terminal of the switch SW2, the drain of the transistor M15 is connected to the source of the transistor M16 and the 0 terminal of the switch SW1, and the drain of the transistor M16 is connected to the 1 terminal of the switch SW1.

[0036] The single terminal of the switch SW8 is connected to the 0 terminal of the switch SW12, the single terminal of the switch SW7 is connected to the 1 terminal of the switch SW12, the single terminal of the switch SW6 is connected to the 0 terminal of the switch SW11, the single terminal of the switch SW5 is connected to the 1 terminal of the switch SW11, the single terminal of the switch SW4 is connected to the 0 terminal of the switch SW10, the single terminal of the switch SW3 is connected to the 1 terminal of the switch SW10, the single terminal of the switch SW2 is connected to the 0 terminal of the switch SW9, the single terminal of the switch SW1 is connected to the 1 terminal of the switch SW9, the single terminal of the switch SW12 is connected to the 0 terminal of the switch SW14, the single terminal of the switch SW11 is connected to the 1 terminal of the switch SW14, the single terminal of the switch SW10 is connected to the 0 terminal of the switch SW13, the single terminal of the switch SW9 is connected to the 1 terminal of the switch SW13, the single terminal of the switch SW14 is connected to the 0 terminal of the switch SW15, the single terminal of the switch SW13 is connected to the 1 terminal of the switch SW15, and the output terminal of the switch SW15 is connected to the OUT terminal.

[0037] The total control switch S0 is connected with the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 and SW8; the total control switch S1 is connected with the switches SW9, SW10, SW11 and SW12; the total control switch S2 is connected with the switches SW13 and SW14; and the total control switch S1 is connected with the control switch SW15.

[0038] As shown in Figure 6 The peak value detection circuit comprises a second operational amplifier OPA2, a transistor and a capacitor, the transistor is an NMOS transistor or a PMOS transistor, the positive terminal of the second operational amplifier OPA2 is connected with the output of the ultra-low power 4-bit programmable operational amplifier, the output terminal of the second operational amplifier OPA2 is connected with the gate of the transistor, and the source of the transistor is connected with the negative terminal of the second operational amplifier OPA2 and the output of the peak value detection circuit respectively.

[0039] The dynamic comparator is characterized in that a dynamic circuit is used to reduce the static power consumption of the comparator, the negative terminal of the dynamic comparator is connected with the reference voltages VREF1 and VREF2, the output of the peak value detection circuit, and the output of the dynamic comparator is connected with a latch. The latch is characterized in that the input of the latch is connected with the output of the dynamic comparator, and the latch stores the output of the dynamic comparator and delivers the result to the Verilog RTL control module.

[0040] The specific method of the Verilog RTL control module for increasing or decreasing the gain of the ultra-low power 4-bit programmable operational amplifier according to the two-bit binary code is as follows: the reference voltage VREF2 is greater than the reference voltage VREF1, the latch stores and outputs the two-bit binary code 00, 01 and 11; the Verilog RTL control module receives the two-bit binary code output control code COTROL_CODE, the control code COTROL_CODE is a four-bit binary code with an initial value; when the peak voltage is lower than the reference voltage VREF1, the output of the latch is 00, at this time, the value of the control code COTROL_CODE is increased by 1; when the peak voltage is higher than VREF2, the output of the latch is 11, and the output value of the control code COTROL_CODE is decreased by 1; when the peak voltage is between the reference voltages VREF2 and VREF2, the output of the latch is 01, and the output value of the control code COTROL_CODE is unchanged; the Verilog RTL module has four control code ports, each port outputs one control code, and the control codes are connected with the total control switches S3, S2, S1 and S0 from high to low; according to the value of each control code, the total control switches S3, S2, S1 and S0 control the connection of the switches connected with the corresponding value terminals, and the gain is increased or decreased.

[0041] For example, the initial value of the control code COTROL_CODE is 0100, the high bits to low bits are 0, 1, 0, 0, at this time the 0 end of the switch SW15 connected by the total control switch S3 is closed, the 1 end of the switch SW13 and the switch SW12 connected by the total control switch S2 is closed, the 0 end of the switch SW9, the switch SW10, the switch SW11, the switch SW12 connected by the total control switch S1 is closed, the 0 end of the switch SW1, the switch SW2, the switch SW3, the switch SW4, the switch SW5, the switch SW6, the switch SW7, the switch SW8 connected by the total control switch S0 is closed, when the control code COTROL_CODE is changed from 0100 to 0101 by increasing 1, on the basis of the above, the switch SW1, the switch SW2, the switch SW3, the switch SW4, the switch SW5, the switch SW6, the switch SW7, the switch SW8 connected by the total control switch S0 is changed to the 1 end closed, when the control code COTROL_CODE is changed from 0100 to 0011 by decreasing 1, on the basis of the above, the switch SW13 and the switch SW12 connected by the total control switch S2 is changed to the 0 end closed, the switch SW9, the switch SW10, the switch SW11, the switch SW12 connected by the total control switch S1 is changed to the 1 end closed, the switch SW1, the switch SW2, the switch SW3, the switch SW4, the switch SW5, the switch SW6, the switch SW7, the switch SW8 connected by the total control switch S0 is changed to the 1 end closed, the control code COTROL_CODE is increased to 1111 at most, and is decreased to 0000 at least.

[0042] Figure 1 is the whole circuit of the programmable operational amplifier, Figure 2 is the structure of the traditional inverse proportional operational amplifier, and according to the principle of virtual short of the operational amplifier, the output is:

[0043]

[0044] The same design Figure 3 M1 in the above formula can be regarded as an equivalent resistance R of the deep linear region M1 Therefore, the other MOS tubes can be regarded as integer times of the resistance. Therefore, the output of the whole circuit can be represented as

[0045]

[0046] In the formula, n is the decimal number corresponding to the binary control code.

[0047] Figure 4 is the schematic diagram of the transistor working in the linear region in Figure 3 The resistance between the source and the drain of the transistor working in the deep linear region can be represented by a linear resistance, and the resistance is equal to

[0048]

[0049] where V gs is the transistor gate-source voltage, V TH is the transistor threshold voltage, is the transistor width-length ratio, C ox is the transistor gate oxide capacitance, u n is the electron vacuum migration rate, V DS is the transistor drain-source voltage, the transistor can be regarded as a resistance with the resistance value controlled by the overdrive voltage, as long as V DS ≤ 2(V GS -V TH ), by controlling the appropriate bias voltage and width-length ratio, the appropriate equivalent resistance can be obtained. The ultra-low power 4-bit programmable operational amplifier uses all-transistors to replace the pure resistance module, and the schematic diagram is as shown in Figure 5 , and the transistor replaces the resistance. The control principle is: a single-pole double-throw switch is used for logic control, when the input control code is 0000, all single-pole double-throw switches in S0 are closed at the 0 end, all switches in S1, S2 and S3 are closed at the 0 end, therefore, the input signal will only be input from the 0 port of SW15 in S3 to the 0 port of SW14 in S2 to SW12 in S1, and the signal will enter SW8 in S0 through SW12, because SW8 is open, therefore, the 0 end of SW8 is open, and thus the signal will flow through two linear region MOS tubes M1 and M2.

[0050] When the input control code is 0001, the 1 end of the single-pole double-throw switch in S0 is closed, and the 0 end of S1, S2 and S3 is closed, therefore, the input signal will only be input from the 0 port of SW15 in S3 to the 0 port of SW14 in S2 to SW12 in S1, and the signal will enter SW8 in S0 through SW12, because SW8 is open, therefore, the 1 end of SW8 is open, and thus the signal will flow through two linear region MOS tubes M1 and M2, which is different from Figure 7 , in which two traditional circuits use resistance arrays, which increases the power consumption and the area of the layout, and in order to control the resistance array, the complexity of the digital circuit has to be increased, which indirectly increases the design complexity and the power consumption of the entire circuit. The all-transistor array used in the present application uses binary control code to switch the switch, which not only greatly reduces the heat loss and waste of layout area caused by the use of resistance, but also reduces the design complexity of the digital control circuit, thereby reducing the static power consumption of the digital circuit.

[0051] Figure 6is a peak detection circuit, which functions to save the peak value of the input useful signal and transmit it to the comparator for comparison. It is composed of an operational amplifier, an NMOS transistor and a capacitor. When the output value of the operational amplifier is higher than the threshold voltage of the NMOS transistor, the output charges the capacitor; when the output voltage is lower than the threshold voltage of the transistor, the charge in the capacitor is released, thus the voltage peak value can be kept.

[0052] Figure 9 is the control flow of the Verilog RTL control module, which outputs a control code named COTROL_CODE. The control code COTROL_CODE is a four-bit binary code. When the latch outputs a two-bit binary code, the control circuit creates three states, 00 corresponding to UP, 11 corresponding to DOWN and 01 corresponding to STEADY. Two reference points, VREF1 and VREF2, are created in the dynamic comparator. When the peak value of the output signal is lower than the two reference voltages, the output of the latch is 00, the value of the control code COTROL_CODE is increased by 1. When the peak value of the output signal is higher than the two reference voltages, the output of the latch is 11, the value of the control code COTROL_CODE is decreased by 1. When the peak value of the output signal is between the two reference voltages, the output of the latch is 01, the value of the control code COTROL_CODE is unchanged. When the defined output value reaches the maximum value 1111, the output value remains unchanged. When the output value reaches 0000, the output value remains the minimum value. In the whole process of the circuit operation, the output will eventually reach a stable state.

[0053] The final effect is shown in Figure 10 The final simulation function diagram of the comparator is shown in the figure, the output of the comparator is low, thus the control code of COTROL_CODE is increased by 1, thus the output of the amplifier is continuously multiplied, the control code is continuously increased from 0001 to 1001, the peak value of the amplifier signal is increased to between VREF1 and VREF2, the output of the comparator is immediately changed to 01, and the output is stable at this time. Figure 11 is the simulation diagram of the output voltage and peak detection circuit, the peak detection circuit tracks the output signal well.

[0054] Table 1 Comparison of performance parameters of the present application and other literatures

[0055]

[0056] From Table 1, it can be seen that the power consumption of the automatic gain control operational amplifier in this paper is greatly reduced compared with the other three.

[0057] [1]Wu C P, Tsao H W. A 110-MHz 84-dB CMOS Programmable Gain Amplifier With Integrated RSSI Function [J]. IEEE Journal of Solid-State Circuits, 2005, 40(6): p. 1249-1258.

[0058] [2]Yao H Y. Design of Digital-Assisted DC Offset Cancellation Automatic Gain Control Circuit [D]. Southeast University, 2016.

[0059] [3]Tacconi E J, Christiansen C F. A wide range and high speed automatic gain control [C] / / Particle Accelerator Conference. IEEE, 1993.

Claims

1. A hybrid digital-to-analog low power automatic gain control amplifier, characterized by: The peak detection circuit, the dynamic comparator, the latch and the Verilog RTL control module are included, the signal is transported to the peak detection circuit through the ultra-low power 4bit programmable operational amplifier, the peak detection circuit detects the highest value of the signal and sends it to the dynamic comparator, the dynamic comparator has two preset reference voltages VREF1 and VREF2, the peak voltage is compared with the reference voltages VREF1 and VREF2, the result of the comparator is sent to the latch and stored, and two-bit binary code is output, and the Verilog RTL control module adds or subtracts the gain of the ultra-low power 4bit programmable operational amplifier according to the two-bit binary code. The ultra-low power 4bit programmable operational amplifier includes a full-transistor switch matrix, a first operational amplifier OPA1 and an equivalent resistance, the full-transistor switch matrix has four total control switches S0, S1, S2 and S3 controlled by the Verilog RTL control module according to two-bit binary code, the output OUT of the full-transistor switch matrix is connected with the output of the first operational amplifier OPA1, the input IN of the full-transistor switch matrix is connected with the negative end of the first operational amplifier OPA1, the positive end of the first operational amplifier OPA1 is connected with an external power supply VCM, the BIAS end of the full-transistor switch matrix is connected with one end of the equivalent resistance, and the other end of the equivalent resistance is a signal input end; The equivalent resistance is a linear region NMOS transistor or PMOS transistor, the gate of the NMOS transistor or the PMOS transistor is connected with the BIAS end, the source of the NMOS transistor or the PMOS transistor is connected with the signal input end, and the drain of the NMOS transistor or the PMOS transistor is connected with the negative end of the first operational amplifier OPA1; The full-transistor switch matrix includes transistors M1-M16, switches SW1-SW15, total control switches S0, S1, S2 and S3. The gate of the transistor M1~M16 is connected with the bias voltage BIAS, the input VIN is connected with the source of the transistor M1, the source of the transistor M2 is connected with the 0 end of the switch SW8 and the drain of the transistor M1, the drain of the transistor M2 is connected with the source of the transistor M3 and the 1 end of the switch SW8, the drain of the transistor M3 is connected with the source of the transistor M4 and the 0 end of the switch SW7, the drain of the transistor M4 is connected with the source of the transistor M5 and the 1 end of the switch SW7, the drain of the transistor M5 is connected with the source of the transistor M6 and the 0 end of the switch SW6, the drain of the transistor M6 is connected with the source of the transistor M7 and the 1 end of the switch SW6, the drain of the transistor M7 is connected with the source of the transistor M8 and the 0 end of the switch SW5, the drain of the transistor M8 is connected with the source of the transistor M9 and the 1 end of the switch SW5, the drain of the transistor M9 is connected with the source of the transistor M10 and the 0 end of the switch SW4, the drain of the transistor M10 is connected with the source of the transistor M11 and the 1 end of the switch SW4, the drain of the transistor M11 is connected with the source of the transistor M12 and the 0 end of the switch SW3, the drain of the transistor M12 is connected with the source of the transistor M13 and the 1 end of the switch SW3, the drain of the transistor M13 is connected with the source of the transistor M14 and the 0 end of the switch SW2, the drain of the transistor M14 is connected with the source of the transistor M15 and the 1 end of the switch SW2, the drain of the transistor M15 is connected with the source of the transistor M16 and the 0 end of the switch SW1, the drain of the transistor M16 is connected with the 1 end of the switch SW1; The single end of the switch SW8 is connected with the 0 end of the switch SW12, the single end of the switch SW7 is connected with the 1 end of the switch SW12, the single end of the switch SW6 is connected with the 0 end of the switch SW11, the single end of the switch SW5 is connected with the 1 end of the switch SW11, the single end of the switch SW4 is connected with the 0 end of the switch SW10, the single end of the switch SW3 is connected with the 1 end of the switch SW10, the single end of the switch SW2 is connected with the 0 end of the switch SW9, the single end of the switch SW1 is connected with the 1 end of the switch SW9, the single end of the switch SW12 is connected with the 0 end of the switch SW14, the single end of the switch SW11 is connected with the 1 end of the switch SW14, the single end of the switch SW10 is connected with the 0 end of the switch SW13, the single end of the switch SW9 is connected with the 1 end of the switch SW13, the single end of the switch SW14 is connected with the 0 end of the switch SW15, the single end of the switch SW13 is connected with the 1 end of the switch SW15, the output end of the switch SW15 is connected with the OUT end; The total control switch S0 is connected with the switch SW1, the switch SW2, the switch SW3, the switch SW4, the switch SW5, the switch SW6, the switch SW7, the switch SW8; the total control switch S1 is connected with the switch SW9, the switch SW10, the switch SW11, the switch SW12; the total control switch S2 is connected with the switch SW13, the switch SW14; the total control switch S1 is connected with the control switch SW15.

2. A hybrid digital-to-analog low power automatic gain control amplifier as claimed in claim 1, characterized in that: The peak detection circuit comprises a second operational amplifier OPA2, a transistor and a capacitor, the transistor is an NMOS transistor or a PMOS transistor, the positive terminal of the second operational amplifier OPA2 is connected with the output of the ultra-low power 4-bit programmable operational amplifier, the output terminal of the second operational amplifier OPA2 is connected with the gate of the transistor, and the source of the transistor is connected with the negative terminal of the second operational amplifier OPA2, the capacitor and the output terminal of the peak detection circuit respectively.

3. The hybrid digital-to-analog low power automatic gain control amplifier of claim 1, wherein: The specific method for adjusting the gain of the ultra-low power 4-bit programmable operational amplifier according to the two-bit binary code by the Verilog RTL control module is as follows: the reference voltage VREF2 is greater than the reference voltage VREF1, the latch stores and outputs the two-bit binary code 00, 01 and 11 of the output of the comparator; the Verilog RTL module receives the two-bit binary code and outputs the control code COTROL_CODE, the control code COTROL_CODE is a four-bit binary code and has an initial value; When the peak voltage is lower than the reference voltage VREF1, the output of the latch is 00, at this time, the value of the control code COTROL_CODE is increased by 1, when the peak voltage is higher than VREF2, the output of the latch is 11, and the output value of the control code COTROL_CODE is reduced by 1, when the peak voltage is between the reference voltages VREF2 and VREF2, the output of the latch is 01, and the output value of the control code COTROL_CODE is unchanged; The Verilog RTL module has four output ports, each port outputs a control code, and the control codes from high to low are connected with the total control switches S3, S2, S1 and S0 in sequence, according to the value of each control code, the total control switches S3, S2, S1 and S0 control the connection of the switches connected with the corresponding value terminals, and the gain is added or subtracted.

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