Multiplexer with high linearity analog switch

Abstract

A multiplexer with high linearity analog switches. The multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to multiplexers, and more specifically, to main pass switch of multiplexers. BACKGROUND

[0002] Analog multiplexers include switches that pass high frequency analog input signals from inputs of the multiplexer to outputs of the multiplexer. The switches can include metal-oxide-silicon (MOS) transistors. When the transistors are enabled, the transistors act as resistors through which the input signals pass. If the resistance associated with the transistors is not constant, then the transistors introduce harmonics of the input signals to the outputs of the multiplexer. This is undesirable.

[0003] All of the subject matter discussed in the Background section is not necessarily prior art, and should not be assumed to be prior art merely because it is discussed in the Background section. In general, the subject matter discussed in the Background section as well as associated descriptions found in the descriptions of the figures can provide background information for understanding the present disclosure. Accordingly, such subject matter can not be assumed to be prior art against a presently claimed disclosure. SUMMARY

[0004] Embodiments of the present disclosure provide a multiplexer having a main pass transistor that maintains a relatively constant resistance when passing signals from inputs of the multiplexer to outputs of the multiplexer. The multiplexer achieves the constant resistance of the transistor by maintaining a constant gate-to-source voltage (VGS) of the transistor. The multiplexer includes two bootstrap circuits coupled to a source terminal and a gate terminal of the transistor. The two bootstrap circuits operate alternately to maintain the constant VGS in operation. BRIEF DESCRIPTION OF DRAWINGS

[0005] Reference will now be made to the drawings, which are provided by way of example only. In the drawings, like reference numerals identify similar elements or acts. In some of the drawings, different reference numerals can be used to identify the same or similar elements. The size and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements can have been exaggerated in the drawings and / or some features can have been somewhat generalized in the interest of brevity and clarity.

[0006] Figure 1 is a block diagram of a multiplexer according to one embodiment.

[0007] Figure 2 is a schematic diagram of a switch circuit used in a multiplexer according to one embodiment.

[0008] Figure 3is a schematic diagram of a switch circuit used in a multiplexer according to one embodiment.

[0009] Figures 4 to 7 is a timing diagram of signals within a multiplexer according to one embodiment.

[0010] Figure 8 is a block diagram of an integrated circuit according to one embodiment.

[0011] Figure 9 is a flowchart of a method for operating a multiplexer according to one embodiment.

[0012] Figure 10 is a flowchart of a method for operating a multiplexer according to one embodiment. DETAILED DESCRIPTION

[0013] In the following description, for purposes of providing a thorough understanding of the various embodiments disclosed, certain specific details are set forth. However, it will be recognized by those of ordinary skill in the art that the embodiments can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known aspects of integrated circuits have not been described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0014] Unless the context clearly requires otherwise, throughout the description, the words “comprise,” “comprising,” “include,” “including,” and the like, are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense. Additionally, the words “first,” “second,” and like terms are used only to distinguish one element from another, and do not otherwise limit the elements. Moreover, recitation of “one or more of’ something are intended to mean any single one of something or any combination of one or more things.

[0015] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0016] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its broadest sense, including either or.

[0017] Figure 1is a block diagram of a multiplexer 102 according to one embodiment. The multiplexer 102 includes N input terminals In 1 through In N and an output. For each input terminal, the multiplexer includes a respective switch circuit 103 that passes a signal from the input to the output when the input is selected. Each switch circuit 103 includes a main switch 104, a first bootstrap circuit 106, and a second bootstrap circuit 108. The main switch 104 and the bootstrap circuits 106 and 108 cooperate to pass a signal from an input terminal In of the multiplexer 102 to an output terminal Out without adding harmonic distortion. Each switch circuit 103 receives a respective selection signal Sel 1 through Sel N. The selection signals select one of the switches 103 to pass a signal to the output Out. Only one switch circuit 103 is selected at a time.

[0018] The following description describes the function of one switch circuit 103. Each switch circuit 103 works in the same way. When the main switch 104 is activated or turned on, the main switch 104 passes a signal from the input terminal In to the output terminal Out. The main switch 104 has a resistance when activated. If the resistance does not remain constant, the signal provided to the output terminal includes not only the input signal, but also harmonics of the input signal. Harmonics correspond to signals having frequencies that are multiples of the frequency of the input signal. Thus, if the input signal has a frequency f, the output signal can include components having frequencies of 2*f, 3*f, etc. if the resistance of the main switch does not remain constant.

[0019] The main switch 104 can have a plurality of terminals including a gate terminal, an input terminal, and then an output terminal. The input terminal of the main switch 104 is coupled to the input terminal In of the multiplexer 102. The output terminal of the main switch 104 is coupled to the output terminal Out of the multiplexer 102. The gate terminal receives a control signal that selectively activates and deactivates the main switch 104.

[0020] The resistance of the main switch 104 is based in part on the voltage across its terminals. For example, the resistance of the main switch 104 can be based on the voltage between the input terminal of the main switch 104 and the gate terminal of the main switch 104. The switch circuit 103 operates to maintain a constant voltage between the input terminal of the main switch 104 and the gate terminal of the main switch 104.

[0021] The first bootstrap circuit 106 and the second bootstrap circuit 108 are both coupled to the main switch 104. The first bootstrap circuit 106 and the second bootstrap circuit 108 cooperate to maintain a constant voltage between the gate terminal and the input terminal of the main switch 104. The first bootstrap circuit 106 and the second bootstrap circuit 108 operate in two alternating phases based on one or more clock signals. During a first phase, the first bootstrap circuit 106 maintains a constant voltage between the input terminal and the gate terminal of the main switch 104.

[0022] In one embodiment, the first bootstrap circuit 106 and the second bootstrap circuit 108 each comprise a respective bootstrap capacitor. During the first phase, the first bootstrap capacitor is coupled between the gate terminal and the input terminal of the main switch 104. During the first phase, the second bootstrap capacitor is decoupled from the gate terminal and the input terminal of the main switch 104. During the first phase, the second bootstrap capacitor is charged to the supply voltage value, i.e. the voltage between the capacitor plates is charged to the supply voltage value. During the second phase, the first bootstrap capacitor is decoupled from the gate terminal and the input terminal of the main switch 104, the second bootstrap capacitor is coupled between the gate terminal and the input terminal of the main switch 104, and the first bootstrap capacitor is charged to the supply voltage value.

[0023] The first bootstrap circuit 106 and the second bootstrap circuit 108 each can comprise a plurality of switches. The switches are turned on and off in accordance with one or more clock signals. The turning on or off of the switches causes the first bootstrap capacitor and the second bootstrap capacitor to be coupled between the gate terminal and the input terminal of the main switch 104 and between the high voltage supply and the low voltage supply terminal and to be decoupled from the gate terminal and the input terminal of the main switch 104 and between the high voltage supply and the low voltage supply terminal.

[0024] The main switch 104 can comprise a field effect transistor. In this case, the input terminal of the main switch 104 is the source terminal of the transistor, the gate terminal of the main switch 104 is the gate terminal of the transistor, and the output terminal of the main switch 104 is the drain terminal of the transistor. The resistance of the field effect transistor is inversely proportional to the voltage between the gate terminal and the source terminal (VGS). During the first phase, the first bootstrap capacitor is coupled between the source terminal and the gate terminal of the transistor. During the second phase, the second bootstrap capacitor is coupled between the source terminal and the gate terminal of the transistor. This ensures that the gate-to-source voltage is always kept at the supply voltage value. Thus, the resistance of the transistor is constant when activated.

[0025] Figure 2 is a schematic diagram of a switch circuit 103 of the multiplexer 102 according to one embodiment. Figure 2 Only a single switch circuit 103 is shown, in practice, the multiplexer comprises a plurality of switch circuits, each coupled to a respective input of the multiplexer 102.

[0026] The switch circuit 103 comprises an input terminal In and an output terminal Out. The switch circuit comprises an NMOS transistor N1 coupled between the input terminal In and the output terminal Out. In particular, the source terminal of the transistor N1 is coupled to the input terminal In. The drain terminal of the transistor N1 is coupled to the output terminal Out. The transistor N1 is the main switch 104 of the switch circuit 103.

[0027] When transistor N1 is activated or turned on, it transmits a signal from the input terminal In to the output terminal OUT. Transistor N1 has resistance when turned on. If the resistance is not constant, the signal supplied to the output terminal includes not only the input signal but also its harmonics. The resistance of transistor N1 is inversely proportional to its gate-source voltage. Therefore, when transistor N1 is activated or turned on, the switching circuit 103 maintains a constant resistance in transistor N1 by keeping its gate-to-source voltage constant. Specifically, the switching circuit 103 utilizes a first bootstrap circuit 106 and a second bootstrap circuit 108 to maintain a constant gate-to-source voltage in transistor N1.

[0028] The first bootstrap circuit 106 includes two NMOS transistors N2 and N3 and two PMOS transistors P1 and P2. The first bootstrap circuit 106 also includes a first bootstrap capacitor C1. The source terminal of transistor N2 is coupled to a low power supply voltage (ground). The drain terminal of transistor N2 is coupled to the lower terminal of the first bootstrap capacitor C1. The gate terminal of transistor N2 receives a clock signal CLK1. The source terminal of transistor N3 is coupled to the lower terminal of the first bootstrap capacitor C1 and the drain terminal of transistor N2. The drain terminal of transistor N3 is coupled to the source terminal of transistor N1. The gate terminal of transistor N3 receives a first phase signal PHASE1. The source terminal of transistor P1 is coupled to a high power supply voltage V. DD The gate terminal of transistor P1 receives the clock signal CLK1N. The drain terminal of transistor P1 is coupled to the upper terminal of the first bootstrap capacitor C1. The drain terminal of transistor P2 is coupled to both the drain terminal of transistor P1 and the upper terminal of the first bootstrap capacitor C1. The source terminal of transistor P2 is coupled to the gate terminal of transistor N1. The gate terminal of transistor P2 receives the clock signal CLK2N.

[0029] The second bootstrap circuit 108 includes two NMOS transistors N4 and N5 and two PMOS transistors P3 and P4. The second bootstrap circuit 108 also includes a second bootstrap capacitor C2. The source terminal of transistor N4 is coupled to a low power supply voltage (ground). The drain terminal of transistor N4 is coupled to the lower terminal of the second bootstrap capacitor C2. The gate terminal of transistor N4 receives the clock signal CLK2. The source terminal of transistor N5 is coupled to the lower terminal of the second bootstrap capacitor C2 and the drain terminal of transistor N4. The drain terminal of transistor N5 is coupled to the source terminal of transistor N1. The gate terminal of transistor N5 receives the second phase signal PHASE2. The source terminal of transistor P3 is coupled to a high power supply voltage V. DDThe gate terminal of transistor P3 receives clock signal CLK2N. The drain terminal of transistor P3 is coupled to the upper terminal of the second bootstrap capacitor C2. The drain terminal of transistor P4 is coupled to the drain terminal of transistor P3 and the upper terminal of the second bootstrap capacitor C2. The source terminal of transistor P4 is coupled to the gate terminal of transistor Nl and the source terminal of transistor P2. The gate terminal of transistor P4 receives clock signal CLKIN.

[0030] The switching circuit 103 further includes a first phase generation circuit 110 and a second phase generation circuit 112. The first phase generation circuit 110 includes an NMOS transistor N6 and a PMOS transistor P5. The source of transistor N6 is coupled to ground. The gate of transistor N6 receives clock signal CLK1. The drain terminal of transistor P5 is coupled to the drain terminal of transistor N6. The source terminal of transistor P5 is coupled to the gate terminal of transistor Nl. The gate terminal of transistor P5 receives clock signal CLK1. The drain terminal of transistor P5 and the drain terminal of transistor N6 correspond to the output of the first phase generation circuit 110 and output a first phase signal PHASE1. The first phase generation circuit 110 can be part of the first bootstrap circuit 106.

[0031] The second phase generation circuit 112 includes an NMOS transistor N7 and a PMOS transistor P6. The source of transistor N7 is coupled to ground. The gate of transistor N7 receives clock signal CLK2. The drain terminal of transistor P6 is coupled to the drain terminal of transistor N7. The source terminal of transistor P6 is coupled to the gate terminal of transistor Nl. The gate terminal of transistor P6 receives clock signal CLK2. The drain terminal of transistor P6 and the drain terminal of transistor N7 correspond to the output of the second phase generation circuit 112 and output a second phase signal PHASE2. The second phase generation circuit 112 can be part of the second bootstrap circuit 108.

[0032] Reference is made to Figures 4 to 7 The functions of the first bootstrap circuit 106 and the second bootstrap circuit 108 can be understood. Figures 4 to 7 A timing diagram of various clock signals and phase signals associated with the multiplexer 102 of Figure 2 Reference is made to Figure 4 , clock signals CLK1 and CLKIN are complementary to each other. In other words, CLKIN is 180° out of phase with CLK1. When CLK1 is high, CLKIN is low, and vice versa. Likewise, clock signals CLK2 and CLK2N are complementary to each other. When CLK2 is high, CLK2N is low, and vice versa. The phases of CLK1 and CLK2 are nearly 180° out of phase. However, from Figure 5As can be seen in the scaled timing diagram, the transition of CLK2 from high to low is slightly earlier than the transition of CLK1 from low to high. Likewise, the transition of CLK1 from high to low is slightly earlier than the transition of CLK2 from low to high. As will be explained in more detail below, this can help to ensure that the VGS of transistor N1 will remain at a constant value.

[0033] Figure 6 The relationship between clock signal CLK1 and first phase signal PHASE1 is shown. Figure 6 The relationship between clock signal CLK2 and second phase signal PHASE2 is also shown. Figure 7 The amplitude of PHASE1 and PHASE2 as a function of input signal Vin is shown.

[0034] Returning again to Figure 2 , the switching circuit 103 of the multiplexer 102 operates in two phases. During phase 1, the first phase signal PHASE1 is high, causing transistor N3 to be turned on. With transistor N3 turned on, the source terminal of transistor N1 is coupled to the bottom terminal of the first bootstrap capacitor Cl. The clock signal CLK2N is low, causing transistor P2 to be turned on. With transistor P2 turned on, the top terminal of capacitor Cl is coupled to the gate terminal of transistor N1. Thus, during the first phase, the source and gate terminals of transistor N1 are coupled between the two terminals of capacitor Cl. The gate-to-source voltage of transistor N1 thus has the value of the voltage between the terminals of the bootstrap capacitor Cl. At the start of the first phase, the first bootstrap capacitor Cl has been charged to the value of the supply voltage V DD . In other words, the voltage difference between the terminals of capacitor Cl corresponds to the voltage difference between ground and V DD .

[0035] During the first phase, the clock signal CLK1N is high, causing transistor Pl to be turned off. During the first phase, the clock signal CLK1 is low, causing transistor N2 to be turned off. Thus, during the first phase, the first bootstrap capacitor Cl is decoupled from the low supply voltage (ground) and the high supply voltage (V DD ). The voltage on the top plate of the bootstrap capacitor Cl is floating with a fixed voltage difference between the top plate and the bottom plate. The bottom plate of the bootstrap capacitor Cl is coupled to the input terminal In of the multiplexer 102 and, accordingly, to the source of transistor N3.

[0036] During phase 1, when an input voltage is received at the input terminal In, the floating top plate of the first bootstrap capacitor Cl is forced to a value that is V DD greater than the input voltage received at the input terminal In. Since the top plate of the first bootstrap capacitor Cl is floating during phase 1, and since the voltage difference at the start of phase 1 is equal to VDD So the voltage difference between the bottom plate and the top plate of the first bootstrap capacitor CI is fixed to V DD . Thus, the voltage on the top plate of the first bootstrap capacitor CI changes depending on the voltage of the source terminal of the transistor Nl coupled to the input terminal of the multiplexer 102. If the input voltage increases, the voltage on the top plate of the first bootstrap capacitor CI increases by the same amount. If the input voltage decreases, the voltage on the top plate of the first bootstrap capacitor CI decreases by the same amount. Thus, the voltage difference between the gate terminal and the source terminal of the transistor Nl is always equal to the high supply voltage V DD . Because the gate-to-source voltage of the transistor Nl is constant, the resistance of the transistor Nl is constant. This ensures that a signal can be passed from the input terminal In through the transistor Nl to the output terminal Out without introducing harmonics in the signal.

[0037] During phase 1, the phase signal PHASE2 is low, such that the transistor N5 is not conductive. The clock signal CLKIN is high, such that the transistor P4 is not conductive. Because the transistors P4 and N5 are not conductive during the first phase, the gate terminal and the source terminal of the transistor Nl are decoupled from the terminal of the second bootstrap capacitor C2.

[0038] During phase 1, the clock signal CLK2 is high, such that the transistor N4 is conductive. Because the transistor N4 is conductive, the bottom plate of the second bootstrap capacitor C2 is coupled to the low supply voltage (ground). During phase 1, the clock signal CLK2N is low, such that the transistor P3 is conductive. Because the transistor P3 is conductive, the top plate of the second bootstrap capacitor C2 is coupled to the high supply voltage V DD . Thus, during phase 1, the bootstrap capacitor C2 charges to V DD . In other words, during phase 1, the terminal of the second bootstrap capacitor C2 is charged to the voltage difference V DD .

[0039] During phase 2, the first bootstrap circuit 106 is decoupled from the source terminal and the gate terminal of the transistor Nl. This is because during the second phase, the signal PHASE1 is low and the clock signal CLK2N is high, such that the transistors N3 and P2 are not conductive. During phase 2, the clock signal CLK1 is high, such that the transistor N2 is conductive. This causes the bottom terminal of the first bootstrap capacitor CI to be coupled to the low supply voltage (ground). During phase 2, the clock signal CLKIN is low, such that the transistor PI is conductive. This causes the top terminal of the first bootstrap capacitor CI to be coupled to the high supply voltage V DD . Thus, during phase 2, when the first bootstrap circuit 106 is decoupled from the transistor Nl, the first bootstrap capacitor CI charges to achieve the voltage difference V DD .

[0040] During phase 2, the second bootstrap circuit 108 is coupled to the source terminal and the gate terminal of the transistor N1. During phase 2, the second phase signal PHASE2 is high, such that the transistor N5 is turned on. Because the transistor N5 is turned on, the source terminal of the transistor N1 is coupled to the bottom plate of the second bootstrap capacitor C2. During phase 2, the clock signal CLK1N is low, such that the transistor P4 is turned on. Because the transistor P4 is turned on, the upper terminal of the second bootstrap capacitor C2 is coupled to the gate terminal of the transistor N1.

[0041] During phase 2, the clock signal CLK2N is high, such that the transistor P3 is not turned on. During phase 2, the clock signal CLK2 is low, such that the transistor N4 is not turned on. Thus, during phase 2, the second bootstrap capacitor C2 is decoupled from the low supply voltage (ground) and the high supply voltage V DD DD The voltage on the top plate of the bootstrap capacitor C2 floats with a fixed voltage difference between the top plate and the bottom plate equal to V DD The bottom plate of the bootstrap capacitor C2 is coupled to the input terminal In of the multiplexer 102 and, accordingly, to the source of the transistor N1.

[0042] During phase 2, when an input voltage is received at the input terminal In, the floating top plate of the second bootstrap capacitor C2 is forced to a value that is V DD greater than the input voltage received at the input terminal In. Since the top plate of the second bootstrap capacitor C2 is floating during phase 2 and since the voltage difference at the beginning of phase 2 is equal to V DD , the voltage difference between the bottom plate and the top plate of the second bootstrap capacitor C2 is fixed to V DD . Thus, the voltage on the top plate of the second bootstrap capacitor C2 changes depending on the voltage of the source terminal of the transistor N1 coupled to the input terminal of the multiplexer 102. If the input voltage increases, the voltage on the top plate of the second bootstrap capacitor C2 increases by the same amount. If the input voltage decreases, the voltage on the top plate of the second bootstrap capacitor C2 decreases by the same amount. Thus, during phase 2, the voltage difference between the gate terminal and the source terminal of the transistor N1 is always equal to the high supply voltage V DD . Because the gate-to-source voltage of the transistor N1 is constant during phase 2, the resistance of the transistor N1 is constant. This ensures that a signal can be passed from the input terminal In through the transistor N1 to the output terminal Out without introducing harmonics in the signal.

[0043] As mentioned above, during phase 1, the first bootstrap capacitor is coupled to the source terminal and the gate terminal of the transistor N1, while the second bootstrap capacitor C2 is decoupled from the source terminal and the gate terminal of the transistor N1 and charged or recharged to V​DD During phase 2, the first bootstrap capacitor is decoupled from the source terminal and the gate terminal of transistor Nl, and is charged or recharged to V DD and the second bootstrap capacitor C2 is coupled to the gate terminal and the source terminal of transistor Nl. Phases 1 and 2 are continuously alternated until the multiplexer decouples the input In from the output Out. During phases 1 and 2, the gate-to-source voltage of transistor Nl remains at a constant value. Thus, during phases 1 and 2, the resistance of transistor Nl remains at a constant value.

[0044] In one embodiment, transistors Nl, N3, and N5 are smaller transistors than the other transistors of the switching circuit 103 of the multiplexer 102. This can mean that transistors Nl, N3, and N5 have a smaller channel length, channel width, or dielectric thickness than the other transistors of the switching circuit 103 of the multiplexer 102. Thus, transistors Nl, N3, and N5 can be low voltage transistors capable of operating at low power supply voltages. The reduced size and voltage of transistors Nl, N3, and N5 cause the transistors Nl, N3, and N5 to have faster switching times. This is because the various capacitances between the terminals of transistors Nl, N3, and N5 are smaller than the various capacitances between the terminals of the other transistors of the switching circuit 103 of the multiplexer 102. The first bootstrap circuit 106 and the second bootstrap circuit 108 protect transistors Nl, N3, and N5 from dangerous high voltages. Thus, transistors Nl, N3, and N5 can be faster switching transistors capable of operating at higher frequencies.

[0045] In one embodiment, the capacitances of bootstrap capacitors Cl and C2 are between 0.5 pF and 2.0 pF. Other capacitance values can be used for bootstrap capacitors Cl and C2 without departing from the scope of the present disclosure. In one embodiment, the power supply voltage V DD is approximately 1 V, although other values can be utilized without departing from the scope of the present disclosure. In one embodiment, the frequencies of clock signals CLKl and CLK2 are between 1 MHz and 1 GHz, although other values can be utilized without departing from the scope of the present disclosure.

[0046] Figure 3 is a schematic diagram of a switching circuit 103 used in the multiplexer 102 according to one embodiment. Except for Figure 3 the switching circuit 103 includes the selection of P7, P8, and N8, Figure 3 the switching circuit 103 is substantially similar to Figure 2 the switching circuit 103. Transistor P7 is coupled between the high power supply voltage V DD and transistor Pl. Transistor P8 is coupled between the high power supply voltage V DDbetween the transistor P3. The transistor N8 is coupled between the gate terminal of the transistor N1 and ground. Each of the transistors P7, P8 and N8 receives a select signal SEL. If the select signal SEL is high, the transistors P7 and P8 are turned off, thereby decoupling the first bootstrap circuit 106 and the second bootstrap circuit 108 from the supply voltage V DD When the select signal is high, the transistor N8 is turned on, thereby coupling the gate terminal of the transistor N1 to ground. Hence, if the select signal SEL is high, the transistor N1 becomes non-conductive and a signal will not be transferred between the input terminal In and the output terminal Out.

[0047] When the select signal SEL is low, the transistors P7 and P8 are turned on, thereby coupling the transistors P1 and P3 to the high supply voltage V DD When the select signal is low, the transistor N8 becomes non-conductive, thereby decoupling the gate terminal of the transistor N1 from ground. When the select signal SEL is low, the bootstrap capacitors C1 and C2 can be charged to V DD and are alternately coupled between the gate terminal and the source terminal of the transistor N1. Hence, when the select signal SEL is low, the transistor N1 is conductive and is able to transfer a signal between the input terminal In and the output terminal Out.

[0048] Figure 8 is a block diagram of an integrated circuit 100 according to an embodiment. The integrated circuit 100 comprises a multiplexer 102. The multiplexer 102 can correspond to the multiplexer 102 described with respect to Figures 1 to 7 The integrated circuit 100 further comprises an input circuit 120 and an analog-to-digital converter (ADC) 122. The input circuit 120 provides an analog input voltage signal Vin to the input terminal In of the multiplexer 102. The multiplexer 102 outputs an analog output voltage signal Vout to the ADC 122. The input voltage signal is passed through a main switch 104, e.g. a transistor N1, to the output Out of the multiplexer 102. Since the resistance of the main switch 104 is kept at a constant value, the output voltage signal Vout does not include harmonics of the input voltage signal. This enables the ADC 122 to perform a reliable digital conversion of the analog voltage output signal Vout.

[0049] Figure 9is a flowchart of a method 900 for operating a multiplexer according to one embodiment. At 902, the method 900 includes selecting a switch circuit from the multiplexer using a select line. At 904, the method 900 includes passing a signal from an input terminal of the selected switch circuit through a main transistor of the selected switch circuit to an output terminal of the multiplexer. At 906, the method 900 includes coupling a first bootstrap capacitor between a gate terminal and a source terminal of the main transistor during a first phase, and charging the second bootstrap capacitor to VDD during the first phase. At 908, the method 900 includes coupling the second bootstrap capacitor between the gate terminal and the source terminal of the main transistor during a second phase, and charging the first bootstrap capacitor to VDD during the second phase. The method 900 alternates between steps 906 and 908 when the switch circuit is selected.

[0050] Figure 10 is a flowchart of a method 1000 for operating a multiplexer according to one embodiment. At 1002, the method 1000 includes passing a signal from an input terminal of the multiplexer through a main transistor of the multiplexer to an output terminal of the multiplexer. At 1004, the method 1000 includes coupling a first bootstrap capacitor between a gate terminal and a source terminal of the main transistor during a first phase. At 1006, the method 1000 includes decoupling a second bootstrap capacitor from the gate terminal and the source terminal during the first phase. At 1008, the method 1000 includes coupling the second bootstrap capacitor between the gate terminal and the source terminal of the main transistor during a second phase that alternates with the first phase. At 1010, the method 1000 includes decoupling the first bootstrap capacitor from the gate terminal and the source terminal during the second phase. In effect, step 1004 and step 1006 occur simultaneously. In effect, step 1008 and step 1010 occur simultaneously. After step 1010, the method 1000 returns to step 1004, and repeats steps 1004 through 1010. In effect, step 1002 occurs continuously throughout steps 1004 through 1010.

[0051] In one embodiment, a multiplexer includes an input terminal, an output terminal, and a main switch coupled between the input terminal and the output terminal and configured to pass a signal between the input terminal and the output terminal. A switch circuit of the multiplexer includes a first bootstrap circuit including a first bootstrap capacitor and configured to couple the first bootstrap capacitor to the main switch during a first phase, and to decouple the first bootstrap capacitor from the main switch during a second phase. The switch circuit of the multiplexer includes a second bootstrap circuit including a second bootstrap capacitor and configured to couple the second bootstrap capacitor to the main switch during the second phase, and to decouple the second bootstrap capacitor from the main switch during the first phase.

[0052] In one embodiment, a method includes passing a signal from an input terminal of a multiplexer through a pass transistor of the multiplexer to an output terminal of the multiplexer, coupling a first bootstrap capacitor between a gate terminal and a source terminal of the pass transistor during a first phase, and coupling a second bootstrap capacitor between the gate terminal and the source terminal of the pass transistor during a second phase that is alternating with the first phase.

[0053] In one embodiment, an integrated circuit includes a multiplexer. The multiplexer includes an input configured to receive an analog signal, an output configured to pass the analog signal, and a pass transistor having a source coupled to the input, a drain coupled to the output, and a gate configured to pass the signal between the input and the output. A switching circuit of the multiplexer includes a first bootstrap capacitor configured to be coupled between the source and the gate during a first phase and decoupled from the source and the gate during a second phase. The switching circuit of the multiplexer includes a second bootstrap capacitor configured to be coupled between the source and the gate during the second phase and decoupled from the source and the gate during the first phase.

[0054] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above- described detailed description. In general, in the appended claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all embodiments falling within the scope of the claims and their equivalents. Accordingly, the claims are not limited to the above-described embodiments.

Claims

1. A multiplexer comprising a plurality of switching circuits, wherein the switching circuits each comprise: an input terminal; an output terminal; a main switch coupled between the input terminal and the output terminal and configured to pass a signal between the input terminal and the output terminal; a first bootstrap circuit comprising a first bootstrap capacitor and configured to couple the first bootstrap capacitor to the main switch during a first phase and to decouple the first bootstrap capacitor from the main switch during a second phase; a second bootstrap circuit comprising a second bootstrap capacitor and configured to couple the second bootstrap capacitor to the main switch during the second phase and to decouple the second bootstrap capacitor from the main switch during the first phase; and a main switch selector for receiving a selection signal and two bootstrap circuit selectors, wherein the main switch selector is coupled between the main switch and ground and the two bootstrap circuit selectors couple a supply voltage to the respective first and second bootstrap circuits, wherein when the selection signal is in a first state, the main switch selector is on and the two bootstrap circuit selectors are off; when the selection signal is in a second state opposite to the first state, the main switch selector is off and the two bootstrap circuit selectors are on.

2. The multiplexer of claim 1, wherein the main switch is a transistor, the transistor comprising: a source terminal coupled to the input terminal; a drain terminal coupled to the output terminal; and a gate terminal.

3. The multiplexer of claim 2, wherein during the first phase, the first bootstrap capacitor is coupled between the source terminal and the gate terminal of the transistor and the second bootstrap capacitor is decoupled from the source terminal and the gate terminal of the transistor.

4. The multiplexer of claim 3, wherein during the second phase, the second bootstrap capacitor is coupled between the source terminal and the gate terminal of the transistor and the first bootstrap capacitor is decoupled from the source terminal and the gate terminal of the transistor.

5. The multiplexer of claim 4, wherein during the first phase, the second bootstrap capacitor is charged to a supply voltage value, wherein during the second phase, the first bootstrap capacitor is charged to the supply voltage value.

6. The multiplexer of claim 5, wherein the first bootstrap circuit comprises a plurality of first switches configured to selectively couple and decouple the first bootstrap capacitor between the gate terminal and the source terminal of the transistor during the first phase and the second phase. ​ ​ 7. The multiplexer of claim 6, wherein the second bootstrap circuit comprises a plurality of second switches configured to selectively couple and decouple the second bootstrap capacitor between the gate terminal and the source terminal of the transistor during the first phase and the second phase.

8. The multiplexer of claim 7, wherein the first phase and the second phase alternate according to a clock signal.

9. The multiplexer of claim 6, wherein the first bootstrap circuit and the second bootstrap circuit collectively maintain a gate-to-source voltage of the transistor at a constant value during the first phase and the second phase.

10. The multiplexer of claim 9, wherein the constant value is the power supply voltage value.

11. A method for operating a multiplexer, wherein the multiplexer comprises a plurality of switch circuits each comprising a main transistor, a first bootstrap circuit, and a second bootstrap circuit, the method comprising: passing a signal from an input terminal of the multiplexer through the main transistor to an output terminal of the multiplexer; during a first phase, coupling a first bootstrap capacitor of the first bootstrap circuit between a gate terminal and a source terminal of the main transistor; and during a second phase that alternates with the first phase, coupling a second bootstrap capacitor of the second bootstrap circuit between the gate terminal and the source terminal of the main transistor; the method further comprising: according to a selection signal in a first state, coupling the main switch with ground using a main switch selector and decoupling the power supply voltage from the respective first and second bootstrap circuits using two bootstrap circuit selectors; according to the selection signal in a second state opposite the first state, decoupling the main switch from ground using the main switch selector and coupling the power supply voltage to the respective first and second bootstrap circuits using the two bootstrap circuit selectors.

12. The method of claim 11, further comprising: during the second phase, decoupling the first bootstrap capacitor from the gate terminal and the source terminal; and during the first phase, decoupling the second bootstrap capacitor from the gate terminal and the source terminal.

13. The method of claim 12, further comprising: during the second phase, charging the first bootstrap capacitor to a power supply voltage value; and during the first phase, charging the second bootstrap capacitor to the power supply voltage value. maintaining a gate-to-source voltage of the transistor at the power supply voltage value during the first phase and the second phase. alternating between the first phase and the second phase based on a clock signal. controlling a plurality of first switches based on the clock signal.

14. The method of claim 13, further comprising: controlling a plurality of second switches based on the clock signal.

15. The method of claim 14, further comprising:

18. An integrated circuit comprising:

16. The method of claim 15, wherein coupling and decoupling the first bootstrap capacitor comprises: a multiplexer comprising a plurality of switch circuits, wherein the switch circuits each comprise:

17. The method of claim 16, wherein coupling and decoupling the second bootstrap capacitor comprises: an input; an output; ​ ​ ​ a main transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal being coupled to the input, the drain terminal being coupled to the output; a first bootstrap circuit coupled to the input, the first bootstrap circuit comprising: a first pair of transistors; a first bootstrap capacitor; and a second pair of transistors, the first bootstrap capacitor being coupled between the first pair of transistors and the second pair of transistors; a second bootstrap circuit coupled to the input, the second bootstrap circuit comprising: a third pair of transistors; a second bootstrap capacitor; and a fourth pair of transistors, the second bootstrap capacitor being coupled between the third pair of transistors and the fourth pair of transistors; and a main switch selector for receiving a selection signal and two bootstrap circuit selectors, wherein the main switch selector is coupled between the gate terminal of the main transistor and ground, and the two bootstrap circuit selectors couple a supply voltage to the respective first and second bootstrap circuits, wherein when the selection signal is in a first state, the main switch selector is on, and the two bootstrap circuit selectors are off; and when the selection signal is in a second state opposite to the first state, the main switch selector is off, and the two bootstrap circuit selectors are on.

19. The integrated circuit of claim 18, further comprising an analog-to-digital converter configured to receive a signal from the output and convert the signal to a digital signal.

20. A method for operating a multiplexer, wherein the multiplexer comprises a plurality of switch circuits each comprising a main switch, a first bootstrap circuit, and a second bootstrap circuit, the method comprising: coupling the main switch between an input terminal and an output terminal of the multiplexer; passing a signal between the input terminal and the output terminal; during a first phase, coupling the first bootstrap circuit comprising a first bootstrap capacitor to the main switch, and during a second phase, decoupling the first bootstrap capacitor from the main switch; and during the second phase, coupling the second bootstrap circuit comprising a second bootstrap capacitor to the main switch, and during the first phase, decoupling the second bootstrap capacitor from the main switch; the method further comprising: in accordance with a selection signal in a first state, coupling the main switch to ground with a main switch selector, and decoupling the respective first and second bootstrap circuits from a supply voltage with two bootstrap circuit selectors; in accordance with the selection signal in a second state opposite to the first state, decoupling the main switch from ground with the main switch selector, and coupling the supply voltage to the respective first and second bootstrap circuits with the two bootstrap circuit selectors.

21. The method of claim 20, comprising coupling a source terminal of the main switch to the input terminal, and coupling a drain terminal of the main switch to the output terminal. ​ 22. The method of claim 21, comprising coupling the first bootstrap capacitor between the source terminal and a gate terminal of the main switch during the first phase, and decoupling the second bootstrap capacitor from the source terminal and the gate terminal of the main switch.

23. The method of claim 22, comprising coupling the second bootstrap capacitor between the source terminal and the gate terminal of the main switch during the second phase, and decoupling the first bootstrap capacitor from the source terminal and the gate terminal of the main switch.

24. An electronic device, comprising: an input terminal; an output terminal; a transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal coupled to the input terminal, and the drain terminal coupled to the output terminal, the transistor configured to pass a signal between the input terminal and the output terminal; a first bootstrap circuit comprising a first bootstrap capacitor, and the first bootstrap circuit configured to couple the first bootstrap capacitor to the transistor during a first phase, and decouple the first bootstrap capacitor from the transistor during a second phase; a second bootstrap circuit comprising a second bootstrap capacitor, and the second bootstrap circuit configured to couple the second bootstrap capacitor to the transistor during the second phase, and decouple the second bootstrap capacitor from the transistor during the first phase; and a main switch selector for receiving a selection signal, and two bootstrap circuit selectors, wherein the main switch selector is coupled between a gate terminal of the transistor and ground, and the two bootstrap circuit selectors couple a supply voltage to the respective first and second bootstrap circuits, wherein when the selection signal is in a first state, the main switch selector is on, and the two bootstrap circuit selectors are off; when the selection signal is in a second state opposite to the first state, the main switch selector is off, and the two bootstrap circuit selectors are on.

25. The electronic device of claim 24, wherein during the first phase, the first bootstrap capacitor is coupled between the source terminal and the gate terminal of the transistor, and the second bootstrap capacitor is decoupled from the source terminal and the gate terminal of the transistor.

26. The electronic device of claim 25, wherein during the second phase, the second bootstrap capacitor is coupled between the source terminal and the gate terminal of the transistor, and the first bootstrap capacitor is decoupled from the source terminal and the gate terminal of the transistor.

27. The electronic device of claim 26, wherein during the first phase, the second bootstrap capacitor is charged to a supply voltage value, and wherein during the second phase, the first bootstrap capacitor is charged to the supply voltage value. ​ 28. The electronic device of claim 27, wherein the first bootstrapping circuit comprises a plurality of first switches configured to selectively couple and decouple the first bootstrap capacitor between the gate terminal and the source terminal of the transistor during the first phase and the second phase.

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