Integrated circuit chip device with thermal control

Abstract

Configured integrated circuit chip devices provide thermal control by directing heat transfer away from heat sensitive components. The structure directs heat transfer away from heat sensitive components so that the heat sensitive components can be maintained at a reduced operating temperature for improved performance.

Description

Background Technology

[0001] Integrated circuits can include multiple components, some of which are more sensitive to heat than others. Some components may also generate heat, which can be transferred to the more heat-sensitive components. As electronics become smaller, the impact of heat-generating components on heat-sensitive components becomes more significant. For example, dark current is a small current flowing through a photosensitive device (such as an image sensor) even when no photons are entering it. Dark current contributes significantly to the noise generated in photosensitive devices. The magnitude of dark current varies drastically with the device's temperature, and it typically increases with increasing temperature. Summary of the Invention

[0002] This article describes various methods, particularly for providing improved construction for integrated circuit chip devices. For example, integrated circuit chip devices include structures that provide thermal control, such that heat transfer is directed away from heat-sensitive components.

[0003] The example chip device includes a substrate, a first component, a second component, and a heat sink. The first component is disposed on the substrate. The second component is disposed on the substrate spaced apart from the first component and generates heat. The heat sink is coupled to the substrate such that at least a portion of the substrate is inserted between the second component and the heat sink. The thermal resistance between the second component and the heat sink is less than the thermal resistance between the second component and the first component.

[0004] The second example chip device includes a substrate, a first component, a second component, a heat sink, and a via. The substrate is constructed of a first material having a first thermal conductivity and includes a cavity. The first component is disposed on the substrate adjacent to the cavity. The second component is disposed on the substrate spaced apart from the first component and generates heat. The heat sink is coupled to the substrate. The via extends between the second component and the heat sink and is constructed of a second material having a second thermal conductivity greater than the first thermal conductivity.

[0005] An example method of manufacturing a chip device with thermal control includes: manufacturing a first wafer; filling the first wafer with a first component and a second component; manufacturing a second wafer; forming a cavity in the second wafer; forming a via in the second wafer; manufacturing a heat sink; and coupling the first wafer, the second wafer, and the heat sink. The second component is spaced apart from the first component and generates heat during use. The second wafer is made of a first material having a first thermal conductivity. The via is constructed of a second material having a second thermal conductivity greater than the first thermal conductivity. The first wafer, the second wafer, and the heat sink are coupled such that the second wafer is at least partially inserted between the heat sink and the first wafer, the first component is arranged adjacent to the cavity, and the via extends between the second component and the heat sink.

[0006] The present invention is provided to present a simplified description of the chosen concepts, which are further described below in the detailed description. The present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Furthermore, it should be noted that the invention is not limited to the specific embodiments described in the detailed description and / or other sections herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art based on the teachings contained herein. Attached Figure Description

[0007] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the invention and, together with this specification, further serve to explain the principles involved and enable those skilled in the art to make and use the disclosed techniques.

[0008] Figure 1 This is a perspective view of an example integrated circuit chip device constructed according to one embodiment.

[0009] Figure 2 According to one embodiment Figure 1 A top view of the structure of an integrated circuit chip device.

[0010] Figure 3 It is an integrated circuit chip device constructed according to one embodiment, corresponding to Figure 2 The cross-sectional view of line 3-3.

[0011] Figure 4 This is a top view of an integrated circuit chip device constructed according to another example embodiment.

[0012] Figure 5 This is a perspective view of an example integrated circuit chip device constructed according to one embodiment.

[0013] Figure 6 According to one embodiment Figure 5 A top view of the structure of an integrated circuit chip device.

[0014] Figure 7 This is a perspective view of an example integrated circuit chip device constructed according to one embodiment.

[0015] Figure 8 According to one embodiment Figure 7 A top view of the structure of an integrated circuit chip device.

[0016] Figures 9a-9e This is a schematic diagram illustrating an example embodiment of an integrated circuit chip device constructed according to one embodiment.

[0017] Figure 10A flowchart depicts an example method for manufacturing an integrated circuit chip device according to one embodiment.

[0018] Figures 11a-11j This is a schematic diagram illustrating steps in an example method for manufacturing an integrated circuit chip device according to one embodiment.

[0019] The features and advantages of the disclosed technology will become clearer when viewed in conjunction with the accompanying drawings, in which the same reference numerals consistently identify corresponding elements. In the drawings, the same reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost numeral in the corresponding reference numeral. Detailed Implementation

[0020] I. Introduction

[0021] The following detailed description refers to the accompanying drawings illustrating exemplary embodiments of the invention. However, the scope of the invention is not limited to these embodiments, but is defined by the appended claims. Therefore, the invention may cover embodiments other than those shown in the drawings (such as modifications of the illustrated embodiments).

[0022] References to "an embodiment," "an embodiment," "an example embodiment," etc., in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is suggested that implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge of those skilled in the art.

[0023] II. Example Implementation

[0024] The example embodiments described herein provide improvements to known constructions of integrated circuit chip devices. Example embodiments of integrated circuit chip device constructions include structures that result in thermal control that directs heat transfer away from heat-sensitive components. By directing heat transfer away from heat-sensitive components, integrated circuit chip devices can provide improved performance, such as reduced noise in photosensitive devices.

[0025] Integrated circuit chip devices are typically constructed using substrates that provide this structure. The substrate can be constructed to direct heat transfer away from heat-sensitive components. For example, the substrate can be etched to reduce or prevent heat conduction to portions of the substrate adjacent to the heat-sensitive component. Etching the substrate reduces the thermal mass of the substrate adjacent to the heat-sensitive component and removes the conduction path to the heat-sensitive component. Reducing heat transfer from the heat-generating component to the heat-sensitive component also allows cooling devices to operate more efficiently to lower the temperature of the heat-sensitive component. Although the chip device construction includes heat-generating components operating at approximately 40°C, it can help achieve an optimal operating temperature of approximately 30°C for the heat-sensitive component.

[0026] Figures 1-3 An example embodiment of an integrated circuit chip device 100, comprising a construction according to an example embodiment, is illustrated. The chip device 100 includes a substrate 102, a first component 104, a second component 106, a plurality of conductors 208, an insulating layer 110, a heat sink 112, and a cooling device 126.

[0027] Substrate 102 forms a structural component in chip device 100 and can be shaped and scaled to provide thermal control by guiding heat transfer through chip device 100. Substrate 102 provides structure, rigidity, and thermal stability to chip device 100. Substrate 102 provides a support on which first component 104 and second component 106 can be constructed and held in a desired spatial relationship. Substrate 102 also provides a structure for supporting conductor 208, which can extend between first component 104 and second component 106, and / or between any other components included in chip device 100. Substrate 102 can be formed of monocrystalline silicon, gallium arsenide, germanium, or any other structurally nonconductive material. In some example embodiments, the thickness of substrate 102 is in the range of approximately 200 μm to approximately 400 μm. In at least one example embodiment, the thickness of substrate 102 is approximately 300 μm.

[0028] A first component 104 is disposed on a substrate 102 and provides the desired functionality. In at least one example embodiment, the first component 104 is a photosensor constructed using germanium. The photosensor may include a plurality of pixels 114 arranged in an array. In some embodiments, the first component 104 is a heat-sensitive component exhibiting efficiency that changes with temperature. For example, the first component 104 may be a photosensor having efficiency that decreases as the temperature of the first component 104 increases. As will be described in more detail, the chip device 100 is constructed to direct heat transfer away from the heat-sensitive component such that heat generated by other components does not harmfully increase the temperature of the heat-sensitive component.

[0029] In an example embodiment, the first component 104 is a photosensor having a 1024x1024 pixel array. For example, each pixel 114 of the array can be scaled to approximately 2.5 μm × 2.5 μm, and the pixels 114 can be spaced approximately 2.5 μm apart. In at least one example embodiment, a plurality of conductors 208 are coupled to and extend from each pixel 114 to form an interconnect. The conductors 208 can be formed from metal traces having a width of approximately 0.1 μm and a thickness of approximately 2200 angstroms. The conductors 208 can be formed from materials such as aluminum, copper, and / or gold, and they can be formed using, for example, electroplating. Any number of conductors 208 can be coupled to each pixel 114. In at least one example embodiment, each pixel 114 includes eight conductors 208. Additionally, the first component 104 can be constructed from a material having a lower thermal conductivity than the substrate 102. In at least one example embodiment, the first component 104 is constructed of germanium having a thermal conductivity of approximately 60.0 W / mK, and the substrate 102 is constructed of silicon having a thermal conductivity of approximately 145.0 W / mK.

[0030] A second component 106 is also disposed on the substrate 102. In at least one example embodiment, the second component 106 includes a component configured to perform analog-to-digital conversion. In this example, the second component 106 may generate heat during use, which can be transferred to other parts of the chip device 100.

[0031] An insulating layer 110 may be disposed between multiple components, for example, between a first component 104 and a substrate 102, and between a second component 106 and a substrate 102. In some example embodiments, the insulating layer 110 may be grown or deposited on the substrate 102. In the illustrated embodiment, the insulating layer 110 forms a first surface 116 of the substrate 102. The insulating layer 110 may provide electrical insulation between conductors 208. The insulating layer 110 may also provide electrical insulation between the first component 104 and the substrate 102, and between the second component 106 and the substrate 102. In some example embodiments, the insulating layer 110 is formed of silicon dioxide (SiO2) grown on the substrate 102, and the SiO2 has a thermal conductivity of approximately 1.5 W / mK. The SiO2 insulating layer 110 may be grown on the silicon substrate 102 using thermal oxidation, wet oxidation, or dry oxidation. In some example embodiments, the thickness of the insulating layer 110 is in the range of approximately 4.0 μm to approximately 5.0 μm. In at least one example embodiment, the thickness of the insulating layer 110 is approximately 4.5 μm.

[0032] A heat sink 112 is coupled to a portion of a substrate 102, such as a second surface 118 of the substrate 102. The heat sink 112 is typically constructed of a high thermal conductivity material, such as a metallic material with a selected thermal conductivity. In some example embodiments, the heat sink 112 is constructed of a material having a greater thermal conductivity than the material used to construct the substrate 102. In at least one example embodiment, the substrate 102 is constructed of single-crystal silicon having a thermal conductivity of approximately 145.0 W / mK, and the heat sink is constructed of a metallic material having a thermal conductivity greater than approximately 145.0 W / mK. In at least one example embodiment, the heat sink 112 is constructed of aluminum having a thermal conductivity of approximately 237.0 W / mK. In at least one example embodiment, the heat sink 112 is constructed of copper having a thermal conductivity of approximately 386.0 W / mK.

[0033] The chip device 100 is configured to provide thermal control over heat transfer through and out of the chip device 100. Specifically, the construction of the substrate 102 and / or the inclusion of one or more isolation features and one or more conductive features can be used to control heat transfer through the chip device 100. The chip device 100 is constructed including portions of selected materials and geometries such that the thermal resistance between the second component 106 (i.e., the heat source) and the heat sink 112 is lower than the thermal resistance between the second component 106 and the first component 104, such that heat transfer from the second component 106 is directed away from the first component 104 and toward the heat sink 112. The thermal resistance of the structure can be defined by the following formula:

[0034] R = x / (A * k) (1)

[0035] Where R is the thermal resistance, x is the distance measured along the path parallel to the heat flow, A is the cross-sectional area perpendicular to the heat flow path, and k is the thermal conductivity of the material. Furthermore, the materials and geometries of multiple portions of the chip device 100 can be configured to prevent heat accumulation in the portion of the substrate 102 adjacent to the first component 104.

[0036] For example, a portion of substrate 102 may be removed or replaced to eliminate a heat transfer path through chip device 100. As illustrated, a portion of substrate 102 adjacent to first component 104 is removed to form cavity 124, which would otherwise support first component 104 between first component and second surface 118 of substrate 102. Cavity 124 reduces the thermal mass of substrate 102 adjacent to first component 104. Furthermore, cavity 124 reduces the available conduction path from heat-generating second component 106 to first component 104, increasing the thermal resistance between second component 106 and first component 104. Cavity 124 may be formed by etching, and the etching may be anisotropic or isotropic. In some example embodiments, wet etching techniques, such as ethylenediamine catechol (EDP), potassium hydroxide (KOH), or tetramethylammonium (TMAH), are used to form cavity 124. In at least one example embodiment, KOH etching is used to utilize the removal properties of anisotropic materials to form the cavity. In some example embodiments, dry etching techniques, such as CF4, SF6, NF3, and Cl2, CCl2F2, are used to form the cavity 124. In at least one example embodiment, the cavity 124 may be tapered, such that it widens in the direction away from the first component 104. In at least one example embodiment, the cavity includes sidewalls that are generally perpendicular to the second surface 118 of the substrate 102, such that the width of the cavity 124 is substantially constant in the direction away from the first component 104.

[0037] The cavity 124 formed in the substrate 102 can be filled. In some embodiments, the cavity 124 is at least partially filled with a material whose thermal conductivity is less than that of the surrounding substrate material. In at least one example embodiment, the cavity 124 is filled with SiO2 having a thermal conductivity of about 1.5 W / mK, and the surrounding substrate is constructed of silicon having a thermal conductivity of about 145.0 W / mK.

[0038] Furthermore, in some example embodiments, cavity 124 can be formed of a variety of materials. For example, cavity 124 can initially be partially filled with a material having relatively low thermal conductivity to provide increased thermal insulation closest to the first component 104. The remainder of cavity 124, or a portion thereof, can subsequently be filled with a material having relatively high thermal conductivity, thereby providing a larger thermally conductive surface area for coupling with heat sink 112. In example embodiments, cavity 124 can be partially filled with SiO2 having relatively low thermal conductivity, followed by filling with a metallic material having relatively high thermal conductivity.

[0039] First component 104 and second component 106 are spaced apart from each other on substrate 102 to thermally and electrically insulate the first component 104 from the second component 106. Isolation features such as shallow trenches 120 may be employed to provide isolation. Trench 120 is interposed between the first component 104 and the second component 106 and forms a boundary that prevents or significantly reduces direct conduction between the first component 104 and the second component 106. In at least one embodiment, trench 120 is filled with a material having a thermal conductivity of less than about 145.0 W / mK. In at least one embodiment, trench 120 is filled with a material having a thermal conductivity of less than about 60.0 W / mK. In at least one embodiment, trench 120 is filled with a material having a thermal conductivity of less than about 2.0 W / mK. In at least one embodiment, trench 120 is filled with SiO2. In some example embodiments, trench 120 forms a gap between the first component 104 and the second component 106.

[0040] The chip device 100 may include conductive features to provide higher conductivity between the heat-generating component and the heat sink 112. For example, the conductive feature may be a via 322 extending between the second component 106 and the heat sink 112, the via 322 being constructed of a material with a thermal conductivity greater than that of the substrate 102. The higher thermal conductivity can provide lower thermal resistance between the second component 106 and the heat sink 112. For example, the via 322 may be constructed of a metallic material having a higher thermal conductivity value than that of the surrounding material of the substrate 102. In an example embodiment, the surrounding material of the substrate 102 is silicon having a thermal conductivity of approximately 145.0 W / mK, and the via 322 is constructed of a material having a thermal conductivity greater than approximately 145.0 W / mK. For example, the metallic material may be electroplated into the channel to form the via 322. In at least one example embodiment, the via 322 is constructed of aluminum having a thermal conductivity of approximately 237.0 W / mK. In at least one example embodiment, the via 322 is constructed of copper having a thermal conductivity of approximately 386.0 W / mK.

[0041] The chip device 100 may also include a cooling device 126 for removing heat. The cooling device 126 may be a solid-state cooling device, such as a Peltier cooler, which transfers heat from one side of the cooling device 126 to the other side while consuming electrical energy. As illustrated, the cooling device 126 may be coupled to a heat sink 112 to draw heat away from the heat sink 112 and the substrate 102. The chip device 100 may include any number of cooling devices 126. In some example embodiments, multiple cooling devices 126 may be included and coupled to different portions of the chip device 100 to provide zoned cooling. For example, the cooling device 126 may be coupled to the heat sink 112, the cooling device 126 may be coupled to a portion of the substrate 102 adjacent to the first component 104, the cooling device 126 may be coupled to a side edge of the substrate 102 adjacent to the second component 106, and / or the cooling device 126 may be directly coupled to one or both of the first component 104 and the second component 106.

[0042] The positions of the first component 104 and the second component 106 on the substrate can also be used to provide thermal control. For example, a heat-sensitive component can be arranged on the substrate 102 relative to a heat-generating component to limit exposure to the heat-generating component. For example, the first component 104 can be arranged adjacent to the outer peripheral edge of the substrate 102, such that at least a portion of the periphery of the first component 104 is exposed to the environment, rather than adjacent to the heat-generating second component 106. In some example embodiments, this configuration can provide a pathway for directly coupling a cooling device 126 to the first component 104.

[0043] refer to Figure 4The chip device 400 may include conductors 408 configured to provide the required heat transfer. The chip device 400 includes a substrate, a first component 404, a second component 406, a plurality of conductors 408, an insulating layer, and a heat sink. Except for the construction of the conductors 408, the chip device 400 has a similar construction to that of the chip device 100. The second component 406 may be a heat-generating component, such as an analog-to-digital converter. The conductors 408 extend between the first component 404 and the second component 406 and may provide a direct heat conduction path from the second component 406 to the first component 404. The conductors 408 may be shaped and positioned to increase the thermal resistance between the second component 406 and the first component 404. In some example embodiments, the length of the conductors 408 may be selected to increase the distance heat needs to travel, thereby increasing the thermal resistance of the conductors 408. For example, the conductors 408 may be configured to have a zigzag or meandering shape to increase the length. Furthermore, the shape of conductor 408 can be selected to position at least a portion of conductor 408 adjacent to a portion of a chip structure having higher thermal conductivity (such as near a conductive feature such as a via), so that heat can be preferentially transferred from conductor 408 to the conductive feature rather than to the first component 404.

[0044] exist Figure 5 and Figure 6 In another embodiment illustrated in the figure, the chip device 500 includes a different configuration in which a first component 504 is located at a corner of a substrate 502, such that two edges of the first component 504 are exposed near two edges of the substrate 502. This configuration can be used to alter the exposure of the first component 504 to other heat-generating components of the chip device 500. The chip device 500 includes a substrate 502, a first component 504, a second component 506, a plurality of conductors, an insulating layer 510, and a heat sink 512. The first component 504 may be a photosensor including a pixel array 514, which is heat-sensitive. The second component 506 may be a heat-generating component, such as an analog-to-digital converter, and may include trenches 520 in the chip device 500 to prevent direct thermal conduction between the first component 504 and the second component. Chip device 500 may also include vias similar to via 322 of chip device 100, extending between the second component 506 and the heat sink 512, and may be constructed of a material with relatively high thermal conductivity to provide low thermal resistance between the second component 506 and the heat sink 512. A portion of substrate 502 may be removed, for example by etching, to form cavity 524, which reduces the thermal mass of the portion of substrate 502 adjacent to the first component 504, which would otherwise support the first component 504, and this increases the thermal resistance between the second component 506 and the first component 504. Similar to the previous example embodiments, cavity 524 may be filled.

[0045] refer to Figure 7 and Figure 8 Additional example embodiments of an integrated circuit chip device including thermal control will be described. In an example embodiment, a first component 704 of the chip device 700 may be surrounded by a second component 706 of the chip device 700 that generates heat, and the chip device 700 may be configured such that heat transfer is directed away from the first component 704. The chip device 700 may have various different configurations for providing thermal control, as will be referred to... Figures 9a-9e The schematic diagram in the figure illustrates that the chip device 700 generally includes a substrate 702, a first component 704, a second component 706, and an insulating layer 710.

[0046] Substrate 702 forms a structural component in chip device 700 and can be shaped and scaled to guide heat transfer through chip device 700 to provide thermal control. Substrate 702 provides structure, rigidity, and thermal stability to chip device 700. Substrate 702 provides a support on which first component 704 and second component 706 are constructed and held in a desired spatial relationship. Substrate 702 also provides a structure for supporting conductors that may extend between first component 704 and second component 706 and / or between any other components included in chip device 700. Substrate 702 may be formed of monocrystalline silicon, gallium arsenide, germanium, or other structurally nonconductive materials. In some example embodiments, the thickness of the substrate is in the range of approximately 200 μm to approximately 400 μm. In at least one example embodiment, the thickness of substrate 702 is approximately 300 μm.

[0047] A first component 704 is disposed on a substrate 702. In at least one example embodiment, the first component 704 is a photosensor constructed of germanium. The photosensor may include a plurality of pixels 714 arranged in an array. In some embodiments, the first component 704 is a heat-sensitive component exhibiting efficiency that changes with temperature. For example, the first component 704 may be a photosensor having efficiency that decreases as the temperature of component 104 increases. The chip device 700 is configured to direct heat transfer away from the heat-sensitive component such that heat generated by other components does not harmfully increase the temperature of the heat-sensitive component.

[0048] A second component 706 is also disposed on the substrate 702. In the illustrated embodiment, the second component 706 may surround the first component 704. In at least one example embodiment, the second component 706 provides analog-to-digital conversion. In this example, the second component 706 may generate heat, which may cause an increase in the temperature of other parts of the chip device 700.

[0049] An insulating layer 710 may be disposed on a surface 716 of a substrate 702. In some example embodiments, the insulating layer 710 may be grown or deposited on the substrate 702. In the illustrated embodiment, the insulating layer 710 is disposed on a first surface 716 of the substrate 702 such that the insulating layer 710 is inserted between the first component 704 and the second component 706 and the substrate 702. The insulating layer 710 may provide electrical insulation between conductors included in the chip device 700. The insulating layer 710 may also provide electrical insulation between the first component 704 and the substrate 702 and between the second component 706 and the substrate 702. In some example embodiments, the insulating layer 710 is formed of SiO2 grown on the substrate 702, and the SiO2 has a thermal conductivity of approximately 1.5 W / mK. The SiO2 insulating layer 710 may be grown on the silicon substrate 702 using thermal oxidation, wet oxidation, or dry oxidation. In some example embodiments, the thickness of the insulating layer 710 is in the range of approximately 4.0 μm to approximately 5.0 μm. In at least one example embodiment, the thickness of the insulating layer 710 is approximately 4.5 μm.

[0050] The chip device 700 can have various configurations, including those employing heat sinks and cooling devices, such as... Figures 9a-9e As illustrated in the diagram. Figure 9a In at least one example embodiment shown, chip device 700a includes a substrate 702a, a first component 704a, a second component 706a, an insulating layer 710a, and a heat sink 912a. Isolation features, such as isolation trenches 720a, surround the first component 704a and thermally isolate the first component 704a from the second component 706a to prevent direct conduction between the first component 704a and the second component 706a. The substrate 702a defines a cavity 924a in a portion of the substrate 702a, the cavity 924a being disposed adjacent to the first component 704a, which would otherwise support the first component 704a. The cavity 924a removes the thermal mass of the substrate 702a adjacent to the first component 704a and reduces the conduction path from the periphery of the substrate 702a toward the first component 704a. The heat sink 912a extends across the cavity 724a and is thermally coupled to a peripheral portion of the substrate 702a. Heat sink 912a can be used to seal cavity 924a and cavity 924a can be filled with a fluid, such as liquid or gas, used as a thermal insulator. Substrate 702a may also include a plurality of conductive features such as via 922a, which extends between second component 706a and heat sink 912a and provides reduced thermal resistance between second component 706a and heat sink 912a.

[0051] exist Figure 9bIn another example embodiment shown, chip device 700b includes a substrate 702b, a first component 704b, a second component 706b, an insulating layer 710b, a heat sink 912b, and a cooling device 926b coupled to the heat sink 912b. Isolation features such as isolation trenches 720b surround the first component 704b and thermally isolate the first component 704b from the second component 706b to prevent direct conduction between the first component 704b and the second component 706b. The substrate 702b defines a cavity 924b in a portion of the substrate 702b, the cavity 924b being arranged adjacent to the first component 704b, which would otherwise support the first component 704b. The cavity 924b removes the thermal mass of the substrate 702b adjacent to the first component 704b and reduces the conduction path from the periphery of the substrate 702b toward the first component 704b. The heat sink 912b extends across cavity 924b and is thermally coupled to a peripheral portion of substrate 702b. A cooling device 926b, which may be a solid-state cooling device, is thermally coupled to the heat sink 912b to draw heat away from it. Substrate 702b may also include multiple conductive features such as vias 922b, which extend between the second component 706b and the heat sink 912b and reduce the thermal resistance between them.

[0052] exist Figure 9cIn another example embodiment shown, chip device 700c includes a substrate 702c, a first component 704c, a second component 706c, an insulating layer 710c, a heat sink 912c, and a cooling device 926c inserted between the substrate 702c and the insulating layer 710c. Isolation features, such as isolation trenches 720c, surround the first component 704c and thermally isolate the first component 704c from the second component 706c to prevent direct conduction between the first component 704c and the second component 706c. The substrate 702c defines a cavity 924c in a portion of the substrate 702c, the cavity 924c being arranged adjacent to the first component 704c, which would otherwise support the first component 704c. The cavity 924c removes the thermal mass of the substrate 702c adjacent to the first component 704c and reduces the conduction path from the periphery of the substrate 702c toward the first component 704c. Heat sink 912c extends across cavity 924c and is thermally coupled to a peripheral portion of substrate 702c. Cooling device 926c, which may be a solid-state cooling device, is thermally coupled to substrate 702c and insulating layer 710c to absorb heat from the interface between substrate 702c and insulating layer 710c. In at least one example embodiment, cooling device 926c may be scaled such that it extends only across a portion of chip device 700c, for example, such that cooling device 926c is arranged only adjacent to first component 704c or only adjacent to second component 706c, so that it can be used to selectively cool a portion of chip device 700c. Substrate 702c may also include multiple conductive features such as via 922c, which extends between second component 706c and heat sink 912c to reduce thermal resistance between second component 706c and heat sink 912c.

[0053] exist Figure 9dIn another example embodiment shown, chip device 700d includes a substrate 702d, a first component 704d, a second component 706d, an insulating layer 710d, and a plurality of spaced heat sinks 912d. Isolation features, such as isolation trenches 720d, surround the first component 704d and thermally isolate the first component 704d from the second component 706d to prevent direct conduction between the first component 704d and the second component 706d. The substrate 702d defines a cavity 924d in a portion of the substrate 702d, the cavity 924d being arranged adjacent to the first component 704d, which would otherwise support the first component 704d. The cavity 924d removes the thermal mass of the substrate 702d adjacent to the first component 704d and reduces the conduction path from the periphery of the substrate 702d toward the first component 704d. The plurality of heat sinks 712d are spaced apart from each other and are arranged on the peripheral portion of the substrate 702d. The substrate 702d may also include multiple conductive features such as via 922d, which extends between the second component 706d and the heat sink 912d and reduces the thermal resistance between the second component 706d and the heat sink 912d.

[0054] exist Figure 9e In another example embodiment shown, chip device 700e includes a substrate 702e, a first component 704e, a second component 706e, an insulating layer 710e, a plurality of spaced-apart heat sinks 912e, and a plurality of cooling devices 926e coupled to the heat sinks 912e. Isolation features such as isolation trenches 720e surround the first component 704e and thermally isolate the first component 704e from the second component 706e to prevent direct conduction between the first component 704e and the second component 706e. The substrate 702e defines a cavity 924e in a portion of the substrate 702e, the cavity 924e being arranged adjacent to the first component 704e, which would otherwise support the first component 704e. The cavity 924e removes the thermal mass of the substrate 702e adjacent to the first component 704e and reduces the conduction path from the periphery of the substrate 702e toward the first component 704e. The heat sinks 912e extend across the cavity 924e and are thermally coupled to a peripheral portion of the substrate 702e. Each cooling device 926e of the solid-state cooling device may be thermally coupled to one of a plurality of heat sinks 912e to remove heat from the respective heat sink 912e. The substrate 702e may also include a plurality of conductive features such as vias 922e, which extend between the second component 706e and the heat sink 912e to reduce the thermal resistance between the second component 706e and the heat sink 912e.

[0055] Any embodiment of the chip device described herein can also be housed within a housing. The housing may be sealed to retain air or another gas such as nitrogen, or the housing may be evacuated to restrict convection within the housing. In another example embodiment, the housing may be filled with a refrigerant.

[0056] Figure 10 A flowchart 1000 depicts an example method for manufacturing a chip device with thermal control according to one embodiment. The method of flowchart 1000 can be used to construct various embodiments of the chip device, such as... Figure 1 - The structure illustrated in Figure 9. Based on the discussion of flowchart 1000, further structural and operational embodiments will be clear to those skilled in the art.

[0057] like Figure 10 As shown in the flowchart 1000, the method begins at step 1002. In step 1002, a first wafer is manufactured. For example, a wafer (such as...) Figure 11a The wafer 1100 can be manufactured by slicing and polishing an ingot formed of a high-purity single-crystal semiconductor such as silicon or germanium. In an example embodiment where the wafer 1100 is constructed of silicon, an insulating layer 1102 of SiO2 can be grown or deposited on the wafer 1100, such as... Figure 11b As shown in the image.

[0058] At step 1004, the first wafer is filled using the first and second components. Microfabrication techniques (such as microlithography, doping, thin film application, etching, bonding, and polishing) can be used to fill the first wafer using components. For example, those techniques can be used to fill wafer 1100 using first component 1104 and second component 1106. In some example embodiments, the first component 1104 is a heat-sensitive component, such as a photosensor, and the second component 1106 generates heat, such as an analog-to-digital converter. The first component 1104 and the second component 1106 are arranged on the first wafer such that they are spaced apart, for example, by trench 1108. Figure 11c As shown. Figure 11d As shown, trench 108 can be filled with a material with relatively low thermal conductivity (such as SiO2).

[0059] After filling the first wafer 1100 with selected components, the first wafer 1100 can be prepared for bonding to a second wafer. In at least one example embodiment, the wafer 1100 can be sliced ​​or diced to a selected size or configuration. In at least one example embodiment, the first wafer 1100 can be diced at line D such that the first component 1104 is arranged adjacent to the edge of the first wafer 1100. This configuration can be used to construct chip devices, such as those respectively in… Figure 1 and Figure 5The chip devices 100 and 500 are illustrated in the diagram. Other preparations for bonding to the second wafer may also be performed, such as polishing or depositing a metal bonding layer. In some example embodiments, wafer 1100 is polished to reduce its thickness, such as... Figure 11e As shown in the image.

[0060] At step 1006, a second wafer is manufactured. For example, a wafer (such as...) Figure 11f The wafer 1110 can be manufactured by slicing and polishing an ingot formed of a high-purity single-crystal semiconductor such as silicon or germanium. In an example embodiment where the wafer 1110 is constructed of silicon, a layer of SiO2 can be grown or deposited on the wafer 1110 to serve as a mask for subsequent etching.

[0061] At step 1008, a cavity is formed in the second wafer. For example, cavity 1112 may be etched into the second wafer 1110. Any wet or dry etching technique can be used to etch cavity 1112. In at least one embodiment, anisotropic etching is used to etch cavity 1112, such that the cavity has tapered sidewalls, as... Figure 11g As shown in the figure. In another embodiment, cavity 1112 may be formed in the second wafer 1110 such that cavity 1112 has a constant width.

[0062] At step 1010, a via is formed in the second wafer. For example, a channel can be etched into the second wafer 1110 and filled with a material having relatively high thermal conductivity to form a via 1114, such as... Figure 11h As shown in the diagram. In some example embodiments, the channel is filled with a material having a thermal conductivity greater than that of the material of the adjacent portion of the second wafer 1110. For example, the second wafer may be constructed of silicon having a thermal conductivity of approximately 145.0 W / mK, and the material used to fill the channel may have a thermal conductivity greater than 145.0 W / mK. In at least one example embodiment, copper having a thermal conductivity of approximately 386.0 W / mK may be used to fill the channel. In at least one example embodiment, aluminum having a thermal conductivity of approximately 237.0 W / mK may be used to fill the channel. The material used to fill the channel to form the via 1114 may be deposited using electroplating.

[0063] At step 1012, a heat sink is formed. For example, Figure 1 The heat sink 112 can be constructed from a metal plate or metal foil. In other example embodiments, the heat sink can be formed by depositing a material with relatively high thermal conductivity on a substrate. The heat sink can be constructed as shown in any of the example embodiments described above. For example, the heat sink can be formed from a single heat sink component, or it can be formed from multiple heat sink components.

[0064] At step 1014, the first wafer, the second wafer, and the heat sink are coupled. The first wafer, the second wafer, and the heat sink are coupled such that the first component is adjacent to a cavity formed in the second wafer. The first wafer, the second wafer, and the heat sink are also coupled such that a via extends between the second component and the heat sink. For example, as... Figure 11i and Figure 11j As shown, for example, by using wafer bonding technology, the first wafer 1100, the second wafer 1110, and the heat sink 1116 are aligned into a desired configuration and the components are coupled. Figure 11j As shown, the first wafer 1100, the second wafer 1110, and the heat sink 1116 are coupled such that the first component 1104 is adjacent to the cavity 1112 formed in the second wafer 1110, and such that the via 1114 extends between the second component 1106 and the heat sink 1116.

[0065] III. Further discussion of some example embodiments

[0066] A first example chip device includes a substrate, a first component, a second component, and a heat sink. The first component is disposed on the substrate. The second component is disposed on the substrate spaced apart from the first component, and the second component generates heat. The heat sink is coupled to the substrate such that at least a portion of the substrate is inserted between the second component and the heat sink. The thermal resistance between the second component and the heat sink is less than the thermal resistance between the second component and the first component.

[0067] In a first aspect of the first example chip device, the substrate includes a cavity, and a first component is arranged adjacent to the cavity.

[0068] In a second aspect of the first example chip device, the chip device further includes a via extending between the second component and the heat sink. The substrate is constructed of a first material having a first thermal conductivity, and the via is constructed of a second material having a second thermal conductivity greater than the first thermal conductivity. The second aspect of the first example chip device may be implemented in combination with the first aspect of the first example chip device, but the example embodiments are not limited to this aspect.

[0069] In a third aspect of the first example chip device, the first component is a photosensitive sensor having efficiency that decreases with increasing temperature, wherein the photosensitive sensor includes a pixel array. The third aspect of the first example chip device may be implemented in combination with the first and / or second aspects of the first example chip device, but the example embodiments are not limited to this aspect.

[0070] In a fourth aspect of the first example chip device, the first component is arranged adjacent to the peripheral edge of the substrate. The fourth aspect of the first example chip device may be implemented in combination with the first, second, and / or third aspects of the first example chip device, but the example embodiments are not limited to this aspect.

[0071] In a fifth aspect of the first example chip device, the second component includes an analog-to-digital converter. The fifth aspect of the first example chip device may be implemented in combination with the first, second, third, and / or fourth aspects of the first example chip device, but the example embodiments are not limited to this aspect.

[0072] In a sixth aspect of the first example chip device, the chip device further includes a cooling device coupled to a heat sink. The sixth aspect of the first example chip device may be implemented in combination with the first, second, third, fourth, and / or fifth aspects of the first example chip device, but the example embodiments are not limited to this aspect.

[0073] In a sixth aspect of the first example chip device, the cooling device is a solid-state cooling device.

[0074] The second example chip device includes a substrate, a first component, a second component, a heat sink, and a via. The substrate is constructed of a first material having a first thermal conductivity and includes a cavity. The first component is disposed on the substrate adjacent to the cavity. The second component is disposed on the substrate spaced apart from the first component and generates heat. The heat sink is coupled to the substrate. The via extends between the second component and the heat sink and is constructed of a second material having a second thermal conductivity greater than the first thermal conductivity.

[0075] In a first aspect of the second example chip device, the cavity is filled with a third material having a third thermal conductivity lower than that of the first thermal conductivity.

[0076] In a second aspect of the second example chip device, the first component is a photosensor having efficiency that decreases with increasing temperature, and the photosensor includes a pixel array. The second aspect of the second example chip device can be implemented in conjunction with the first aspect of the second example chip device, but the example embodiments are not limited to this aspect.

[0077] In a third aspect of the second example chip device, the first component is arranged adjacent to the peripheral edge of the substrate. The third aspect of the second example chip device may be implemented in combination with the first and / or second aspects of the second example chip device, but the example embodiments are not limited to this aspect.

[0078] In a fourth aspect of the second example chip device, the second component includes an analog-to-digital converter. This fourth aspect of the second example chip device may be implemented in combination with the first, second, and / or third aspects of the second example chip device, but the example embodiments are not limited to this aspect.

[0079] In a fifth aspect of the second example chip device, the chip device further includes a cooling device coupled to a heat sink. The fifth aspect of the second example chip device may be implemented in combination with the first, second, third, and / or fourth aspects of the second example chip device, but the example embodiments are not limited to this aspect.

[0080] In a fifth aspect of the second example chip device, the cooling device is a solid-state cooling device.

[0081] An example method of manufacturing a chip device with thermal control includes: manufacturing a first wafer; filling the first wafer with a first component and a second component; manufacturing a second wafer; forming a cavity in the second wafer; forming a via in the second wafer; manufacturing a heat sink; and coupling the first wafer, the second wafer, and the heat sink. The second component is spaced apart from the first component and generates heat during use. The second wafer is made of a first material having a first thermal conductivity. The via is formed in the second wafer and is constructed of a second material having a second thermal conductivity greater than the first thermal conductivity. The first wafer, the second wafer, and the heat sink are coupled such that the second wafer is at least partially inserted between the heat sink and the first wafer, the first component is arranged adjacent to the cavity, and the via extends between the second component and the heat sink.

[0082] In a first aspect of the example method, the method further includes dicing the first wafer adjacent to the first component.

[0083] In a second aspect of the example method, the method further includes forming a first metal layer on a first wafer and forming a second metal layer on a second wafer. The first metal layer of the first wafer is coupled to the second metal layer of the second wafer. The second aspect of the example method can be implemented in combination with the first aspect of the example method, but the example embodiments are not limited to this aspect.

[0084] In a third aspect of the example method, the method further includes filling the cavity with a third material having a third thermal conductivity lower than the first thermal conductivity. The third aspect of the example method may be implemented in combination with the first and / or second aspects of the example method, but the example embodiments are not limited to this aspect.

[0085] In a fourth aspect of the example method, the method further includes coupling a solid-state cooling device to a heat sink. This fourth aspect of the example method may be implemented in combination with the first, second, and / or third aspects of the example method, but the example embodiments are not limited to this aspect.

[0086] IV. Conclusion

[0087] Although the subject matter has been described in language specific to structural features and / or actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as examples of implementing the claims, and other equivalent features and actions are intended to be within the scope of the claims.

Claims

1. A chip device comprising: a first wafer; a first component disposed on the first wafer, the first component having an efficiency that decreases as a temperature of the first component increases; a second component disposed on the first wafer spaced apart from the first component, wherein the second component generates heat; a second wafer constructed of a first material having a first thermal conductivity, wherein the second wafer includes a cavity and a via, and wherein the via is constructed of a second material having a second thermal conductivity that is greater than the first thermal conductivity; and a heat sink coupled to the second wafer such that at least a portion of the second wafer is interposed between the first wafer and the heat sink, wherein a thermal resistance between the second component and the heat sink is less than a thermal resistance between the second component and the first component, wherein the first component is disposed adjacent to the cavity, and wherein the via extends between the second component and the heat sink.

2. The chip device of claim 1, wherein the first component is a photosensitive sensor having an efficiency that decreases as a temperature of the photosensitive sensor increases, wherein the photosensitive sensor includes an array of pixels.

3. The chip device of claim 1, wherein the first component is disposed adjacent to a peripheral edge of the first wafer.

4. The chip device of claim 1, wherein the second component includes an analog-to-digital converter.

5. The chip device of claim 1, further comprising a cooling device coupled to the heat sink.

6. The chip device of claim 5, wherein the cooling device is a solid-state cooling device.

7. A chip device comprising: a first wafer; a second wafer constructed of a first material having a first thermal conductivity, the second wafer including a cavity; a first component disposed on the first wafer, wherein a projection of the first component on a surface of the first wafer overlaps a projection of the cavity on the surface of the first wafer; a second component disposed on the first wafer spaced apart from the first component, wherein the second component generates heat; a heat sink coupled to the second wafer, wherein a thermal resistance between the second component and the heat sink is less than a thermal resistance between the second component and the first component; and a via disposed in the second wafer and extending between the second component and the heat sink, wherein the via is constructed of a second material having a second thermal conductivity that is greater than the first thermal conductivity.

8. The chip device of claim 7, wherein the cavity is filled with a third material having a third thermal conductivity that is less than the first thermal conductivity.

9. The chip device of claim 7, wherein the first component is a photosensitive sensor having an efficiency that decreases as a temperature of the photosensitive sensor increases, wherein the photosensitive sensor includes an array of pixels.

10. The chip device of claim 9, wherein the first component is disposed adjacent to a peripheral edge of the first wafer.

11. The chip device of claim 7, wherein the second component comprises an analog-to-digital converter.

12. The chip device of claim 7, further comprising a cooling device coupled to the heat spreader.

13. The chip device of claim 12, wherein the cooling device is a solid-state cooling device.

14. A method of fabricating a chip device having thermal control, the method comprising: fabricating a first wafer; populating the first wafer with a first component and a second component, the second component spaced apart from the first component, wherein the second component generates heat during use; fabricating a second wafer from a first material having a first thermal conductivity; forming a cavity in the second wafer; forming a via in the second wafer, wherein the via is constructed from a second material having a second thermal conductivity, the second thermal conductivity greater than the first thermal conductivity; fabricating a heat spreader, wherein a thermal resistance between the second component and the heat spreader is less than a thermal resistance between the second component and the first component; and coupling the first wafer, the second wafer, and the heat spreader such that the second wafer is at least partially interposed between the heat spreader and the first wafer, wherein the first component is disposed adjacent to the cavity, and wherein the via extends between the second component and the heat spreader.

15. The method of fabricating a chip device of claim 14, further comprising dicing the first wafer adjacent to the first component.

16. The method of fabricating a chip device of claim 14, further comprising: forming a first metal layer on the first wafer; and forming a second metal layer on the second wafer, wherein the first metal layer of the first wafer is coupled to the second metal layer of the second wafer.

17. The method of fabricating a chip device of claim 14, further comprising populating the cavity with a third material having a third thermal conductivity less than the first thermal conductivity.

18. The method of fabricating a chip device of claim 14, further comprising coupling a solid-state cooling device to the heat spreader.

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