Fabricating semiconductor structures with multiple quantum wells

Abstract

The example relates to a method for fabricating a semiconductor structure having multiple quantum wells. The method includes: providing a substrate comprising a binary semiconductor compound having a first lattice constant; depositing at least a first layer on the substrate and a second layer in contact with the first layer to form a first stack of substantially planar semiconductor layers on the substrate, the first layer being a first semiconductor alloy comprising InP, and the second layer being a second semiconductor alloy comprising InP; depositing a third layer of the binary semiconductor compound having the first lattice constant in contact with the first stack; depositing at least a fourth layer on the third layer and a fifth layer in contact with the fourth layer to form a second stack of substantially planar semiconductor layers on the third layer, the fourth layer comprising a third semiconductor alloy containing InP, and the fifth layer comprising a fourth semiconductor alloy containing InP.

Description

Technical Field

[0001] This disclosure generally relates to a method for fabricating a semiconductor structure having multiple quantum wells. Background Technology

[0002] Quantum wells are commonly used in semiconductor structures to provide electronic confinement. For example, in optoelectronic devices, quantum wells are used to tune the electronic bandgap, thereby tuning the energy (or frequency) of photons that are emitted (in the case of an emitter) or absorbed (in the case of an absorber).

[0003] In many applications, the effect of a single quantum well can be enhanced by providing multiple quantum wells in a stack. In the case of an emitter (such as a laser), this can increase the rate of stimulated emission in the emitter, while in the case of an absorber, it can increase the absorption rate.

[0004] A commonly used commercial material platform for optoelectronic devices is indium phosphide (InP), which allows for the integration of active and passive optical functions into so-called photonic integrated circuits (PICs).

[0005] It is desirable to provide a more reliable method for fabricating a semiconductor structure with multiple quantum wells. Summary of the Invention

[0006] One aspect of this disclosure provides a method for fabricating a semiconductor structure having multiple quantum wells. The method includes: providing a substrate comprising a binary semiconductor compound having a first lattice constant; depositing at least a first layer on the substrate and a second layer in contact with the first layer to form a first stack of substantially planar semiconductor layers on the substrate, wherein the first layer, being a first semiconductor alloy, comprises InP, and the second layer, being a second semiconductor alloy, comprises InP; depositing a third layer of the binary semiconductor compound having the first lattice constant in contact with the first stack; depositing at least a fourth layer on the third layer and a fifth layer in contact with the fourth layer to form a second stack of substantially planar semiconductor layers on the third layer, wherein the fourth layer comprises a third semiconductor alloy containing InP, and the fifth layer comprises a fourth semiconductor alloy containing InP.

[0007] Another aspect of this disclosure provides a semiconductor structure having multiple quantum wells. The semiconductor structure includes: a substrate comprising a binary semiconductor compound having a first lattice constant; a first stack of substantially planar semiconductor layers on the substrate, the first stack including at least a first layer on the substrate and a second layer in contact with the first layer, the first layer being a first semiconductor alloy comprising InP, the second layer being a second semiconductor alloy comprising InP; a third layer in contact with the first stack, the third layer being a binary semiconductor compound having the first lattice constant; and a second stack of substantially planar semiconductor layers on the third layer, the second stack including at least a fourth layer on the third layer and a fifth layer in contact with the fourth layer, the fourth layer comprising a third semiconductor alloy containing InP, the fifth layer comprising a fourth semiconductor alloy containing InP.

[0008] This disclosure further provides an electro-absorption modulator or an electro-refractive modulator including a semiconductor structure. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure with multiple quantum wells, based on an example.

[0010] Figure 2 This is a scanning electron micrograph of a semiconductor structure with multiple InP-containing quantum wells, which shows the defects in the resulting structure;

[0011] Figure 3 It is a scanning electron micrograph of a semiconductor structure with multiple quantum wells that do not contain InP;

[0012] Figure 4 It is a schematic diagram of a semiconductor structure based on an example; and

[0013] Figure 5 This is a scanning electron micrograph of a semiconductor structure with multiple InP-containing quantum wells, based on an example. Detailed Implementation

[0014] The examples described in this article relate to methods for fabricating semiconductor structures. Specifically, but not exclusively, they relate to fabricating semiconductor structures with multiple quantum wells.

[0015] As will be explained in detail below, at least in an example of a semiconductor structure having a quantum well including InP, the examples described herein provide an improved semiconductor structure. Therefore, this structure reduces the scattering of light transmitted through it, increases the stimulated emission rate in the light-emitting portion, and increases the absorption rate in the light-absorbing portion. This allows for a more efficient optoelectronic device, and thus a more efficient PIC.

[0016] Figure 1 This is a flowchart illustrating, in a common manner, a method 100 for fabricating a semiconductor structure having multiple quantum wells according to an example. See below for reference. Figure 5 Describe a corresponding example semiconductor structure.

[0017] At block 102, a substrate is provided. The substrate comprises a binary semiconductor compound having a first lattice constant.

[0018] For example, the substrate may be an InP substrate. That is, the substrate mainly comprises InP. The substrate may be pure InP (within acceptable purity tolerances), or it may include other materials, such as dopants or impurities, wherein the material comprises at least 99% InP. For example, the substrate may be doped with a dopant material such that the substrate can be considered n-doped, or the substrate may be doped with a dopant material such that the substrate can be considered p-doped.

[0019] At block 104, method 100 includes depositing at least: a first layer on a substrate and a second layer in contact with the first layer to form a first stack of substantially planar semiconductor layers on the substrate. The first layer is a first semiconductor alloy comprising InP, and the second layer is a second semiconductor alloy comprising InP.

[0020] The first stack comprises multiple layers. The number of layers in the first stack is less than a threshold number; exceeding this threshold number will result in one or more layers in the stack exhibiting a defect. The fabrication of the first stack involves interleaving several layers of a first semiconductor alloy and a corresponding number of layers of a second semiconductor alloy. See below for reference. Figure 3 As described, at least in some instances, specifically in instances where the first and second layers include InP, the tendency for defects to appear in the semiconductor layers of the first stack increases with the increase in the number of semiconductors.

[0021] By assuming that the layers are substantially planar, it is conceivable, for example, to deposit the layers on a substrate such that the upper surface of each of the layers is parallel to the surface of the substrate on which the first layer is deposited.

[0022] In some instances, the first layer is on the substrate in the sense that it is deposited to contact the substrate. In other instances, the first layer is on the substrate because it is supported by the substrate but does not directly contact it. For example, there may be one or more intermediate layers, such as materials that do not include InP, such as indium aluminum arsenide (InAlAs).

[0023] As a general reference to the term "on" as used herein, a layer is specified as being in direct contact with a layer (such as an underlying layer); and a layer on top of a layer (such as an underlying layer) may be in direct contact with or be supported by that layer, wherein there is one or more intermediate layers (such as layers of a material excluding InP) between such layers.

[0024] In some instances, each of these layers is deposited substantially across the entire surface area of ​​the substrate (except for the area of ​​the substrate held by a wafer jig in a reactor where semiconductors are being manufactured).

[0025] Figure 2 This is a scanning electron micrograph of a semiconductor structure comprising multiple (32 in total) quantum wells containing InP; in this example, the quantum wells are formed from thin layers of indium gallium arsenide phosphide (InGaAsP) configured to avoid strain by matching the lattice constant of the substrate. Figure 2 As shown, growing numerous consecutive semiconductor quantum wells including InP can lead to morphological defects in the layers of the semiconductor structure, as described below. These defects can manifest as significant nonplanarity (e.g., undulations) in one or more layers of the semiconductor. Such defects can prevent epitaxial growth or cause device failure in a device incorporating the semiconductor structure, thus limiting the number of quantum wells that can be grown in the structure.

[0026] like Figure 2 As shown, in cross-section, undulations are exhibited within the layers of the structure. These undulations may not exist at the surface of the treated structure, which may still exhibit a planar surface; for example, this could be due to the planarization effect of an InP layer deposited on the semiconductor structure (e.g., to form an electrical contact).

[0027] Therefore, the inventors have learned that a problem arises when using InP to fabricate multiple quantum wells, a problem that, to date, has not occurred when fabricating multiple quantum wells using other semiconductor material platforms. The inventors have determined that, depending on the processing conditions (e.g., pressure and temperature), defects are observed when growing more than approximately 16 quantum wells in a stack.

[0028] Therefore, in some instances, the number of layers in each of the first semiconductor alloy and the second semiconductor alloy is greater than 8 and less than 16, such that the total number of layers in the first stack is less than 32.

[0029] On the contrary, Figure 3 This is a scanning electron micrograph of a semiconductor structure comprising 36 quantum wells, excluding InP; in this example, the quantum wells are formed from indium gallium arsenide (InAlGaAs). As shown, Figure 2 The quantum well shown is substantially planar; although more quantum wells can be created using InP-containing quantum wells without forming a pattern like... Figure 2 The defects shown are illustrated.

[0030] To resolve the above reference Figure 2 The problem described involves depositing a third layer, comprising a binary semiconductor material having a first lattice constant, in contact with the first stack at block 106. For example, if the substrate is InP, the third layer can also be InP.

[0031] Subsequently, at block 108, method 100 includes depositing at least: a fourth layer in contact with the third layer and a fifth layer in contact with the fourth layer, to form a second stack of substantially planar semiconductor layers on the third layer. The fourth layer includes a third semiconductor alloy comprising InP, and the fifth layer includes a fourth semiconductor alloy comprising InP.

[0032] As those skilled in the art will understand, various techniques can be used to deposit semiconductor material layers based on the examples described herein. These techniques may include chemical vapor deposition techniques, such as metal-organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE).

[0033] Figure 4 This is a diagram of a semiconductor structure 400 based on an example. (Refer to the above reference.) Figure 1 The described method is used to fabricate semiconductor structures.

[0034] The semiconductor structure 400 includes a substrate 402 on which quantum wells are grown.

[0035] Semiconductor structure 400 includes a first stack 404 of quantum wells. The first stack 404 includes multiple alternating layers of a first semiconductor alloy 406 and a second semiconductor alloy 408. (See above reference.) Figure 1 As described in block 104, a first layer of a first semiconductor alloy 406 is deposited on a substrate 402, and a second layer of a second semiconductor alloy 408 is deposited in contact with the first layer of the first semiconductor alloy 406. Multiple quantum wells are fabricated by alternating between deposition processes for depositing the first semiconductor alloy 406 and deposition processes for depositing the second semiconductor alloy 408.

[0036] For the reasons described above, the first stack 404 comprises fewer than 32 layers. That is, the first stack comprises fewer than 16 layers of first semiconductor alloy 406 and fewer than 16 layers of second semiconductor alloy 408.

[0037] In some instances, each of the first semiconductor alloy 406 and the second semiconductor alloy 408 comprises a ternary semiconductor alloy or a quaternary semiconductor alloy. For example, each of the first semiconductor alloy 406 and the second semiconductor alloy 408 comprises InGaAsP, wherein the relative amounts of indium phosphide (InP), gallium arsenide (GaAs), indium arsenide (InAs), and gallium phosphide (GaP) are different between the first semiconductor alloy 406 and the second semiconductor alloy 408. Each of the first semiconductor alloy 406 and the second semiconductor alloy 408 may be doped (e.g., p-doped or n-doped).

[0038] Although in some instances it is envisioned that neither of the first semiconductor alloy 406 nor the second semiconductor alloy 408 is subjected to strain (e.g., the lattice constant of a layer matches the layer in which it contacts), it is desirable to select a lattice constant that introduces strain to modify, for example, the optical absorption or emission properties of the semiconductor structure 400.

[0039] In some instances, the layers of each of the first semiconductor alloy 406 and the second semiconductor alloy 408 are less than 15 nanometers (nm).

[0040] A third layer 410 is deposited in contact with the first stack 404. The third layer 410 is a binary semiconductor whose lattice constant is substantially equal to that of the substrate 402, as shown in the reference above. Figure 1 The block 106 describes it as "[substantially equal]", meaning that the introduction of the third layer 410 is not intended to cause strain.

[0041] The thickness of the third 410 layer can range from 4nm to 100nm.

[0042] The inclusion of a third semiconductor layer 410 having a lattice constant substantially equal to that of the substrate 402 means that the manufacturing process can be performed prior to the manufacture of the third layer 410 without modifying the manufacturing reactor or making any modifications to the reactor's process conditions (such as temperature or pressure). Figure 2 (The method). In this example, it makes it easy to integrate into existing manufacturing processes.

[0043] Furthermore, the effect of adding only a single thin layer of binary semiconductor material on the overall electro-optic properties of semiconductor structure 400 is negligible, and therefore the performance of the device incorporating semiconductor structure 400 is not adversely affected by the inclusion of the third layer 410.

[0044] A second stack 412 of the quantum well is deposited in contact with a third layer 410. The second stack 412 includes multiple alternating layers of a third semiconductor alloy 414 and a fourth semiconductor alloy 416. As described above with reference to block 108, a layer of the third semiconductor alloy 414 is deposited on the third layer 410, and a layer of the fourth semiconductor alloy 416 is deposited on the layer of the third semiconductor alloy 414 deposited in contact with the third layer 410. Multiple quantum wells are fabricated by alternating between deposition processes for depositing the third semiconductor alloy 414 and deposition processes for depositing the fourth semiconductor alloy 416.

[0045] For the reasons stated above, the second stack 412 also includes fewer than 32 layers. That is, the first stack includes fewer than 16 layers of first semiconductor alloy 406 and fewer than 16 layers of second semiconductor alloy 408.

[0046] In some instances, each of the third semiconductor alloy 414 and the fourth semiconductor alloy 416 comprises a ternary semiconductor alloy or a quaternary semiconductor alloy. For example, each of the third semiconductor alloy 414 and the fourth semiconductor alloy 416 comprises InGaAsP, wherein the relative amounts of indium phosphide (InP), gallium arsenide (GaAs), indium arsenide (InAs), and gallium phosphide (GaP) differ between the third semiconductor alloy and the fourth semiconductor alloy (414, 416). Each of the third semiconductor alloy 414 and the fourth semiconductor alloy 416 may be doped (e.g., p-doped or n-doped).

[0047] Although it is envisioned that in some instances neither of the third semiconductor alloy 414 nor the fourth semiconductor alloy 416 undergoes strain (e.g., the lattice constant of one layer matches that of the adjacent layer), it may be desirable to select a lattice constant that introduces strain to modify, for example, the optical absorption or emission properties of the semiconductor structure 400.

[0048] In some instances, references can be repeated. Figure 1 The processes described in blocks 106 and 108 are for further increasing the number of quantum wells in the semiconductor structure 400.

[0049] Despite Figure 4 In the example shown, the first stack 404 and the second stack 412 have an equal number of layers, such that the third layer 410 is at the center of the overall stack. However, in other examples, the first stack 404 and the second stack 412 have different numbers of quantum well layers. That is, the third layer 410 may be located elsewhere within the semiconductor structure 400, and not necessarily in the exact center of the quantum well layers. For example, in a semiconductor structure 400 comprising 25 quantum well layers, the third layer 410 may be deposited after nine quantum wells have already been fabricated, and 16 quantum wells may be fabricated above the third layer 410.

[0050] Figure 5 This is a scanning electron micrograph of a semiconductor structure comprising 24 quantum wells containing InP; in this example, the quantum wells are formed from thin layers of indium gallium arsenide phosphide (InGaAsP), which are configured to avoid strain by matching the lattice constant of the substrate. The aforementioned third layer 410 can be identified as a bright band approximately at the center of a stack within the darker band (corresponding to the quantum well structure). Figure 2 As shown, the introduction of a third layer 410 (which is a single thin layer of a material) enables, for example, Figure 2 The presence of the defects shown significantly increases the number of InP-containing quantum well layers that can be fabricated in a semiconductor structure. Therefore, the above reference... Figure 1 The described method provides a simple and efficient approach to allow for the growth of thicker stacks containing InP quantum wells.

[0051] For example, increasing the total thickness of a stack of repeating epitaxial quantum wells by increasing optical confinement in the semiconductor can be useful. For instance, this could produce a more efficient electro-absorption or electro-refractive modulator, since the efficiency of electro-absorption and electro-refractive modulators is related to optical confinement.

[0052] The examples above should be understood as illustrative. It should be understood that any feature described with respect to any example may be used alone or in combination with other described features, and may also be used in combination with one or more features of any other such example or any combination of such examples. Furthermore, equivalents and modifications not described above may be employed without departing from the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure having multiple quantum wells, the method comprising: A substrate is provided, the substrate comprising a binary semiconductor compound having a first lattice constant; A first stack of quantum wells is formed on the substrate. The first stack includes a planar semiconductor layer comprising more than 8 and less than 16 layers of a first semiconductor alloy including InP and more than 8 and less than 16 layers of a second semiconductor alloy including InP. The first stack is formed by depositing at least: A first layer on the substrate, the first layer of the first semiconductor alloy comprising InP, and A second layer in contact with the first layer, the second layer of the second semiconductor alloy comprising InP, A third layer of a binary semiconductor compound having the first lattice constant of the substrate is deposited in contact with the first stack. Deposition at least: A fourth layer on the third layer, the fourth layer comprising a third semiconductor alloy containing InP, and A fifth layer in contact with the fourth layer, the fifth layer comprising a fourth semiconductor alloy containing InP, A second stack, comprising a quantum well including planar semiconductor layers, is formed on the third layer.

2. The method of claim 1, wherein the first stack comprises a plurality of layers, the plurality of layers including the first layer and the second layer, wherein a total number of layers in the first stack is less than a threshold number of layers, and if the threshold number of layers is exceeded, one or more layers of the first stack will exhibit a defect.

3. The method of claim 1, wherein the first stack comprises a plurality of layers, the plurality of layers including the first layer and the second layer, and in the absence of the third layer and the first stack comprising additional layers, there is a tendency for at least one layer of the first stack to exhibit a defect.

4. The method according to any one of claims 2 to 3, wherein the defect is at least one of the following: one or more undulations and irregularities in the planarity.

5. The method of claim 3, wherein the third layer at least partially eliminates the tendency, such that the second stack is free of the defect.

6. The method according to any one of claims 2, 3, and 5, wherein the first stack comprises fewer than 32 layers.

7. The method according to any one of claims 1-3 and 5, wherein at least one of the following is present: The third semiconductor alloy is the same as the first semiconductor alloy, and The fourth semiconductor alloy is the same as the second semiconductor alloy.

8. The method according to any one of claims 1-3 and 5, wherein each of the first semiconductor alloy, the second semiconductor alloy, the third semiconductor alloy and the fourth semiconductor alloy is a ternary semiconductor alloy and a quaternary semiconductor alloy, respectively.

9. The method according to any one of claims 1-3, 5, wherein each of the first semiconductor alloy, the second semiconductor alloy, the third semiconductor alloy, and the fourth semiconductor alloy is InGaAsP, wherein the relative amounts of InP, GaAs, InAs, and GaP are different between the first semiconductor alloy and the second semiconductor alloy, and between the third semiconductor alloy and the fourth semiconductor alloy.

10. The method according to any one of claims 2, 3, and 5, wherein the second stack comprises a plurality of layers, wherein the number of layers in the second stack is equal to the number of layers in the first stack.

11. The method according to any one of claims 1-3, 5, wherein the third layer is InP.

12. The method according to any one of claims 1-3 and 5, wherein the substrate is InP.

13. The method according to any one of claims 1-3, 5, wherein the thickness of the third layer is greater than 4 nanometers.

14. The method according to any one of claims 1-3, 5, wherein the thickness of the third layer is less than 100 nanometers.

15. The method according to any one of claims 1-3, 5, wherein the first layer is in contact with the substrate.

16. A semiconductor structure having multiple quantum wells, the semiconductor structure comprising: A substrate comprising a binary semiconductor compound having a first lattice constant; A first stack of quantum wells, the first stack including a planar semiconductor layer on the substrate, the first stack comprising: A first semiconductor alloy comprising more than 8 layers and less than 16 layers, the layers of the first semiconductor alloy being included in a first layer on the substrate, and A second semiconductor alloy comprising InP with more than 8 layers and less than 16 layers, wherein the layers of the second semiconductor alloy include a second layer in contact with the first layer; A third layer in contact with the first stack, the third layer of a binary semiconductor compound having the first lattice constant of the substrate; and A second stack of quantum wells, the second stack including a planar semiconductor layer on the third layer, the second stack including at least: A fourth layer on the third layer, the fourth layer comprising a third semiconductor alloy containing InP, and A fifth layer in contact with the fourth layer, the fifth layer comprising a fourth semiconductor alloy containing InP.

17. The semiconductor structure of claim 16, wherein the substrate is InP.

18. The semiconductor structure according to claim 16 or claim 17, wherein the thickness of the third layer is greater than 4 nanometers.

19. The semiconductor structure according to claim 16 or claim 17, wherein the thickness of the third layer is less than 100 nanometers.

20. The semiconductor structure of claim 16 or claim 17, wherein the first stack comprises fewer than 32 layers.

21. The semiconductor structure of claim 16 or claim 17, wherein the second stack comprises a plurality of layers, wherein the number of layers in the second stack is equal to the number of layers in the first stack.

22. An electro-absorption modulator or an electro-refractive modulator, comprising a semiconductor structure according to any one of claims 16 to 21.

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