Uninterruptible power supply device

Abstract

In this uninterruptible power supply device, AC currents (I1-I3) including a feedback component containing values corresponding to these deviations (ΔVDC) and a feedforward component obtained by multiplying load currents (I4-I6) by a gain (K) are caused to flow into the converter (1) in a manner such that the terminal voltage (VDC) of the capacitor (Cd) becomes a reference voltage (VDCr). The gain (K) is set to a first gain (K1) in the inverter power supply mode and in the bypass power supply mode, and is set to a second gain (K2) smaller than the first gain (K1) during a switching period in which the inverter power supply mode and the bypass power supply mode are switched, thereby preventing the terminal voltage (VDC) of the capacitor (Cd) from exceeding an upper limit voltage (VDCH) in the overlap power supply mode.

Description

Technical Field

[0001] This invention relates to uninterruptible power supply (UPS) devices, and particularly to UPS devices having an inverter power supply mode that supplies AC power from an inverter to a load, a bypass power supply mode that supplies AC power from a bypass AC power source to a load, and an overlapping power supply mode that supplies AC power from both the inverter and the bypass AC power source to the load. Background Technology

[0002] For example, Japanese Patent No. 6533357 (Patent Document 1) discloses an uninterruptible power supply (UPS) device having an inverter power supply mode, a bypass power supply mode, and an overlapping power supply mode. This UPS device includes: a rectifier that converts a first AC voltage supplied from a commercial AC power source into a DC voltage; a capacitor that smooths the DC output voltage of the rectifier; an inverter that converts the voltage between the capacitor terminals into a second AC voltage; a first switch, one terminal of which receives the second AC voltage and the other terminal of which is connected to a load; and a second switch, one terminal of which receives a third AC voltage supplied from a bypass AC power source and the other terminal of which is connected to a load.

[0003] In inverter power supply mode, the first switch is turned on and the second switch is turned off. In bypass power supply mode, the second switch is turned on and the first switch is turned off. In overlapping power supply mode, both the first and second switches are turned on. Overlapping power supply mode is executed during the switching between inverter power supply mode and bypass power supply mode.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 6533357 Summary of the Invention

[0007] The technical problem that the invention aims to solve

[0008] Typically, in such uninterruptible power supply (UPS) devices, the capacitor's terminal voltage is maintained at the reference voltage by allowing an alternating current, including a feedback component that corresponds to the deviation between the reference voltage and the voltage across the capacitor terminals, to flow from a commercial AC power source to the rectifier. In this method, to maintain the capacitor's terminal voltage at the reference voltage even under sudden changes in load current, the feedback component needs to be controlled at high speed. However, high-speed control of the feedback component can lead to control instability.

[0009] As a countermeasure, a method can be considered in which an alternating current including a feedback component and a feedforward component corresponding to a value of the load current is caused to flow from the commercial alternating power source to the rectifier, thereby maintaining the voltage between the terminals of the capacitor at the reference voltage. According to this method, stabilization of the control can be achieved by slowly controlling the feedback component, and the sudden change in the load current can be dealt with by introducing the feedforward component.

[0010] However, in this method, if the load current is supplied from both the bypass alternating power source and the inverter during the overlap power supply mode, the output of the rectifier becomes larger than the output of the inverter, and there is a problem in that the voltage between the terminals of the capacitor rises. When the voltage between the terminals of the capacitor exceeds the upper limit voltage, the operation of the uninterruptible power supply device stops, and the operation of the load stops.

[0011] Therefore, the main object of the present application is to provide an uninterruptible power supply device capable of stably controlling the voltage between the terminals of the capacitor and preventing the voltage between the terminals of the capacitor from exceeding the upper limit voltage.

[0012] Means for solving the technical problem

[0013] The uninterruptible power supply device of the present application includes a rectifier, a capacitor, an inverter, a first switch, a second switch, a first current detector, a second current detector, a first control unit, and a second control unit. The rectifier converts a first alternating voltage supplied from a first alternating power source into a direct current voltage. The capacitor smoothes the direct current output voltage of the rectifier. The inverter converts the voltage between the terminals of the capacitor into a second alternating voltage. One terminal of the first switch receives the second alternating voltage, and the other terminal of the first switch is connected to a load. One terminal of the second switch receives a third alternating voltage supplied from a second alternating power source, and the other terminal of the second switch is connected to the load. The first current detector detects an alternating current flowing between the first alternating power source and the rectifier. The second current detector detects a load current. The first control unit controls the first switch and the second switch. The second control unit controls the rectifier based on the detection results of the first current detector and the second current detector.

[0014] The first control unit causes the first switch to be turned on and the second switch to be turned off in a first mode in which the second alternating voltage is supplied to the load. The first control unit causes the second switch to be turned on and the first switch to be turned off in a second mode in which the third alternating voltage is supplied to the load. The first control unit executes a third mode in which the first switch and the second switch are turned on to supply the second alternating voltage and the third alternating voltage to the load during a switching period in which the mode is switched from either one of the first mode and the second mode to the other mode.

[0015] The second control section causes a first alternating current including a first feedback component corresponding to a deviation between the first reference voltage and the voltage across the terminals of the capacitor and a first feedforward component obtained by multiplying the load current by a first gain to flow from the first alternating current source to the rectifier in the first mode and the second mode in such a manner that the voltage across the terminals of the capacitor becomes the first reference voltage. The second control section causes a second alternating current including a second feedback component corresponding to a deviation between the second reference voltage and the voltage across the terminals of the capacitor and a second feedforward component obtained by multiplying the load current by a second gain smaller than the first gain to flow from the first alternating current source to the rectifier in the switching period in such a manner that the voltage across the terminals of the capacitor becomes the second reference voltage. The second control section is configured to prevent the voltage across the terminals of the capacitor from exceeding an upper limit voltage higher than the first reference voltage and the second reference voltage.

[0016] Effects of the Invention

[0017] In the uninterruptible power supply device of the present application, an alternating current including a feedback component and a feedforward component is caused to flow into the rectifier, so that stabilization of control can be achieved by controlling the feedback component at a low speed, and sudden changes in the load current can be dealt with by the feedforward component. In addition, since the feedforward component is reduced during the switching period, the voltage across the terminals of the capacitor can be prevented from exceeding the upper limit voltage in the third mode. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a circuit block diagram showing the structure of the uninterruptible power supply device of Embodiment 1 of the present application.

[0019] Figure 2 is a circuit diagram showing the structure of the converter and the inverter shown in Figure 1

[0020] Figure 3 is an equivalent circuit diagram showing the structure of the commercial alternating current power supply shown in Figure 1

[0021] Figure 4 is an equivalent circuit diagram showing the structure of the bypass alternating current power supply shown in Figure 1

[0022] Figure 5 is a graph showing the relationship between the three-phase alternating current voltage of the commercial alternating current power supply shown in Figure 3 Figure 4

[0023] Figure 6 is a circuit block diagram for explaining the circulating current flowing in the overlap power supply mode.

[0024] Figure 7 ​​​​​is another circuit block diagram for explaining circulating current flowing at the time of the overlap power supply mode.

[0025] Figure 8 is a circuit block diagram for explaining a problem point at the time of the overlap power supply mode.

[0026] Figure 9 is a block diagram showing Figure 1 the main part of the control device shown in Fig. 1.

[0027] Figure 10 is a block diagram showing Figure 9 the structure of the control section 14 shown in Fig. 1.

[0028] Figure 11 is a block diagram showing Figure 10 the structure of the direct-current voltage control circuit shown in Fig. 1.

[0029] Figure 12 is a timing chart showing Figure 9 the operation of the control device shown in Fig. 1.

[0030] Figure 13 is another timing chart showing Figure 9 the operation of the control device shown in Fig. 1.

[0031] Figure 14 is a circuit block diagram showing the main part of the uninterruptible power supply device of Embodiment 2 of the present application.

[0032] Figure 15 is a block diagram showing Figure 14 the structure of the direct-current voltage control circuit shown in Fig. 1. DETAILED DESCRIPTION

[0033] [Embodiment 1]

[0034] Figure 1 is a circuit block diagram showing the structure of the uninterruptible power supply device of Embodiment 1 of the present application. In Figure 1 , the uninterruptible power supply device is provided with capacitors C1 to C6, Cd, reactors L1 to L6, current detectors CT1 to CT6, a converter 1, a direct-current positive bus Lp, a direct-current negative bus Ln, a bidirectional chopper 2, an inverter 3, switches S1 to S6, an operation section 4, and a control device 5.

[0035] The uninterruptible power supply device receives three-phase alternating-current electric power of a commercial frequency from a commercial alternating-current power supply 6 and a bypass alternating-current power supply 7, and supplies three-phase alternating-current electric power of a commercial frequency to a load 8. The commercial alternating-current power supply 6 (first alternating-current power supply) outputs three-phase alternating-current voltages Vu1, Vv1, Vw1 (first alternating-current voltages) to alternating-current output terminals 6a to 6c, respectively. A neutral point terminal 6d of the commercial alternating-current power supply 6 receives a ground voltage GND.

[0036] The instantaneous values of the three-phase alternating voltages Vu1, Vv1, Vw1 are detected by the control device 5. The control device 5 detects whether a power failure of the commercial alternating power source 6 has occurred, based on the alternating output voltages Vu1, Vv1, Vw1 of the commercial alternating power source 6.

[0037] The bypass alternating power source 7 (second alternating power source) outputs three-phase alternating voltages Vu2, Vv2, Vw2 (second alternating voltages) to the alternating output terminals 7a to 7c, respectively. The neutral point terminal 7d of the bypass alternating power source 7 receives the ground voltage GND. The alternating input terminals 8a to 8c of the load 8 receive three-phase alternating voltages from the uninterruptible power supply device. The load 8 is driven by the three-phase alternating electric power supplied from the uninterruptible power supply device.

[0038] One electrode of each of the capacitors C1 to C3 is connected to the alternating output terminals 6a to 6c of the commercial alternating power source 6, and the other electrodes thereof are connected to each other. One terminal of each of the reactors L1 to L3 is connected to the alternating output terminals 6a to 6c of the commercial alternating power source 6, and the other terminals thereof are connected to the three input nodes of the converter 1, respectively.

[0039] The capacitors C1 to C3 and the reactors L1 to L3 constitute an alternating filter Fl. The alternating filter Fl is a low-pass filter, which allows the alternating current of the commercial frequency to flow from the commercial alternating power source 6 to the converter 1, and prevents signals of the switching frequency from flowing from the converter 1 to the commercial alternating power source 6. The current detectors CT1 to CT3 detect the alternating currents II to I3 flowing through the reactors L1 to L3, respectively, and supply signals indicative of the detected values to the control device 5.

[0040] The positive-side output node of the converter 1 is connected to the positive-side input node of the inverter 3 via a direct-current positive bus Lp. The negative-side output node of the converter 1 is connected to the negative-side input node of the inverter 3 via a direct-current negative bus Ln. The capacitor Cd is connected between the buses Lp, Ln, so as to smooth the direct-current voltage VDC between the buses Lp, Ln. The instantaneous value of the direct-current voltage VDC is detected by the control device 5.

[0041] The converter 1 is controlled by the control device 5, so as to convert the three-phase alternating electric power from the commercial alternating power source 6 into direct-current electric power, in a case where the three-phase alternating electric power is normally supplied from the commercial alternating power source 6 (in a non-fault state of the commercial alternating power source 6). The direct-current electric power generated by the converter 1 is supplied to the bidirectional chopper 2 and the inverter 3 via the buses Lp, Ln.

[0042] In a case where the supply of the three-phase alternating current power from the commercial alternating current power source 6 is stopped (at the time of power failure of the commercial alternating current power source 6), the operation of the converter 1 is stopped. The alternating current filter Fl and the converter 1 correspond to one embodiment of a "rectifier" that converts the three-phase alternating current power from the commercial alternating current power source 6 into direct current power. The current detectors CT1 to CT3 correspond to one embodiment of a "first current detector" that detects the alternating current flowing from the commercial alternating current power source 6 to the rectifier.

[0043] The bidirectional chopper 2 is controlled by the control device 5, and accumulates the direct current power generated by the converter 1 in the battery Bl at the time of non-failure of the commercial alternating current power source 6, and supplies the direct current power of the battery Bl to the inverter 3 via the bus bars Lp and Ln in accordance with the occurrence of the power failure of the commercial alternating current power source 6. The instantaneous value of the terminal voltage VB of the battery Bl is detected by the control device 5.

[0044] The inverter 3 is controlled by the control device 5, and converts the direct current power supplied from the converter 1 and the bidirectional chopper 2 into three-phase alternating current power of a commercial frequency.

[0045] The three output nodes of the inverter 3 are connected to one terminal of the reactors L4 to L6, respectively. The other terminals of the reactors L4 to L6 are connected to one terminal of the switches S1 to S3, respectively, and the other terminals of the switches S1 to S3 are connected to the three alternating current input terminals 8a to 8c of the load 8, respectively. The switches S1 to S3 correspond to one embodiment of a "first switch". One electrode of the capacitors C4 to C6 is connected to the other terminal of the reactors L4 to L6, respectively, and the other electrodes of the capacitors C4 to C6 are connected to the other electrode of the capacitors C1 to C3.

[0046] The capacitors C4 to C6 and the reactors L4 to L6 constitute an alternating current filter F2. The alternating current filter F2 is a low-pass filter that allows the alternating current of the commercial frequency to flow from the inverter 3 to the load 8 and prevents the signal of the switching frequency from flowing from the inverter 3 to the load 8. In other words, the alternating current filter F2 converts the three-phase rectangular wave voltage output from the inverter 3 into the three-phase alternating current voltage Va, Vb, Vc in a sinusoidal shape.

[0047] The inverter 3 and the alternating current filter F2 correspond to one embodiment of an "inverter" that converts the terminal voltage VDC of the capacitor Cd into the three-phase alternating current voltage Va to Vc. The instantaneous values of the three-phase alternating current voltage Va to Vc are detected by the control device 5.

[0048] One terminal of the switches S4 to S6 is connected to the alternating current output terminals 7a to 7c of the bypass alternating current power source 7, respectively, and the other terminals thereof are connected to the alternating current input terminals 8a to 8c of the load 8, respectively. The switches S1 to S6 are controlled by the control device 5. The switches S4 to S6 correspond to one embodiment of a "second switch".

[0049] The current detector CT4 detects the alternating current I4 flowing between the other terminal of the switches S1, S4 and the alternating current input terminal 8a of the load 8, and supplies a signal representing the detected value to the control device 5. The current detector CT5 detects the alternating current I5 flowing between the other terminal of the switches S2, S5 and the alternating current input terminal 8b of the load 8, and supplies a signal representing the detected value to the control device 5. The current detector CT6 detects the alternating current I6 flowing between the other terminal of the switches S3, S6 and the alternating current input terminal 8c of the load 8, and supplies a signal representing the detected value to the control device 5. The current detectors CT4 to CT6 correspond to one embodiment of the "second current detector" that detects the load currents I4 to I6.

[0050] In the inverter power supply mode (first mode) in which the three-phase alternating current power generated by the inverter 3 is supplied to the load 8, the control device 5 turns on the switches S1 to S3, and turns off the switches S4 to S6.

[0051] In the bypass power supply mode (second mode) in which the three-phase alternating current power from the bypass alternating current power source 7 is supplied to the load 8, the control device 5 turns off the switches S1 to S3, and turns on the switches S4 to S6. In the overlap power supply mode (third mode) in which the three-phase alternating current power from both the inverter 3 and the bypass alternating current power source 7 is supplied to the load 8, the control device 5 turns on the switches S1 to S6.

[0052] The operation section 4 (selection section) includes a plurality of buttons operated by the user of the uninterruptible power supply device, an image display section that displays various information, and the like. The user can turn on and off the power supply of the uninterruptible power supply device, or select any of the automatic driving mode, the bypass power supply mode, and the inverter power supply mode, by operating the operation section 4.

[0053] The control device 5 controls the entire uninterruptible power supply device on the basis of the signals from the operation section 4, the alternating current output voltages Vu1, Vv1, Vw1 of the commercial alternating current power source 6, the alternating current input currents I1 to I3, the inter-terminal voltage VDC of the capacitor Cd, the inter-terminal voltage VB of the battery B1, the load currents I4 to I6, the alternating current output voltages Va to Vc, the alternating current output voltages Vu2, Vv2, Vw2 of the bypass alternating current power source 7, and the like.

[0054] That is, the control device 5 controls the converter 1 based on the alternating-current input currents I1 to I3, the voltage VDC between the terminals of the capacitor Cd, the load currents I4 to I6, and the like. In the inverter power supply mode and the bypass power supply mode, the control device 5 causes the three-phase alternating-current currents I1 to I3, which include a first feedback component corresponding to a deviation ΔVDC = VDCr1 - VDC between a reference voltage VDCr1 (first reference voltage) and the voltage VDC between the terminals of the capacitor Cd, and a first feedforward component obtained by multiplying the load currents I4 to I6 by a gain K1 (first gain, for example, 1.0), to flow from the commercial alternating-current power source 6 to the converter 1.

[0055] In addition, during switching from either of the inverter power supply mode and the bypass power supply mode to the other mode, the control device 5 causes the three-phase alternating-current currents I1 to I3, which include a second feedback component corresponding to a deviation ΔVDC = VDCr2 - VDC between a reference voltage VDCr2 (second reference voltage) higher than the reference voltage VDCr1 and the voltage VDC between the terminals of the capacitor Cd, and a second feedforward component obtained by multiplying the load currents I4 to I6 by a gain K2 (second gain, for example, 0.7) smaller than the gain K1, to flow from the commercial alternating-current power source 6 to the converter 1.

[0056] During the switching, the converter 1 is controlled so that the voltage VDC between the terminals of the capacitor Cd becomes the reference voltage VDCr2 higher than the reference voltage VDCr1, in order to prevent a circulating current from flowing between the commercial alternating-current power source 6 and the bypass alternating-current power source 7.

[0057] The reference voltage VDCr1 is set to a voltage lower than a voltage twice as large as the peak value of the three-phase alternating-current voltages Vu1, Vv1, Vw1 of the commercial alternating-current power source 6. The reference voltage VDCr2 is set to a voltage equal to or higher than a voltage twice as large as the peak value of the three-phase alternating-current voltages Vu1, Vv1, Vw1 of the commercial alternating-current power source 6. The relationship between the reference voltages VDCr1, VDCr2 and the circulating current is described in detail later ( Figures 2-7 ).

[0058] The three-phase alternating-current currents I1 to I3, which include the feedforward component obtained by multiplying the load currents I4 to I6 by the gain K, are caused to flow to the converter 1, in order to improve the response speed of the converter 1 with respect to variations in the load currents I4 to I6. By introducing the feedforward component, it is possible to perform control of the feedback component at a low speed, and it is possible to achieve stabilization of the control.

[0059] Further, during the switching period, three-phase alternating currents II ~ 13 including a second feed-forward component obtained by multiplying load currents I4 ~ 16 by a gain K2 smaller than the gain Kl are caused to flow to the converter 1 in order to prevent the terminal-to-terminal voltage VDC of the capacitor Cd from exceeding the upper limit voltage VDCH higher than the reference voltages VDCrI, VDCr2 when the overlap power supply mode is in operation, the input of the converter 1 (i.e., the output of the converter 1) being greater than the output of the inverter 3. When the terminal-to-terminal voltage VDC of the capacitor Cd exceeds the upper limit voltage VDCH, the operation of the uninterruptible power supply device is stopped, and the operation of the load 8 is stopped. The reason why the terminal-to-terminal voltage VDC of the capacitor Cd rises when the overlap power supply mode is in operation will be described later. Figure 8

[0060] Further, the control device 5 controls the bidirectional chopper 2 so that the terminal-to-terminal voltage VB of the battery Bl becomes the reference voltage VBr when the commercial AC power source 6 is not in trouble, and controls the bidirectional chopper 2 so that the terminal-to-terminal voltage VDC of the capacitor Cd becomes the reference voltage VDCrI when the commercial AC power source 6 is in trouble. Furthermore, the control device 5 controls the inverter 3 so that the alternating output voltages Va ~ Vc of the inverter 3 become the alternating output voltages Vu2, Vv2, Vw2 of the bypass AC power source 7.

[0061] Here, the operation of the uninterruptible power supply device will be described simply. When the automatic driving mode is selected by the operation section 4 in the non-trouble state of the commercial AC power source 6, three-phase alternating currents II ~ 13 including the first feedback component and the first feed-forward component are caused to flow to the converter 1 from the commercial AC power source 6 so that the terminal-to-terminal voltage VDC of the capacitor Cd becomes the reference voltage VDCrI. By causing the first feed-forward component to flow through the converter 1, the converter 1 can be stably controlled, and the converter 1 can be controlled at high speed in response to a change in the load currents I4 ~ 16.

[0062] Further, the bidirectional chopper 2 is controlled so that the terminal-to-terminal voltage VB of the battery Bl becomes the reference voltage VBr, and the inverter 3 is controlled so that the alternating output voltages Va ~ Vc become the alternating output voltages Vu2, Vv2, Vw2 of the bypass AC power source 7, respectively.

[0063] Further, the switches SI ~ S3 are turned on, and the switches S4 ~ S6 are turned off, and the inverter 3 is connected to the load 8 via the AC filter F2 and the switches SI ~ S3. Thus, the alternating output voltages Va ~ Vc are supplied to the load 8 via the switches SI ~ S3, and the load 8 is driven.

[0064] ​In the case where the commercial AC power source 6 is out of operation, the operation of the converter 1 is stopped, the bidirectional chopper 2 is controlled so that the terminal-to-terminal voltage VDC of the capacitor Cd becomes the reference voltage VDCr1, and the inverter 3 is controlled so that the AC output voltages Va to Vc become the AC output voltages Vu2, Vv2, and Vw2 of the bypass AC power source 7, respectively.

[0065] In the case where the DC power of the battery Bl is consumed and the terminal-to-terminal voltage VB of the battery Bl reaches the lower limit voltage, the operation of the bidirectional chopper 2 and the inverter 3 is stopped. Therefore, even in the case where the commercial AC power source 6 is out of operation, the operation of the load 8 can be continued until the terminal-to-terminal voltage VB of the battery Bl reaches the lower limit voltage.

[0066] In addition, in the case where the inverter power supply mode is selected by the operation section 4 at the time of non-failure of the commercial AC power source 6, the converter 1 is controlled so that the terminal-to-terminal voltage VDC of the capacitor Cd becomes the reference voltage VDCr1, and the bidirectional chopper 2 is controlled so that the terminal-to-terminal voltage VB of the battery Bl becomes the reference voltage VBr, as in the automatic operation mode described above. In addition, the inverter 3 is controlled so that the AC output voltages Va to Vc become the AC output voltages Vu2, Vv2, and Vw2 of the bypass AC power source 7, respectively, the switches S1 to S3 are turned on, and the switches S4 to S6 are turned off.

[0067] In the inverter power supply mode, in the case where the bypass power supply mode is selected by the operation section 4, the three-phase AC currents II to I3 including the second feedback component and the second feedforward component are caused to flow from the commercial AC power source 6 to the converter 1 so that the terminal-to-terminal voltage VDC of the capacitor Cd becomes the reference voltage VDCr2 higher than the reference voltage VDCr1.

[0068] When VDC = VDCr2, the overlap power supply mode is executed for a predetermined time, and all the switches S1 to S6 are turned on, so that the three-phase AC power is supplied from the inverter 3 and the bypass AC power source 7 to the load 8 in both directions. At this time, since VDC = VDCr2, no circulating current flows in the uninterruptible power supply device. In addition, by causing the second feedforward component smaller than the first feedforward component to flow through the converter 1, it is possible to prevent the terminal-to-terminal voltage VDC of the capacitor Cd from exceeding the upper limit voltage VDCr.

[0069] When the overlap power supply mode ends, the switches S1 to S3 are turned off and only the switches S4 to S6 are turned on. In addition, the converter 1 is controlled so that the voltage VDC between the terminals of the capacitor Cd falls to the reference voltage VDCr1, and the switching from the inverter power supply mode to the bypass power supply mode is completed. In the bypass power supply mode, three-phase alternating current power is supplied from the bypass alternating current power source 7 to the load 8 via the switches S4 to S6, and the load 8 is driven. In the bypass power supply mode, for example, repair, periodic inspection, and the like of the converter 1, the bidirectional chopper 2, the inverter 3, the battery Bl, and the like are performed.

[0070] In addition, in a case where the inverter power supply mode is selected using the operation section 4 in the bypass power supply mode, three-phase alternating currents I1 to I3 including the second feedback component and the second feedforward component are caused to flow from the commercial alternating current power source 6 to the converter 1 so that the voltage VDC between the terminals of the capacitor Cd becomes the reference voltage VDCr2 which is higher than the reference voltage VDCr1.

[0071] When VDC = VDCr2, the overlap power supply mode is executed for a prescribed time, and all of the switches S1 to S6 are turned on, and three-phase alternating current power is supplied from the inverter 3 and the bypass alternating current power source 7 to the load 8. At this time, since VDC = VDCr2, circulating current does not flow in the uninterruptible power supply device. In addition, by causing the second feedforward component which is smaller than the first feedforward component to flow through the converter 1, it is possible to prevent the voltage VDC between the terminals of the capacitor Cd from exceeding the upper limit voltage VDCr.

[0072] If the overlap power supply mode ends, the switches S4 to S6 are turned off and only the switches S1 to S3 are turned on, and the voltage VDC between the terminals of the capacitor Cd is lowered to the reference voltage VDCr1 by the converter 1, and the switching from the bypass power supply mode to the inverter power supply mode is completed.

[0073] Next, the relationship between the circulating current flowing in the uninterruptible power supply device and the reference voltages VDCr1 and VDCr2 will be described in detail. Figure 2 is a circuit diagram showing the configuration of the converter 1 and the inverter 3. In Figure 2 The converter 1 includes IGBTs (Insulated Gate Bipolar Transistor) Q1 to Q6 and diodes D1 to D6. The IGBTs constitute switching elements. The collectors of the IGBTs Q1 to Q3 are connected to the direct current positive bus line Lp, and the emitters thereof are connected to the input nodes 1a, 1b, and 1c, respectively.

[0074] The input nodes 1a, 1b, and 1c are connected to the reactors L1 to L3 Figure 1The other terminal of the IGBT Q4 is connected to the other terminal of the diode D4. The collector of the IGBT Q4 is connected to the input node 1a, and the emitter of the IGBT Q4 is connected to the DC negative bus Ln. The diode D4 is connected in reverse parallel to the IGBT Q4.

[0075] The IGBT Q1 is controlled by the gate signal Al, and the IGBT Q4 is controlled by the gate signal Bl. The gate signal Bl is the inverted signal of the gate signal Al.

[0076] The IGBT Q1 is turned on when the gate signal Al is set to the "H" level, and is turned off when the gate signal Al is set to the "L" level. The IGBT Q4 is turned on when the gate signal Bl is set to the "H" level, and is turned off when the gate signal Bl is set to the "L" level.

[0077] The gate signals Al and Bl, and the gate signals A2 and B2 are pulse signal trains, and are PWM (Pulse Width Modulation) signals. The phases of the gate signals Al and Bl, the phases of the gate signals A2 and B2, and the phases of the gate signals A3 and B3 are basically shifted by 120 degrees. The gate signals Al, Bl, A2, B2, and A3 and B3 are generated by the control device 5. For example, in the case where the level of the AC input voltage Vu1 is higher than the level of the AC input voltage Vv1, the IGBT Q1 is turned on, and the current flows from the input node 1a via the IGBT Q1, the DC positive bus Lp, the capacitor Cd, the DC negative bus Ln, and the IGBT Q5 to the input node 1b, and the capacitor Cd is charged.

[0078] On the contrary, in the case where the level of the AC input voltage Vv1 is higher than the level of the AC input voltage Vu1, the IGBT Q2 is turned on, and the current flows from the input node 1b via the IGBT Q2, the DC positive bus Lp, the capacitor Cd, the DC negative bus Ln, and the IGBT Q4 to the input node 1a, and the capacitor Cd is charged. The same applies to the other cases.

[0079] The IGBT Q1 to Q6 are turned on and turned off at predetermined timings by the gate signals Al, Bl, A2, B2, A3, and B3, respectively, and by adjusting the respective on-time of the IGBT Q1 to Q6, the three-phase AC voltage supplied to the input nodes 6a to 6c can be converted into the DC voltage VDC (the voltage between the terminals of the capacitor Cd).

[0080] The inverter 3 includes IGBTs Q11 to Q16 and diodes D11 to D16. The IGBTs constitute switching elements. The collectors of the IGBTs Q11 to Q13 are connected to the direct-current positive bus Lp, and the emitters thereof are connected to the output nodes 3a, 3b, 3c, respectively. The output nodes 3a, 3b, 3c are connected to one end of the reactors L4 to L6 (L4, L5, L6), respectively. The collectors of the IGBTs Q14 to Q16 are connected to the output nodes 3a, 3b, 3c, respectively, and the emitters thereof are connected to the direct-current negative bus Ln. The diodes D11 to D16 are connected in antiparallel to the IGBTs Q11 to Q16, respectively. Figure 1 ) The collectors of the IGBTs Q11 to Q13 are connected to the direct-current positive bus Lp, and the emitters thereof are connected to the output nodes 3a, 3b, 3c, respectively. The output nodes 3a, 3b, 3c are connected to one end of the reactors L4 to L6 (L4, L5, L6)

[0081] The IGBTs Q11, Q14 are controlled by the gate signals X1, Y1, respectively, the IGBTs Q12, Q15 are controlled by the gate signals X2, Y2, respectively, and the IGBTs Q13, Q16 are controlled by the gate signals X3, Y3, respectively. The gate signals Y1, Y2, Y3 are inverted signals of the gate signals X1, X2, X3, respectively.

[0082] The IGBTs Q11 to Q13 are turned on when the gate signals X1, X2, X3 are set to the "H" level, respectively, and are turned off when the gate signals X1, X2, X3 are set to the "L" level, respectively. The IGBTs Q14 to Q16 are turned on when the gate signals Y1, Y2, Y3 are set to the "H" level, respectively, and are turned off when the gate signals Y1, Y2, Y3 are set to the "L" level, respectively.

[0083] The gate signals X1, Y2, X3, Y1, X2, Y3 are pulse signal trains, and are PWM signals. The phases of the gate signals X1, Y1, the phases of the gate signals X2, Y2, and the phases of the gate signals X3, Y3 are substantially shifted by 120 degrees. The gate signals X1, Y1, X2, Y2, X3, Y3 are generated by the control device 5.

[0084] For example, when the IGBTs Q11, Q15 are turned on, the direct-current positive bus Lp is connected to the output node 3a via the IGBT Q11, and the output node 3b is connected to the direct-current negative bus Ln via the IGBT Q15, and a positive voltage is output between the output nodes 3a, 3b.

[0085] In addition, when the IGBTs Q12, Q14 are turned on, the direct-current positive bus Lp is connected to the output node 3b via the IGBT Q12, and the output node 3a is connected to the direct-current negative bus Ln via the IGBT Q14, and a negative voltage is output between the output nodes 3a, 3b.

[0086] The IGBTs Q11 to Q16 are turned on and off at predetermined timings by the gate signals X1, Y1, X2, Y2, X3, Y3, and by adjusting the on-time of each of the IGBTs Q11 to Q16, the DC voltage VDC between the bus lines Lp and Ln can be converted into the three-phase AC voltages Va, Vb, Vc.

[0087] Figure 3 is an equivalent circuit diagram showing the structure of the commercial AC power source 6. In Figure 3 , the commercial AC power source 6 includes 3-phase AC power sources 6U, 6V, 6W which are star-connected (Y-connected) with respect to a neutral point terminal 6d. The AC power source 6U is connected between an AC output terminal 6a and the neutral point terminal 6d, and outputs an AC voltage Vu1 to the AC output terminal 6a. The AC power source 6V is connected between an AC output terminal 6b and the neutral point terminal 6d, and outputs an AC voltage Vv1 to the AC output terminal 6b. The AC power source 6W is connected between an AC output terminal 6c and the neutral point terminal 6d, and outputs an AC voltage Vw1 to the AC output terminal 6c.

[0088] The AC voltages Vu1, Vv1, Vw1 vary in sinusoidal wave shapes at a commercial frequency (e.g., 60 Hz) respectively. The peak values (1.414 times the effective value) of the AC voltages Vu1, Vv1, Vw1 are the same, and their phases are shifted by 120 degrees. The AC power sources 6U, 6V, 6W correspond to, for example, the windings of the final stage three-phase of a three-phase transformer included in the final stage of the commercial AC power source 6.

[0089] Figure 4 is an equivalent circuit diagram showing the structure of the bypass AC power source 7. In Figure 4 , the bypass AC power source 7 includes 3-phase AC power sources 7U, 7V, 7W which are star-connected with respect to a neutral point terminal 7d. The AC power source 7U is connected between an AC output terminal 7a and the neutral point terminal 7d, and outputs an AC voltage Vu2 to the AC output terminal 7a. The AC power source 7V is connected between an AC output terminal 7b and the neutral point terminal 7d, and outputs an AC voltage Vv2 to the AC output terminal 7b. The AC power source 7W is connected between an AC output terminal 7c and the neutral point terminal 7d, and outputs an AC voltage Vw2 to the AC output terminal 7c.

[0090] The AC voltages Vu2, Vv2, Vw2 vary in sinusoidal wave shapes at a commercial frequency respectively. The peak values of the AC voltages Vu2, Vv2, Vw2 are the same, and their phases are shifted by 120 degrees. The AC power sources 7U, 7V, 7W correspond to, for example, the coils of the three-phase of a home generator.

[0091] In the bypass power supply mode and the parallel power supply mode, the phases (and the peak values) of the AC voltages Vu2, Vv2, Vw2 of the bypass AC power supply 7 respectively coincide with the phases (and the peak values) of the AC voltages Vu1, Vv1, Vw1 of the commercial AC power supply 6. In this state, no circulating current flows in the uninterruptible power supply device.

[0092] However, in the overlap power supply mode, when the switches S1-S3 or the switches S4-S6 are turned on, the load current of the bypass AC power supply 7 greatly fluctuates, and the phases, the peak values of the AC voltages Vu2, Vv2, Vw2 fluctuate. Therefore, the AC voltages Vu2, Vv2, Vw2 respectively do not coincide with the AC voltages Vu1, Vv1, Vw1.

[0093] Figure 5 (A) to (C) of FIG. 8 are graphs showing the relationship between the AC voltages Vu1, Vv1, Vw1 of the commercial AC power supply 6 and the AC voltages Vu2, Vv2, Vw2 of the bypass AC power supply 7. The AC voltages Vu1, Vv1, Vw1, Vu2, Vv2, Vw2 are respectively shown by vectors. The phases of the AC voltages Vu1, Vv1, Vw1 are each shifted by 120 degrees, and the phases of the AC voltages Vu2, Vv2, Vw2 are each shifted by 120 degrees. Figure 5 (A) of FIG. 8 shows a case where the phases of the AC voltages Vu2, Vv2, Vw2 respectively coincide with the phases of the AC voltages Vu1, Vv1, Vw1.

[0094] Figure 5 (B) of FIG. 8 shows a case where the phases of the AC voltages Vu2, Vv2, Vw2 respectively delay by 60 degrees from the phases of the AC voltages Vu1, Vv1, Vw1. For example, the phase of the AC voltage Vu1 is shifted by 180 degrees from the phase of the AC voltage Vw2. When the AC voltage Vu1 becomes a positive peak value and the AC voltage Vw2 becomes a negative peak value, the voltage AV12 = Vu1-Vw2 of the difference between the AC voltages Vu1 and Vw2 becomes the sum of the peak values of the AC voltages Vu1, Vw2. On the contrary, when the AC voltage Vu1 becomes a negative peak value and the AC voltage Vw2 becomes a positive peak value, the voltage AV21 = Vw2-Vu1 of the difference between the AC voltages Vw2 and Vu1 becomes the sum of the peak values of the AC voltages Vu1, Vw2.

[0095] Figure 5(C) shows a case where the phases of the alternating voltages Vu2, Vv2, Vw2 are respectively 60 degrees ahead of the phases of the alternating voltages Vu1, Vv1, Vv1. For example, the phase of the alternating voltage Vu1 is shifted by 180 degrees from the phase of the alternating voltage Vv2. When the alternating voltage Vu1 is at a positive peak and the alternating voltage Vv2 is at a negative peak, the voltage AV12 = Vu1 - Vv2, which is the difference between the alternating voltages Vu1 and Vv2, is the sum of the peaks of the alternating voltages Vu1, Vv2. Conversely, when the alternating voltage Vu1 is at a negative peak and the alternating voltage Vv2 is at a positive peak, the voltage AV21 = Vv2 - Vu1, which is the difference between the alternating voltages Vv2 and Vu1, becomes the sum of the peaks of the alternating voltages Vu1, Vv2.

[0096] If the voltage VDC between the terminals of the capacitor Cd is smaller than the sum of the peak of the alternating voltages Vu1, Vv1, Vw1 and the peak of the alternating voltages Vu2, Vv2, Vw2 in the overlapping power supply mode, the following problem occurs. For example, as shown in (B) of FIG. 9, in a case where the phases of the alternating voltages Vu1, Vw2 are shifted by 180 degrees and the voltage AV12 = Vu1 - Vw2, which is the difference between the alternating voltages Vu1 and Vw2, becomes the sum of the peaks of the alternating voltages Vu1, Vw2, the circulating current IC flows in the path shown in (A) of FIG. 9. Figure 5 Figure 6

[0097] That is, the circulating current IC flows in a path from one terminal (the alternating output terminal 6a) of the alternating power supply 6U via the input node la of the converter 1, the diode D1 (D1), the direct-current positive bus line Lp, the capacitor Cd, the direct-current negative bus line Ln, the diode D16 (D16), the output node 3c of the inverter 3, the neutral point terminal 6d, and the ground voltage GND to the other terminal of the alternating power supply 6U. Also, in the path shown in (B) of FIG. 9, the circulating current IC flows in a path from the neutral point terminal 6d via the diode D16 (D16), the direct-current negative bus line Ln, the capacitor Cd, the direct-current positive bus line Lp, the diode D1 (D1), the input node la of the converter 1, the alternating output terminal 6a, the neutral point terminal 7d, the alternating power supply 7W, and the output node 3c of the inverter 3 to the neutral point terminal 6d. Figure 2 Figure 2 Figure 6

[0098] Conversely, in a case where the voltage AV21 = Vw2 - Vu1, which is the difference between the alternating voltages Vw2 and Vu1, becomes the sum of the peaks of the alternating voltages Vu1, Vw2, the circulating current IC flows in the path shown in (B) of FIG. 9. That is, the circulating current IC flows in a path from one terminal (the alternating output terminal 7c) of the alternating power supply 7W via the output node 3c of the inverter 3, the diode D13 (D13), the direct-current positive bus line Lp, the capacitor Cd, the direct-current negative bus line Ln, the diode D4 (D4), the neutral point terminal 6d, and the ground voltage GND to the other terminal of the alternating power supply 7W. Figure 7 Figure 2 Figure 2 ​​​​​​​), the input node la of the converter 1, the line of the AC power supply 6U, the neutral point terminal 6d, the line of the ground voltage GND, and the path to the other end of the AC power supply 7W via the circulating current IC.

[0099] When the circulating current IC flows, there is a case where the capacitor Cd is charged by the circulating current IC, the terminal-to-terminal voltage VDC of the capacitor Cd exceeds the upper limit voltage VDCH, the abnormality is determined by the control device 5, and the operation of the uninterruptible power supply device is stopped, and the operation of the load 8 is stopped. In addition, sometimes the detection value of the current detector CT1 to CT6 exceeds the upper limit current IH, the abnormality is determined by the control device 5, and the operation of the uninterruptible power supply device is stopped, and the operation of the load 8 is stopped.

[0100] Therefore, in the present embodiment 1, in the overlap power supply mode, the terminal-to-terminal voltage VDC of the capacitor Cd is set to the reference voltage VDCr2 that is higher than the voltage of the sum of the peak value of the AC voltage Vu1, Vv1, Vw1 and the peak value of the AC voltage Vu2, Vv2, Vw2, and the circulating current IC is prevented from flowing through the uninterruptible power supply device.

[0101] In addition, in the present embodiment 1, in the inverter power supply mode and in the bypass power supply mode, the terminal-to-terminal voltage VDC of the capacitor Cd is set to the reference voltage VDCr1 that is lower than the voltage of the sum of the peak value of the AC voltage Vu1, Vv1, Vw1 and the peak value of the AC voltage Vu2, Vv2, Vw2, and thus the reduction of the power consumption and the improvement of the efficiency are achieved.

[0102] In the case where the bypass AC power supply 7 is stable, the AC output voltage Vu2, Vv2, Vw2 of the bypass AC power supply 7 coincides with the AC output voltage Vu1, Vv1, Vw1 of the commercial AC power supply 6, and thus the voltage of the sum of the peak value of the AC voltage Vu1, Vv1, Vw1 and the peak value of the AC voltage Vu2, Vv2, Vw2 is equal to the voltage of twice the peak value of the AC voltage Vu1, Vv1, Vw1. In addition, the peak value of the AC voltage Vu1, Vv1, Vw1 is the same value.

[0103] For example, the effective value of the AC voltage Vu1 is 277 V, and the peak value thereof is 392 V. The voltage of twice the peak value of the AC voltage Vu1 is 784 V. The reference voltage VDCr1 is set to 750 V that is lower than 784 V. The reference voltage VDCr2 is set to 920 V that is higher than 784 V. In addition, the reference voltage VDCr2 is set to a value that is lower than the upper limit value VDCH (for example, 1000 V) of the terminal-to-terminal voltage VDC of the capacitor Cd.

[0104] As a result, in the overlapping power supply mode, for example, even when the AC voltage Vu1 has a positive peak (+392V) and the AC voltage Vw2 has a negative peak (-392V), the inter-terminal voltage VDC = VDCr2 (920V) of capacitor Cd is higher than the sum of the peak values ​​of AC voltages Vu1 and Vw2 (784V). Therefore, diodes D1 and D16 ( Figure 2 It is not conductive, and therefore the circulating current does not flow through the IC.

[0105] Conversely, even when the AC voltage Vu1 has a negative peak value (-392V) and the AC voltage Vw2 has a positive peak value (+392V), because the voltage across the terminals of capacitor Cd, VDC = VDCr2 (920V), is higher than the sum of the peak values ​​of AC voltages Vu1 and Vw2 (784V), diodes D13 and D4 ( Figure 2 The circuit is not conducting, and the circulating current IC does not flow. Because the circulating current IC does not flow, the overcurrent and overvoltage of capacitor Cd are detected, and the operation of the uninterruptible power supply is stopped, but the operation of load 8 will not stop.

[0106] Next, the control method for the inter-terminal voltage VDC of capacitor Cd under each power supply mode will be explained. Figure 8 Figures (A) through (C) represent circuit block diagrams for bypass power supply mode, overlapping power supply mode, and inverter power supply mode, respectively. To simplify the figures and explanations, only the parts associated with one of the three phases are shown, and only switches S1 and S4 of switches S1 through S6 are shown. Furthermore, illustrations of AC filters F1 and F2, current detectors CT1 through CT6, etc., are omitted.

[0107] In bypass power supply mode, such as Figure 8 As shown in (A), switch S4 is turned on and switch S1 is turned off, supplying load current I4 from bypass AC power supply 7 to load 8 via switch S4. Additionally, converter 1 is controlled with the inter-terminal voltage VDC of capacitor Cd as the reference voltage VDCr1. A first feedback component IFB1, corresponding to the deviation ΔVDC = VDCr1 - VDC between the reference voltage VDCr1 and the inter-terminal voltage VDC of capacitor Cd, and a first feedforward component IFF1 = K1 × I4, obtained by multiplying the load current I4 by the gain K1, flow from commercial AC power supply 6 to converter 1.

[0108] In this case, by allowing the first feedforward component IFF1 to flow through converter 1, the response speed of the first feedback component IFB1 can be set to a small value to stably control the inter-terminal voltage VDC of the capacitor, and the inter-terminal voltage VDC of the capacitor can be controlled at a high speed in response to changes in the load current I4. When the inter-terminal voltage VDC of capacitor Cd is charged to the reference voltage VDCr1, the first feedback component IFB1 and the first feedforward component IFF1 are canceled out, and the input current I1 of converter 1 is approximately 0A.

[0109] During the switch from bypass power supply mode to inverter power supply mode, an overlapped power supply mode is executed. In overlapped power supply mode, such as... Figure 8 As shown in (B), both switches S1 and S4 are closed. When switch S1 is closed, the load of the bypass AC power supply 7 (e.g., a generator) changes abruptly, causing a frequency fluctuation in the output voltage of the bypass AC power supply 7. The output voltage of the bypass AC power supply 7 is out of phase with the output voltage of the inverter 3, and current I4 is supplied from both the inverter 3 and the bypass AC power supply 7 to the load 8 in both directions in proportion to their phase difference. Figure 8 In (B), it is shown that 60% of the load current I4 is supplied from inverter 3 and 40% of the load current I4 is supplied from bypass AC power supply 7.

[0110] When current flows from inverter 3 to load 8, the inter-terminal voltage VDC of capacitor Cd decreases, and the input current I1 of converter 1 increases. In this case, similar to the bypass power supply mode, if a current I1 = IFB1 + K1 × I4 flows from commercial AC power supply 6 to converter 1, the input current I1 of converter 1 becomes too large compared to the output current 0.6 × I4 of inverter 3. The feedback control cannot keep up, and the inter-terminal voltage VDC of capacitor Cd rises compared to the reference voltage VDCr2, potentially exceeding the upper limit voltage VDCH.

[0111] Therefore, in this embodiment 1, in order to prevent the rise of the inter-terminal voltage VDC of capacitor Cd, the feedforward component of the input current I1 of converter 1 is reduced in the overlapping power supply mode. That is, converter 1 is controlled in such a way that the inter-terminal voltage VDC of capacitor Cd is used as the reference voltage VDCr2, and the current I1 = IFB2 + IFF2 = IFB2 + K2 × I4, which includes a second feedback component IFB2 corresponding to the deviation ΔVDC = VDCr2 - VDC between the reference voltage VDCr2 and the inter-terminal voltage VDC of capacitor Cd, and a second feedforward component IFF1 obtained by multiplying the load current I4 by a gain K2 (0.7) which is smaller than the gain K1 (e.g., 1.0), flows from commercial AC power supply 6 to converter 1.

[0112] Therefore, it is possible to prevent the input current I1 of converter 1 from becoming too large compared to the output current 0.6×I4 of inverter 3, and to prevent the output voltage VDC of converter 1 (i.e., the inter-terminal voltage VDC of capacitor Cd) from exceeding the upper limit voltage VDCH, which is higher than the reference voltage VDCr2.

[0113] In inverter power supply mode, such as Figure 8 As shown in (C), switch S1 is turned on and switch S4 is turned off, supplying load current I4 from inverter 3 to load 8 via switch S1. Converter 1 is controlled with the inter-terminal voltage VDC of capacitor Cd as the reference voltage VDCr1. The current I1 = IFB1 + IFF1 = IFB1 + K1 × I4, which includes a first feedback component IFB1 corresponding to the deviation ΔVDC = VDCr1 - VDC between the reference voltage VDCr1 and the inter-terminal voltage VDC of capacitor Cd, and a first feedforward component IFF11 = K1 × I4 obtained by multiplying the load current I4 by the gain K1, flows from commercial AC power supply 6 to converter 1.

[0114] In this case, by allowing the first feedforward component IFF1 to flow through the converter 1, the response speed of the first feedback component IFB1 can be reduced, thereby stably controlling the inter-terminal voltage VDC of the capacitor, and the inter-terminal voltage VDC of the capacitor can be controlled at high speed in response to changes in the load current I4.

[0115] Furthermore, the same control is performed when switching from inverter power supply mode to bypass power supply mode via overlapping power supply mode. However, when switching from overlapping power supply mode to bypass power supply mode, the operation of converter 1 stops when the voltage VDC between the terminals of capacitor Cd rises. Even when the operation of converter 1 stops, current I4 is supplied to load 8 from bypass AC power supply 7 via switch S4, and the operation of load 8 continues.

[0116] Next, the control method for converter 1 and switches S1 to S6 will be explained. Figure 9 This is a block diagram showing the structure of the parts associated with the control of the converter 1 and switches S1 to S6 in the control device 5. Figure 9 In the middle, the control device 5 includes a signal generation circuit 11, a timer 12, and control units 13 and 14.

[0117] Operation Unit 4 ( Figure 1) in the inverter power supply mode selected by the user of the uninterruptible power supply device, and the mode selection signal MS is made an "H" level in the bypass power supply mode. The signal generating circuit 11 makes the switching command signal PC rise to an "H" level for a prescribed time in response to each of the rising edge and the falling edge of the mode selection signal MS from the operation section 4.

[0118] The timer 12 measures the first time Tl, the second time T2, and the third time T3 in that order in response to the rising edge of the switching command signal PC. In addition, the timer 12 makes the switching signal φC an "H" level, which is an active level, from the rising edge of the switching command signal PC to the third time T3. Also, the timer 12 sets the overlap command signal φOL to an "H" level, which is an active level, from the first time Tl to the second time T2.

[0119] The control section 13 controls the switches S1 to S6 in accordance with the mode selection signal MS and the overlap command signal φOL. In the case where both the mode selection signal MS and the overlap command signal φOL are "L" levels, the control section 13 makes the switches S1 to S3 ON, and makes the switches S4 to S6 OFF. The control section 13 corresponds to one embodiment of the "first control section".

[0120] In the case where the overlap command signal φOL is an "H" level, the control section 13 makes all of the switches S1 to S6 ON. In the case where the mode selection signal MS is an "H" level and the overlap command signal φOL is an "L" level, the control section 13 makes the switches S4 to S6 ON and makes the switches S1 to S3 OFF.

[0121] The control section 14 operates based on the AC input voltages Vu1, Vv1, Vw1, the three-phase input currents I1 to I3, the load currents I4 to I6, and the DC voltage VDC to control the converter 1 in such a manner that the voltage VDC across the capacitor Cd coincides with the reference voltage VDCr. The control section 14 corresponds to one embodiment of the "second control section".

[0122] Figure 10 is a circuit block diagram showing the structure of the control section 14. In Figure 10 The control section 14 includes a reference voltage generating circuit 20, voltage detectors 21, 28, subtractors 22, 26A to 26C, a DC voltage control circuit 23, a sine wave generating circuit 24, multipliers 25A to 25C, a current control circuit 27, adders 29A to 29C, a PWM circuit 30, and a gate circuit 31.

[0123] The reference voltage generation circuit 20 outputs a reference voltage VDCr based on a switching signal φC from the timer 12. In a case where the switching signal φC is at an inactive level "L" level, the reference voltage VDCr is set to a reference voltage VDCr1. In a case where the switching signal φC is at an active level "H" level, the reference voltage VDCr is set to a reference voltage VDCr2.

[0124] The voltage detector 21 detects the voltage VDC between the terminals of the capacitor Cd and outputs a signal indicative of the detected value. The subtracter 22 subtracts the voltage VDC between the terminals of the capacitor Cd indicated by the output signal of the voltage detector 21 from the reference voltage VDCr generated by the reference voltage generation circuit 20, and obtains a deviation ΔVDC = VDCr - VDC between the reference voltage VDCr and the direct current voltage VDC.

[0125] The direct current voltage control circuit 23 generates a current command value Ic for commanding the input currents I1 to I3 of the converter 1 based on the deviation ΔVDC, the load currents I4 to I6, and the switching signal φC. Figure 11 is a circuit block diagram indicative of the structure of the direct current voltage control circuit 23. In Figure 11 , the direct current voltage control circuit 23 includes a PI (Proportional-Integral) control circuit 41, an effective value operation section 42, a gain generation circuit 43, a multiplier 44, and an adder 45.

[0126] The PI control circuit 41 obtains a feedback component Ifb corresponding to the value of the deviation ΔVDC = VDCr - VDC by performing proportional-integral operation of the deviation ΔVDC. The feedback component Ifb is represented by the following equation (1).

[0127] [Mathematical Expression 1]

[0128] I fb = K p × ΔVDC + K i0 T ΔVDCdt... (1)

[0129] The feedback control is performed in such a manner that the feedback component Ifb increases if the deviation ΔVDC increases and the deviation ΔVDC decreases, and the feedback component Ifb decreases if the deviation ΔVDC decreases and the deviation ΔVDC disappears.

[0130] The effective value operation section 42 calculates the effective value Ie of the load currents I4 to I6 indicated by the output signals of the current detectors CT4 to CT6, and outputs a signal indicating the effective value Ie. The gain generation circuit 43 outputs a gain K in accordance with the switching signal φC. In the case where the switching signal φC is at the "L" level, the gain K is set to the gain K1. In the case where the switching signal φC is at the "H" level, the gain K is set to the gain K2 which is smaller than the gain K1.

[0131] The multiplier 44 multiplies the effective value Ie of the load currents I4 to I6 by the gain K, and generates a feedforward component Iff = K x Ie of the current command value Ic. The adder 45 adds the feedback component Ifb to the feedforward component Iff, and generates the current command value Ic = Ifb + Iff.

[0132] In the present embodiment 1, since the feedforward component Iff is introduced to the current command value Ic, it is possible to set the proportional gain Kp of the feedback component Ifb to a relatively small value, and to stabilize the PI control.

[0133] Referring again to Figure 10 , the sine wave generation circuit 24 generates three-phase sine wave signals in phase with the three-phase alternating voltages Vu1, Vv1, Vw1 from the commercial alternating power source 6. The multipliers 25A to 25C multiply the three-phase sine wave signals by the current command value Ic, respectively, and generate three-phase current command values I1c to I3c.

[0134] The subtracter 26A calculates a deviation ΔI1 = I1c - I1 between the current command value I1c and the alternating current I1 detected by the current detector CT1. The subtracter 26B calculates a deviation ΔI2 = I2c - I2 between the current command value I2c and the alternating current I2 detected by the current detector CT2. The subtracter 26C calculates a deviation ΔI3 = I3c - I3 between the current command value I3c and the alternating current I3 detected by the current detector CT3.

[0135] The current control circuit 27 generates the voltage command values V1a, V2a, V3a in such a manner that the deviations ΔI1, ΔI2, ΔI3 are 0, respectively. The current control circuit 27 generates the voltage command values V1a, V2a, V3a, for example, by performing proportional control or proportional integral control on the deviations ΔI1, ΔI2, ΔI3. The voltage detector 28 detects the instantaneous values of the three-phase alternating voltages Vu1, Vv1, Vw1 from the commercial alternating power source 6, and outputs signals indicating the detected values thereof.

[0136] Adder 29A adds the voltage command value V1a and the AC voltage Vu1 detected by voltage detector 28 to generate the voltage command value V1c. Adder 29B adds the voltage command value V2a and the AC voltage Vv1 detected by voltage detector 28 to generate the voltage command value V2c. Adder 29C adds the voltage command value V3a and the AC voltage Vw1 detected by voltage detector 28 to generate the voltage command value V3c.

[0137] PWM circuit 30 generates PWM control signals φ1 to φ3 for controlling converter 1 based on voltage command values ​​V1c to V3c. Gate circuit 31 generates gate signals A1, B1, A2, B2, A2, B2 based on the PWM control signals φ1 to φ3. Figure 2 ).

[0138] By controlling it in this way, in both inverter power supply mode and bypass power supply mode, the inter-terminal voltage VDC of capacitor Vd can be made to be the reference voltage VDCr1, so that the AC current I1 to I3, which includes the first feedback component corresponding to the deviation ΔVDC = VDCr1 - VDC between the reference voltage VDCr1 and the inter-terminal voltage VDC of the capacitor, and the first feedforward component obtained by multiplying the load currents I4 to I6 by the gain K1, can flow from the commercial AC power supply 6 to the converter 1.

[0139] In addition, during the switching period, the AC current I1 to I3, which includes a second feedback component corresponding to the deviation ΔVDC = VDCr2 between the reference voltage VDCr2 and the voltage VDC of the capacitor Cd, and a second feedforward component obtained by multiplying the load currents I4 to I6 by a gain K2 smaller than the gain K1, can be made to flow from the commercial AC power supply 6 to the converter 1 in such a way that the inter-terminal voltage VDC of the capacitor Cd is made to the reference voltage VDCr2.

[0140] Figure 12 (A)~(I) represent Figure 9 The timing diagram of the operation of the control device 5 shown. Figure 12 (A) represents the waveform of the mode selection signal MS. Figure 12 (B) represents the waveform of the switching command signal PC. Figure 12 (C) represents the waveform of the switching signal φC. Figure 12 (D) represents the waveform of the overlapping command signal φOL.

[0141] in addition, Figure 12 (E) represents the gain K. Figure 12 (F) represents the reference voltage VDCr. Figure 12 (G) represents the voltage VDC between the terminals of capacitor Cd. Figure 12(H) indicates the state of switches S1-S3, Figure 12 (I) indicates the state of switches S4-S6. In Figure 12 (A) to (I), the operation in the case where the inverter power supply mode is switched to the bypass power supply mode is shown.

[0142] At time t0, the inverter power supply mode is executed, the mode selection signal MS, the switching instruction signal PC, the switching signal φC, and the overlap instruction signal φOL are set to the "L" level. In addition, the gain K is set to the gain Kl, the reference voltage VDCr is set to the reference voltage VDCrl, the terminal voltage VDC of the capacitor Cd is set to the reference voltage VDCrl, the switches S1-S3 are turned on, and the switches S4-S6 are turned off.

[0143] When the bypass power supply mode is selected using the operation section 4 at a certain time tl, the mode selection signal MS rises from the "L" level to the "H" level, and the switching instruction signal PC is raised to the "H" level for a prescribed time by the signal generation circuit 11. In response to the rising edge of the switching instruction signal PC, the timer 12 sequentially measures the first time Tl, the second time T2, and the third time T3, and generates the switching signal φC and the overlap instruction signal φOL based on the measurement results.

[0144] The switching signal φC is set to the "H" level from the rising edge of the switching instruction signal PC (time tl) to the third time T3 (time t4). The overlap instruction signal φOL is set to the "H" level from the first time Tl (time t2) to the second time T2 (time t3).

[0145] If the switching signal φC rises from the "L" level to the "H" level (time tl), the gain K is lowered from the gain Kl to the gain K2, and the reference voltage VDCr is raised from the reference voltage VDCrl to the reference voltage VDCr2. The converter 1 is controlled by the control section 14 so that the terminal voltage VDC of the capacitor Cd becomes the reference voltage VDCr2.

[0146] During the period in which the terminal voltage VDC of the capacitor Cd becomes the reference voltage VDCr2, the overlap instruction signal φOL becomes the "H" level and the overlap power supply mode is executed. If the overlap instruction signal φOL rises to the "H" level (time t2), the switches S4-S6 are turned on. At this time, since the terminal voltage VDC of the capacitor Cd is raised to the reference voltage VDCr2, the circulating current IC does not flow. Figure 6 、 Figure 7 In addition, the gain K is lowered to the gain K2, so that the terminal voltage VDC of the capacitor Cd can be prevented from rising. If the overlap instruction signal φOL falls to the "L" level (time t3), the switches S1-S3 are turned off, and the overlap power supply mode ends.

[0147] If the switching signal φC falls to the "L" level (time t4), the gain K rises from the gain K2 to the gain K1, and the reference voltage VDCr falls to the reference voltage VDCr1, and the capacitor Cd is discharged. When the voltage VDC between the terminals of the capacitor Cd becomes the reference voltage VDCr1, the switching from the inverter power supply mode to the bypass power supply mode is completed.

[0148] Figure 13 (A) to (I) are indicative of Figure 9 the other timing chart showing the operation of the control device 5 shown in Figure 12 (A) to (I) of FIG. 10. In Figure 13 (A) to (I), the operation in the case where the bypass power supply mode is switched to the inverter power supply mode is shown.

[0149] At time tO, the bypass power supply mode is executed, the mode selection signal MS is at the "H" level, and the switching command signal PC, the switching signal φC, and the overlap command signal φOL are all at the "L" level. In addition, the gain K is set to the gain K1, the reference voltage VDCr is set to the reference voltage VDCr1, the voltage VDC between the terminals of the capacitor Cd is set to the reference voltage VDCr1, and the switches S1 to S3 are turned off and the switches S4 to S6 are turned on.

[0150] When the inverter power supply mode is selected using the operation section 4 at a certain time tl, the mode selection signal MS falls from the "H" level to the "L" level, and the switching command signal PC is raised to the "H" level by the signal generating circuit 11 for a prescribed time. In response to the rising edge of the switching command signal PC, the timer 12 measures the first time Tl, the second time T2, and the third time T3 in this order, and generates the switching signal φC and the overlap command signal φOL based on the measurement results.

[0151] The switching signal φC is set to the "H" level from the rising edge of the switching command signal PC (time tl) to the third time T3 (time t4). The overlap command signal φOL is set to the "H" level from the first time Tl (time t2) to the second time T2 (time t3).

[0152] If the switching signal φC rises from the "L" level to the "H" level (time tl), the gain K falls from the gain K1 to the gain K2, and the reference voltage VDCr rises from the reference voltage VDCr1 to the reference voltage VDCr2, and the converter 1 is controlled by the control section 14 so that the voltage VDC between the terminals of the capacitor Cd becomes the reference voltage VDCr2.

[0153] During the period in which the voltage VDC between the terminals of the capacitor Cd becomes the reference voltage VDCr2, the overlap command signal φOL becomes the "H" level and the overlap power supply mode is executed. If the overlap command signal φOL rises to the "H" level (time t2), the switches S1 to S3 are turned on. At this time, since the voltage VDC between the terminals of the capacitor Cd is raised to the reference voltage VDCr2, the circulating current IC does not flow. Figure 6 , Figure 7 ). In addition, the gain K is lowered to the gain K2, so the voltage VDC between the terminals of the capacitor Cd can be prevented from rising. If the overlap command signal φOL falls to the "L" level (time t3), the switches S4 to S6 are turned off and the overlap power supply mode ends.

[0154] If the switching signal φC falls to the "L" level (time t4), the gain K rises from the gain K2 to the gain K1 and the reference voltage VDCr falls to the reference voltage VDCr1, and the capacitor Cd is discharged. When the voltage VDC between the terminals of the capacitor Cd becomes the reference voltage VDCr1, the switching from the bypass power supply mode to the inverter power supply mode is completed.

[0155] As described above, in the present embodiment 1, the alternating currents I1 to I3 including the feedback component and the feedforward component are caused to flow into the converter 1, so the feedback component can be controlled at a low speed to achieve stabilization of the control, and the feedforward component can cope with the sudden change in the load currents I4 to I6. In addition, during the switching period in which the inverter power supply mode and the bypass power supply mode are switched, the gain K is reduced to reduce the feedforward component, so the voltage VDC between the terminals of the capacitor Cd can be prevented from exceeding the upper limit voltage VDCH in the overlap power supply mode.

[0156] In addition, during the switching period, the converter 1 is controlled so that the voltage VDC between the terminals of the capacitor Cd becomes the reference voltage VDCr2 which is higher than the reference voltage VDCr1, thereby preventing the circulating current IC from flowing in the path including the capacitor Cd and the like. Therefore, even in the case where the neutral terminal 6d of the commercial alternating current power supply 6 and the neutral terminal 7d of the bypass alternating current power supply 7 are grounded, the circulating current IC can be prevented from flowing.

[0157] Further, in the present embodiment 1, the gain K of the feedback component is controlled in response to the switching signal φC, and the gain K is set to the gain K2 which is smaller than the gain K1 during the switching period, but it is not limited thereto, and the gain K can be controlled in response to the overlap command signal φOL and the gain K can be set to the gain K2 only in the overlap power supply mode.

[0158] [Embodiment 2]

[0159] Figure 14is a circuit block diagram showing the main part of the uninterruptible power supply device of Embodiment 2 of the present application, and is the same as Figure 10 the comparative drawing. Referring to Figure 14 , the uninterruptible power supply device differs from the uninterruptible power supply device of Embodiment 1 in that the DC voltage control circuit 23 is replaced by a DC voltage control circuit 23A.

[0160] The DC voltage control circuit 23A replaces the gain generating circuit 43 of the DC voltage control circuit 23 with a gain generating circuit 43A as shown in Figure 15 . The gain generating circuit 43A sets the gain K to a gain Kl (first value) in the case where the deviation ΔVDC = VDCr - VDC between the reference voltage VDCr and the terminal voltage VDC of the capacitor Cd is 0. In addition, the gain generating circuit 43A reduces the gain K in accordance with the deviation ΔVDC in the case where the deviation ΔVDC exceeds 0, thereby setting the gain K to a gain Kc (second value) smaller than the gain Kl. Since the other structures and operations are the same as those of Embodiment 1, the description thereof is not repeated.

[0161] As described above, in this Embodiment 2, in the case where the terminal voltage VDC of the capacitor Cd rises and the deviation ΔVDC increases, the gain K is reduced and the feedforward component is reduced, and therefore, it is possible to prevent the terminal voltage VDC of the capacitor Cd from exceeding the upper limit voltage VDCH not only in the overlap power supply mode but also in the inverter power supply mode and the bypass power supply mode.

[0162] It should be understood that the embodiments disclosed this time are illustrative and not restrictive in all aspects. The present application is not shown by the above description but by the claims, and it is intended to include all modifications equivalent in meaning and scope to the claims.

[0163] Explanation of Reference Numerals

[0164] C1-C6, Cd capacitor, L1-L6 reactor, CT1-CT6 current detector, 1 converter, Lp DC positive bus, Ln DC negative bus, 2 bidirectional chopper, 3 inverter, S1-S6 switch, 4 operation unit, 5 control device, 6 commercial AC power supply, 6d, 7d neutral point terminal, 6U, 6V, 6W, 7U, 7V, 7W AC power supply, 7 bypass AC power supply, 8 load, Q1-Q6, Q11-Q16 IGBT, D1-D6, D11-D16 diode, 11 signal generating circuit, 12 timer, 13, 14 control unit, 20 reference voltage generating circuit, 21, 28 voltage detector, 22, 26A-26C subtracter, 23, 23A DC voltage control circuit, 24 sine wave generating circuit, 25A-25C, 44 multiplier, 27 current control circuit, 29A-29C, 45 adder, 30 PWM circuit, 31 gate circuit, 41 PI control circuit, 42 effective value operation unit, 43, 43A gain generating circuit.

Claims

1. An uninterruptible power supply device, comprising: a rectifier that converts a first alternating-current voltage supplied from a first alternating-current power source into a direct-current voltage; a capacitor that smoothes a direct-current output voltage of the rectifier; an inverter that converts a voltage between terminals of the capacitor into a second alternating-current voltage; a first switch that has one terminal receiving the second alternating-current voltage and the other terminal connected to a load; a second switch that has one terminal receiving a third alternating-current voltage supplied from a second alternating-current power source and the other terminal connected to the load; a first current detector that detects an alternating-current current flowing between the first alternating-current power source and the rectifier; a second current detector that detects a load current; a first control unit that controls the first switch and the second switch; and a second control unit that controls the rectifier on the basis of detection results of the first current detector and the second current detector, wherein the first control unit is configured to: (i) in a first mode in which the second alternating-current voltage is supplied to the load, turn on the first switch and turn off the second switch, (ii) in a second mode in which the third alternating-current voltage is supplied to the load, turn on the second switch and turn off the first switch, and (iii) in a switching period in which a mode is switched from either one of the first mode and the second mode to the other mode, execute a third mode in which the first switch and the second switch are turned on to supply the second alternating-current voltage and the third alternating-current voltage to the load, and wherein the second control unit is configured to prevent the voltage between the terminals of the capacitor from exceeding an upper limit voltage higher than first and second reference voltages by: (iv) in the first mode and the second mode, causing a first alternating-current current including a first feedback component and a first feedforward component to flow from the first alternating-current power source to the rectifier in such a manner that the voltage between the terminals of the capacitor becomes the first reference voltage, the first feedback component being a value corresponding to a deviation between the first reference voltage and the voltage between the terminals of the capacitor, and the first feedforward component being a product of the load current and a first gain, and (v) in the switching period, causing a second alternating-current current including a second feedback component and a second feedforward component to flow from the first alternating-current power source to the rectifier in such a manner that the voltage between the terminals of the capacitor becomes the second reference voltage, the second feedback component being a value corresponding to a deviation between the second reference voltage and the voltage between the terminals of the capacitor, and the second feedforward component being a product of the load current and a second gain smaller than the first gain.

2. The uninterruptible power supply device according to claim 1, wherein the second control unit is configured to prevent circulating current from flowing from either one of the first alternating-current power source and the second alternating-current power source to the other alternating-current power source via the capacitor by setting the second reference voltage higher than the first reference voltage.

3. The uninterruptible power supply device according to claim 2, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The first AC power source and the second AC power source each include a three-phase AC power source connected in a star configuration with respect to a neutral point, The neutral points of the first AC power source and the second AC power source are each grounded, The first AC voltage to the third AC voltage each include a three-phase AC voltage, The first switch includes 3 one-side terminals that receive a three-phase AC voltage included in the second AC voltage, and 3 other-side terminals connected to the load, The second switch includes 3 one-side terminals that receive a three-phase AC voltage included in the third AC voltage, and 3 other-side terminals connected to the load, The first reference voltage is lower than 2 times the peak value of the first AC voltage, The second reference voltage is 2 times the peak value of the first AC voltage or more.

4. The uninterruptible power supply device according to claim 3, wherein The first AC power source is a commercial AC power source, The second AC power source is a generator.

5. The uninterruptible power supply device according to claim 2, wherein Further comprising: a selection section that selects either one of the first mode and the second mode; a signal generation circuit that outputs a switching instruction signal in accordance with a case where the mode selected by the selection section is changed from one mode to another mode; and a timer that sequentially measures a first time, a second time, and a third time in response to the switching instruction signal, During the switching period, the first control section executes the third mode from when the first time is measured by the timer until the second time is measured, During the switching period, the second control section causes the second AC current to flow from the first AC power source to the rectifier from when the switching instruction signal is output until the third time is measured by the timer.

6. The uninterruptible power supply device according to claim 5, wherein The second control section includes: a gain generation circuit that outputs the first gain at the first mode and the second mode, and outputs the second gain from when the switching instruction signal is output until the third time is measured by the timer; a reference voltage generation circuit that outputs the first reference voltage at the first mode and the second mode, and outputs the second reference voltage from when the switching instruction signal is output until the third time is measured by the timer; and a voltage detector that detects the voltage between the terminals of the capacitor, The second control section, calculates the first feedforward component and the second feedforward component based on the load current and the gain output from the gain generation circuit, calculates the first feedback component and the second feedback component based on the deviation between the output voltage of the reference voltage generation circuit and the detection value of the voltage detector.

7. The uninterruptible power supply device according to claim 1, wherein Further provided is a bidirectional chopper that, when the first AC power source is not malfunctioning, accumulates DC power generated by the rectifier in a power storage device, and that, when the first AC power source is out of service, supplies DC power of the power storage device to the inverter.

8. An uninterruptible power supply device, comprising: a rectifier that converts a first AC voltage supplied from a first AC power source into a DC voltage; a capacitor that smooths a DC output voltage of the rectifier; an inverter that converts a voltage between terminals of the capacitor into a second AC voltage; a first switch whose one terminal receives the second AC voltage and whose other terminal is connected to a load; a second switch whose one terminal receives a third AC voltage supplied from a second AC power source and whose other terminal is connected to the load; a first current detector that detects an AC current that flows between the first AC power source and the rectifier; a second current detector that detects a load current; a first control unit that controls the first switch and the second switch; and a second control unit that controls the rectifier on the basis of detection results of the first current detector and the second current detector, the first control unit is configured to: (i) in a first mode in which the second AC voltage is supplied to the load, turn on the first switch and turn off the second switch, (ii) in a second mode in which the third AC voltage is supplied to the load, turn on the second switch and turn off the first switch, (iii) in a switching period in which switching from either one of the first mode and the second mode to the other mode is performed, execute a third mode in which the first switch and the second switch are turned on to supply the second AC voltage and the third AC voltage to the load, the second control unit is configured to prevent a voltage between terminals of the capacitor from exceeding an upper limit voltage that is higher than a reference voltage by: (iv) causing an AC current that includes a feedback component and a feedforward component to flow from the first AC power source to the rectifier in such a manner that the voltage between terminals of the capacitor becomes the reference voltage, the feedback component being a value corresponding to a deviation between the reference voltage and the voltage between terminals of the capacitor, the feedforward component being a product of the load current and a gain, (v) in a case where the voltage between terminals of the capacitor exceeds the reference voltage, reducing the gain in accordance with a difference between the voltage between terminals of the capacitor and the reference voltage.

9. The uninterruptible power supply device according to claim 8, wherein the second control unit is configured to prevent circulation of a current from either one of the first AC power source and the second AC power source to the other AC power source via the capacitor by: in the first mode and the second mode, setting the reference voltage to a first voltage value, in the switching period, setting the reference voltage to a second voltage value that is higher than the first voltage value.

10. The uninterruptible power supply device according to claim 9, wherein The first and second AC power sources each include a three-phase AC power source connected in a star configuration with respect to a neutral point, The neutral points of the first and second AC power sources are each grounded, The first to third AC voltages each include a three-phase AC voltage, The first switch includes three one-side terminals that receive a three-phase AC voltage included in the second AC voltage, and three other-side terminals that are connected to the load, The second switch includes three one-side terminals that receive a three-phase AC voltage included in the third AC voltage, and three other-side terminals that are connected to the load, The first voltage value is lower than a voltage that is twice a peak value of the first AC voltage, The second voltage value is equal to or higher than a voltage that is twice the peak value of the first AC voltage.

11. The uninterruptible power supply device according to claim 10, wherein The first AC power source is a commercial AC power source, The second AC power source is a generator.

12. The uninterruptible power supply device according to claim 9, wherein Further comprising: a selection section that selects either one of the first mode and the second mode; a signal generation circuit that outputs a switching instruction signal in accordance with a case where one mode changes to another mode selected by the selection section; and a timer that sequentially measures a first time, a second time, and a third time in response to the switching instruction signal, During the switching period, the first control section executes the third mode from when the first time is measured by the timer until the second time is measured, During the switching period, the second control section sets the reference voltage to the second voltage value from when the switching instruction signal is output until the third time is measured by the timer.

13. The uninterruptible power supply device according to claim 12, wherein The second control section includes: a gain generation circuit that sets the gain to a first value in a case where the voltage across the terminals of the capacitor is lower than the reference voltage, and sets the gain to a second value that is smaller than the first value in accordance with a difference between the voltage across the terminals of the capacitor and the reference voltage in a case where the voltage across the terminals of the capacitor is higher than the reference voltage; a reference voltage generation circuit that sets the reference voltage to the first voltage value at the time of the first mode and the second mode, and sets the reference voltage to a second voltage value that is higher than the first voltage value from when the switching instruction signal is output until the third time is measured by the timer; and a voltage detector that detects the voltage across the terminals of the capacitor, The second control section, multiplies the load current by the gain set by the gain generation circuit to obtain the feed-forward component, obtains the feedback component based on a deviation between the reference voltage set by the reference voltage generation circuit and a detection value of the voltage detector.

14. The uninterruptible power supply device according to claim 8, wherein Further, a bidirectional chopper is provided, which accumulates DC power generated by the rectifier in a power storage device when the first AC power source is not in trouble, and supplies DC power of the power storage device to the inverter when the first AC power source is out of service.

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