Microelectromechanical devices and methods of forming the same

Abstract

This invention provides a microelectromechanical device (MEMS) and a method for forming the same. The MEMS includes a composite substrate, a cavity, a piezoelectric stacked structure, and a mass. The composite substrate includes a first semiconductor layer, an adhesive layer, and a second semiconductor layer stacked sequentially from bottom to top. The cavity is disposed within the composite substrate, extending from the second semiconductor layer to the first semiconductor layer but not penetrating it. The piezoelectric stacked structure is disposed on the composite substrate, and includes a suspension region located above the cavity. The mass is disposed within the cavity and connected to the piezoelectric stacked structure.

Description

Technical Field

[0001] This invention relates to a microelectromechanical device (MEMS) and a method for forming the same, and more particularly to a MEMS and a method for forming the same for use in the field of acoustics. Background Art

[0002] Micro-electromechanical systems (MEMS) are tiny mechanical components manufactured using conventional semiconductor processes. These micrometer-sized mechanical components are created through semiconductor techniques such as deposition or selective etching of material layers. MEMS devices can operate using electromagnetic, electrostrictive, thermoelectric, piezoelectric, or piezoresistive effects, combining both electronic and mechanical functions. Therefore, they are commonly used in microelectronics fields, such as in accelerometers, gyroscopes, mirrors, and acoustic sensors.

[0003] In recent years, the rapid development of true wireless stereo (TWS) earphones has opened up new possibilities for acoustic transducers by enabling the use of microelectromechanical systems (MEMS) accelerators to sense sound vibrations. Incorporating MEMS accelerators into these earphones allows them to effectively capture sound even in noisy environments. However, because MEMS accelerators are currently widely used in mobile phones, their designs tend to be thick and large, which does not meet the miniaturization requirements of wireless earphones. Therefore, a new accelerator design is still needed for application in the acoustic field. Summary of the Invention

[0004] This invention provides a microelectromechanical device (MEMS) and a method for forming the same. The MEMS has a miniaturized proof mass, which occupies a relatively small area compared to suspension structures such as cantilever or diaphragm. With the aforementioned configuration, the MEMS of this invention can be applied to wireless Bluetooth headsets to assist microphone voice vibration.

[0005] To achieve the above objectives, one embodiment of the present invention provides a microelectromechanical device (MEMS) comprising a composite substrate, a cavity, a piezoelectric stack structure, and a mass. The composite substrate comprises a first semiconductor layer, an adhesive layer, and a second semiconductor layer stacked sequentially from bottom to top. The cavity is disposed within the first semiconductor layer, extending from the second semiconductor layer through the first semiconductor layer without penetrating it. The piezoelectric stack structure is disposed on the composite substrate, and includes a suspension region located on the cavity. The mass is disposed within the cavity and connected to the piezoelectric stack structure.

[0006] To achieve the above objectives, one embodiment of the present invention provides a method for forming a microelectromechanical device (MEMS), comprising the following steps: First, a composite substrate is provided, the composite substrate comprising a first semiconductor layer, an adhesive layer, and a second semiconductor layer stacked sequentially from bottom to top. A cavity is formed within the composite substrate, the cavity extending from the second semiconductor layer through the first semiconductor layer but not penetrating the first semiconductor layer. Next, a piezoelectric stack structure is formed on the composite substrate, the piezoelectric stack structure including a suspension region located above the cavity. Then, a mass block is formed within the cavity, the mass block connecting to the piezoelectric stack structure. Attached Figure Description

[0007] Figure 1 This is a top view of a microelectromechanical device (MEMS device) of the present invention after a cavity has been formed.

[0008] Figure 2 for Figure 1 A cross-sectional view along the tangent line A-A'.

[0009] Figure 3 This is a cross-sectional schematic diagram of a microelectromechanical device of the present invention after the formation of a groove.

[0010] Figure 4 This is a top view schematic diagram of a microelectromechanical device of the present invention after undergoing an oxidation process.

[0011] Figure 5 for Figure 4 A schematic diagram of the cross section of the microelectromechanical device along the tangent A-A'.

[0012] Figure 6 This is a top view schematic diagram of a microelectromechanical device of the present invention after forming a piezoelectric stack structure.

[0013] Figure 7 for Figure 6 A schematic diagram of the cross section of the microelectromechanical device along the tangent A-A'.

[0014] Figure 8 This is a schematic cross-sectional view of a microelectromechanical device of the present invention after thinning a composite substrate.

[0015] Figure 9 This is a top view of a microelectromechanical device of the present invention after the piezoelectric stack structure is released.

[0016] Figure 10 for Figure 9 A schematic diagram of the cross section of the microelectromechanical device along the tangent A-A'.

[0017] Figure 11 This is a top view schematic diagram of a microelectromechanical device according to another embodiment of the present invention.

[0018] Figure 12 This is a cross-sectional schematic diagram of a microelectromechanical device according to another embodiment of the present invention.

[0019] The following are the descriptions of the reference numerals:

[0020] 200: Piezoelectric stacking structure

[0021] 201a: First piezoelectric layer

[0022] 201b: Second piezoelectric layer

[0023] 202: Insulation layer

[0024] 203a: First metal layer

[0025] 203b: Second metal layer

[0026] 203c: Third metal layer

[0027] 205a: Connecting pad

[0028] 205b: Connecting pad

[0029] 207: Perforation

[0030] 210: Suspension Area

[0031] 210a: Half of the suspension area adjacent to the anchoring end

[0032] 210f: Half of the suspension area adjacent to the free end

[0033] 211: Connecting pad

[0034] 300, 500: Microelectromechanical devices

[0035] 310: Base

[0036] 310a: First surface

[0037] 310b: Second surface

[0038] 311, 312: First semiconductor layer

[0039] 311a: Initial cavity

[0040] 313: Adhesive layer

[0041] 313a: Undercut portion

[0042] 315: Second semiconductor layer

[0043] 315a: Groove

[0044] 315b: Grid

[0045] 315c: Mass Block Region

[0046] 316: Oxidized region

[0047] 317: Insulation layer

[0048] 320: Cavity

[0049] 330: Insulation layer

[0050] 330a: Undercut portion

[0051] 331: Insulation layer

[0052] 350: Protective layer

[0053] 370: Oxide layer

[0054] 390: Overlay

[0055] 450: Cap layer

[0056] 450a: Cavity

[0057] AE: Anchoring end

[0058] d1, d2, d3: Dimensions

[0059] FE: Free end

[0060] T1, T2, T4: Thickness

[0061] T3: Total Thickness

[0062] x, y: Direction Detailed Implementation

[0063] To enable those skilled in the art to further understand the present invention, several preferred embodiments of the present invention are listed below, and the composition and desired effects of the present invention are described in detail with reference to the accompanying drawings. Furthermore, those skilled in the art can also, without departing from the spirit of the present invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0064] In this invention, the description of "a first component being formed on or above a second component" can refer to either "the first component and the second component being in direct contact" or "other components existing between the first component and the second component," resulting in the first component and the second component not being in direct contact. Furthermore, various embodiments of this invention may use repeated component symbols and / or text markings. The use of these repeated component symbols and text markings is for the purpose of making the description more concise and clear, rather than to indicate the relationship between different embodiments and / or configurations. Additionally, regarding spatially related descriptive terms mentioned in this invention, such as "below," "above," "low," "high," "below," "above," "under," "above," "bottom," "top," and similar terms, for ease of description, their use is to describe the relative relationship between one component or feature and another (or more) components or features in the drawings. Besides the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientation of the semiconductor device during manufacturing, use, and operation. For example, when a semiconductor device is rotated 180 degrees, a component that was originally positioned "above" other components will become positioned "below" other components. Therefore, as the orientation of a semiconductor device changes (rotates 90 degrees or other angles), the spatial descriptions used to describe its orientation should also be interpreted accordingly.

[0065] Although the present invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by such terminology. Such terminology is only used to distinguish one element, component, region, layer, and / or section from another, and does not in itself imply or represent any prior ordinal number of the elements, nor does it represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section, etc.

[0066] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0067] Please refer to Figures 1 to 10 As shown, it illustrates a schematic diagram of the manufacturing process of the microelectromechanical device 300 in the first embodiment of the present invention, wherein, Figure 1 , Figure 4 , Figure 6 as well as Figure 9 Draw a top view of a microelectromechanical device (MEMS) during the manufacturing process, and the other drawings show cross-sectional views of the same MEMS during the manufacturing process. First, as... Figure 1 as well as Figure 2 As shown, a composite substrate 310, such as a silicon-on-insulator (SOI) substrate, is provided for fabricating a microelectromechanical device 300. The composite substrate 310 further includes a first semiconductor layer 311, made of materials such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other suitable materials; an adhesive layer 313, made of materials such as silicon monoxide (SiO), silicon oxynitride (SiON), or silicon dioxide (SiO2); and a second semiconductor layer 315, made of materials such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other suitable materials. The first semiconductor layer 311, the adhesive layer 313, and the second semiconductor layer 315 are stacked sequentially from bottom to top to form the composite substrate 310. In this embodiment, the thickness T1 of the second semiconductor layer 315 is preferably less than the thickness of the first semiconductor layer 311 (not shown). For example, the thickness of the first semiconductor layer 311 is approximately 400 micrometers (μm) to 500 micrometers, and the thickness T1 of the second semiconductor layer 315 can be approximately 50 micrometers to 100 micrometers, but is not limited thereto. Preferably, the thickness T1 of the second semiconductor layer 315 can be equivalent to a predetermined thickness of the subsequently formed mass block, for example, 50 micrometers, but is not limited thereto. Those skilled in the art should readily understand that the thickness of the second semiconductor layer 315 can also be further adjusted according to the sensing accuracy required by the actual product, referring to the following formula (I).

[0068] Formula (I): Among them, κ B ω is Boltzmann's constant; T is absolute temperature; ω0 is the resonance frequency; m i denoted by , where is the mass of the sensor; Q is the mass coefficient.

[0069] An initial cavity 311a is formed in the composite substrate 310. The initial cavity 311a extends, for example, from the top surface of the first semiconductor layer 311 into the interior of the first semiconductor layer 311. Figure 2 As shown, the adhesive layer 313 covers the top surface of the first semiconductor layer 311 and the inner surface of the initial cavity 311a. In one embodiment, the composite substrate 310 may be formed, for example, by the following steps: First, two semiconductor layers (not shown) with a thickness of approximately 400 to 500 micrometers are provided. An initial cavity 311a is formed on one of the two semiconductor layers. The surface of one of the two semiconductor layers is oxidized to form the adhesive layer 313. The two semiconductor layers are then bonded together by the adhesive layer 313. Then, the other of the two semiconductor layers is thinned to a certain thickness, for example, thickness T1, to obtain the composite substrate 310. In another embodiment, the adhesive layer 313 may also be disposed directly on the semiconductor layer and the initial cavity 311a. The adhesive layer 313 may include an organic material, such as polyimide, photoresist, or other suitable materials.

[0070] In detail, the composite substrate 310 has two opposing surfaces, such as Figure 2 The first surface 310a and the second surface 310b are shown, wherein an initial cavity 311a is formed adjacent to the first surface 310a, that is, the initial cavity 311a is formed on the front side of the composite substrate 310, and its size (e.g., aperture) d1 is, for example, about 100 micrometers to 150 micrometers, but not limited thereto. In other words, the initial cavity 311a is used to initially define the size and position of the cavity to be formed subsequently, so that the size d1 of the initial cavity 311a can be further adjusted according to the predetermined size of the cavity to be formed subsequently. On the other hand, an insulating layer 317 is then formed on the second surface 310b (i.e., the back side of the composite substrate 310). The insulating layer 317 may include silicon monoxide or silicon dioxide, but is not limited thereto. In one embodiment, the insulating layer 317 may be formed, for example, by an oxidation process, for example, by forming it in the same oxidation process as the adhesive layer 313, but is not limited thereto.

[0071] Next, as Figure 3 As shown, a plurality of trenches 315a are formed in the composite substrate 310, such that each trench 315a penetrates both opposing surfaces of the second semiconductor layer 315. The trenches 315a are spaced apart and positioned corresponding to the lower initial cavity 311a to define at least one mass block region 315c within the area of ​​the initial cavity 311a, as shown. Figure 3As shown. Preferably, the size (width) d3 of the mass block region 315c can be substantially equivalent to the predetermined size of the mass block subsequently formed, and the predetermined size of the mass block can be determined according to the sensing accuracy required for the actual product, for example, it can be set according to the aforementioned formula (I). In one embodiment, a plurality of gates 315b are spaced apart from each other between the trenches 315a, and the size (width) d2 of each trench 315a is preferably determined by the oxidation rate required in the subsequent oxidation process. In one embodiment, each trench 315a and each gate 315b can have the same size (width) d2, such as about 0.5 micrometers to 2.5 micrometers, preferably about 0.6 micrometers to 0.8 micrometers, but not limited thereto. In another embodiment, the trenches 315a and gates 315b can also be selected to have different sizes, or multiple trenches or multiple gates with different sizes can be formed, thereby enabling different oxidation rates in the actual process.

[0072] Then, as Figure 4 as well as Figure 5 As shown, an oxidation process, such as a wet oxidation process or a dry oxidation process, is performed to form an oxide region 316 within the second semiconductor layer 315. In one embodiment, the oxide region 316 preferably comprises the same material as the adhesive layer 313, or comprises a material having the same etch selectivity as the adhesive layer 313, but is not limited thereto. Specifically, the oxide region 316 is formed by oxidizing the gate 315b. Because the volume of the oxidized gate 315b is significantly increased compared to its original volume, it can fill adjacent trenches 315a and further merge all the oxidized gates 315b to form the oxide region 316. In one embodiment, the second semiconductor layer 315 may comprise silicon, and the volume of the oxidized gates 315b (e.g., comprising silicon monoxide or silicon dioxide) may be increased by approximately two times, thereby filling trenches 315a and merging them together. However, the material of the second semiconductor layer 315 is not limited to the aforementioned. It should also be noted that, since the oxidation process is performed uniformly on all exposed surfaces of the second semiconductor layer 315, therefore, as Figure 5 As shown, the bottom surface of the mass block region 315c is also oxidized, and an insulating layer 330 can be further formed on the top surface of the second semiconductor layer 315 (i.e., the first surface 310a of the composite substrate 310). In this case, the mass block region 315c can be surrounded by these oxidized portions, which include, for example, the oxidized region 316 and the insulating layer 330. It should be noted that, in one embodiment, one or more mass block regions can be selectively defined at the location corresponding to the initial cavity 311a. For example, such as Figure 4As shown, three mass block regions 315c can be defined simultaneously within the same initial cavity 311a, but this is not the only possibility. Those skilled in the art will readily understand that any number of mass block regions can be formed within the initial cavity 311a to meet different product requirements.

[0073] Then, as Figure 6 as well as Figure 7 As shown, a piezoelectric stack structure 200 is further formed on the insulating layer 330, wherein the piezoelectric stack structure 200 is disposed on the front side of the composite substrate 310. The piezoelectric stack structure 200 can be any suitable semiconductor structure formed using known semiconductor processes such as deposition and / or selective etching of material layers. In one embodiment, the piezoelectric stack structure 200 includes at least one piezoelectric layer, such as two piezoelectric layers 201a and 201b, and at least one metal layer 203, such as three metal layers 203a, 203b, and 203c, which are alternately stacked on an insulating layer 202 above the insulating layer 330. The piezoelectric layer may include, for example, a piezoelectric material, such as aluminum nitride (AlN), doped aluminum nitride, scandium aluminum nitride (ScAlN), doped scandium aluminum nitride, lead zirconate titanate (PZT), zinc oxide (ZnO), polyvinylidene fluoride (PVDF), lead manganese niobate-lead titanate, lithium niobate (LiNbO3), or lithium tantalate (LiTaO3). The metal layer may include, for example, copper (Cu), molybdenum (Mo), tungsten (W), titanium (Ti), platinum (Pt), or aluminum (Al), but is not limited thereto. In detail, a first piezoelectric layer 201a is stacked on a first metal layer 203a above an insulating layer 202, a second piezoelectric layer 201b is stacked on a second metal layer 203b above the first piezoelectric layer 201a, and then a third metal layer 203c is stacked on the second piezoelectric layer 201b, as follows. Figure 7As shown, but not limited to, in another embodiment, two metal layers and a piezoelectric layer may be formed stacked on top of each other. Furthermore, the piezoelectric stack structure 200 also includes at least one connecting pad, for example, two connecting pads 205a and 205b passing through the piezoelectric stack structure 200 to electrically connect different metal layers (such as the second metal layer 203b and the first metal layer 203a), respectively. The connecting pad may include a conductive material, such as copper or aluminum. This invention is intended to clearly illustrate the arrangement position between the piezoelectric stack structure 200 and its underlying components (such as the mass block region 315c). Figure 6 The detailed components of the piezoelectric stack structure 200, such as connecting pads 205a and 205b, have been omitted from the drawing.

[0074] The piezoelectric stack structure 200 also includes at least one suspension region 210 corresponding to the initial cavity 311a below, and at least one through-hole 207 is formed on the piezoelectric stack structure 200 adjacent to the suspension region 210, such as... Figure 7 As shown, the structure disposed within the suspension region 210 can be partially separated from the composite substrate 310 in subsequent processes, forming a suspension structure similar to a cantilever or diaphragm (not shown). The suspension structure, for example, includes a top electrode (such as the second metal layer 203b), a piezoelectric layer (such as the second piezoelectric layer 201a), and a bottom electrode (such as the first metal layer 203a) stacked sequentially from top to bottom, thereby enabling it to vibrate at a specific frequency in subsequent processes. In one embodiment, one or more suspension regions 210 may be formed within the piezoelectric stack structure 200, located above the initial cavity 311a. For example, three suspension regions 210 may be formed simultaneously, and three mass block regions 315c are respectively disposed below the three suspension regions 210, such as... Figure 6 As shown, the vibration frequency of each suspension structure can be adjusted to meet product requirements.

[0075] Then, as Figure 8As shown, a protective layer 350 is formed on the piezoelectric stack structure 200 to protect the components disposed in the piezoelectric stack structure 200. The protective layer 350 may include, for example, the same material as the adhesive layer 313 and the insulating layer 330, or a material with the same etch selectivity as the adhesive layer 313 and the insulating layer 330, such as silicon monoxide or silicon dioxide, but is not limited thereto. Then, a thinning process is performed on the composite substrate 310, for example, from the back side of the composite substrate 310 (i.e., the side where the second surface 310b is located). As a result, the insulating layer 317 disposed on the second surface 310b is completely removed, and a portion of the first semiconductor layer 311 is also removed, such that the remaining first semiconductor layer 312 has a smaller thickness T2. In one embodiment, the thickness T2 of the remaining first semiconductor layer 312 (i.e., the thinned first semiconductor layer) is, for example, about 200 micrometers to 300 micrometers; therefore, the total thickness T3 of the composite substrate 310 may be about 300 micrometers to 400 micrometers, but is not limited thereto.

[0076] After that, as Figures 9 and 10 As shown, an etching process, such as an isotropic wet etching process, is performed from the front side of the composite substrate 310 to completely remove the protective layer 350 and the oxide region 316, and to partially remove the insulating layer 330 and the adhesive layer 313, which are made of similar materials or have similar etch selectivity. This releases the suspension region 210 within the piezoelectric stack structure 200, forming the microelectromechanical device 300. Figure 10 As shown, when removing the oxidized region 316, the portions of the insulating layer 330 and the adhesive layer 313 near the oxidized region 316 are also removed, thereby exposing part of the bottom surface of the suspension region 210, as shown. Figure 10 As shown. In this condition, the space created by removing the oxide region 316 and the initial cavity 311a can together form a cavity 320 within the composite substrate 310. The cavity 320 extends from the top surface of the second semiconductor layer 315 into the thinned first semiconductor layer 312 and is connected to the exposed bottom surface of the suspension region 210. Furthermore, the cavity 320 may have an opening of uniform size d1, such as... Figure 10 As shown.

[0077] On the other hand, after removing the oxide region 316, the mass block region 315c in the second semiconductor layer 315 can be separated from the remaining portion of the second semiconductor layer 315. Thus, the mass block region 315c is connected to the bottom surface of the suspension region 210 only through the insulating layer 330, and can serve as the mass block of the microelectromechanical device 300. Therefore, the thickness of each mass block can be substantially equal to the thickness T2 of the second semiconductor layer 315, for example, approximately 50 micrometers to 100 micrometers, preferably 50 micrometers. Figure 10As shown, a portion of the insulating layer 331 is sandwiched between each suspension region 210 and each mass block (i.e., each mass block region 315c). During the aforementioned etching process, the sidewalls of the portion of the insulating layer 331, as well as the remaining sidewalls of the insulating layer 330 and the adhesive layer 313, can be slightly removed, forming undercut portions 330a and 313a near the cavity 320. Figure 10 As shown.

[0078] The aforementioned process can form the microelectromechanical device 300 of the first embodiment of the present invention. The microelectromechanical device 300 includes a piezoelectric stack structure 200, a cavity 320, and at least one mass block (i.e., the mass block region 315c of the second semiconductor layer 315) disposed inside the cavity 320. It should be noted that due to the formation of the through-hole 207, after removing the protective layer 350 and the oxide region 316, one end of each suspension region 210 can be separated from the composite substrate 310, making the end of each suspension region 210 adjacent to the through-hole 207 a free end (FE). On the other hand, the other end of the suspension region 210 remains connected to the composite substrate 310, becoming the anchor end (AE) of the suspension region 210, such as... Figures 9 and 10 As shown. In this configuration, each suspension region 210 can be suspended above the composite substrate 310. When the suspension structure within each suspension region 210 receives sound waves or electrical signals, it generates corresponding vibrations. Furthermore, the suspension structure is adjusted by the mass block so that the suspension structure can have a resonant frequency that matches the desired audio range.

[0079] Furthermore, compared to the size of each suspension region 210, each of the mass blocks has a relatively small size. For example, the coverage area of ​​each mass block can be reduced by about 10% to 90% relative to the coverage area of ​​each suspension region 210, preferably by about 25% to 50%. In this embodiment, each of the mass blocks is preferably disposed on the half portion 210f of the suspension region 210 adjacent to the free end FE, such as... Figure 9 As shown. Therefore, each of the mass blocks can effectively improve the sensing accuracy of the microelectromechanical device 300 without causing rigid impact to the suspension structure. In a preferred embodiment, each of the mass blocks, for example, only partially overlaps half 210f of the suspension region 210 adjacent to the free end FE, and does not overlap half 210a of the suspension region 210 adjacent to the anchor end AE, but is not limited thereto. With this configuration, the microelectromechanical device 300 of this embodiment can serve as a microelectromechanical system accelerator (MEMS piezoelectric accelerometer device), and thus can be applied to wireless Bluetooth headsets to assist the microphone's voice vibration.

[0080] The main feature of the fabrication process of the microelectromechanical device 300 in this embodiment is the formation of trenches 315a in the composite substrate 310, followed by oxidation of the gates 315b between the trenches 315a, thereby forming an oxide region 316 and simultaneously defining a mass block region 315c within the second semiconductor layer 315. With this setup, the mass block (i.e., mass block region 315c) and cavity 320 of the microelectromechanical device 300 can be conveniently and precisely formed by removing the oxide region 316 in a subsequent process. Thus, the cavity 320 can have an opening of uniform size d1, and the size of the mass block and its position within the cavity 320 can also be accurately defined simultaneously. Those skilled in the art will readily understand that although in the foregoing embodiment the formation of the trenches 315a or the oxide region 316 is performed after the formation of the silicon-coated insulating substrate, other variations or process sequences are possible in actual fabrication processes. For example, in another embodiment (not shown), it is also possible to form a plurality of trenches on one of the two semiconductor layers constituting the silicon-coated insulating substrate (e.g., forming trenches such as...). Figure 3 The trench 315a (not shown) can then be oxidized between these trenches before or after bonding the two semiconductor layers. Subsequently, thinning one of the two semiconductor layers can still achieve the desired result. Figure 5 A similar structure as shown.

[0081] Furthermore, although the aforementioned microelectromechanical device 300 manufacturing process is described as an embodiment forming three suspension regions 210, such that all three suspension regions 210 extend in the same direction (e.g., the y-direction, as shown in the image), Figure 9 As shown in the figure, the suspension area 210 is connected to each of the corresponding mass blocks, but the present invention is not limited to the aforementioned method. In another embodiment, the number and arrangement of the mass blocks can be further adjusted according to the sensing accuracy required by the microelectromechanical device. For example, as Figure 11 As shown, a smaller number of suspension regions 210 and mass blocks can be selected according to the aforementioned formula (I) to obtain different detection signals. Furthermore, the suspension regions 210 can also be selected to extend in another direction, such as... Figure 11 As shown in the x-direction, signals from different directions can be sensed. In another embodiment, suspension areas (not shown) extending in different directions can be further formed, thereby enabling the sensing of signals from multiple different directions to further meet actual product requirements.

[0082] The following description will focus on other embodiments or variations of the microelectromechanical device and its formation method of the present invention. For the sake of simplicity, the following description will focus on the differences between the embodiments, without repeating the similarities. Furthermore, identical elements in the embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0083] Please refer to Figure 12 The diagram illustrates a microelectromechanical device 500 according to a second embodiment of the present invention. The structure of the microelectromechanical device 500 in this embodiment is generally similar to that in the previous embodiments, and will not be described again here. The difference between this embodiment and the previous embodiments is that an additional capping layer 450 is formed on the piezoelectric stack structure 200 to form a vacuum cavity within the microelectromechanical device 500.

[0084] Specifically, the capping layer 450 includes, for example, a rigid substrate material such as silicon or glass, and is bonded to the front side of the composite substrate 310, such that a cavity 450a can be formed between the capping layer 450 and the piezoelectric stacked structure 200 disposed above the composite substrate 310. Preferably, the cavity 450a may have a thickness T4, approximately 5 micrometers to 20 micrometers, and the cavity 450a can be set in a vacuum state to further apply it to a high-gravity environment. It should be noted that the capping layer 450 is bonded to the connecting pad 211 on the piezoelectric stacked structure 200 by a protruding structure thereon. In one embodiment, the protruding structure may be disposed around the peripheral area of ​​the capping layer 450, so the protruding structure may appear as a ring when viewed from a top view (not shown), and as... Figure 12 The side sectional view shown reveals two separated protruding structures. These protruding structures may include an oxide layer 370 and a capping layer 390 covering the oxide layer 370. The oxide layer 370 may include silicon monoxide or silicon dioxide, and the capping layer 390 may include a metallic material, such as aluminum germanium (AlGe), but is not limited thereto. Preferably, the thickness of the oxide layer 370 may be approximately 2 micrometers to 10 micrometers, allowing sufficient space for the cavity 450a formed within the microelectromechanical device 500.

[0085] Thus, the microelectromechanical device 500 of the second embodiment of the present invention can be completed. The microelectromechanical device 500 includes a piezoelectric stack structure 200, a cavity 320, a mass block disposed inside the cavity 320 (i.e., the mass block region 315c of the second semiconductor layer 315), and a capping layer 450. In this way, an additional vacuum cavity 450a can be formed between the capping layer 450 and the piezoelectric stack structure 200, so that the microelectromechanical device 500 can be applied as a high-gravity accelerometer (e.g., about 10g to 300g) under a high-impact condition, thereby achieving better sensing performance.

[0086] Overall, one of the objectives of this invention is to provide a microelectromechanical device (MEMS) having a miniaturized and precisely sized mass, such that the coverage area of ​​the mass is reduced by approximately 10% to 90%, preferably by approximately 25% to 50%, relative to the coverage area of ​​a corresponding suspension region. However, this is not a limitation. Furthermore, one or more mass blocks can be optionally positioned in the MEMS to correspond to one or more suspension regions, allowing each mass block to be connected to its respective suspension region, thereby further adjusting the vibration frequency. With this configuration, the MEMS of this invention can function as a MEMS accelerator and can be applied to wireless Bluetooth headsets to assist microphone voice vibration.

[0087] Another object of the present invention is to provide a process for manufacturing a microelectromechanical device (MEMS). First, multiple trenches are formed in a composite substrate, and the gates between the trenches are oxidized to define the region and size of a mass block. Then, in subsequent processes, a mass block with accurate position and size, i.e., a cavity with uniform opening size, can be obtained simultaneously by simply removing the oxidized regions. This allows the formed MEMS to have improved functionality and performance.

[0088] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A microelectromechanical device, characterized in that, Include: A composite substrate comprising a first semiconductor layer, an adhesive layer, and a second semiconductor layer stacked sequentially from bottom to top; A cavity is disposed within the first semiconductor layer, the cavity extending from the second semiconductor layer into the first semiconductor layer but not penetrating the first semiconductor layer; A piezoelectric stack structure is disposed on the composite substrate, the piezoelectric stack structure including a suspension region located on the cavity, the suspension region having a free end; as well as A mass block is disposed within the cavity and connected to the piezoelectric stack structure, and is disposed on the half of the suspension region adjacent to the free end, laterally separated from the free end of the suspension region.

2. The microelectromechanical device as described in claim 1, characterized in that, The material of the mass block is the same as that of the second semiconductor layer.

3. The microelectromechanical device as described in claim 2, characterized in that, The thickness of the mass block is the same as the thickness of the second semiconductor layer.

4. The microelectromechanical device as described in claim 1, characterized in that, The coverage area of ​​the mass block is reduced by 10% to 90% compared to the coverage area of ​​the suspension region.

5. The microelectromechanical device as described in claim 1, characterized in that, It also includes an insulating layer disposed between the second semiconductor layer and the piezoelectric stack structure.

6. The microelectromechanical device as described in claim 5, characterized in that, The piezoelectric stack structure further includes: A metal layer is disposed on the insulating layer; A first piezoelectric layer is disposed on the metal layer; and A second metal layer is disposed on the first piezoelectric layer.

7. The microelectromechanical device as claimed in claim 1, characterized in that, It also includes a capping layer disposed on the piezoelectric stack structure, wherein a vacuum cavity is disposed between the capping layer and the piezoelectric stack structure.

8. The microelectromechanical device as described in claim 7, characterized in that, The capping layer is connected to the piezoelectric stack structure via a protruding structure.

9. The microelectromechanical device as claimed in claim 1, characterized in that, The piezoelectric stack structure includes a plurality of the suspension regions, and a plurality of the mass blocks are disposed within the cavity to connect the suspension regions.

10. A method for forming a microelectromechanical device, characterized in that, Include: A composite substrate is provided, the composite substrate comprising a first semiconductor layer, an adhesive layer and a second semiconductor layer stacked sequentially from bottom to top; A cavity is formed within the first semiconductor layer, the cavity extending from the second semiconductor layer into the first semiconductor layer but not penetrating the first semiconductor layer; A piezoelectric stack structure is formed on the composite substrate, the piezoelectric stack structure including a suspension region located above the cavity, the suspension region having a free end; as well as A mass block is formed within the cavity, the mass block is connected to the piezoelectric stack structure, and is disposed on the half of the suspension region adjacent to the free end, laterally separated from the free end of the suspension region.

11. The method for forming a microelectromechanical device as described in claim 10, characterized in that, Also includes: A plurality of trenches are formed within the second semiconductor layer to define a plurality of gates and the mass block between the trenches; The gate is oxidized to form an oxidized region, wherein the oxidized region surrounds the mass block; as well as The oxidized region is removed to form a portion of the cavity, wherein the mass block is connected to the piezoelectric stack structure.

12. The method for forming a microelectromechanical device as claimed in claim 11, characterized in that, The piezoelectric stack structure is formed after the oxide region is formed, and the piezoelectric stack structure is formed on the oxide region.

13. The method for forming a microelectromechanical device as claimed in claim 11, characterized in that, Also includes: Before the piezoelectric stack structure is formed, an insulating layer is formed on one surface of the second semiconductor layer, the insulating layer being disposed between the oxide region and the mass block; as well as After the piezoelectric stack structure is formed, the insulating layer is removed to partially expose one bottom surface of the piezoelectric stack structure.

14. The method for forming a microelectromechanical device as described in claim 13, characterized in that, The insulating layer is removed when the oxidized region is removed.

15. The method for forming a microelectromechanical device as described in claim 13, characterized in that, Also includes: During the formation of the piezoelectric stack structure, an initial cavity is formed within the first semiconductor layer, and an insulating layer is formed on the surface of the first semiconductor layer and the initial cavity.

16. The method for forming a microelectromechanical device as claimed in claim 11, characterized in that, The trench is formed between two opposing surfaces of the second semiconductor layer.

17. The method for forming a microelectromechanical device as claimed in claim 10, characterized in that, The mass block is formed from a portion of the second semiconductor layer.

18. The method for forming a microelectromechanical device as claimed in claim 10, characterized in that, The coverage area of ​​the mass block is 10% to 90% less than the coverage area of ​​the suspension area.

19. The method for forming a microelectromechanical device as claimed in claim 10, characterized in that, Also includes: A capping layer is formed on the piezoelectric stacked structure, wherein a vacuum cavity is disposed between the capping layer and the piezoelectric stacked structure.

20. The method for forming a microelectromechanical device as claimed in claim 10, characterized in that, Also includes: A plurality of suspension regions are formed within the piezoelectric stack structure, the suspension regions extending in the same direction; and A plurality of mass blocks are formed within the cavity to connect to each of the suspension regions.

Images