Test control circuit and test control method for a processor

Abstract

The present disclosure provides a test control circuit and a test control method for a processor. The processor includes a plurality of test access ports connected in parallel between a signal input end and a signal output end. The signal input end is directly connected to a test signal end to receive a test signal and control whether the plurality of test access ports turn on to input the test signal. The test control circuit includes: a logic selection circuit connected to the signal input end, the signal output end, and the test signal end; a port selection circuit connected to the logic selection circuit. The logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal end. The port selection circuit performs port selection in response to the first selection signal and outputs a second selection signal. The signal input end and the signal output end control one or more of the plurality of test access ports to turn on to input the test signal and turn on to output test data based on the second selection signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of processor technologies, and more particularly to a test control circuit and a test control method for a processor. Background Art

[0002] The test access port (TAP) developed based on the Joint Test Action Group (JTAG) is mainly used to detect and debug the functions inside a processor. It is commonly present in current chips, especially essential in large-scale system-on-chip (SoC) chips. Generally, there are multiple JTAG TAPs in a chip to complete the test processes for different functional modules. In addition, during the manufacturing process of a chip, different manufacturers usually produce different functional modules that are then combined to form the final chip. Therefore, the manufacturers configure corresponding JTAG TAPs for the produced functional modules. This makes the layout of the connection methods of the multiple JTAG TAPs included in the chip and the design of the test process extremely important. Summary of the Invention

[0003] Embodiments of the present disclosure provide a test control circuit and a test control method for a processor, which are used to provide a reasonable layout for the connection methods of multiple test access ports (TAPs) included in the processor, improve the automation level of chip testing, and reduce the difficulty of using test cases.

[0004] According to an aspect of the present disclosure, there is provided a test control circuit for a processor. The processor includes multiple test access ports configured to be connected in parallel between a signal input end and a signal output end. Among them, the signal input end is directly connected to a test signal end to receive a test signal from the test signal end and control whether to enable the input of the test signal to the multiple test access ports. The signal output end controls whether to enable the output of test data from the multiple test access ports. The test control circuit includes: a logic selection circuit configured to be connected to the signal input end, the signal output end, and the test signal end; and a port selection circuit configured to be connected to the logic selection circuit. Among them, the logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal end. The port selection circuit performs port selection in response to the first selection signal and outputs a second selection signal. Among them, the signal input end and the signal output end control one or more of the multiple test access ports to enable the input of the test signal and enable the output of the test data based on the second selection signal.

[0005] According to some embodiments of the present disclosure, the multiple test access ports are ports compliant with the Joint Test Action Group (JTAG) specification, and the test signals include a test clock signal, a test mode selection signal, a test data input signal, and a test reset signal.

[0006] According to some embodiments of the present disclosure, the logic selection circuit includes a state machine and a monitoring circuit. The state machine is configured to receive the test mode selection signal, the test clock signal, and the test reset signal, and the monitoring circuit is configured to receive the test data input signal, the test clock signal, and the test reset signal. Wherein, the logic selection circuit outputs a first selection signal to the port selection circuit based on the test signals received from the test signal terminals, including: the state machine determines that the multiple test access ports are in an idle state based on the test mode selection signal and outputs an idle signal to the monitoring circuit; the monitoring circuit receives the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal, and when it is determined that the verification signal is met, outputs the first selection signal to the port selection circuit.

[0007] According to some embodiments of the present disclosure, the monitoring circuit includes a first register circuit, a controller, and a second register circuit. The first register circuit is configured to receive the idle signal, the test data input signal, the test clock signal, and the test reset signal. The controller is configured to be connected to the first register circuit and the second register circuit and stores the verification signal. The second register circuit is connected to the port selection circuit. Wherein, the monitoring circuit receives the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal, and when it is determined that the verification signal is met, the monitoring circuit outputs the first selection signal to the port selection circuit, including: the first register circuit receives the test data input signal in response to the idle signal; the controller determines whether the test data input signal received by the first register circuit meets the verification signal, and when it is determined that the verification signal is met, outputs an enable signal to the second register circuit; and the second register circuit outputs the first selection signal to the port selection circuit in response to the enable signal.

[0008] According to some embodiments of the present disclosure, the first register circuit is a shift register composed of multiple registers.

[0009] According to some embodiments of the present disclosure, the port selection circuit is further configured to be connected to a signal input terminal and a signal output terminal. Wherein, the port selection circuit performs port selection and outputs a second selection signal in response to the first selection signal, including: the port selection circuit enables the input test mode selection signal in response to the first selection signal; the port selection circuit performs port selection based on the test mode selection signal and generates a second selection signal.

[0010] According to some embodiments of the present disclosure, a plurality of test access ports are further configured to be connected to the interface under test in the processor, so as to test the interface under test connected thereto based on the test signal received from the signal input end and output test data.

[0011] According to some embodiments of the present disclosure, the interface under test includes a peripheral component interconnect high-speed interface and a memory interface.

[0012] According to another aspect of the present disclosure, there is provided a test control method for a processor, which is applicable to a test control circuit. The processor includes a plurality of test access ports, and the plurality of test access ports are configured to be connected in parallel between a signal input end and a signal output end. The signal input end is directly connected to a test signal end to receive a test signal from the test signal end and control whether the plurality of test access ports are turned on to input the test signal. The signal output end controls whether the plurality of test access ports are turned on to output test data. The test control circuit includes: a logic selection circuit configured to be connected to the signal input end, the signal output end, and the test signal end; and a port selection circuit configured to be connected to the logic selection circuit. The test control method includes: using the logic selection circuit to output a first selection signal to the port selection circuit based on the test signal received from the test signal end; and using the port selection circuit to perform port selection and output a second selection signal in response to the first selection signal, wherein the signal input end and the signal output end control one or more of the plurality of test access ports to be turned on to input the test signal and turned on to output test data based on the second selection signal.

[0013] According to some embodiments of the present disclosure, the plurality of test access ports are ports compliant with the Joint Test Action Group specification, and the test signal includes a test clock signal, a test mode selection signal, a test data input signal, and a test reset signal.

[0014] According to some embodiments of the present disclosure, the logic selection circuit includes a state machine and a monitoring circuit. The state machine is configured to receive the test mode selection signal, the test clock signal, and the test reset signal. The monitoring circuit is configured to receive the test data input signal, the test clock signal, and the test reset signal. Wherein, outputting the first selection signal to the port selection circuit based on the test signal received from the test signal end includes: using the state machine to determine that the plurality of test access ports are in an idle state based on the test mode selection signal and output an idle signal to the monitoring circuit; using the monitoring circuit to receive the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal, and outputting the first selection signal to the port selection circuit when it is determined that the verification signal is met.

[0015] According to some embodiments of the present disclosure, the monitoring circuit includes a first register circuit, a controller, and a second register circuit. The first register circuit is configured to receive an idle signal, a test data input signal, a test clock signal, and a test reset signal. The controller is configured to be connected to the first register circuit and the second register circuit and stores a verification signal. The second register circuit is connected to a port selection circuit. Wherein, in response to the idle signal, the test data input signal is received to determine whether the test data input signal meets the preset verification signal. In the case where it is determined that the verification signal is met, outputting a first selection signal to the port selection circuit includes: using the first register circuit to receive the test data input signal in response to the idle signal; using the controller to determine whether the test data input signal received by the first register circuit meets the verification signal. In the case where it is determined that the verification signal is met, an enable signal is output to the second register circuit; and using the second register circuit to output a first selection signal to the port selection circuit in response to the enable signal.

[0016] According to some embodiments of the present disclosure, the first register circuit is a shift register composed of multiple registers.

[0017] According to some embodiments of the present disclosure, the port selection circuit is further configured to be connected to a signal input end and a signal output end. Wherein, in response to the first selection signal, port selection is performed and a second selection signal is output, including: using the port selection circuit to enable an input test mode selection signal in response to the first selection signal; using the port selection circuit to perform port selection based on the test mode selection signal and generate a second selection signal.

[0018] According to some embodiments of the present disclosure, multiple test access ports are further configured to be connected to a device under test interface in a processor. The test control method further includes: using the multiple test access ports to test the device under test interface connected thereto based on a test signal received from the signal input end and outputting test data.

[0019] According to some embodiments of the present disclosure, the device under test interface includes a peripheral component interconnect high-speed interface and a memory interface.

[0020] Using the test control circuit and test control method for a processor provided by the embodiments of the present disclosure, a test topology can be implemented, where multiple test access ports (TAPs) are configured to be connected in parallel between a signal input end and a signal output end, and the signal input end is directly connected to a test signal end to directly receive a test signal from the test signal end. Further, a logical selection circuit and a port selection circuit provided for multiple TAPs in the processor are used to select between the multiple TAPs, so that the selected TAP can perform a test process based on the received test signal and output test data. Through the above test control circuit and test control method, manual participation in TAP selection during the software debugging process can be avoided, the automation level of chip testing is improved, and since the signal input end is directly connected to the test signal end, the difficulty of using test cases is reduced. In addition, the test control circuit provided according to the embodiments of the present disclosure can also reduce the board-level design complexity and save board-level resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1A FIG. shows a connection topology diagram for multiple TAPs in the related art;

[0023] Figure 1B FIG. shows another connection topology diagram for multiple TAPs in the related art;

[0024] Figure 2 FIG. shows a connection topology diagram for multiple TAPs according to some embodiments of the present disclosure;

[0025] Figure 3 FIG. shows another connection topology diagram for multiple TAPs according to some embodiments of the present disclosure;

[0026] Figure 4 FIG. shows a circuit schematic diagram of a logical selection circuit and a port selection circuit according to some embodiments of the present disclosure;

[0027] Figure 5 FIG. shows a detailed circuit diagram of a logical selection circuit and a port selection circuit according to some embodiments of the present disclosure;

[0028] Figure 6 FIG. shows a flowchart of a test control method for a processor according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0030] In addition, as shown in the present disclosure and the claims, unless the context clearly indicates an exception, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include the plural. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, words such as "comprising" or "including" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0031] The test access port TAP based on JTAG is ubiquitous in chips, especially essential in SoCs. Generally, there are multiple JTAG TAPs in a chip to complete the test processes for different functional modules. The test functions of JTAG are in two aspects. On the one hand, it is used to detect the electrical characteristics of the chip, and on the other hand, it is used to debug the peripheral devices of the chip. JTAG realizes the test process by defining the test access port TAP (Test Access Port) inside the chip. Specifically, a dedicated JTAG test tool is used to detect and debug the internal nodes of the chip. There is a standard IEEE 1149.1 for JTAG, in which the registers are divided into a data register (Data Register, DR) and an instruction register (Instruction Register, IR). The instruction register IR can be used to control the data register DR, such as selecting a target scan chain. Specifically, the test access port TAP can be implemented as a general-purpose port, and through the test access port TAP, the data register and the instruction register provided by the chip can be accessed. For example, the TAP may include devices such as a state machine and registers.

[0032] The standard IEEE1149.1 (which can also be expressed as the JTAG specification) stipulates some standard test signals for the Test Access Port (TAP). For example, the Test Mode Select (TMS) signal is used to control the state transition of the state machine of the Test Access Port (TAP); the Test Clock (TCK) signal; the Test Data Input (TDI) signal; and the Test Reset (TRST) signal, which is used to reset the Test Access Port (TAP). In addition, the standard IEEE1149.1 also stipulates the Test Data Output (TDO) signal, that is, the output test signal. Moreover, the standard IEEE1149.1 also stipulates some other signals, which will not be listed one by one here.

[0033] During the test process, the Test Access Port (TAP) determines whether to be enabled based on the received Test Mode Select (TMS) signal. That is, the TMS signal is used to implement the selection process for the Test Access Port (TAP). The registers in the selected Test Access Port (TAP) will be able to receive test signals (which can also be called test data, such as test cases) from the Test Data Input (TDI) terminal, and output the test results via the Test Data Output (TDO) terminal. For the sake of description, in this article, both the data input terminal and the signal input via this Test Data Input terminal are represented as TDI, and both the Test Data Output terminal and the signal output via this Test Data Output terminal are represented as TDO.

[0034] As mentioned above, during the production and manufacturing process of a chip, usually multiple manufacturers produce different functional modules and form the final chip. That is, there may be multiple manufacturers for a chip, and each manufacturer configures its own JTAG TAP for the produced functional module and provides a large number of test cases for the functional module. This makes the connection method layout and test process design for the multiple JTAG TAPs included in the chip particularly important.

[0035] As an example, Figure 1A shows the connection topology diagram for multiple Test Access Ports (TAPs) in the related art. In Figure 1A , N Test Access Ports (TAPs) are connected together in series. Each Test Access Port (TAP) is directly connected to the Test Clock (TCK) signal, the Test Mode Select (TMS) signal, and the Test Reset (TRST) signal. Moreover, the Test Data Input (TDI) terminal and the Test Data Output (TDO) terminal are respectively connected to the head and the tail of the N Test Access Ports (TAPs).

[0036] For a test access port TAP gated based on TMS, for example, test access port TAP 2 will receive a test signal from TDI to perform a test process on the chip and output test results via TDO. After the test process is completed, the gated test access port TAP 2 will enter an idle state until it is gated again based on TMS. It can be seen that Figure 1A The shown topology is not conducive to the requirements of efficient chip testing. As the number of test access ports TAP increases, the length of the test chain will increase accordingly, resulting in an increase in the detection or debugging time, thereby reducing the test speed, which is particularly disadvantageous for the testing of large-scale chips such as SoCs.

[0037] In the related art, there is also Figure 1B A topology designed in the form of a daisy chain as shown. In such a topology, multiple test access ports TAP are connected together in parallel. As Figure 1B shown, test access ports TAP 1 to TAP 5 are connected in parallel between the signal input terminal IN and the signal output terminal OUT. The signal input terminal IN is used to control whether to enable multiple test access ports TAP to input test signals, and the signal output terminal OUT is used to control whether to enable multiple test access ports TAP to output test data (for example, test results). In Figure 1B the example, the signal input terminal IN and the signal output terminal OUT can be gated to select which TAP based on the signal output by MST TAP. For example, TAP1 is gated to perform the test process. According to some embodiments of the present disclosure, the signal input terminal IN and the signal output terminal OUT can implement a multiplexer (MUX) to achieve the above gating process. In Figure 1B , only the gated test access port TAP can receive input data via IN and OUT and output test results.

[0038] For Figure 1B the multiple TAPs connected in parallel in Figure 1B , in order to gate the required test access port TAP based on TMS, that is, to enable the test access port TAP that needs to be tested currently, Figure 1B a main test access port (Master TAP, MST TAP) for gating the test access port TAP is provided in the topology. MST TAP is connected to the test signal terminal (such as Figure 1BThe signals shown in [description] include those between TMS, TRST, TDI, and TCK) and IN. During implementation, the MST TAP first receives the test signals, then determines the TAPs that need to be strobed based on the test signals, and generates output signals. Specifically, the MST TAP will output the strobe signal TAP_SEL via its output port MST_TDO and transmit it to IN and OUT, so that the corresponding TAP (such as TAP 2) can be switched to the enabled state and receive and output data via IN and OUT, while the other non-strobed TAPs will remain in the idle state, and the TAPs in the idle state do not receive or output data.

[0039] Reference Figure 1B , since the test signals need to first enter the MST TAP to generate the strobe signal TAP_SEL before entering each TAP, this increases the clock cycle of the test clock signal due to the MST TAP, which is not conducive to testing. As described above, the test cases provided by the manufacturer for the functional modules usually do not take into account the clock delay caused by the MST TAP. If the chip tester hopes to use the provided test cases for testing, additional work is required to modify the test cases, and the test pattern and program control will become more complex.

[0040] To solve the above technical problems in the related art, some embodiments of the present disclosure provide a test control circuit for a processor. The processor has multiple test access ports TAPs for testing. The test control circuit is used to provide a reasonable layout for the topological structure of the multiple test access ports TAPs included in the processor, improve the automation level of chip testing, and reduce the difficulty of using test cases. It can be understood that the processor involved herein generally refers to various types of integrated circuit structures, such as microprocessors, central processing units (CPUs), graphics processing units (GPUs), general-purpose computing on graphics processing units (GPGPUs), system-on-chips (SoCs), etc., which are not limited herein. Unless otherwise defined, all terms used herein have the same meaning commonly understood by those of ordinary skill in the art to which the present disclosure belongs.

[0041] The test control circuit provided by some embodiments of the present disclosure can implement a test topology, in which multiple test access ports (TAPs) are configured to be connected in parallel between a signal input end and a signal output end, and the signal input end is directly connected to a test signal end to directly receive a test signal from the test signal end. Further, a logic selection circuit and a port selection circuit provided for multiple TAPs in a processor are used to select between the multiple TAPs, so that the selected TAP can perform a test process based on the received test signal and output test data. Through the above test control circuit, manual participation in TAP selection during the software debugging process can be avoided, the automation level of chip testing is improved, and since the signal input end is directly connected to the test signal end, the difficulty of using test cases is reduced. In addition, the test control circuit provided according to the embodiments of the present disclosure can also reduce the board-level design complexity and save board-level resources.

[0042] The connection manner between the test control circuit and the TAP topology and the specific circuit structure according to some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0043] Figure 2 A connection topology diagram for multiple TAPs according to some embodiments of the present disclosure is shown, as Figure 2 shown, multiple test access ports (TAPs) are configured to be connected in parallel between a signal input end IN and a signal output end OUT, and the signal input end IN is directly connected to a test signal end JTAG_* to directly receive a test signal from the test signal end JTAG_*, where the test signal can be the above-mentioned TMS, TDI, CLK, and TRST, etc. The signal input end IN is used to control whether the multiple test access ports (TAPs) turn on the input test signal based on the received selection signal, and the signal output end OUT is used to control whether the multiple test access ports (TAPs) turn on the output test data based on the received selection signal. Only the selected TAP can receive and output data via IN and OUT, and other unselected TAPs will be in an idle state. In some embodiments according to the present disclosure, a logic selection circuit and a port selection circuit are provided, where the logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal end, and the port selection circuit performs port selection in response to the first selection signal and outputs a second selection signal, so that the signal input end IN and the signal output end OUT can control one or more of the multiple test access ports to turn on the input test signal and turn on the output test data based on the second selection signal.

[0044] Compared with Figure 1BThe topological connection method shown does not require an additional gating circuit (MST TAP) to be arranged between IN and JTAG_*, so that the test signal can be directly input to the TAP for testing via IN, avoiding the clock delay generated in the implementation method shown in Figure 1B . Therefore, the test efficiency can be improved, and the test cases do not need to be adjusted according to the structure of the MST TAP, which reduces the difficulty of using the test cases.

[0045] Next, as shown in Figure 2 , in order to implement the gating of multiple TAPs, that is, to generate the gating signal TAP_SEL, a test control circuit is provided according to some embodiments of the present disclosure. Specifically, according to the functional distinction, the test control circuit is represented as including a logic selection circuit and a port selection circuit. It can be understood that the logic selection circuit and the port selection circuit in the test control circuit according to the embodiments of the present disclosure implement the function of gating the TAP as a whole.

[0046] Next, referring to Figure 2 , the logic selection circuit is configured to be connected to the signal input terminal IN, the signal output terminal OUT, and the test signal terminal JTAG_*. The port selection circuit is configured to be connected to the logic selection circuit. According to some embodiments of the present disclosure, the logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal terminal JTAG_*, and the port selection circuit performs port selection and outputs a second selection signal in response to the first selection signal, wherein the signal input terminal IN and the signal output terminal OUT control one or more of the multiple test access ports to turn on the input of the test signal and turn on the output of the test data based on the second selection signal.

[0047] According to some embodiments of the present disclosure, the above-mentioned multiple test access ports TAP are further configured to be connected to the device under test interface in the processor to test the device under test interface connected thereto based on the test signal received from the signal input terminal and output the test data. As an example, the device under test interface may include, for example, a peripheral component interconnect express interface (PCIe), a memory interface (DDR), that is, the functions of PCIe, DDR, or other nodes inside the processor are detected and debugged via the TAP.

[0048] By using the signal processing process between the above-mentioned logic selection circuit and the port selection circuit, the corresponding TAP can be automatically selected according to the input test signal for the corresponding test process, thereby avoiding manual participation in TAP selection during the software debugging process and improving the automation level of chip testing. In addition, in the above implementation of the logic selection circuit and the port selection circuit, only the test signal compliant with the JTAG standard is required to achieve the function of selecting the TAP, and no additional signal needs to be designed. The circuit structure is simple and easy to implement.

[0049] As an implementation, the above port selection circuit can be implemented as a TAP. Specifically, Figure 3 shows another connection topology for multiple TAPs. In Figure 3 's implementation, the port selection circuit is connected between IN and OUT in the form of a TAP and is connected in parallel with other TAPs. In Figure 3 , the test signal of the test signal terminal JTAG_* is first transmitted to the logic selection circuit, so that the logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal. For example, it can be Figure 3 TAP_SEL shown in, that is, in this process, the logic selection circuit first generates a first selection signal based on the test signal to enable the port selection circuit implemented as a TAP, so that the port selection TAP can receive the test signal via IN, and enable the detection data register (Test Data Register, TDR) in the port selection TAP to perform data processing for port selection and output a second selection signal. It can be understood that in other implementation manners, the port selection circuit can also be implemented as other circuit structures, which are not limited herein.

[0050] Regarding the specific implementation process of the logic selection circuit, the first selection signal, the port selection circuit, and the second selection signal, it will be described in detail in combination with Figure 4 and Figure 5 in the circuit diagram.

[0051] Specifically, Figure 4 shows a circuit schematic diagram of the logic selection circuit and the port selection circuit according to some embodiments of the present disclosure. Figure 5 shows a detailed circuit diagram of the logic selection circuit and the port selection circuit according to some embodiments of the present disclosure.

[0052] As Figure 4As shown, the logic selection circuit (TAP_SELECT_LOGIC) may include a finite state machine (FSM) and a monitor circuit (MONITOR). The FSM is configured to receive a test mode selection signal TMS, a test clock signal TCK, and a test reset signal TRST. The monitor circuit MONITOR is configured to receive a test data input signal TDI, a test clock signal TCK, and a test reset signal TRST.

[0053] According to some embodiments of the present disclosure, the above-mentioned logic selection circuit outputs a first selection signal to the port selection circuit based on test signals received from test signal terminals, including: the FSM determines that multiple test access ports TAPs are in an idle state based on the test mode selection signal TMS, and outputs an idle signal to the monitor circuit MONITOR. As an example, the FSM can first determine, based on the TMS signal, whether, for example Figure 3 TAP 1 to TAP 5 among them are in an idle state. If it is determined that they are in an idle state, an idle signal IDLE is output to the monitor circuit MONITOR.

[0054] According to some embodiments of the present disclosure, the monitor circuit MONITOR receives the test data input signal TDI in response to the idle signal IDLE to determine whether the test data input signal TDI meets a preset verification signal. When it is determined that the verification signal is met, the monitor circuit MONITOR outputs a first selection signal to the port selection circuit. In Figure 3 the example of, this first selection signal can select the port selection TAP, that is, cause the state machine of the port selection TAP to perform a jump to start receiving test signals from IN, and determine the TAP to be selected for testing based on the received test signals, and output a second selection signal.

[0055] According to some embodiments of the present disclosure, the monitor circuit may specifically include a first register circuit, a controller, and a second register circuit. According to some embodiments of the present disclosure, the first register circuit is configured to receive an idle signal, a test data input signal, a test clock signal, and a test reset signal; the controller is configured to be connected to the first register circuit and the second register circuit and stores the above-mentioned verification signal; the second register circuit is connected to the port selection circuit. The above-mentioned first register circuit may be a shift register composed of multiple registers for receiving TDI. For example, the shift register can be set according to the number of bits of the pre-defined verification signal.

[0056] According to some embodiments of the present disclosure, the monitoring circuit receives a test data input signal in response to an idle signal to determine whether the test data input signal meets a preset verification signal. When it is determined that the verification signal is met, the monitoring circuit outputs a first selection signal to the port selection circuit, including: the first register circuit receives the test data input signal in response to the idle signal; the controller determines whether the test data input signal received by the first register circuit meets the verification signal, and when it is determined that the verification signal is met, outputs an enabling signal to the second register circuit; and the second register circuit outputs the first selection signal to the port selection circuit in response to the enabling signal.

[0057] According to some embodiments of the present disclosure, the port selection circuit is further configured to be connected to a signal input end and a signal output end. Wherein, the port selection circuit performs port selection and outputs a second selection signal in response to the first selection signal, including: the port selection circuit enables an input test mode selection signal in response to the first selection signal; the port selection circuit performs port selection based on the test mode selection signal and generates the second selection signal.

[0058] Figure 5 The specific circuit structure of the state machine FSM, the monitoring circuit MONITOR, and the connection manner with the port selection TAP are shown. The overall implementation process of the test monitoring circuit as some embodiments of the present disclosure will be described below in conjunction with Figure 5 Describe the overall implementation process of the test monitoring circuit as some embodiments of the present disclosure.

[0059] As Figure 5 shown, the logic selection circuit includes a state machine FSM and a monitoring circuit. Among them, the monitoring circuit may include a first register circuit, a controller, and a second register circuit. First, the state machine FSM receives a test signal from the test signal terminal JTAG_*. According to some embodiments of the present disclosure, the test signal includes a test mode selection signal TMS, a test clock signal TCK, and a test reset signal TRST that meet the JTAG specification. The state machine FSM can, for example, determine whether the TAP is in an idle state based on TMS. If it is determined that the TAP is in an idle state, it outputs an idle signal IDLE to the first register circuit in the monitoring circuit.

[0060] As Figure 5 shown, the first register circuit is configured to receive the idle signal IDLE output by the state machine FSM, and also receives a test data input signal TDI, a test clock signal TCK, and a test reset signal TRST. When the FSM determines based on TMS that the connected TAP is in an idle state, it will output the idle signal IDLE to the first register circuit, and the first register circuit receives TDI in response to the idle signal IDLE. As Figure 5As shown, the first register circuit consists of a group of shift registers and a logic gate unit. First, after the AND gate in the first register circuit receives the idle signal IDLE, the shift register can receive the TDI signal. Then, the controller determines whether the TDI signal received by the shift register is consistent with the pre-stored verification signal. As an example, the verification signal can be a set of data for comparison with the received TDI signal. If they are consistent, the controller outputs an enable signal to the register in the second register circuit.

[0061] As Figure 5 shown, the enable signal is transmitted to the reset terminal of the register in the second register circuit, causing the register to output a first selection signal in response to the enable signal. Specifically, when the port selection circuit is implemented as Figure 3 shown port selection TAP, this first selection signal can be understood as the strobe signal TAP_SEL for this port selection TAP. That is, the strobe signal TAP_SEL output by the second register circuit in response to the enable signal is used to strobe the port selection TAP, so that the port selection TAP can be in an enabled state and determine the TAP to be tested based on the received TMS. Specifically, the port selection TAP can configure the test data register TDR based on the received TMS and generate an updated strobe signal UPDATE_TAP_SEL.

[0062] As Figure 5 shown, the strobe signal UPDATE_TAP_SEL generated by the port selection TAP can be output to IN and OUT via the second register circuit, so that the TAP to be tested is converted from the idle state to the enabled state, and receives test data via IN and outputs test results via OUT.

[0063] Using the test control circuit for a processor provided by some embodiments of the present disclosure can avoid manual participation in TAP selection during software debugging, improve the automation level of chip testing, and since the signal input terminal is directly connected to the test signal terminal, this reduces the difficulty of using test cases. In addition, the test control circuit provided by the embodiments of the present disclosure can also reduce the board-level design complexity and save board-level resources.

[0064] According to another aspect of the present disclosure, a test control method for a processor is also provided. Specifically, the processor may include a plurality of test access ports TAP, and the plurality of test access ports are configured to be connected in parallel between a signal input end and a signal output end. Wherein, the signal input end is directly connected to the test signal end to receive a test signal from the test signal end and control whether to enable the input of the test signal for the plurality of test access ports based on a selection signal output by the port selection circuit, and the signal output end also controls whether to enable the output of the test data for the plurality of test access ports based on the selection signal output by the port selection circuit. According to some embodiments of the present disclosure, the plurality of test access ports TAP are ports that conform to the Joint Test Action Group JTAG specification (which may also be expressed as JTAG TAP). According to the JTAG standard, the test signal may include, for example, a test clock signal TCK, a test mode selection signal TMS, a test data input signal TDI, and a test reset signal TRST, etc.

[0065] The test control method according to some embodiments of the present disclosure is applicable to a test control circuit. The test control circuit according to some embodiments of the present disclosure includes a logic selection circuit and a port selection circuit. Wherein, the logic selection circuit is configured to be connected to the signal input end, the signal output end, and the test signal end, and the port selection circuit is configured to be connected to the logic selection circuit. The circuit structure and implementation manner of this test control circuit can be combined with the above description about Figures 2 - 5 and will not be repeated here.

[0066] To more clearly illustrate the test control method according to the embodiments of the present disclosure, Figure 6 is provided, which is used to show the flowchart of the test control method according to the embodiments of the present disclosure. The implementation process of the test control method according to the embodiments of the present disclosure will be described below in combination with Figure 6 .

[0067] As Figure 6 shown, in step S601, the logic selection circuit is used to output a first selection signal to the port selection circuit based on the test signal received from the test signal end. Then, in step S602, the port selection circuit is used to perform port selection in response to the first selection signal and output a second selection signal, wherein the signal input end and the signal output end control one or more of the plurality of test access ports to enable the input of the test signal and enable the output of the test data based on the second selection signal.

[0068] According to some embodiments of the present disclosure, the logic selection circuit includes a state machine and a monitoring circuit. The state machine is configured to receive a test mode selection signal, a test clock signal, and a test reset signal. The monitoring circuit is configured to receive a test data input signal, a test clock signal, and a test reset signal. Wherein, outputting a first selection signal to the port selection circuit based on the test signal received from the test signal terminal includes: using the state machine to determine that multiple test access ports are in an idle state based on the test mode selection signal, and outputting an idle signal to the monitoring circuit; using the monitoring circuit to receive the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal, and when it is determined that the verification signal is met, outputting the first selection signal to the port selection circuit.

[0069] According to some embodiments of the present disclosure, the monitoring circuit includes a first register circuit, a controller, and a second register circuit. The first register circuit is configured to receive an idle signal, a test data input signal, a test clock signal, and a test reset signal. The controller is configured to be connected to the first register circuit and the second register circuit and stores a verification signal. The second register circuit is connected to the port selection circuit. Wherein, receiving the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal, and when it is determined that the verification signal is met, outputting the first selection signal to the port selection circuit includes: using the first register circuit to receive the test data input signal in response to the idle signal; using the controller to determine whether the test data input signal received by the first register circuit meets the verification signal, and when it is determined that the verification signal is met, outputting an enable signal to the second register circuit; and using the second register circuit to output the first selection signal to the port selection circuit in response to the enable signal.

[0070] According to some embodiments of the present disclosure, the first register circuit is a shift register composed of multiple registers.

[0071] According to some embodiments of the present disclosure, the port selection circuit is further configured to be connected to a signal input terminal and a signal output terminal. Wherein, performing port selection and outputting a second selection signal in response to the first selection signal includes: using the port selection circuit to enable the input test mode selection signal in response to the first selection signal; and using the port selection circuit to perform port selection based on the test mode selection signal and generate a second selection signal.

[0072] According to some embodiments of the present disclosure, the multiple test access ports are further configured to be connected to the device under test interface in the processor. The test control method further includes: using the multiple test access ports to test the device under test interface connected thereto based on the test signal received from the signal input terminal and outputting test data. According to some embodiments of the present disclosure, the device under test interface includes a peripheral component interconnect high-speed interface, a memory interface.

[0073] Using the test control circuit and test control method for a processor provided by the embodiments of the present disclosure, a test topology can be implemented, where multiple test access ports (TAPs) are configured to be connected in parallel between a signal input end and a signal output end, and the signal input end is directly connected to a test signal end to directly receive a test signal from the test signal end. Further, a logical selection circuit and a port selection circuit provided for multiple TAPs in the processor are used to select between the multiple TAPs, so that the selected TAP can perform a test process based on the received test signal and output test data. Through the above test control circuit and test control method, it is possible to avoid manual participation in TAP selection during the software debugging process, improve the automation level of chip testing, and since the signal input end is directly connected to the test signal end, this reduces the difficulty of using test cases. In addition, the test control circuit provided according to the embodiments of the present disclosure can also reduce the board-level design complexity and save board-level resources.

[0074] Those skilled in the art can understand that the content disclosed in the present disclosure can have various variations and improvements. For example, the various devices or components described above can be implemented by hardware, or by software, firmware, or some or all of the combinations of the three.

[0075] Flowcharts are used in the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the steps before or after do not necessarily need to be carried out precisely in sequence. On the contrary, they can be carried out in reverse order or various steps can be processed simultaneously. At the same time, other operations can also be added to these processes.

[0076] Those of ordinary skill in the art can understand that all or part of the steps in the above methods can be instructed by a computer program to complete the relevant hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disc, etc. Optionally, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Correspondingly, the above modules / units in the embodiments can be implemented in the form of hardware or in the form of software function modules. The present disclosure is not limited to any specific form of combination of hardware and software.

[0077] The foregoing is a description of the present disclosure and should not be construed as a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily appreciate that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing is a description of the present disclosure and should not be considered limited to the particular embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A test control circuit for a processor, characterized in that, The processor includes a plurality of test access ports configured to be connected in parallel between a signal input end and a signal output end. Among them, the signal input end is directly connected to a test signal end to receive a test signal from the test signal end and control whether the plurality of test access ports are turned on to input the test signal. The signal output end controls whether the plurality of test access ports are turned on to output test data. Among them, the plurality of test access ports are ports compliant with the Joint Test Action Group specification. The test signal includes a test clock signal, a test mode selection signal, a test data input signal, and a test reset signal. The test control circuit includes: A logic selection circuit configured to be connected to the signal input end, the signal output end, and the test signal end; and A port selection circuit configured to be connected to the logic selection circuit, where The logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal end. The port selection circuit performs port selection in response to the first selection signal and outputs a second selection signal. Among them, the signal input end and the signal output end control one or more of the plurality of test access ports to be turned on to input the test signal and turned on to output test data based on the second selection signal, Among them, the logic selection circuit includes a state machine and a monitoring circuit. The state machine is configured to receive the test mode selection signal, the test clock signal, and the test reset signal. The monitoring circuit is configured to receive the test data input signal, the test clock signal, and the test reset signal. The logic selection circuit outputting the first selection signal to the port selection circuit based on the test signal received from the test signal end includes: The state machine determines that the plurality of test access ports are in an idle state based on the test mode selection signal and outputs an idle signal to the monitoring circuit; and the monitoring circuit receives the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal. When it is determined that the verification signal is met, the monitoring circuit outputs the first selection signal to the port selection circuit, Among them, the monitoring circuit includes a first register circuit, a controller, and a second register circuit. The first register circuit is configured to receive the idle signal, the test data input signal, the test clock signal, and the test reset signal. The controller is configured to be connected to the first register circuit and the second register circuit and stores the verification signal. The second register circuit is connected to the port selection circuit, where The monitoring circuit receives the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal. When it is determined that the verification signal is met, the monitoring circuit outputting the first selection signal to the port selection circuit includes: The first register circuit receives the test data input signal in response to the idle signal; the controller determines whether the test data input signal received by the first register circuit meets the verification signal, and outputs an enable signal to the second register circuit when it is determined that the verification signal is met; and the second register circuit outputs the first selection signal to the port selection circuit in response to the enable signal.

2. The test control circuit according to claim 1, wherein The first register circuit is a shift register composed of a plurality of registers.

3. The test control circuit according to claim 1, wherein The port selection circuit is further configured to be connected to the signal input terminal and the signal output terminal, wherein The port selection circuit performs port selection in response to the first selection signal and outputs a second selection signal, including: The port selection circuit enables the input of the test mode selection signal in response to the first selection signal; The port selection circuit performs port selection based on the test mode selection signal and generates the second selection signal.

4. The test control circuit according to claim 1, characterized in that, The plurality of test access ports are further configured to be connected to the device under test interfaces in the processor, so as to test the device under test interfaces connected thereto based on the test signals received from the signal input terminal and output test data.

5. The test control circuit according to claim 4, wherein The device under test interfaces include a peripheral component interconnect high-speed interface and a memory interface.

6. A test control method for a processor, characterized in that, The test control method is applicable to a test control circuit. The processor includes a plurality of test access ports, and the plurality of test access ports are configured to be connected in parallel between a signal input terminal and a signal output terminal. Among them, the signal input terminal is directly connected to a test signal terminal to receive a test signal from the test signal terminal and control whether the plurality of test access ports enable the input of the test signal, and the signal output terminal controls whether the plurality of test access ports enable the output of test data. Among them, the plurality of test access ports are ports compliant with the Joint Test Action Group specification, and the test signals include a test clock signal, a test mode selection signal, a test data input signal, and a test reset signal. The test control circuit includes: a logic selection circuit configured to be connected to the signal input terminal, the signal output terminal, and the test signal terminal; and a port selection circuit configured to be connected to the logic selection circuit, wherein the test control method includes: Using the logic selection circuit to output a first selection signal to the port selection circuit based on the test signal received from the test signal terminal; Using the port selection circuit to perform port selection in response to the first selection signal and output a second selection signal, wherein the signal input terminal and the signal output terminal control one or more of the plurality of test access ports to enable the input of test signals and enable the output of test data based on the second selection signal. Among them, the logic selection circuit includes a state machine and a monitoring circuit. The state machine is configured to receive the test mode selection signal, the test clock signal, and the test reset signal. The monitoring circuit is configured to receive the test data input signal, the test clock signal, and the test reset signal. Among them, the output of the first selection signal to the port selection circuit based on the test signal received from the test signal terminal includes: using the state machine to determine that the multiple test access ports are in an idle state based on the test mode selection signal and output an idle signal to the monitoring circuit; and using the monitoring circuit to receive the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal. When it is determined that the verification signal is met, the first selection signal is output to the port selection circuit. Among them, the monitoring circuit includes a first register circuit, a controller, and a second register circuit. The first register circuit is configured to receive the idle signal, the test data input signal, the test clock signal, and the test reset signal. The controller is configured to be connected to the first register circuit and the second register circuit and stores the verification signal. The second register circuit is connected to the port selection circuit. Among them, The receiving of the test data input signal in response to the idle signal to determine whether the test data input signal meets a preset verification signal and, when it is determined that the verification signal is met, outputting the first selection signal to the port selection circuit includes: using the first register circuit to receive the test data input signal in response to the idle signal; using the controller to determine whether the test data input signal received by the first register circuit meets the verification signal, and when it is determined that the verification signal is met, outputting an enable signal to the second register circuit; and using the second register circuit to output the first selection signal to the port selection circuit in response to the enable signal.

7. The test control method according to claim 6, wherein The first register circuit is a shift register composed of multiple registers.

8. The test control method according to claim 6, wherein The port selection circuit is further configured to be connected to the signal input terminal and the signal output terminal. Among them, The port selection and output of the second selection signal in response to the first selection signal includes: Using the port selection circuit to enable the input of the test mode selection signal in response to the first selection signal; Using the port selection circuit to perform port selection based on the test mode selection signal and generate the second selection signal.

9. The test control method according to claim 6, wherein The multiple test access ports are further configured to be connected to the device under test interface in the processor. The test control method further includes: Using the multiple test access ports to test the device under test interface connected thereto based on the test signal received from the signal input terminal and output test data.

10. The test control method according to claim 9, wherein The device under test interface includes a peripheral component interconnect high-speed interface and a memory interface.

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