A full-system dynamic binary translation method based on translation rules

Abstract

The application belongs to the technical field of dynamic binary translation in computer architecture, and designs a system-level dynamic binary translation method based on translation rules, which proposes a new state saving and restoring mechanism to deal with conflicts in special scenarios of system-level dynamic binary translator. Specifically, it includes the following three steps: first, the instructions that will affect the system-level implementation are identified in the client instruction analysis stage, and are separated and identified for monitoring; then, in the translation rule application stage, the instructions related to system-level instruction problems, memory management problems and exception / interrupt problems are checked and processed; finally, two conditional code optimization schemes are proposed by analyzing the instruction flow information to improve the translation efficiency. The method realizes efficient dynamic binary translation while ensuring correct translation.

Description

Technical Field

[0001] This invention belongs to the field of system simulation, specifically involving a dynamic binary translation method that uses translation rules for binary translation. Background Technology

[0002] Dynamic binary translation technology is a technique that translates binary programs of a source instruction set architecture into binary programs of a target instruction set architecture at runtime (which also includes emulation of CPU, memory management, and devices).

[0003] Generally, dynamic binary translators have two operating modes: user-mode and system-mode. User-mode dynamic binary translators typically run only a single process compiled from the source machine's instruction set architecture, while system-mode dynamic binary translators need to simulate the entire virtual machine environment (including the source operating system, memory management unit, exception handling mechanisms, and devices). Therefore, system-mode dynamic binary translators have a larger software scale and greater complexity. Due to the simplified translation process and the advantage of utilizing the host operating system, user-mode dynamic binary translators perform closer to native code, while the fine-grained translation of system-mode dynamic binary translators results in poorer performance.

[0004] Traditional dynamic binary translators on the market use intermediate representation code in their design to facilitate the expansion to support more instruction set architectures. The process of a dynamic binary translator becomes: first, the source instruction sequence is translated into intermediate representation code by a front-end parser; then, the intermediate representation code is used by a back-end compiler to generate the target machine code. This design using intermediate representation code improves the scalability of the entire system and greatly reduces the coupling and manual cost of the entire translation work from the source instruction architecture to the target instruction architecture. However, this approach also results in poorer target code quality.

[0005] To address the poor performance of translation using intermediate representation code, Chinese patent CN202010625228.5 proposed a novel dynamic binary translation method in recent years. This method automatically learns and generates translation rules, applying these rules between the source and target architectures to achieve dynamic binary translation. However, this method is currently only applicable to user-level dynamic binary translators and cannot be directly applied to system-level dynamic binary translators. This is mainly because system-level dynamic binary translators have more complex implementations for two reasons: First, at the system level, some system instructions cannot be learned during the learning process, and these system instructions can affect the state management scheme in rule-based learning methods, thus preventing direct application. Second, rule-based learning methods, implemented on existing dynamic binary translators, cannot guarantee 100% code coverage, resulting in two context management environments. At the system level, due to memory management, exception handling, and other special circumstances, constant switching between the rule-based learning context and the translator's own context is required, which previous methods could not guarantee. Summary of the Invention

[0006] This invention addresses the aforementioned problems by providing a system-wide dynamic binary translation method based on translation rules. It primarily solves system-level implementation issues through adjustments and design in the client instruction parsing, translation rule matching and application, and condition code optimization stages. The invention employs the following technical solution:

[0007] This invention provides a system-wide dynamic binary translation method based on translation rules, characterized by the following steps: Step S1, parsing a client instruction sequence using a parser and identifying and monitoring special instructions within the client instruction sequence; Step S2, matching and translating the client instruction sequence using a translator and applying pre-generated translation rules, wherein the special instructions undergo instruction behavior checking to generate correct target machine code; Step S3, optimizing the target machine code using an optimizer and a system-level condition code optimization strategy to improve the quality of the target machine code.

[0008] The system-wide dynamic binary translation method based on translation rules provided by this invention may also have the following technical features: In step S1, the operands, condition codes, and corresponding operation information of the special instruction are recorded using intermediate representation codes, thereby identifying and monitoring the special instruction; In step S2, the corresponding operation information is extracted from the intermediate representation codes, and the instruction behavior is checked and processed based on the operation information.

[0009] The system-wide dynamic binary translation method based on translation rules provided by this invention may also have the following technical features, wherein the special instructions include system instructions, and step S2, the instruction behavior check processing of the system instructions includes the following steps: step A1, determining whether the system instruction is a read instruction or a modify instruction of the CPSR / SPSR register; step A2, if step A1 determines that it is the read instruction, synchronizing the CPU status information to the latest value; step A3, if step A1 determines that it is the modify instruction, after executing the modify instruction, immediately notifying the translator of the change in the storage location of the condition code information.

[0010] The system-wide dynamic binary translation method based on translation rules provided by this invention may also have the following technical features: the special instructions include memory access instructions, the translation rules include the translation implementation process of the memory access instructions, and in step S2, the instruction behavior check processing of the memory access instructions includes the following steps: step B1, before translating the memory access instructions, it is determined whether the current fixed register, Eflags register and other CPU state information need to be saved; step B2, if step B1 determines that it is yes, the fixed register, the Eflags register and the other CPU state information are synchronized back to memory.

[0011] The system-wide dynamic binary translation method based on translation rules provided by this invention may also have the following technical features: the translator translates in units of basic blocks; the special instructions include exception instructions, which correspond to internal exceptions or switching exceptions; the internal exception is an exception / interrupt occurring within the basic block during translation; and the switching exception is an exception / interrupt occurring when switching the basic block. In step S2, the instruction behavior check processing for the exception instructions includes the following steps: Step C1, when the exception instruction corresponds to the internal exception, the CPU state information is saved before the internal exception occurs, and the saved CPU state information is restored after the internal exception ends; Step C2, when the exception instruction corresponds to the switching exception, the condition code information temporarily stored in the Eflags register at the end of each basic block is parsed, and the parsed result is stored back in the corresponding memory location, so that the correct condition code information can be used when processing the switching exception.

[0012] The system-wide dynamic binary translation method based on translation rules provided by this invention may also have the following technical features, wherein, in step S3, the system-level condition code optimization strategy includes a condition code delayed storage optimization strategy, comprising the following steps: Step D1, directly storing the value of the Eflags register storing condition code information back into memory; Step D2, when an exception / interrupt occurs, before the execution of the corresponding exception / interrupt handling function, parsing the value of the Eflags register stored in the memory into each condition code flag bit.

[0013] The system-wide dynamic binary translation method based on translation rules provided by this invention may also have the following technical features: the target machine code is a target machine instruction sequence; in step S3, the system-level condition code optimization strategy includes a continuous condition execution instruction optimization strategy, comprising the following steps: step E1, performing instruction flow analysis on the target machine instruction sequence; step E2, generating an instruction condition code usage dependency graph based on the analysis results of step E1; step E3, based on the instruction condition code usage dependency graph, loading only once the instructions in the target machine instruction sequence that continuously require condition codes, while omitting other redundant loading operations.

[0014] Invention Function and Effect

[0015] The system-wide dynamic binary translation method based on translation rules according to the present invention identifies and separately monitors special instructions that affect system-level implementation during the client instruction parsing stage. Subsequently, during the translation rule application stage, the identified special instructions are checked and processed accordingly. Therefore, the method of the present invention can handle conflicts in special scenarios within a system-level dynamic binary translator, thereby achieving system-wide dynamic binary translation based on translation rules. Furthermore, the method of the present invention employs a system-level condition code optimization strategy to optimize the translated target machine code, thus improving the quality and efficiency of binary translation and achieving efficient dynamic binary translation while ensuring correct translation. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the system-wide dynamic binary translation method based on translation rules in an embodiment of the present invention.

[0017] Figure 2 This is a flowchart of the system-wide dynamic binary translation method based on translation rules in an embodiment of the present invention;

[0018] Figure 3 This is a flowchart illustrating the handling of system instruction issues in an embodiment of the present invention;

[0019] Figure 4This is a flowchart illustrating the handling of memory access instruction issues in an embodiment of the present invention;

[0020] Figure 5 This is a flowchart illustrating the handling of abnormal instruction issues in an embodiment of the present invention;

[0021] Figure 6 This is a flowchart illustrating the condition code delay optimization strategy in an embodiment of the present invention.

[0022] Figure 7 This is a flowchart illustrating the continuous conditional execution instruction optimization strategy in an embodiment of the present invention. Detailed Implementation

[0023] To make the technical means, creative features, objectives and effects of this invention easy to understand, the following describes the system-wide dynamic binary translation method based on translation rules in detail with reference to embodiments and accompanying drawings.

[0024] <Example>

[0025] In this embodiment, based on the QEMU dynamic binary translation system, the ARM instruction set is used as the source instruction set architecture and the x86 instruction set is used as the target instruction set architecture during the experiment.

[0026] Figure 1 This is a flowchart illustrating the system-wide dynamic binary translation method based on translation rules in this embodiment.

[0027] Figure 2 This is a flowchart of the system-wide dynamic binary translation method based on translation rules in this embodiment.

[0028] like Figure 1 and Figure 2 As shown, the system-wide dynamic binary translation method based on translation rules includes the following steps:

[0029] Step S1: The parser parses the client instruction sequence and identifies and monitors special instructions in the client instruction sequence.

[0030] Specifically, in step S1, special instructions are identified and monitored, mainly through several specially designed intermediate representation codes (IRs). These IRs are used to identify system-level instructions (mainly instructions for reading and writing CPSR / SPSR registers), all memory access instructions involving address translation, and instructions that may generate exceptions / interrupts in the basic block during translation. The IRs are used to record the operands, condition codes, and operations that need to be performed during processing (such as register checks, whether to save or restore CPU state, etc.) of these instructions, so that the saved IR information can be extracted and implemented when applying translation rules.

[0031] Step S2 involves using a translator to match and translate the client instruction sequence using pre-generated translation rules, and performing instruction behavior checks on special instructions to generate the correct target machine code.

[0032] In this embodiment, special instructions include system instructions, access instructions, and exception instructions. During the translation rule application phase, instruction behavior checks are performed, primarily utilizing the IR information of the special instructions collected in step S1. Constraint operations are applied to the translation of system-level instructions, memory access instructions, and potentially exception / interrupt instructions. Specifically, constraint checks and state saving and recovery steps are inserted before and after the translation result of these instructions. This ensures that a semantically correct system-level translation result can be initially generated after this step.

[0033] Specifically, in step S2, the corresponding operation information is extracted from the intermediate representation code, and the instruction behavior is checked and processed based on the operation information.

[0034] Figure 3 This is a flowchart illustrating the handling of system instruction issues in this embodiment.

[0035] In step S2, such as Figure 3 As shown, the specific steps for performing behavior checks on system commands include:

[0036] Step A1: Determine whether the system instruction is a read or modify instruction for the CPSR / SPSR register;

[0037] When step A2 or step A1 determines that a CPSR / SPSR register read instruction is being executed, the CPU status information is synchronized to the latest value.

[0038] When step A3 or step A1 determines that a modification instruction for the CPSR / SPSR register is being executed, the translator is immediately notified of the change in the storage location of the condition code information after the modification instruction is executed, so that it can redefine the latest CPU status information in subsequent processes.

[0039] Since system instructions cannot be translated using translation rules, but only by the translator's own mechanism, the above steps are required to process them accordingly.

[0040] Figure 4 This is a flowchart illustrating the handling of memory access instruction issues in this embodiment.

[0041] like Figure 4 As shown, the behavior inspection and processing of access commands specifically includes the following steps:

[0042] Step B1: Before translating the memory access instruction, determine whether the current fixed registers, Eflags register, and other CPU state information need to be saved.

[0043] If step B2 or step B1 determines that the fixed register, the Eflags register, and other CPU status information are synchronized back to memory.

[0044] In system-level dynamic binary translators, to adapt to the address translation function of the system-level simulated memory management unit when translating memory access instructions, they do so by inserting additional target machine instructions in the fast translation path and jumping out of the current basic block in the slow translation path. Therefore, to solve these two problems, the above steps are required for corresponding processing.

[0045] Figure 5 This is a flowchart illustrating the handling of abnormal instruction issues in this embodiment.

[0046] like Figure 5 As shown, the specific steps for performing behavioral checks on abnormal commands include:

[0047] Step C1: When the exception instruction corresponds to the internal exception, save the CPU state information before the internal exception occurs, and restore the saved CPU state information after the internal exception ends.

[0048] The most significant problem with anomalies occurring within a translation block is the loss of CPU state. Therefore, it is necessary to monitor these potential anomaly locations by saving the CPU state before the anomaly occurs and restoring the CPU state after the anomaly ends.

[0049] Step C2: When the exception instruction corresponds to the switching exception, the condition code information temporarily stored in the Eflags register at the end of each basic block is parsed, and the parsed result is stored back in the corresponding memory location, so that the correct condition code information can be used when handling the switching exception.

[0050] The main reason for exceptions / interruptions during translation block switching is that the original cross-block condition code optimization strategy requires a defined program execution flow. Device interruptions can occur at any time, altering the program execution flow and leading to invalid cross-block analysis. Since it's unknown whether exceptions / interruptions will occur during the switching process after the current block execution, it's necessary to parse the condition code information temporarily stored in the Eflags register of the original optimization strategy at the end of each block and store the parsed results back to the corresponding memory location. This ensures that the correct condition code information can be used when handling exceptions / interruptions.

[0051] Step S3: Optimize the target machine code using an optimizer and a system-level condition code optimization strategy to improve the quality of the target machine code.

[0052] Specifically, in step S3, a system-level conditional optimization strategy is applied to the target machine code to improve code quality.

[0053] In this embodiment, the system-level condition optimization strategy includes condition code delayed storage optimization and continuous condition execution instruction optimization.

[0054] Figure 6 This is an example flowchart of the condition code delay optimization strategy in this embodiment.

[0055] In step 3, such as Figure 6 As shown, optimizing the condition code lazy storage of the target machine code includes the following steps:

[0056] Step D1: Directly store the value of the Eflags register containing the condition code information back into memory;

[0057] Step D2: When an exception / interrupt occurs, before the corresponding exception / interrupt handling function is executed, the value of the Eflags register stored in the memory is parsed into each condition code flag bit.

[0058] Figure 7 This is a flowchart illustrating the continuous conditional execution instruction optimization strategy in an embodiment of the present invention.

[0059] like Figure 7 As shown, optimizing the target machine code for continuous conditional execution instructions includes the following steps:

[0060] Step E1: Perform instruction flow analysis on the target machine instruction sequence;

[0061] Step E2: Based on the analysis results of step E1, generate an instruction condition code dependency graph;

[0062] Step E3: Based on the instruction condition code dependency graph, load only once the consecutive instructions that require condition codes in the target machine instruction sequence, while omitting other redundant loading operations.

[0063] As mentioned above, condition code delay optimization mainly corrects the storage method of condition codes at the end of each basic block, replacing the instruction storing all client condition codes with fewer instructions storing Eflags, and inserting the operation of parsing Eflags before exception function handling. This saves about ten target machine instructions during the translation of each basic block, effectively improving the quality of translated instructions. The continuous conditional execution instruction optimization method mainly analyzes the client instruction flow, including both instruction key register dependencies and condition code dependencies, and optimizes redundant instructions that can be removed. This helps to eliminate some redundant instructions generated during the translation of continuous conditional execution instructions, improving the translation quality.

[0064] Functions and effects of the embodiments

[0065] According to the system-wide dynamic binary translation method based on translation rules provided in this embodiment, by identifying special instructions that affect system-level implementation during the client instruction parsing stage and separating them for identification and monitoring, and then checking and correspondingly handling special instructions involved in system-level instruction problems, memory management problems, and exception / interrupt problems during the translation rule application stage, and finally proposing two condition code optimization strategies by analyzing instruction flow information to improve translation quality and efficiency, the translation method of this embodiment can not only efficiently utilize translation rules for translation, but also ensure the accuracy of system-level implementation, and can generate high-quality target machine code.

[0066] In this embodiment, performance and code coverage at the system level were evaluated through experiments. The standard SPEC CPU 2006 test suite was used for testing. As can be seen, compared to QEMU 4.1, this embodiment shows a 1.12x performance improvement, and its dynamic code coverage reaches 94.13%, verifying the effectiveness of the dynamic binary translation method at the system level.

[0067] The above embodiments are only used to illustrate specific implementations of the present invention, and the present invention is not limited to the scope of the description of the above embodiments.

Claims

1. A system-wide dynamic binary translation method based on translation rules, characterized in that, Includes the following steps: Step S1: The parser parses the client instruction sequence and identifies and monitors special instructions in the client instruction sequence. Step S2: The client instruction sequence is matched and translated by a translator and pre-generated translation rules are applied. In this step, instruction behavior checks are performed on the special instructions to generate the correct target machine code. Step S3: The target machine code is optimized using an optimizer and a system-level condition code optimization strategy to improve its quality. The target machine code is a sequence of target machine instructions. The special instructions include system instructions, memory access instructions, and exception instructions. In step S3, the system-level condition code optimization strategy includes a condition code delayed storage optimization strategy and a continuous conditional execution instruction optimization strategy. The condition code delayed storage optimization strategy includes the following steps: Step D1: Directly store the value of the Eflags register containing the condition code information back into memory; Step D2: When an exception / interrupt occurs, before the corresponding exception / interrupt handling function is executed, the value of the Eflags register stored in the memory is parsed into the various condition code flag bits. The continuous conditional execution instruction optimization strategy includes the following steps: Step E1: Perform instruction flow analysis on the target machine instruction sequence; Step E2: Based on the analysis results of step E1, generate an instruction condition code dependency graph; Step E3: Based on the instruction condition code dependency graph, load only once the consecutive instructions that require condition codes in the target machine instruction sequence, while omitting other redundant loading operations.

2. The system-wide dynamic binary translation method based on translation rules according to claim 1, characterized in that: in, In step S1, intermediate representation codes are used to record the operands, condition codes, and corresponding operation information of the special instruction, thereby enabling the identification and monitoring of the special instruction. In step S2, the corresponding operation information is extracted from the intermediate representation code, and the instruction behavior check is performed based on the operation information.

3. The system-wide dynamic binary translation method based on translation rules as described in claim 2, Its features are: In step S2, the instruction behavior check processing of the system instructions includes the following steps: Step A1: Determine whether the system instruction is a read instruction or a modify instruction for the CPSR / SPSR register; Step A2: When step A1 determines that the read instruction is received, the CPU status information is synchronized to the latest value. When step A3 or step A1 determines that the modification instruction is correct, after executing the modification instruction, the translator is immediately notified of the change in the storage location of the condition code information.

4. The system-wide dynamic binary translation method based on translation rules according to claim 2, characterized in that: in, The translation rules include the translation implementation process of the memory access instructions. Step S2, the instruction behavior check processing for the memory access instruction includes the following steps: Step B1: Before translating the memory access instruction, determine whether the current fixed registers, Eflags register, and other CPU state information need to be saved; If step B2 or step B1 determines that the fixed register, the Eflags register, and other CPU status information are synchronized back to memory.

5. The system-wide dynamic binary translation method based on translation rules according to claim 2, characterized in that: in, The translator translates in units of basic blocks. The exception instruction corresponds to an internal exception or a switching exception. The internal exception refers to the exception / interrupt that occurs within the basic block during translation. The switching exception is an exception / interrupt that occurs when switching the basic block. Step S2, the instruction behavior inspection and processing of the abnormal instruction includes the following steps: Step C1: When the abnormal instruction corresponds to the internal abnormality, save the CPU state information before the internal abnormality occurs, and restore the saved CPU state information after the internal abnormality ends. Step C2: When the exception instruction corresponds to the switching exception, the condition code information temporarily stored in the Eflags register at the end of each basic block is parsed, and the parsed result is stored back in the corresponding memory location, so that the correct condition code information can be used when processing the switching exception.

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