Data extraction method and device

Abstract

The present application provides a data extraction method and apparatus for extracting data to be extracted in the uplink direction of a physical layer field programmable gate array (FPGA) of a base station subsystem, wherein the data to be extracted includes ingress data or egress data. The method comprises: configuring parameter information of the data to be extracted, wherein the parameter information includes: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number, wherein the optical port number includes the ingress number or egress number of the data to be extracted; comparing the packet header format of the basic frame data of the optical port number with the parameter information; if the comparison result is a match, extracting the ingress data or egress data that matches the parameter information and writing the extracted data to a random access memory; and reading the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface. The present application can improve the efficiency of abnormal location in base station systems.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data extraction method and device. Background Art

[0002] When a base station experiences an anomaly in the field, it's often necessary to analyze and locate the physical layer FPGA (Field-Programmable Gate Array). For example, adding an integrated logic analyzer to the project and using it with a simulator to extract data from each node in the physical layer FPGA to locate the anomaly is a relatively effective method.

[0003] Currently, the main method for board-level debugging of FPGAs is to extract data from each FPGA node using the Integrated Logic Analyzer (ILA) core. For example, by adding the ILA IP (Intellectual Property) core to an FPGA project and using it with a simulator to extract data from each module node, the problem module can be analyzed.

[0004] However, this method is generally applicable to the development phase of the physical layer FPGA. Furthermore, when a base station experiences an anomaly in the field, it's difficult to insert an emulator into the baseband board, limiting its applicability. Furthermore, a deeper ILA core consumes more resources, limiting its depth and thus reducing the amount of data extracted. Summary of the Invention

[0005] The embodiments of the present application provide a data extraction method and device, which can be applied to complex test environments such as field or laboratory, and can improve the efficiency of abnormal location of base station systems.

[0006] In a first aspect, an embodiment of the present application provides a data extraction method for extracting data to be extracted in an uplink direction of a physical layer field programmable gate array (FPGA) of a base station subsystem, wherein the data to be extracted includes ingress data or egress data, and the method comprises:

[0007] Configuring parameter information of the data to be extracted, the parameter information including: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number, wherein the optical port number includes an entry number or an exit number of the data to be extracted;

[0008] Comparing the packet header format of the basic frame data of the optical port number with the parameter information, if the comparison result is a match, extracting the ingress data or egress data that matches the parameter information, and writing the extracted data into a random access memory;

[0009] The extracted uplink data is read from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

[0010] Optionally, the parameter information of configuring the data to be extracted includes:

[0011] Configuring parameter information of the data to be extracted by configuring fields of a preset register, wherein the fields of the preset register correspond to the parameters in the parameter information;

[0012] The comparing the packet header format of the current basic frame data with the parameter information includes:

[0013] Each field in the header format of the current basic frame data is compared one by one with each field of the preset register to determine whether each field in the header format of the current basic frame data matches each field of the preset register, wherein the header format of the current basic frame data includes at least the following fields: a second subframe number, a second symbol, a second antenna number, and a second physical resource block number.

[0014] Optionally, in the case of extracting entry data matching the parameter information, the method further includes:

[0015] Performing asynchronous clock domain processing on the input data to obtain processed input data;

[0016] Writing the extracted data into a random access memory comprises:

[0017] The processed entry data is written into a random access memory.

[0018] Optionally, extracting the input data or output data matching the parameter information and writing the extracted data into a random access memory includes:

[0019] When the header format of the current basic frame data matches the parameter information, extracting basic frame data of a preset length starting from the current basic frame data for the optical port number indicated in the parameter information;

[0020] The extracted basic frame data of the preset length is packaged and then written into a random access memory.

[0021] Optionally, the step of reading the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface comprises:

[0022] Setting the default channel of the PCIE interface to the physical random access channel PRACH message channel;

[0023] Upon receiving a request for the uplink data channel to occupy the PCIE interface, releasing the PRACH message channel and switching to the uplink data channel to read the extracted uplink data from the random access memory through the uplink data channel;

[0024] After the uplink data channel is released, the PRACH message channel is switched to.

[0025] Optionally, after obtaining the extracted data from the random access memory, the method further includes:

[0026] According to the extracted inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, the transmission data of the upper-level subsystem of the base station subsystem is analyzed to locate abnormalities in each subsystem of the base station.

[0027] In a second aspect, an embodiment of the present application provides a data extraction device, the device being used to extract data to be extracted in the uplink direction of a physical layer field programmable gate array (FPGA) of a base station subsystem, the data to be extracted including ingress data or egress data, the device comprising a memory, a transceiver, and a processor, wherein the memory is used to store a computer program; the transceiver is used to transmit and receive data under the control of the processor; and the processor is used to read the computer program in the memory and perform the following operations:

[0028] Configuring parameter information of the data to be extracted, the parameter information including: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number, wherein the optical port number includes an entry number or an exit number of the data to be extracted;

[0029] Comparing the packet header format of the basic frame data of the optical port number with the parameter information, if the comparison result is a match, extracting the ingress data or egress data that matches the parameter information, and writing the extracted data into a random access memory;

[0030] The extracted uplink data is read from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

[0031] Optionally, the parameter information for configuring the data to be extracted specifically includes:

[0032] Configuring parameter information of the data to be extracted by configuring fields of a preset register, wherein the fields of the preset register correspond to the parameters in the parameter information;

[0033] The comparing the packet header format of the current basic frame data with the parameter information includes:

[0034] Each field in the header format of the current basic frame data is compared one by one with each field of the preset register to determine whether each field in the header format of the current basic frame data matches each field of the preset register, wherein the header format of the current basic frame data includes at least the following fields: a second subframe number, a second symbol, a second antenna number, and a second physical resource block number.

[0035] Optionally, when extracting entry data matching the parameter information, the processor is further configured to read a computer program in the memory and perform the following operations:

[0036] Performing asynchronous clock domain processing on the input data to obtain processed input data;

[0037] Writing the extracted data into a random access memory comprises:

[0038] The processed entry data is written into a random access memory.

[0039] Optionally, extracting the inlet data or outlet data matching the parameter information and writing the extracted data into a random access memory specifically includes:

[0040] When the header format of the current basic frame data matches the parameter information, extracting basic frame data of a preset length starting from the current basic frame data for the optical port number indicated in the parameter information;

[0041] The extracted basic frame data of the preset length is packaged and then written into a random access memory.

[0042] Optionally, the step of reading the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface specifically includes:

[0043] Setting the default channel of the PCIE interface to the physical random access channel PRACH message channel;

[0044] Upon receiving a request for the uplink data channel to occupy the PCIE interface, releasing the PRACH message channel and switching to the uplink data channel to read the extracted uplink data from the random access memory through the uplink data channel;

[0045] After the uplink data channel is released, the PRACH message channel is switched to.

[0046] Optionally, the processor is further configured to read the computer program in the memory and perform the following operations:

[0047] According to the extracted inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, the transmission data of the upper-level subsystem of the base station subsystem is analyzed to locate abnormalities in each subsystem of the base station.

[0048] In a third aspect, an embodiment of the present application provides a data extraction device for extracting data to be extracted in an uplink direction of a physical layer field programmable gate array (FPGA) of a base station subsystem, wherein the data to be extracted includes ingress data or egress data, and the device includes:

[0049] A parameter configuration module, configured to configure parameter information of the data to be extracted, the parameter information including: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number, wherein the optical port number includes an entry number or an exit number of the data to be extracted;

[0050] a comparison and extraction module, configured to compare the packet header format of the basic frame data of the optical port number with the parameter information, and if the comparison result is a match, extract the ingress data or egress data that matches the parameter information, and write the extracted data into a random access memory;

[0051] The data reading module is used to read the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

[0052] Optionally, the parameter configuration module is specifically configured to configure parameter information of the data to be extracted by configuring fields of a preset register, wherein the fields of the preset register correspond to parameters in the parameter information;

[0053] The comparison and extraction module is specifically used to compare each field in the header format of the current basic frame data with each field of the preset register one by one to determine whether each field in the header format of the current basic frame data matches each field of the preset register, and the header format of the current basic frame data includes at least the following fields: a second subframe number, a second symbol, a second antenna number, and a second physical resource block number.

[0054] Optionally, in the case of extracting entry data matching the parameter information, the apparatus further comprises:

[0055] A clock processing module, configured to perform asynchronous clock domain processing on the input data to obtain processed input data;

[0056] The comparison and extraction module is specifically used to write the processed entry data into a random access memory.

[0057] Optionally, the comparison and extraction module includes:

[0058] an extraction submodule, configured to extract basic frame data of a preset length starting from the current basic frame data for the optical port number indicated in the parameter information when a header format of the current basic frame data matches the parameter information;

[0059] The writing submodule is used to package the extracted basic frame data of a preset length and write the data into a random access memory.

[0060] Optionally, the data reading module includes:

[0061] A default setting submodule, used to set the default channel of the PCIE interface to the physical random access channel PRACH message channel;

[0062] A first switching submodule is configured to release the PRACH message channel and switch to the uplink data channel upon receiving a request for the uplink data channel to occupy the PCIE interface, so as to read the extracted uplink data from the random access memory through the uplink data channel;

[0063] The second switching submodule is configured to switch to the PRACH message channel after the uplink data channel is released.

[0064] Optionally, the device further comprises:

[0065] The data analysis module is used to analyze the transmission data of the upper-level subsystem of the base station subsystem based on the extracted inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, so as to locate the abnormality of each subsystem of the base station.

[0066] In a fourth aspect, an embodiment of the present application provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the aforementioned data extraction method when executing the program.

[0067] In a fifth aspect, an embodiment of the present application provides a processor-readable storage medium, characterized in that the processor-readable storage medium stores a computer program executable by the processor of the aforementioned method.

[0068] The embodiments of the present application include the following advantages:

[0069] The embodiment of the present application uses the PCIE interface to extract the inbound or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, which can speed up the data extraction speed and thus improve the efficiency of abnormal location. In addition, the embodiment of the present application reuses the high-bandwidth PCIE interface by polling the PCIE interface without affecting the normal transmission of the PRACH message, saving a lot of time resources while reducing the required PCIE interface resources. Furthermore, the process of extracting data in the embodiment of the present application does not require the insertion of an emulator into the baseband board, and can be applied to complex test environments such as the field or laboratory. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0071] Figure 1 A flow chart showing an embodiment of a data extraction method of the present application is shown;

[0072] Figure 2 A schematic diagram showing fields of a configuration preset register of the present application is shown;

[0073] Figure 3 A schematic diagram of the present application showing a method of gating 10 channel data by configuring a preset register;

[0074] Figure 4 A schematic diagram of a packet header format of a basic frame matching a preset register in the present application is shown;

[0075] Figure 5 A schematic diagram of extracting 43 basic frames in an example of the present application is shown;

[0076] Figure 6 A schematic diagram of polling each channel of a PCIE interface according to the present application is shown;

[0077] Figure 7 A schematic diagram of the overall process of extracting inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction through the PCIE interface of the present application is shown;

[0078] Figure 8 A structural block diagram of an embodiment of a data extraction device of the present application is shown;

[0079] Figure 9 A structural block diagram of an embodiment of a data extraction device of the present application is shown;

[0080] Figure 10 A schematic structural diagram of an electronic device provided in this application is shown. DETAILED DESCRIPTION

[0081] In the embodiments of this application, the term "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship. In the embodiments of this application, the term "plurality" refers to two or more, and other quantifiers are similar.

[0082] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0083] Reference Figure 1 , shows a flow chart of an embodiment of a data extraction method of the present application, the method is used to extract data to be extracted in the uplink direction of a physical layer field programmable gate array FPGA of a base station subsystem, the data to be extracted includes ingress data or egress data, and the method may specifically include:

[0084] Step 101: Configure parameter information of data to be extracted, wherein the parameter information includes: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number. The optical port number includes an entry number or an exit number of the data to be extracted.

[0085] Step 102: Compare the packet header format of the basic frame data of the optical port number with the parameter information. If the comparison result is a match, extract the ingress data or egress data that matches the parameter information and write the extracted data into a random access memory.

[0086] Step 103: Read the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

[0087] The present application proposes a data extraction method, which extracts the inbound or outbound data of the physical layer field programmable gate array (FPGA) of the base station subsystem in the uplink direction through the PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interface. Then, the inbound and outbound data of the physical layer FPGA of the base station subsystem in the uplink direction can be used to locate abnormalities in the base station system in the field or laboratory.

[0088] The technical solution provided in the embodiment of the present application can be applicable to a variety of systems, especially 5G systems. For example, the applicable system can be a global system of mobile communication (GSM) system, a code division multiple access (CDMA) system, a wideband code division multiple access (WCDMA) general packet radio service (GPRS) system, a long term evolution (LTE) system, a LTE frequency division duplex (FDD) system, a LTE time division duplex (TDD) system, an advanced long term evolution (LTE-A) system, a universal mobile telecommunication system (UMTS), a world-wide interoperability for microwave access (WiMAX) system, a 5G new air interface (NR) system, etc. These various systems include terminal equipment and network equipment. The system may also include a core network part, such as an evolved packet system (EPS), a 5G system (5GS), etc.

[0089] Specifically, first configure parameter information of the data to be extracted, the parameter information including: optical port number, first subframe number, first symbol, first antenna number, first physical resource block number, the optical port number including the entry number or exit number of the data to be extracted.

[0090] The purpose of configuring the parameter information of the data to be extracted is to indicate which frame data of which inlet or outlet should be extracted at the current moment. It will be understood that the embodiments of the present application do not limit the specific method of configuring the parameter information of the data to be extracted. For example, the parameter information of the data to be extracted can be configured through a configuration file, or the parameter information of the data to be extracted can also be configured through registers. In order to improve the efficiency of reading the parameter information of the data to be extracted, the embodiments of the present application preferably use registers to configure the parameter information of the data to be extracted.

[0091] In an optional embodiment of the present application, configuring the parameter information of the data to be extracted in step 101 includes: configuring the parameter information of the data to be extracted by configuring a field of a preset register, wherein the field of the preset register corresponds to each parameter in the parameter information;

[0092] The comparison of the packet header format of the current basic frame data with the parameter information in step 102 includes: comparing each field in the packet header format of the current basic frame data with each field of the preset register one by one to determine whether each field in the packet header format of the current basic frame data matches each field of the preset register, and the packet header format of the current basic frame data includes at least the following fields: a second subframe number, a second symbol, a second antenna number, and a second physical resource block number.

[0093] The embodiment of the present application configures the parameter information of the data to be extracted by configuring the fields of the preset register, wherein the fields of the preset register correspond to the parameters in the parameter information. Figure 2 , showing a schematic diagram of fields for configuring a preset register according to an embodiment of the present application. In this embodiment of the present application, the preset register for configuring parameter information of the data to be extracted is recorded as i_aur_debug_config. The preset register i_aur_debug_config includes at least the following fields: optical port number, first subframe number, first symbol, first antenna number, and first physical resource block number.

[0094] It can be understood that the "first" and "second" in the first subframe number, the first symbol, the first antenna number, the first physical resource block number, the second subframe number, the second symbol, the second antenna number, and the second physical resource block number in the embodiments of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0095] like Figure 2As shown, the preset register i_aur_debug_config field configuration is 0x80000002. Among them, bits 0 to 3 represent the subframe number, bits 4 to 7 represent the symbol, bits 8 to 11 represent the antenna number, bits 12 to 20 represent the physical resource block number (PRB), bits 24 to 25 are opt selection bits, used to indicate the ingress optical port number to be extracted, bits 26 to 28 are au port channel selection bits, used to indicate the egress optical port number to be extracted, bit 30 is opt or au selection bit, used to indicate whether the ingress data or egress data to be extracted is 0, indicating the ingress data to be extracted, and 1 indicating the egress data to be extracted. Bit 31 is the extraction valid bit, used to indicate whether the data extraction operation can be performed currently. If this bit is valid (such as this bit is 1), the data extraction operation can be performed. Figure 2 The configuration field of the preset register i_aur_debug_config shown indicates that data with the subsystem inlet optical port number being 0, the first subframe number being 2, the first symbol being 0, the first antenna number being 0, and the first resource block number being 0 needs to be extracted.

[0096] In a specific implementation, the PCIE interface can extract data from one entry or one exit at a time. Therefore, when configuring the parameter information of the data to be extracted, the optical port number of the data to be extracted can be specified in the parameter information. The optical port number includes the entry number of the data to be extracted or the exit number of the data to be extracted. Figure 2 As shown, bits 24 to 25 of the preset register i_aur_debug_config are 00, and bit 30 is 0, indicating that the data currently being extracted is the data of the subsystem inlet optical port number 0.

[0097] In one example, the embodiment of the present application extracts the inlet data of 4 subsystems and the data of three cells at the exit through PCIE, wherein each cell includes the data of two exit channels, thus extracting the data of 10 channels in total. Figure 3 , shows a schematic diagram of the embodiment of the present application for gating the above 10 channel data by configuring the preset register. Figure 3 As shown, by configuring the preset register, the 4 inbound data and 6 outbound data of the physical layer FPGA of the base station subsystem in the uplink direction can be extracted. Which channel data of these 4 inbound data and 6 outbound data needs to be extracted at a certain moment can be determined by the 24th to 28th and 30th bits in the currently configured preset register i_aur_debug_config field. For example, Figure 2 The current configuration of the preset register i_aur_debug_config is used to extract the inlet optical port number 0 (i.e. Figure 3 Data of entry 0 in .

[0098] The physical layer FPGA interface usually performs data packetization according to the CPRI (Common Public Radio Interface) protocol. When the optical port data is packetized according to the CPRI protocol, the packet header format PRACHHD of a cpri_chip (CPRI basic frame) includes at least the following fields: the second subframe number slot, the second symbol sym, the second antenna number ant, and the second physical resource block number prb.

[0099] by Figure 2 For example, the packet header format of the basic frame data with the inlet optical port number 0 is compared one by one with the preset register i_aur_debug_config field to determine whether each field in the packet header format of the current basic frame data matches each field in the preset register. If the comparison result is a match, extraction starts from the current basic frame data and the extracted data is written to the random access memory RAM.

[0100] For example, Figure 2 Indicates that the data with the first subframe number of 2, the first symbol of 0, the first antenna number of 0, and the first resource block number of 0 with the inlet optical port number of 0 is to be extracted. When the fields in the packet header format PRACHHD of a basic frame (cpri_chip) with the inlet optical port number of 0 are matched with the fields in i_aur_debug_config, that is, the second subframe number slot, the second symbol sym, the second antenna number ant, and the second physical resource block number prb in the packet header format PRACHHD of the basic frame are respectively the same as those in i_aur_debug_config. Figure 2 If the first subframe number, the first symbol, the first antenna number, and the first physical resource block number in the preset register i_aur_debug_config are consistent, data extraction starts from the basic frame.

[0101] In an optional embodiment of the present application, when extracting entry data matching the parameter information, the method further includes:

[0102] Performing asynchronous clock domain processing on the input data to obtain processed input data;

[0103] Writing the extracted data into a random access memory comprises:

[0104] The processed entry data is written into a random access memory.

[0105] In a specific implementation, the clock frequency of the inbound data may differ from the clock frequency of the extracted data. In this case, asynchronous clock domain processing can be performed on the inbound data to obtain processed inbound data, so that the clock frequency of the processed inbound data is synchronized with the clock frequency of the extracted data. In one example, the clock frequency of the inbound data is 368.64 MHz, and the clock frequency of the extracted data is 491.52 MHz. These two clocks are asynchronous clocks. Therefore, when extracting the inbound data, the inbound data is subjected to asynchronous clock domain processing, and data type conversion can then be performed, such as converting 64 bits of inbound data into 128 bits of processed inbound data, and writing the 128 bits of processed inbound data to a random access memory.

[0106] In an optional embodiment of the present application, extracting the inlet data or outlet data matching the parameter information and writing the extracted data into a random access memory in step 102 includes:

[0107] Step S11: When the header format of the current basic frame data matches the parameter information, extracting basic frame data of a preset length starting from the current basic frame data for the optical port number indicated in the parameter information;

[0108] Step S12: Packaging the extracted basic frame data of the preset length and writing the data into a random access memory.

[0109] Due to the limited resources of random access memory RAM, in an embodiment of the present application, when the header format of the current basic frame data matches the parameter information, the optical port number indicated in the parameter information is extracted starting from the current basic frame data to extract the basic frame data of a preset length.

[0110] It is understood that the preset length can be set based on actual hardware and software resources. This embodiment of the present application does not impose any restrictions on this. In one example, this embodiment of the present application sets the preset length of the extracted entry data to 43 basic frames, that is, 43 basic frames of the physical layer FPGA entry are extracted at a time. This embodiment of the present application groups the extracted entry data according to cpri_chip, and one basic frame is 96 clk (clock).

[0111] Reference Figure 4 , shows a schematic diagram of the packet header format of a basic frame that matches a preset register in an embodiment of the present application. Assume that Figure 4The second subframe number slot, second symbol sym, second antenna number ant, and second physical resource block number prb of the packet header format PRACHHD of the second basic frame shown can match the fields configured in i_aur_debug_config. Therefore, 43 basic frame data are extracted from the second basic frame to the 44th basic frame and written into RAM. In addition, the extraction valid bit is valid from the second clk to the 96th clk (a total of 95 clks), so the actual amount of data extracted at one time is 43×95=4085. Figure 5 , shows a schematic diagram of extracting 43 basic frames in this example. Compared with extracting data from each FPGA node through the ILA core, the embodiment of the present application can extract a larger amount of data at a time, which can further improve the efficiency of data extraction.

[0112] In practical applications, various FPGA models typically have PCIE interface resources. PCIE interfaces offer advantages such as high bandwidth and high speed. For example, a 16xGen3 PCIE interface has a theoretical bandwidth of 16*8=128Gbps. The present embodiment utilizes PCIE interface resources to extract uplink ingress or egress data from the physical layer FPGA of a base station subsystem, thereby increasing both the amount and speed of data extraction.

[0113] Typically, PARCH messages are also uploaded through the PCIE interface, thus occupying a certain channel. Extracting uplink / downlink data also requires occupying PCIE interface resources. Therefore, the embodiment of the present application reuses PCIE interface resources through polling, writes the real-time extracted inbound or outbound data of the base station subsystem physical layer FPGA in the uplink direction into RAM, and then reads the extracted data from RAM through the preset debugging interface (osp), thereby obtaining the extracted inbound or outbound data of the base station subsystem physical layer FPGA in the uplink direction. Through the embodiment of the present application, the speed of data extraction can be accelerated, thereby improving the efficiency of problem locating, saving a large amount of time resources while reducing the occupied PCIE interface resources.

[0114] In an optional embodiment of the present application, the step of reading the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface includes:

[0115] Step S21: Setting the default channel of the PCIE interface to the physical random access channel PRACH message channel;

[0116] Step S22: upon receiving a request for the uplink data channel to occupy the PCIE interface, releasing the PRACH message channel and switching to the uplink data channel to read the extracted uplink data from the random access memory through the uplink data channel;

[0117] Step S23: After the uplink data channel is released, switch to the PRACH message channel.

[0118] In specific applications, PARCH messages are generally uploaded through the PCIE interface, so they will also occupy a certain channel, and extracting uplink data / downlink data also requires occupying the PCIE interface. Therefore, the embodiment of the present application reuses PCIE interface resources through polling.

[0119] It should be noted that the embodiment of the present application does not limit the specific number of channels occupied by the PARCH message and the number of channels occupied by extracting uplink data / downlink data. In an example, it is set that the PARCH message occupies 3 channels, the extraction of uplink data occupies 2 channels, and the extraction of downlink data occupies 1 channel. Figure 6 , shows a schematic diagram of polling each channel of the PCIE interface of the present application. Figure 6 As shown, the PCIE interface includes six channels, including three PARCH message channels for uploading PARCH messages; two uplink data channels for extracting uplink data; and one downlink data channel for extracting downlink data.

[0120] In the embodiment of the present application, the default channel of the PCIE interface is set to the PRACH message channel (eg Figure 6 (The channel corresponding to the optical port 0 PRACH message shown in the figure) When a request is received that the uplink data channel needs to occupy the PCIE interface, the PRACH message channel is released and the uplink data channel is switched to read the extracted uplink data from the random access memory through the uplink data channel. After the uplink data reading is completed, the uplink data channel is released and the default PRACH message channel is automatically switched back.

[0121] That is, the PCIE interface defaults to the PRACH message channel. When the uplink data channel requests to occupy the PCIE interface, the default PRACH message channel is released. After the uplink data channel is released, it automatically switches back to the default PRACH message channel. Therefore, the embodiment of the present application does not affect the normal transmission of PRACH messages while extracting uplink data through the PCIE interface.

[0122] Reference Figure 7, shows a schematic diagram of the overall process of extracting inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction through the PCIE interface according to an embodiment of the present application. Figure 7 As shown in the figure, the process of extracting data mainly includes the steps of configuring preset registers, selecting subsystem inlet or outlet data, asynchronous clock domain processing of inlet data, data type conversion, data extraction channel selection, and data output to the PCIE interface. Among them, configuring the preset register is used to configure the parameter information of the data to be extracted. The asynchronous clock domain processing of inlet data is used to synchronize the clock frequency of the inlet data. The data type conversion is used to convert the data type of the extracted inlet data or outlet data. The data extraction channel selection is used to select the data type of the extracted inlet data or outlet data. Figure 7 By polling the six channels, when the uplink data channel requests to occupy the PCIE interface, the extracted uplink data is read from the random access memory via the uplink data channel. Outputting data to the PCIE interface means that after the extracted uplink data is read from the random access memory via the uplink data channel, the read uplink data is output via the PCIE interface.

[0123] In an optional embodiment of the present application, after obtaining the extracted data from the random access memory, the method further includes:

[0124] According to the extracted inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, the transmission data of the upper-level subsystem of the base station subsystem is analyzed to locate abnormalities in each subsystem of the base station.

[0125] When locating problems in the field or laboratory, due to the large size of the system, it is usually only possible to roughly locate the problem, and then check each one one by one, resulting in low efficiency in locating abnormalities. Through the embodiments of the present application, it is possible to extract the inbound or outbound data of the physical layer FPGA of a subsystem in the uplink direction, and then, based on the extracted inbound or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, it is possible to analyze the transmission data of the upper-level subsystem of the base station subsystem to analyze whether the data transmitted by the upper-level subsystem is correct, so as to know whether the operation of the upper-level subsystem is normal, and to quickly locate the abnormal subsystem, thereby improving the efficiency of abnormality locating.

[0126] In summary, the embodiment of the present application uses the PCIE interface to extract the inbound or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, which can speed up the data extraction and thus improve the efficiency of abnormal location. In addition, the embodiment of the present application reuses the high-bandwidth PCIE interface by polling the PCIE interface without affecting the normal transmission of the PRACH message, thereby saving a lot of time resources while reducing the required PCIE interface resources. Furthermore, the process of extracting data in the embodiment of the present application does not require the insertion of an emulator into the baseband board, and can be applied to complex test environments such as the field or laboratory.

[0127] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0128] Device embodiment

[0129] Reference Figure 8 , shows a structural block diagram of an embodiment of a data extraction device of the present application, the device is used to extract data to be extracted in the uplink direction of a physical layer field programmable gate array FPGA of a base station subsystem, the data to be extracted includes ingress data or egress data, the device includes a memory 801, a transceiver 802, and a processor 803, wherein the memory 801 is used to store a computer program; the transceiver 802 is used to send and receive data under the control of the processor; the processor 803 is used to read the computer program in the memory and perform the following operations:

[0130] Configuring parameter information of the data to be extracted, the parameter information including: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number, wherein the optical port number includes an entry number or an exit number of the data to be extracted;

[0131] Comparing the packet header format of the basic frame data of the optical port number with the parameter information, if the comparison result is a match, extracting the ingress data or egress data that matches the parameter information, and writing the extracted data into a random access memory;

[0132] The extracted uplink data is read from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

[0133] Optionally, the parameter information for configuring the data to be extracted specifically includes:

[0134] Configuring parameter information of the data to be extracted by configuring fields of a preset register, wherein the fields of the preset register correspond to the parameters in the parameter information;

[0135] The comparing the packet header format of the current basic frame data with the parameter information includes:

[0136] Each field in the header format of the current basic frame data is compared one by one with each field of the preset register to determine whether each field in the header format of the current basic frame data matches each field of the preset register, wherein the header format of the current basic frame data includes at least the following fields: a second subframe number, a second symbol, a second antenna number, and a second physical resource block number.

[0137] Optionally, when extracting entry data matching the parameter information, the processor is further configured to read a computer program in the memory and perform the following operations:

[0138] Performing asynchronous clock domain processing on the input data to obtain processed input data;

[0139] Writing the extracted data into a random access memory comprises:

[0140] The processed entry data is written into a random access memory.

[0141] Optionally, extracting the inlet data or outlet data matching the parameter information and writing the extracted data into a random access memory specifically includes:

[0142] When the header format of the current basic frame data matches the parameter information, extracting basic frame data of a preset length starting from the current basic frame data for the optical port number indicated in the parameter information;

[0143] The extracted basic frame data of the preset length is packaged and then written into a random access memory.

[0144] Optionally, the step of reading the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface specifically includes:

[0145] Setting the default channel of the PCIE interface to the physical random access channel PRACH message channel;

[0146] Upon receiving a request for the uplink data channel to occupy the PCIE interface, releasing the PRACH message channel and switching to the uplink data channel to read the extracted uplink data from the random access memory through the uplink data channel;

[0147] After the uplink data channel is released, the PRACH message channel is switched to.

[0148] Optionally, the processor is further configured to read the computer program in the memory and perform the following operations:

[0149] According to the extracted inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, the transmission data of the upper-level subsystem of the base station subsystem is analyzed to locate abnormalities in each subsystem of the base station.

[0150] Among them, Figure 8 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically linking together various circuits of one or more processors represented by processor 803 and memory represented by memory 801. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are all well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 802 may be a plurality of components, i.e., a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, such as a wireless channel, a wired channel, an optical cable, and the like. The processor 803 is responsible for managing the bus architecture and general processing, and the memory 801 may store data used by the processor 803 when performing operations.

[0151] The processor 803 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a complex programmable logic device (CPLD). The processor may also adopt a multi-core architecture.

[0152] It should be noted here that the above-mentioned device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned method embodiment and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0153] Reference Figure 9 , shows a structural block diagram of an embodiment of a data extraction device of the present application, the device is used to extract data to be extracted in the uplink direction of a physical layer field programmable gate array FPGA of a base station subsystem, the data to be extracted includes ingress data or egress data, the device specifically includes:

[0154] Parameter configuration module 901, configured to configure parameter information of the data to be extracted, the parameter information including: optical port number, first subframe number, first symbol, first antenna number, first physical resource block number, the optical port number including the entry number or exit number of the data to be extracted;

[0155] a comparison and extraction module 902 for comparing the packet header format of the basic frame data of the optical port number with the parameter information; if the comparison result is a match, extracting the ingress data or egress data that matches the parameter information, and writing the extracted data into a random access memory;

[0156] The data reading module 903 is configured to read the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

[0157] Optionally, the parameter configuration module is specifically configured to configure parameter information of the data to be extracted by configuring fields of a preset register, wherein the fields of the preset register correspond to parameters in the parameter information;

[0158] The comparison and extraction module is specifically used to compare each field in the header format of the current basic frame data with each field of the preset register one by one to determine whether each field in the header format of the current basic frame data matches each field of the preset register, and the header format of the current basic frame data includes at least the following fields: a second subframe number, a second symbol, a second antenna number, and a second physical resource block number.

[0159] Optionally, in the case of extracting entry data matching the parameter information, the apparatus further comprises:

[0160] A clock processing module, configured to perform asynchronous clock domain processing on the input data to obtain processed input data;

[0161] The comparison and extraction module is specifically used to write the processed entry data into a random access memory.

[0162] Optionally, the comparison and extraction module includes:

[0163] an extraction submodule, configured to extract basic frame data of a preset length starting from the current basic frame data for the optical port number indicated in the parameter information when a header format of the current basic frame data matches the parameter information;

[0164] The writing submodule is used to package the extracted basic frame data of a preset length and write the data into a random access memory.

[0165] Optionally, the data reading module includes:

[0166] A default setting submodule, used to set the default channel of the PCIE interface to the physical random access channel PRACH message channel;

[0167] A first switching submodule is configured to release the PRACH message channel and switch to the uplink data channel upon receiving a request for the uplink data channel to occupy the PCIE interface, so as to read the extracted uplink data from the random access memory through the uplink data channel;

[0168] The second switching submodule is configured to switch to the PRACH message channel after the uplink data channel is released.

[0169] Optionally, the device further comprises:

[0170] The data analysis module is used to analyze the transmission data of the upper-level subsystem of the base station subsystem based on the extracted inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, so as to locate the abnormality of each subsystem of the base station.

[0171] It should be noted that the division of units in the embodiments of the present application is schematic and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0172] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0173] It should be noted here that the above-mentioned device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned method embodiment and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0174] The embodiment of the present disclosure also provides an electronic device, see Figure 10 , including: a processor 1001, a memory 1002, and a computer program 10021 stored in the memory and executable on the processor, wherein the processor implements the data extraction method of the aforementioned embodiment when executing the program.

[0175] An embodiment of the present disclosure further provides a processor-readable storage medium storing a computer program executable by a processor for executing the aforementioned data extraction method.

[0176] The processor-readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO)), optical storage (such as CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (such as ROMs, EPROMs, EEPROMs, non-volatile memories (NANDFLASH), solid-state drives (SSDs)), etc.

[0177] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems may also be used together with the teachings herein. Based on the above description, it is apparent that the structure required for constructing such systems is suitable. In addition, the embodiments of the present disclosure are not directed to any specific programming language. It should be understood that various programming languages ​​may be utilized to implement the contents of the embodiments of the present disclosure described herein, and the above description of specific languages ​​is intended to disclose the best mode of implementation of the embodiments of the present disclosure.

[0178] In the description provided herein, numerous specific details are described. However, it is understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0179] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present disclosure, various features of the embodiments of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed approach should not be interpreted as reflecting an intention that the claimed embodiments of the present disclosure require more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all of the features of the individual embodiments disclosed above. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present disclosure.

[0180] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition may be divided into multiple submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed herein may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0181] The various component embodiments of the embodiments of the present disclosure may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components of the sorting device according to the embodiments of the present disclosure. The embodiments of the present disclosure may also be implemented as a device or apparatus program for executing part or all of the methods described herein. Such a program implementing the embodiments of the present disclosure may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0182] It should be noted that the above embodiments illustrate rather than limit the embodiments of the present disclosure, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbols placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The embodiments of the present disclosure may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0183] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0184] The above description is merely a preferred embodiment of the embodiments of the present disclosure and is not intended to limit the embodiments of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the embodiments of the present disclosure shall be included in the protection scope of the embodiments of the present disclosure.

[0185] The above description is merely a specific implementation of the embodiments of the present disclosure, but the scope of protection of the embodiments of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the embodiments of the present disclosure should be included in the scope of protection of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure should be based on the scope of protection of the claims.

[0186] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) that contain computer-usable program code.

[0187] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0188] These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the processor-readable memory produce an article of manufacture comprising an instruction device that implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0189] These processor-executable instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0190] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A data extraction method, characterized in that: The method is used to extract data to be extracted in the uplink direction of a physical layer field programmable gate array (FPGA) of a base station subsystem, wherein the data to be extracted includes ingress data or egress data. The method comprises: Configuring parameter information of the data to be extracted, the parameter information including: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number, wherein the optical port number includes an entry number or an exit number of the data to be extracted; Comparing the packet header format of the basic frame data of the optical port number with the parameter information, if the comparison result is a match, extracting the ingress data or egress data that matches the parameter information, and writing the extracted data into a random access memory; The extracted uplink data is read from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

2. The method according to claim 1, characterized in that The parameter information for configuring the data to be extracted includes: Configuring parameter information of the data to be extracted by configuring fields of a preset register, wherein the fields of the preset register correspond to the parameters in the parameter information; The comparing the packet header format of the basic frame data of the optical port number with the parameter information includes: Each field in the header format of the current basic frame data is compared one by one with each field of the preset register to determine whether each field in the header format of the current basic frame data matches each field of the preset register, wherein the header format of the current basic frame data includes at least the following fields: a second subframe number, a second symbol, a second antenna number, and a second physical resource block number.

3. The method according to claim 1, characterized in that In the case of extracting entry data matching the parameter information, the method further comprises: Performing asynchronous clock domain processing on the input data to obtain processed input data; Writing the extracted data into a random access memory comprises: The processed entry data is written into a random access memory.

4. The method according to claim 1, wherein The extracting the inlet data or the outlet data matching the parameter information and writing the extracted data into a random access memory comprises: When the header format of the current basic frame data matches the parameter information, extracting basic frame data of a preset length starting from the current basic frame data for the optical port number indicated in the parameter information; The extracted basic frame data of the preset length is packaged and then written into a random access memory.

5. The method according to claim 1, wherein The method of reading the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface comprises: Setting the default channel of the PCIE interface to the physical random access channel PRACH message channel; Upon receiving a request for the uplink data channel to occupy the PCIE interface, releasing the PRACH message channel and switching to the uplink data channel to read the extracted uplink data from the random access memory through the uplink data channel; After the uplink data channel is released, the PRACH message channel is switched to.

6. The method according to claim 1, characterized in that After obtaining the extracted data from the random access memory, the method further includes: According to the extracted inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, the transmission data of the upper-level subsystem of the base station subsystem is analyzed to locate abnormalities in each subsystem of the base station.

7. A data extraction device, characterized in that: The device is used to extract data to be extracted in the uplink direction of a physical layer field programmable gate array (FPGA) of a base station subsystem, wherein the data to be extracted includes ingress data or egress data. The device includes a memory, a transceiver, and a processor, wherein the memory is used to store a computer program; the transceiver is used to transmit and receive data under the control of the processor; and the processor is used to read the computer program in the memory and perform the following operations: Configuring parameter information of the data to be extracted, the parameter information including: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number, wherein the optical port number includes an entry number or an exit number of the data to be extracted; Comparing the packet header format of the basic frame data of the optical port number with the parameter information, if the comparison result is a match, extracting the ingress data or egress data that matches the parameter information, and writing the extracted data into a random access memory; The extracted uplink data is read from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

8. The device according to claim 7, characterized in that The parameter information for configuring the data to be extracted specifically includes: Configuring parameter information of the data to be extracted by configuring fields of a preset register, wherein the fields of the preset register correspond to the parameters in the parameter information; The comparing the packet header format of the basic frame data of the optical port number with the parameter information includes: Each field in the header format of the current basic frame data is compared one by one with each field of the preset register to determine whether each field in the header format of the current basic frame data matches each field of the preset register, wherein the header format of the current basic frame data includes at least the following fields: a second subframe number, a second symbol, a second antenna number, and a second physical resource block number.

9. The device according to claim 7, characterized in that In the case of extracting entry data matching the parameter information, the processor is further configured to read the computer program in the memory and perform the following operations: Performing asynchronous clock domain processing on the input data to obtain processed input data; Writing the extracted data into a random access memory comprises: The processed entry data is written into a random access memory.

10. The device according to claim 7, characterized in that The extracting the inlet data or the outlet data matching the parameter information and writing the extracted data into a random access memory specifically includes: When the header format of the current basic frame data matches the parameter information, extracting basic frame data of a preset length starting from the current basic frame data for the optical port number indicated in the parameter information; The extracted basic frame data of the preset length is packaged and then written into a random access memory.

11. The device according to claim 7, characterized in that The method of reading the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface specifically includes: Setting the default channel of the PCIE interface to the physical random access channel PRACH message channel; Upon receiving a request for the uplink data channel to occupy the PCIE interface, releasing the PRACH message channel and switching to the uplink data channel to read the extracted uplink data from the random access memory through the uplink data channel; After the uplink data channel is released, the PRACH message channel is switched to.

12. The device according to claim 7, characterized in that The processor is further configured to read the computer program in the memory and perform the following operations: According to the extracted inbound data or outbound data of the physical layer FPGA of the base station subsystem in the uplink direction, the transmission data of the upper-level subsystem of the base station subsystem is analyzed to locate abnormalities in each subsystem of the base station.

13. A data extraction device, characterized in that: The device is used to extract data to be extracted in the uplink direction of a physical layer field programmable gate array (FPGA) of a base station subsystem, wherein the data to be extracted includes ingress data or egress data, and the device includes: A parameter configuration module, configured to configure parameter information of the data to be extracted, the parameter information including: an optical port number, a first subframe number, a first symbol, a first antenna number, and a first physical resource block number, wherein the optical port number includes an entry number or an exit number of the data to be extracted; a comparison and extraction module, configured to compare the packet header format of the basic frame data of the optical port number with the parameter information, and if the comparison result is a match, extract the ingress data or egress data that matches the parameter information, and write the extracted data into a random access memory; The data reading module is used to read the extracted uplink data from the random access memory by polling a high-speed serial computer expansion bus standard PCIE interface.

14. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the data extraction method according to any one of claims 1 to 6 is implemented.

15. A processor-readable storage medium, characterized in that: The processor-readable storage medium stores a computer program executable by a processor for executing the method according to any one of claims 1 to 6.

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