Array substrate and display device

Abstract

The present application discloses an array substrate and a display device. The array substrate includes a plurality of data lines, a plurality of driver chips and at least one signal transmission line. The driver chips are connected to the data lines in a one-to-one correspondence. The same signal transmission line is connected to at least two driver chips, and the same signal transmission line is configured to transmit data signals corresponding to at least two data lines and addressing signals corresponding to the data signals in a one-to-one correspondence. Each of the driver chips is used to output the corresponding data signal to the data line connected to the driver chip according to the addressing signal. The present application can effectively reduce the number of signal transmission lines, thereby improving the product yield.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Due to the difficulty in manufacturing, affected by impedance and yield, the production of super-large display screens often requires high technology and is difficult to produce. By arranging smaller display panels of uniform specifications neatly, a large-sized spliced ​​display screen can be obtained. Among them, the border width of the small-sized display panel will affect the look and feel of the spliced ​​display screen. In the splicing process, the splicing seams are mainly reduced by routing the lines on the side of the display panel. In addition, for a single display panel, the display of an area is now mostly controlled by COF (Chip On Flim), and COF has more output channels, which means that more signal lines will be input into the display panel.

[0003] If the related technology is still used to use one signal transmission line to transmit the data signal required by one data line, then as the display resolution increases, the number of signal transmission lines will also increase, and dense routing will easily lead to a decrease in product yield. Summary of the invention

[0004] The present application provides an array substrate and a display device to solve the technical problem in the prior art that there are too many signal transmission lines, resulting in reduced product yield.

[0005] The present application provides an array substrate, which includes:

[0006] Multiple data lines;

[0007] A plurality of driving chips, wherein the driving chips are connected to the data lines in a one-to-one correspondence;

[0008] at least one signal transmission line, the same signal transmission line being connected to at least two of the driving chips, and the same signal transmission line being configured to transmit data signals corresponding to at least two of the data lines and addressing signals corresponding one to one to the data signals;

[0009] Wherein, each of the driving chips is used to output the corresponding data signal to the data line connected to the driving chip according to the addressing signal.

[0010] Optionally, in some embodiments of the present application, each of the driver chips has an address signal, and the address signals of the multiple driver chips connected to the same signal transmission line are matched one-to-one with the addressing signal transmitted by the same signal transmission line.

[0011] Optionally, in some embodiments of the present application, each of the driving chips includes a matching module;

[0012] The matching module is used to read the addressing signal and match the addressing signal to match the address signal of the driving chip.

[0013] Optionally, in some embodiments of the present application, the driver chip has a control pin;

[0014] The array substrate also includes multiple control units, a first end of each control unit is connected to the control pin, a second end of each control unit is connected to the corresponding driver chip, and a third end of each control unit is connected to the corresponding data line, and the control unit is used to control the connection between the driver chip and the data line based on the potential of the control pin.

[0015] Optionally, in some embodiments of the present application, the control unit includes a transistor, a gate of the transistor is connected to the first end, a source of the transistor is connected to the second end, and a drain of the transistor is connected to the third end.

[0016] Optionally, in some embodiments of the present application, each of the control units is integrated inside the corresponding driver chip.

[0017] Optionally, in some embodiments of the present application, each of the driver chips includes a feedback pin, and the plurality of driver chips connected to the same signal transmission line are connected to each other through the feedback pin;

[0018] When each of the driving chips matches the corresponding addressing signal, a feedback signal is output to the adjacent driving chip.

[0019] Optionally, in some embodiments of the present application, the signal transmission line is further used to transmit an end signal corresponding one-to-one to the addressing signal and the data signal;

[0020] The same signal transmission line sequentially outputs the addressing signal, the data signal and the end signal corresponding to the plurality of data lines.

[0021] Optionally, in some embodiments of the present application, the addressing signal includes a first characteristic value and a first address, and the data signal includes a second characteristic value and a grayscale signal.

[0022] Optionally, in some embodiments of the present application, the array substrate includes a first surface, a second surface and a side surface respectively adjacent to the first surface and the second surface, the data line and the driving chip are arranged on the first surface, and the signal transmission line is arranged on the first surface and extends to the second surface through the side surface.

[0023] Correspondingly, the present application also provides a display device, which includes at least one display unit and at least one source driver chip connected to the display unit, the display unit includes any of the array substrates described above, and the source driver chip is connected to the signal transmission line.

[0024] The present application provides an array substrate and a display device. The array substrate includes a plurality of data lines, a plurality of driver chips and at least one signal transmission line. The present application sets a driver chip corresponding to each data line, and the same signal transmission line transmits an addressing signal corresponding to the data signal one by one while transmitting the data signals corresponding to the plurality of data lines. Then, each driver chip can output the corresponding data signal to the data line connected to the driver chip according to the addressing signal, thereby effectively reducing the number of signal transmission lines and improving the yield of the product. In addition, both the data signal and the addressing signal are transmitted by the signal transmission line, which can further reduce the routing in the array substrate and reduce the routing density. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 is a first structural schematic diagram of an array substrate provided in the present application;

[0027] Figure 2 This is a first signal structure diagram transmitted by a signal transmission line provided by the present application;

[0028] Figure 3 is a second signal structure diagram transmitted by the signal transmission line provided by the present application;

[0029] Figure 4 is a second structural schematic diagram of the array substrate provided by the present application;

[0030] Figure 5 is a third structural schematic diagram of the array substrate provided in the present application;

[0031] Figure 6 is a fourth structural schematic diagram of the array substrate provided in the present application;

[0032] Figure 7 It is a structural schematic diagram of a display device provided in this application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0034] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first" and "second" etc. may explicitly or implicitly include one or more of the features, and therefore should not be understood as limiting this application.

[0035] The present application provides an array substrate and a display device, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.

[0036] See also Figure 1 , Figure 1 1 is a first structural schematic diagram of an array substrate provided in the present application. In the embodiment of the present application, the array substrate 100 includes a plurality of data lines 10 , a plurality of driving chips 20 and at least one signal transmission line 30 .

[0037] The driving chips 20 are connected to the data lines 10 in a one-to-one correspondence. The same signal transmission line 30 is connected to at least two driving chips 20. The same signal transmission line 30 is configured to transmit data signals corresponding to at least two data lines 10 and addressing signals corresponding to the data signals in a one-to-one correspondence.

[0038] Among them, the number of data lines 10 is set according to the size and resolution of the array substrate 100. The signal transmission line 30 can be set to one, two, three or more. For example, when the signal transmission line 30 is set to one, all data lines 10 are connected to the same signal transmission line 30 through the corresponding driver chip 20. At this time, during the scanning time of each row of pixels, the signal transmission line 30 must output the data signals corresponding to all data lines 10 and the addressing signals corresponding to the data signals one by one. Of course, in order to improve the transmission efficiency of the data signal and ensure the charging rate, a plurality of signal transmission lines 30 can be set in the embodiment of the present application. The number of signal transmission lines 30 can be determined by the number of data lines 10 and the number of driver chips 20 connected to each signal transmission line 30.

[0039] The same signal transmission line 30 is configured to transmit data signals corresponding to at least two data lines 10 and addressing signals corresponding to the data signals one by one, which means that within the same row of pixel scanning time, one signal transmission line 30 sequentially outputs data signals corresponding to multiple data lines 10 and addressing signals corresponding to the data signals one by one. For example, one signal transmission line 30 sequentially outputs addressing signal-data signal-addressing signal-data signal, etc.

[0040] The addressing signal is an address segment used to identify multiple data signals output by the same signal transmission line 30. The driver chip 20 can select and output a data signal corresponding to the data line 10 connected to the driver chip 20 from among the multiple data signals according to the addressing signal.

[0041] In the present application, a driver chip 20 is provided for each data line 10, and the same signal transmission line 30 transmits the addressing signal corresponding to the data signal while transmitting the data signals corresponding to the multiple data lines 10. Then, each driver chip 20 can output the corresponding data signal to the data line 10 connected to the driver chip 20 according to the addressing signal, thereby effectively reducing the number of signal transmission lines 30 and improving the yield of the product. In addition, the data signal and the addressing signal are both transmitted by the signal transmission line 30, which can further reduce the routing in the array substrate 100 and reduce the routing density.

[0042] In the embodiment of the present application, when the same signal transmission line 30 sequentially outputs addressing signals and data signals corresponding to multiple data lines 10, each driver chip 20 can determine whether to output the data signal corresponding to the addressing signal according to the order of the read addressing signals.

[0043] For example, Figure 2 As shown, Figure 2 1 is a first signal structure diagram of the signal transmission line provided by the present application. When the same signal transmission line 30 is connected to 6 driver chips 20, the same signal transmission line 30 needs to sequentially output the data signals and addressing signals corresponding to the 6 data lines 10 ( Figure 2 Only part is shown in the figure). When the first driver chip 20 reads the first addressing signal, it outputs the data signal corresponding to the first addressing signal. When the second driver chip 20 reads the second addressing signal, it does not output the data signal corresponding to the second addressing signal. When the second driver chip 20 reads the second addressing signal, it outputs the data signal corresponding to the second addressing signal. And so on, which will not be repeated here one by one.

[0044] The signal transmission line 30 is also used to transmit an end signal corresponding to the address signal and the data signal. The same signal transmission line 30 sequentially outputs the address signal, the data signal and the end signal corresponding to multiple data lines.

[0045] It is understandable that, since the same signal transmission line 30 is used to transmit data signals corresponding to at least two data lines 10 and addressing signals corresponding to the data signals one by one, each driver chip 20 needs to match at least two addressing signals to determine whether the corresponding data signal should be output to the corresponding data line 10. In this regard, adding an end signal between the current data signal and the next addressing signal can extend the matching time of the driver chip 20 for each addressing signal and improve the matching accuracy, thereby avoiding data signal output errors.

[0046] Further, such as Figure 3 As shown, Figure 3 1 is a second signal structure diagram of the signal transmission line provided by the present application. In the embodiment of the present application, the addressing signal includes a first characteristic value and an address. The data signal includes a second characteristic value and a grayscale signal. The end signal includes a third characteristic value and an end.

[0047] Among them, the first characteristic value, the second characteristic value and the third characteristic value can all be a string of specific binary characters. For example, the first characteristic value is 111, the second characteristic value is 101, and the third characteristic value is 000. Then when the driver chip 20 detects the string of characters 111, it is considered that the data packet is an addressing signal. After the string of characters representing the first characteristic value ends transmission, the subsequent data is considered to be address information. When the driver chip 20 detects the second characteristic value, it is considered that the addressing signal transmission is completed, and then the data signal should be transmitted. The end signal is similar and will not be repeated.

[0048] Among them, the first characteristic value, the second characteristic value and the third characteristic value are all the same for the plurality of data lines 10. In the embodiment of the present application, by setting characteristic values ​​in the addressing signal, the data signal and the end signal, when the driver chip 20 determines that the current addressing signal does not match and needs to continue to compare the next addressing signal, it can be ensured that the driver chip 20 determines the addressing signal instead of the data signal or the end signal, thereby improving the matching accuracy of the addressing signal.

[0049] See also Figure 4 , Figure 4 is a second structural schematic diagram of the array substrate provided in this application. Figure 1 The difference of the array substrate 100 shown is that, in the embodiment of the present application, the driver chip 20 has a control pin A. Initially, the control pin A has a first potential. When the driver chip 20 matches the data signal corresponding to the data line 10 connected to the driver chip 20 according to the addressing information, the potential of the control pin A is changed to a second potential.

[0050] Further, the array substrate 100 further includes a plurality of control units 40. A first end of each control unit 40 is connected to the control pin A. A second end of each control unit 40 is connected to a corresponding driver chip 20. A third end of each control unit 40 is connected to a corresponding data line 10. The control unit 40 is used to control the connection between the driver chip 20 and the data line 10 based on the potential of the control pin A.

[0051] Wherein, when the first potential is a high level potential, the second level is a low level potential. When the first potential is a low level potential, the second level is a high level potential. The specific setting can be made according to the specific circuit structure of the control unit 40.

[0052] Therefore, when the driver chip 20 matches the corresponding addressing signal, the corresponding data signal can be output to the data line 10 connected to the driver chip 20, thereby preventing the driver chip 20 from erroneously outputting other data signals to the data line 10 connected thereto, thereby improving the accuracy of data signal transmission.

[0053] Optionally, in some embodiments of the present application, the control unit 40 includes a transistor T. The gate of the transistor T is connected to the control pin A. The source of the transistor T is connected to the driving chip 20 . The drain of the transistor T is connected to the data line 10 .

[0054] Among them, the transistor T in the embodiment of the present application can be one or more of a low-temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor or an amorphous silicon thin film transistor. In addition, each transistor T can also be a P-type transistor or an N-type transistor. When the transistor T is a P-type transistor, when the first potential is a high-level potential, the second level is a low-level potential. When the transistor T is an N-type transistor, when the first potential is a low-level potential, the second level is a high-level potential. Furthermore, the transistors T in the embodiment of the present application can be set to the same type of transistors, so as to avoid the differences between different types of transistors T from having an adverse effect on the touch sensitivity.

[0055] In the embodiment of the present application, the channel length-width ratios of the transistors T in the multiple control units 40 are all equal. It can be understood that the channel length-width ratio of the transistor T affects the resistance of the transistor T, that is, affects the conductivity of the transistor T. In the embodiment of the present application, the channel length-width ratios of the transistors T are set to be equal, which can reduce the difference in data voltages transmitted to each data line 10 and improve display uniformity.

[0056] Of course, in other embodiments of the present application, the control unit 40 may also include other switching elements or voltage stabilizing elements, which are not described in detail here.

[0057] In an embodiment of the present application, each control unit 40 can be arranged between the driver chip 20 and the data line 10 to control the connection between the driver chip 20 and the data line 10. In other embodiments of the present application, each control unit 40 can be integrated inside the corresponding driver chip 20. Integrating the control unit 40 inside the driver chip 20 can improve the integration of the driver chip 20, while further reducing the number of wirings on the array substrate 100, and avoiding poor signal transmission due to dense wiring. In an embodiment of the present application, the array substrate 100 includes a first surface 10a, a second surface 10b, and a side surface (not shown in the figure) adjacent to the first surface 10a and the second surface 10b respectively. The data line 10 and the driver chip 20 are arranged on the first surface 10a. The signal transmission line 30 is arranged on the first surface 10a and extends to the second surface 10b through the side.

[0058] Therefore, when a display panel is made by using the array substrate 100 in the embodiment of the present application, the border width of the display panel can be reduced. In addition, when a spliced ​​screen is made by using the array substrate 100 in the embodiment of the present application, the side wiring can be reduced. Since the side wiring process is relatively immature, the yield of the spliced ​​product can be improved.

[0059] See also Figure 5 , Figure 5 is a third structural schematic diagram of an array substrate provided in this application. Figure 4 The difference of the array substrate 100 shown is that in the embodiment of the present application, each driver chip 20 has an address signal. The address signals of multiple driver chips 20 connected to the same signal transmission line 30 are matched one by one with the addressing signal transmitted by the same signal transmission line 30.

[0060] The address signal of each driver chip 20 and the corresponding addressing signal can be exactly the same. The address signal of each driver chip 20 and the corresponding addressing signal can also be different, but can match each other according to the same rule. The address signal and the addressing signal can be numbers or letters. The bytes of the address signal and the addressing signal are not limited, and can be one byte or multiple bytes.

[0061] Thus, each driver chip 20 can identify the addressing signal that matches it according to its own address signal, and then output the data signal corresponding to the matching addressing signal. Data signals corresponding to other addressing signals that do not match the address signal of the driver chip 20 will not be output by the same driver chip 20. Thus, multiple data signals output by the same signal transmission line 30 are respectively output to the corresponding data lines 10 to achieve normal display.

[0062] Specifically, in the embodiment of the present application, each driver chip 20 includes a matching module 21. The matching module 21 is used to read the addressing signal and match the addressing signal that matches the address signal of the driver chip 20.

[0063] For example, the matching module 21 may include a storage unit, a reading unit, and a comparison unit. The storage unit is used to store the address information of the driver chip 20. The reading unit is used to read the current addressing information transmitted to the driver chip 20 by the signal transmission line 30. The comparison unit is used to retrieve the current addressing information read by the reading unit and the address information stored by the storage unit, and compare the two to determine whether the current addressing signal matches the address signal of the driver chip 20. If they match, the data signal corresponding to the current addressing signal is output, and the matching action is stopped. If they do not match, the reading unit continues to read the next addressing signal, and the cycle repeats until an addressing signal matching the address signal of the driver chip 20 is found, and the corresponding data signal is output.

[0064] When the driving chip 20 does not have an addressing signal, the storage unit of each driving chip 20 may also directly store an addressing signal corresponding to the data signal that should be output by the driving chip 20 .

[0065] In the embodiment of the present application, a matching module 21 is provided in the driving chip 20. By comparing the addressing signal through the matching module 21, the accuracy of data signal transmission can be improved.

[0066] See also Figure 6 , Figure 6 is a fourth structural schematic diagram of an array substrate provided in the present application. Figure 1 Each driver chip 20 shown includes a feedback pin B. Multiple driver chips 20 connected to the same signal transmission line 30 are connected to each other through the feedback pin B. When each driver chip 20 matches a corresponding addressing signal, it outputs a feedback signal to an adjacent driver chip 20 .

[0067] Among them, two adjacent driver chips 20 can output feedback signals to each other. The same driver chip 20 can output a feedback signal to at least one of the driver chips 20 located on both sides thereof. Thus, any driver chip 20 can know the matching status of the adjacent driver chip 20. When one of the driver chips 20 learns that the adjacent driver chip 20 matches the corresponding addressing signal, it outputs the corresponding data signal, which can improve the synchronization of the data signals output by multiple driver chips 20 to a certain extent. Thereby, the charging uniformity can be improved.

[0068] Accordingly, the present application also provides a display device. The display device includes at least one display unit and at least one source driver chip connected to the display unit. The display unit includes the array substrate described in any of the above embodiments, which will not be described one by one here.

[0069] The display device provided in the present application may be a smart phone, a tablet computer, an e-book reader, a smart watch, a camera, a game console, etc., and the present application does not limit this.

[0070] For details, please refer to Figure 7 , Figure 7 : is a structural schematic diagram of a display device provided by the present application. The display device includes at least one display unit 200 and at least one source driver chip 300. The display unit 200 includes the array substrate described in any of the above embodiments. The source driver chip 300 can be arranged above the display unit 200, or it can be arranged below the display unit 200. Of course, the source driver chip 300 can also be arranged on the side of the display unit 200 away from the light-emitting surface. That is, the source driver chip 300 can be arranged on the second side of the array substrate in the above embodiment. The source driver chip 300 is used to transmit data signals and addressing signals to the array substrate of the display unit 200. In some embodiments, the source driver chip 300 can be bound to the display unit 200 through COF (Chip On Film), and this application does not make specific limitations on this.

[0071] When the display device 1000 is a spliced ​​screen, the display device 1000 may include at least two display units 200. The display unit 200 may be a liquid crystal display panel or a light emitting diode display panel, which is not limited in the present application.

[0072] In the display device 1000 of the embodiment of the present application, the display device 1000 includes at least one display unit 200. Each display unit 200 includes an array substrate. The array substrate includes multiple data lines, multiple driver chips and at least one signal transmission line. In the embodiment of the present application, a driver chip is provided for each data line, and the same signal transmission line transmits an addressing signal corresponding to the data signal one by one while transmitting the data signals corresponding to the multiple data lines. Then, each driver chip can output the corresponding data signal to the data line connected to the driver chip according to the addressing signal, thereby effectively reducing the number of signal transmission lines, thereby reducing the side wiring. Since the side wiring process is relatively immature, the embodiment of the present application can improve the yield of the display device 1000.

[0073] The array substrate and display device provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: Multiple data lines; A plurality of driving chips, wherein the driving chips are connected to the data lines in a one-to-one correspondence; at least one signal transmission line, the same signal transmission line being connected to at least two of the driving chips, and the same signal transmission line being configured to transmit data signals corresponding to at least two of the data lines and addressing signals corresponding one to one to the data signals; Each of the driver chips is used to output the corresponding data signal to the data line connected to the driver chip according to the addressing signal; Each of the driving chips comprises a feedback pin, and a plurality of the driving chips connected to the same signal transmission line are connected to each other through the feedback pin; When each of the driving chips matches the corresponding addressing signal, a feedback signal is output to the adjacent driving chip.

2. The array substrate according to claim 1, characterized in that: Each of the driving chips has an address signal, and the address signals of the plurality of driving chips connected to the same signal transmission line are matched one by one with the addressing signal transmitted by the same signal transmission line.

3. The array substrate according to claim 2, characterized in that: Each of the driving chips includes a matching module; The matching module is used to read the addressing signal and match the addressing signal to match the address signal of the driving chip.

4. The array substrate according to claim 1, characterized in that: The driving chip has a control pin; The array substrate also includes multiple control units, a first end of each control unit is connected to the control pin, a second end of each control unit is connected to the corresponding driver chip, and a third end of each control unit is connected to the corresponding data line, and the control unit is used to control the connection between the driver chip and the data line based on the potential of the control pin.

5. The array substrate according to claim 4, characterized in that: The control unit includes a transistor, a gate of the transistor is connected to the first end, a source of the transistor is connected to the second end, and a drain of the transistor is connected to the third end.

6. The array substrate according to claim 4, characterized in that: Each of the control units is integrated inside the corresponding driving chip.

7. The array substrate according to claim 1, characterized in that: The signal transmission line is also used to transmit an end signal corresponding to the addressing signal and the data signal one by one; The same signal transmission line sequentially outputs the addressing signal, the data signal and the end signal corresponding to the plurality of data lines.

8. The array substrate according to claim 1, characterized in that: The addressing signal includes a first characteristic value and a first address, and the data signal includes a second characteristic value and a grayscale signal.

9. The array substrate according to claim 1, characterized in that: The array substrate includes a first surface, a second surface and a side surface adjacent to the first surface and the second surface respectively. The data line and the driving chip are arranged on the first surface. The signal transmission line is arranged on the first surface and extends to the second surface through the side surface.

10. A display device, characterized in that: It comprises at least one display unit and at least one source driver chip connected to the display unit, wherein the display unit comprises the array substrate according to any one of claims 1 to 9.

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