Radiation-resistant magnetic storage unit, memory and device

Abstract

The present invention provides a radiation-resistant magnetic storage unit, a memory, and a device. The unit includes a first switching element, a first isolation unit, a second switching element, a second isolation unit, and a magnetic memory. The magnetic memory includes a spin-orbit moment layer and a magnetic tunnel junction provided on the spin-orbit moment layer. The first switching element is respectively connected to a write signal input end of the spin-orbit moment layer and a memory array bit line, and the first isolation unit is respectively connected to a write signal output end of the spin-orbit moment layer and a memory array source line. One end of the second switching element is connected to the top of the magnetic tunnel junction through the second isolation unit, and the other end is connected to the memory array bit line. The second isolation unit is in a conducting state. The present invention can improve the radiation resistance and reliability of the magnetic memory device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a radiation-resistant magnetic storage unit, a memory and a device. Background Art

[0002] As semiconductor process sizes continue to shrink, Moore's Law slows, and increased leakage current and interconnect delays become bottlenecks for traditional CMOS memory. Magnetic random access memory (MRAM), with its advantages of unlimited erase and write cycles, non-volatility, fast read and write speeds, and radiation resistance, is poised to become a universal memory and an ideal device for building next-generation non-volatile main memory and cache. The magnetic tunnel junction (MTJ) is the fundamental storage unit of MRAM. Second-generation spin-transfer torque (STT-MRAM) suffers from drawbacks such as long incubation times and read-write interference, limiting its further development. Spin-orbit torque MRAM (SOT-MRAM) has attracted widespread attention from both industry and academia due to its advantages such as fast write speeds, separate read and write paths, and low power consumption.

[0003] However, the sub-nanosecond write speed of SOT-MRAM makes the magnetization switching speed of the SOT-MTJ close to the width of the radiation current pulse, making the SOT-MTJ storage state susceptible to single-event transient disturbances. This makes the SOT-MRAM write mechanism sensitive to single-event upsets (SEUs) and multiple-bit upsets (MBUs). When the memory array is bombarded by high-energy particles, electron-hole pairs are easily generated inside the sensitive transistor switching elements of the SOT-MRAM, forming parasitic transient current pulses, which can cause soft errors such as SEUs and MBUs. Summary of the Invention

[0004] One object of the present invention is to provide a radiation-resistant magnetic storage unit to improve the radiation resistance and reliability of magnetic storage devices. Another object of the present invention is to provide a radiation-resistant magnetic storage device. Another object of the present invention is to provide a computer device.

[0005] In order to achieve the above objectives, the present invention discloses, on one hand, a radiation-resistant magnetic storage unit, comprising a first switching element, a first isolation unit, a second switching element, a second isolation unit, and a magnetic memory;

[0006] The magnetic memory includes a spin-orbit moment layer and a magnetic tunnel junction provided on the spin-orbit moment layer;

[0007] The first switch element is connected to the write signal input end of the spin-track moment layer and the memory array bit line respectively, and the first isolation unit is connected to the write signal output end of the spin-track moment layer and the memory array source line respectively;

[0008] One end of the second switch element is connected to the top of the magnetic tunnel junction through the second isolation unit, and the other end is connected to the memory array bit line, and the second isolation unit is in a conducting state;

[0009] When writing data, the first switching element turns on the storage array bit line and the spin-orbit moment layer in response to a first write signal, and the first isolation unit turns on the storage array source line and the spin-orbit moment layer in response to a second write signal; when reading data, the second switching element turns on the storage array bit line and the magnetic tunnel junction in response to a first read signal, and the first isolation unit turns on the storage array source line and the spin-orbit moment layer in response to a second read signal.

[0010] Preferably, the first switching element is a first transistor;

[0011] The control end of the first transistor is connected to the first signal end for inputting the first write signal, the first end is connected to the memory array bit line, and the second end is connected to the write signal input end of the spin-track moment layer.

[0012] Preferably, the first isolation unit includes a third switching element;

[0013] The third switch element conducts the memory array source line and the spin-track moment layer in response to a second write signal, and conducts the memory array source line and the spin-track moment layer in response to a second read signal.

[0014] Preferably, the third switching element is a second transistor;

[0015] The control end of the second transistor is respectively connected to the second signal end for inputting the second write signal and the third signal end for inputting the second read signal, the first end is connected to the write signal output end of the spin-track moment layer, and the second end is connected to the storage array source line.

[0016] Preferably, the second switching element is a third transistor;

[0017] The control end of the third transistor is connected to the fourth signal end for inputting the first read signal, the first end is connected to the memory array bit line, the second end is connected to the second isolation unit, the first end is a source end, and the second end is a drain end.

[0018] Preferably, the second isolation unit includes a fourth switching element;

[0019] The fourth switch element is in a turned-on state based on a preset signal.

[0020] Preferably, the fourth switching element is a fourth transistor;

[0021] The control end of the fourth transistor is connected to the preset signal end, is in a conductive state based on a preset signal of the preset signal end, has a first end connected to the second switch element, and has a second end connected to the top of the magnetic tunnel junction.

[0022] Preferably, the magnetic memory comprises a reference layer, a barrier layer and a free layer arranged in sequence from top to bottom;

[0023] The bottom surface of the free layer and the top surface of the spin-orbit moment layer are fixedly arranged;

[0024] A top surface of the reference layer is connected to the second isolation unit.

[0025] The present invention also discloses a radiation-resistant magnetic memory, comprising a plurality of the radiation-resistant magnetic storage units described above arranged in an array.

[0026] The present invention also discloses a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0027] The processor and / or the memory include the radiation-hardened magnetic storage unit as described above.

[0028] The radiation-resistant magnetic storage unit of the present invention includes a first switching element, a first isolation unit, a second switching element, a second isolation unit, and a magnetic storage device. The magnetic storage device includes a spin-orbit moment layer and a magnetic tunnel junction disposed on the spin-orbit moment layer. The first switching element is connected to a write signal input terminal of the spin-orbit moment layer and a storage array bit line, respectively. The first isolation unit is connected to a write signal output terminal of the spin-orbit moment layer and a storage array source line, respectively. One end of the second switching element is connected to the top of the magnetic tunnel junction via the second isolation unit, and the other end is connected to the storage array bit line. The second isolation unit is in a conductive state. Thus, when writing data, the first switching element, which may be in a reverse bias condition in other magnetic storage cells in the same column as the magnetic storage device, is isolated from the storage array source line by the first isolation unit, preventing the first switching element from being susceptible to particle flipping and causing soft errors when in a reverse bias condition. Similarly, the second switching elements of other magnetic storage cells in the same column as the magnetic storage device are isolated from the magnetic tunnel junction by the second isolation unit, preventing particle flipping from affecting the second switching elements and causing soft errors, thereby improving the radiation resistance and storage reliability of the magnetic storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 A schematic diagram showing a sensitive node in a magnetic random access memory in the prior art;

[0031] Figure 2 A schematic diagram showing a sensitive node in a magnetic random access memory cell in the prior art;

[0032] Figure 3 A schematic diagram showing a specific embodiment of a magnetic random access memory cell according to the present invention;

[0033] Figure 4 A schematic structural diagram of a computer device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] It should be noted that, in one or more embodiments of the present invention, STT stands for spin transfer torque, a technology that can flip the magnetic moment of a magnetic tunnel junction device.

[0036] It should be noted that in one or more embodiments of the present invention, SOT stands for spin-orbit moment. There is a heavy metal layer under the magnetic tunnel junction. The technology in which current flows through the heavy metal layer to flip the magnetic moment of the magnetic tunnel junction generally requires external magnetic field assistance.

[0037] like Figure 1As shown, in the magnetic random access memory in the prior art, when a write operation is performed on the MTJ0 of a certain SOT selected by addressing, the unselected transistors NMOS11 in the column where the MTJ0 is located are all sensitive tubes. The sensitive path is composed of the unselected SOT-MTJ device and the bit line (Bit Line, BL) and source line (Source Line, SL) of the selected unit, thereby affecting the storage state of the unselected SOT-MTJ in the column. When the read operation is performed, a read error is caused. In addition, during the write process, the read selection transistor NMOS10 of the selected SOT-MTJ is in the off state, and its drain terminal A is a single-particle sensitive node, which has a write interference problem. In short, the node in the SOT-MTJ memory cell where the transistor is directly connected to the MTJ port, and the node has a reverse bias condition, is likely to be a sensitive node.

[0038] like Figure 2 As shown in the figure, the structural characteristics of the SOT-MTJ three-port device can achieve read-write circuit isolation. However, the drain terminal of the write gate transistor NMOS20 is connected to the heavy metal layer. When the write current Iread0 direction is from SL to BL, the drain terminal of the other turned-off write gate transistors in the column is in a reverse voltage bias state, which is a single-particle sensitive node. In addition, for the SOT-MTJ to be written, the turned-off read gate transistor NMOS21 also has a reverse voltage bias state at the drain terminal, which is a single-particle sensitive node.

[0039] Therefore, to address the problem in the prior art that SOT-MRAM storage arrays are susceptible to SEU and MBU interference, the present invention proposes a radiation-resistant magnetic storage unit, memory, and device, which can effectively improve the radiation resistance and reliability of non-volatile storage units.

[0040] Based on this, according to one aspect of the present invention, this embodiment discloses a radiation-resistant magnetic storage unit, wherein the radiation-resistant magnetic storage unit includes a first switching element, a first isolation unit, a second switching element, a second isolation unit, and a magnetic memory.

[0041] The magnetic memory includes a spin-orbit moment layer 4 and a magnetic tunnel junction provided on the spin-orbit moment layer 4 .

[0042] The first switch element is connected to the write signal input terminal of the spin-track moment layer 4 and the memory array bit line BL respectively. The first isolation unit is connected to the write signal output terminal of the spin-track moment layer 4 and the memory array source line SL respectively.

[0043] One end of the second switch element is connected to the top of the magnetic tunnel junction through the second isolation unit, and the other end is connected to the memory array bit line BL. The second isolation unit is in a conducting state.

[0044] When writing data, the first switching element turns on the storage array bit line BL and the spin-orbit moment layer 4 in response to a first write signal, and the first isolation unit turns on the storage array source line SL and the spin-orbit moment layer 4 in response to a second write signal; when reading data, the second switching element turns on the storage array bit line BL and the magnetic tunnel junction in response to a first read signal, and the first isolation unit turns on the storage array source line SL and the spin-orbit moment layer 4 in response to a second read signal.

[0045] The radiation-resistant magnetic storage unit of the present invention includes a first switching element, a first isolation unit, a second switching element, a second isolation unit, and a magnetic storage unit. The magnetic storage unit includes a spin-orbit moment layer 4 and a magnetic tunnel junction disposed on the spin-orbit moment layer 4. The first switching element is connected to a write signal input terminal of the spin-orbit moment layer 4 and a storage array bit line BL, respectively. The first isolation unit is connected to a write signal output terminal of the spin-orbit moment layer 4 and a storage array source line SL, respectively. One end of the second switching element is connected to the top of the magnetic tunnel junction via the second isolation unit, and the other end is connected to the storage array bit line BL. The second isolation unit is in a conductive state. Thus, when writing data, the first switching element, which may be in a reverse bias condition with other magnetic storage cells in the same column as the magnetic storage unit, is isolated from the storage array source line SL by the first isolation unit, thereby preventing the first switching element from being susceptible to particle flips and causing soft errors when in a reverse bias state. Similarly, the second switching elements of other magnetic storage cells in the same column as the magnetic storage cell are isolated from the magnetic tunnel junction by the second isolation unit, thereby preventing particle flipping from affecting the second switching elements and causing soft errors, thereby improving the radiation resistance and storage reliability of the magnetic storage device.

[0046] In a preferred embodiment, see Figure 3 The first switching element is a first transistor NMOS1. The control terminal of the first transistor NMOS1 is connected to the first signal terminal WWL1 inputting the first write signal, the first terminal is connected to the memory array bit line BL, and the second terminal is connected to the write signal input terminal of the spin-track moment layer 4.

[0047] Specifically, in this preferred embodiment, the first transistor NMOS1 is a write-enable transistor. When writing data, the first transistor NMOS1 receives a first write signal sent by the first signal terminal WWL1 and connects the memory array bit line BL to the write signal input terminal of the spin-orbit moment layer 4. Under the action of a second write signal, the first isolation unit connects the memory array source line SL to the write signal input terminal of the spin-orbit moment layer 4. Consequently, a path is formed between the memory array source line SL and the memory array bit line BL via the first transistor NMOS1, the spin-orbit moment layer 4, and the first isolation unit. This allows an SOT current Iwrite to be input from the memory array source line SL or the memory array bit line BL to the spin-orbit moment layer 4, causing a deterministic flip in the magnetic moment of the free layer 3 of the magnetic tunnel junction, thereby enabling data writing.

[0048] In a preferred embodiment, the first isolation unit includes a third switch element, wherein the third switch element conducts between the memory array source line SL and the spin-track moment layer 4 in response to a second write signal and conducts between the memory array source line SL and the spin-track moment layer 4 in response to a second read signal.

[0049] Specifically, in the prior art, the spin-orbit moment layer 4 is directly connected to the storage array source line SL. When an SOT current Iwrite is input from the storage array source line SL to the spin-orbit moment layer 4 for data writing, the write-select transistors in other magnetic storage cells are directly connected to the spin-orbit moment layer 4 and are reverse-biased by the SOT current Iwrite from the storage array source line SL. This makes them susceptible to particle flipping in the magnetic tunnel junction during data writing, causing soft errors and altering the stored data. Compared to the prior art, the present invention isolates the storage array source line SL from the spin-orbit moment layer 4 through a first isolation unit. When no data is being written to the magnetic tunnel junction, the first isolation unit is disconnected, and the node connecting the first switching element to the spin-orbit moment layer 4 is always in a low voltage state, thereby preventing the first switching element from being reverse-biased and eliminating sensitive nodes in the first switching element.

[0050] In a preferred embodiment, see Figure 3 The third switching element is a second transistor NMOS2. The control terminal of the second transistor NMOS2 is connected to a second signal terminal WWL2 for inputting the second write signal and a third signal terminal RWL1 for inputting the second read signal, respectively. A first terminal of the second transistor NMOS2 is connected to a write signal output terminal of the spin-track moment layer 4, and a second terminal of the second transistor NMOS2 is connected to the memory array source line SL.

[0051] Specifically, in this preferred embodiment, the third switching element is a second transistor NMOS2. When writing data, the second transistor NMOS2 receives a second write signal sent by the second signal terminal WWL2 and connects the storage array source line SL to the write signal output terminal of the spin-orbit moment layer 4. Simultaneously, under the action of the first write signal, the first switching element connects the storage array bit line BL to the write signal input terminal of the spin-orbit moment layer 4. Thus, a path is formed between the storage array source line SL and the storage array bit line BL via the first switching element (e.g., the first transistor NMOS1), the spin-orbit moment layer 4, and the second transistor NMOS2. This allows an SOT current Iwrite to be input from the storage array source line SL or the storage array bit line BL to the spin-orbit moment layer 4, causing a deterministic flip in the magnetic moment of the free layer 3 of the magnetic tunnel junction, thereby achieving data writing.

[0052] Similarly, when reading data, the second transistor NMOS2 receives the second read signal sent by the third signal terminal RWL1 and connects the storage array source line SL to the write signal output terminal of the spin-orbit moment layer 4. Simultaneously, the second switch element, under the action of the first read signal, connects the storage array bit line BL to the top of the magnetic tunnel junction. Consequently, a path is formed between the storage array source line SL and the storage array bit line BL via the second switch element, the second isolation unit, the magnetic tunnel junction, the spin-orbit moment layer 4, and the first isolation unit. A read current Iread can be input from the storage array source line SL or the storage array bit line BL through the spin-orbit moment layer 4 to the magnetic tunnel junction, thereby determining the resistance state of the magnetic tunnel junction and, therefore, the data stored in the magnetic tunnel junction, thereby enabling data reading.

[0053] It can be understood that when an SOT current is input from the memory array bit line BL to the memory array source line SL, the first switching elements of the other magnetic memory cells are in an off state, thereby disconnecting the memory array bit line BL from the spin-orbit moment layer 4. The node connecting the second transistor NMOS2 to the spin-orbit moment layer 4 is always in a low voltage state, thereby preventing the second transistor NMOS2 from being in a reverse bias state, eliminating sensitive nodes in the second transistor NMOS2, and avoiding the introduction of new sensitive nodes. Furthermore, the first switching element and the third switching element are respectively the first transistor NMOS1 and the second transistor NMOS2, ensuring the symmetry of the write path, avoiding asymmetry in the drive capability of the write gate transistor, and improving the reliability of data writing.

[0054] In a preferred embodiment, see Figure 3 The second switch element is a third transistor NMOS3. The control terminal of the third transistor NMOS3 is connected to the fourth signal terminal RWL2 for inputting the first read signal, the first terminal is connected to the memory array bit line BL, the second terminal is connected to the second isolation unit, the first terminal is a source terminal, and the second terminal is a drain terminal.

[0055] Specifically, in this preferred embodiment, the third transistor NMOS3 is a read-select transistor. When reading data, the third transistor NMOS3 receives a first read signal sent by the fourth signal terminal RWL2 and conducts between the storage array bit line BL and the second isolation unit. The second isolation unit is in an on state, conducting between the third transistor NMOS3 and the top of the magnetic tunnel junction. Thus, a path is formed between the storage array bit line BL and the storage array source line SL via the third transistor NMOS3, the second isolation unit, the magnetic tunnel junction, the spin-track moment layer 4, and the first isolation unit. This allows a read current Iread to be input from the storage array source line SL or the storage array bit line BL to the magnetic tunnel junction to read the resistance state of the magnetic tunnel junction, determine the data stored in the magnetic tunnel junction, and implement data reading.

[0056] In a preferred embodiment, the second isolation unit includes a fourth switch element, and the fourth switch element is in a conducting state based on a preset signal.

[0057] Specifically, the fourth switch element is in the on state and is arranged between the second switch element and the magnetic tunnel junction. Therefore, when there is an SOT current on the memory array source line SL, the single-particle upset in the magnetic tunnel junction directly acts on the fourth switch element instead of the second switch element that is read-selected, thereby avoiding the influence of the single-particle upset on the second switch element and effectively improving the reliability of data writing.

[0058] In a preferred embodiment, see Figure 3 The fourth switching element is a fourth PMOS transistor. The control terminal of the fourth PMOS transistor is connected to the preset signal terminal, the fourth PMOS transistor is in an on state based on a preset signal at the preset signal terminal, the first terminal is connected to the second switching element, and the second terminal is connected to the top of the magnetic tunnel junction.

[0059] Specifically, in this preferred embodiment, the fourth switching element is a fourth transistor PMOS, which can be turned on by a preset signal at a preset signal terminal, thereby conducting the second switching element and the magnetic tunnel junction and isolating the magnetic tunnel junction from the second switching element.

[0060] In a specific example, the fourth transistor PMOS is preferably a PMOS transistor. It is understood that the PMOS transistor is turned on under the action of a low level, thereby grounding the control terminal of the fourth transistor PMOS, so that the fourth transistor PMOS of the PMOS is always in the on state. Furthermore, the fourth transistor PMOS is preferably a PMOS transistor, and the fourth transistor PMOS is always in the on state, without introducing a new sensitive node.

[0061] In a preferred embodiment, see Figure 3 The magnetic memory includes a reference layer 1, a barrier layer 2, and a free layer 3 arranged in order from top to bottom. The bottom surface of the free layer 3 is fixed to the top surface of the spin-orbit moment layer 4. The top surface of the reference layer 1 is connected to the second isolation unit.

[0062] It is understood that the resistance of the magnetic tunnel junction depends on the magnetization directions of the reference layer 1 and the free layer 3, and the magnetization directions of the free layer 3 and the reference layer 1 are determined by the directions of the magnetic moments. When the directions of the magnetic moments of the reference layer 1 and the free layer 3 are the same, the magnetic tunnel junction is in a low resistance state (low resistance state), and when the directions of the magnetic moments of the reference layer 1 and the free layer 3 are opposite, the magnetic tunnel junction is in a high resistance state (high resistance state). The high resistance state and low resistance state of the magnetic tunnel junction can be pre-assigned to different data, for example, the high resistance state can be pre-assigned to data "1" and the low resistance state can be pre-assigned to data "0". Then, a current or voltage is input to the magnetic tunnel junction through a reading circuit. Based on the change in current or voltage, it can be determined whether the resistance state of the magnetic tunnel junction is a high resistance state or a low resistance state. Based on the resistance state of the magnetic tunnel junction, it can be determined whether the data stored in the magnetic tunnel junction is "1" or "0". Among them, determining the range of the high resistance state and the low resistance state is a common technical means in this field. Those skilled in the art can determine the resistance range of the high resistance state and the low resistance state of the magnetic tunnel junction based on common knowledge, and the present invention will not go into details here.

[0063] In an optional embodiment, the magnetic tunnel junction may further include at least one of an insertion layer, a pinning layer, a seed layer, and a capping layer. Each layer may be configured as one or more layers according to actual needs, and those skilled in the art may configure the top-down arrangement order of the magnetic tunnel junction layers as required, which is not limited by the present invention.

[0064] Optionally, the shape of the magnetic tunnel junction on the spin-orbit moment layer 4 can be any one of a cube, a cylinder, a square, an elliptical cylinder, etc. The bottom surface of the at least one magnetic tunnel junction provided on the spin-orbit moment layer 4, i.e., the bottom surface of the free layer 3 is coupled to the spin-orbit moment layer 4.

[0065] Preferably, the spin-orbit moment layer 4 can be rectangular, so that the top surface area of ​​the spin-orbit moment layer 4 is larger than the area occupied by at least one magnetic tunnel junction disposed on the spin-orbit moment layer 4. That is, at least one magnetic tunnel junction can be disposed on the spin-orbit moment layer 4, and the outer edge of at least one magnetic tunnel junction is located inward of the outer edge of the spin-orbit moment layer 4. The spin-orbit moment layer 4 can preferably be a heavy metal strip film or an antiferromagnetic strip film.

[0066] In a preferred embodiment, the magnetic random access memory unit can input current to the spin-orbit moment layer 4 and the magnetic tunnel junction by providing electrodes on the spin-orbit moment layer 4 and the magnetic tunnel junction. For example, a top electrode is provided on the top of the magnetic tunnel junction, and an input electrode and an output electrode are provided on opposite sides of the spin-orbit moment layer 4. Preferably, the material of the electrodes can be any one of tantalum Ta, aluminum Al, gold Au, or copper Cu.

[0067] Preferably, the material of the free layer 3 and the fixed layer may be a ferromagnetic metal, and the material of the barrier layer 2 may be an oxide. The magnetic tunnel junction has perpendicular magnetic anisotropy, which means that the magnetization directions of the free layer 3 and the fixed layer forming the magnetic tunnel junction are in the perpendicular direction. The ferromagnetic metal may be a mixed metal material formed by at least one of cobalt iron CoFe, cobalt iron boron CoFeB or nickel iron NiFe, and the proportions of the mixed metal materials may be the same or different. The oxide may be one of oxides such as magnesium oxide MgO or aluminum oxide Al2O3, which is used to generate a tunneling magnetoresistance effect. In practical applications, the ferromagnetic metal and the oxide may also be made of other feasible materials, and the present invention is not limited to this.

[0068] The free layer 3 of the magnetic tunnel junction is in contact with and fixed to the spin-orbit moment layer 4. The layers of the magnetic tunnel junction and the spin-orbit moment layer 4 can be deposited on the substrate in sequence from bottom to top by conventional methods such as ion beam epitaxy, atomic layer deposition or magnetron sputtering, and then the magnetic tunnel junction can be prepared by conventional nanodevice processing techniques such as photolithography and etching.

[0069] In this embodiment, the magnetic tunnel junction includes a top fixed layer, a free layer 3 in contact with a spin-orbit moment layer 4, and a barrier layer 2 disposed between the fixed layer and the free layer 3. The magnetic tunnel junction is a three-layer structure and includes only one free layer 3. In other embodiments, the free layer 3 may be provided as a plurality, that is, more than two free layers 3. The magnetic tunnel junction then includes a top fixed layer, a plurality of free layers 3, and a barrier layer 2 disposed between each two adjacent layers, with the bottom free layer 3 disposed in contact with the spin-orbit moment layer 4. For example, in a specific example, when two free layers 3 are included, the magnetic storage unit structure may include a spin-orbit moment layer 4, a second free layer 3 sequentially disposed on the spin-orbit moment layer 4, a barrier layer 2, a first free layer 3, a barrier layer 2, and a fixed layer.

[0070] The present invention will be further described below through a specific example. Figure 3As shown, in this specific example, the first switching element is a first transistor NMOS1, the first isolation unit is a second transistor NMOS2, the second switching element is a third transistor NMOS3, and the second isolation unit is a fourth transistor PMOS. The first transistor NMOS1, the second transistor NMOS2, and the third transistor NMOS3 are NMOS transistors, and the fourth transistor PMOS is a PMOS transistor.

[0071] The control terminal of the first transistor NMOS1 is connected to the first signal terminal WWL1, the first terminal is connected to the storage array bit line BL, and the second terminal is connected to the spin-orbit moment layer 4; the control terminal of the second transistor NMOS2 is connected to the second signal terminal WWL2 and the third signal terminal RWL1, the first terminal is connected to the spin-orbit moment layer 4, and the second terminal is connected to the storage array source line SL; the control terminal of the third transistor NMOS3 is connected to the fourth signal terminal RWL2, the first terminal is connected to the storage array bit line BL, and the second terminal is connected to the first terminal of the fourth transistor PMOS; the control terminal of the fourth transistor PMOS is grounded, and the second terminal is connected to the top of the magnetic tunnel junction.

[0072] When performing read and write operations on the magnetic storage unit, the read and write related signal voltage conditions of the magnetic storage unit are shown in Table 1.

[0073] Table 1

[0074]

[0075] Specifically, when data "0" is written, the voltage of the memory array bit line BL is V dd , the voltage of the memory array source line SL is GND, the voltage of the first signal terminal WWL1 and the second signal terminal WWL2 is V dd , the voltage of the fourth signal terminal RWL2 is GND. Then the first transistor NMOS1 and the second transistor NMOS2 are turned on, and the third transistor NMOS3 is turned off. The voltage of the memory array bit line BL is V dd If the voltage of the memory array source line SL is GND, the write current is directed from BL to SL. The voltage between the third transistor NMOS3 and the fourth transistor PMOS is substantially zero, and no sensitive node exists. Similarly, the drain terminals of the transistors in the unselected magnetic memory cells in this column are all maintained at a low voltage, and no sensitive node exists.

[0076] When writing data "1", the voltage of the memory array bit line BL is GND, and the voltage of the memory array source line SL is V dd , the voltage between the first signal terminal WWL1 and the second signal terminal WWL2 is V dd, the voltage of the fourth signal terminal RWL2 is GND. Then the first transistor NMOS1 and the second transistor NMOS2 are turned on, and the third transistor NMOS3 is turned off. The voltage of the memory array bit line BL is GND, and the voltage of the memory array source line SL is V dd , the direction of the write current is from SL to BL, the voltage between the third transistor NMOS3 and the fourth transistor PMOS is substantially zero, and no sensitive node exists. Similarly, the drain terminals of the transistors of the unselected magnetic storage cells in this column are all maintained at a low voltage, and no sensitive node exists.

[0077] When reading data, the voltage of the memory array bit line BL is V dd , the voltage of the memory array source line SL is GND, the voltage of the third signal terminal RWL1 and the fourth signal terminal RWL2 is V dd , the voltage of the first signal terminal WWL1 is GND. Then the second transistor NMOS2 and the third transistor NMOS3 are turned on, and the first transistor NMOS1 is turned off. The voltage of the memory array bit line BL is V dd If the voltage of the memory array source line SL is GND, the write current is directed from BL to SL. The voltage between the third transistor NMOS3 and the fourth transistor PMOS is substantially zero, and no sensitive node exists. Similarly, the drain terminals of the transistors in the unselected magnetic memory cells in this column are all maintained at a low voltage, and no sensitive node exists.

[0078] Based on the same principle, this embodiment also discloses a radiation-resistant magnetic memory, which includes a plurality of radiation-resistant magnetic storage units as described in this embodiment arranged in an array.

[0079] Radiation-hardened magnetic storage includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of radiation-hardened magnetic storage include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0080] Since the principle of solving the problem of the radiation-resistant magnetic memory is similar to that of the above radiation-resistant magnetic storage unit, the implementation of the radiation-resistant magnetic memory can refer to the implementation of the above radiation-resistant magnetic storage unit, which will not be repeated here.

[0081] Based on the same principle, this embodiment also discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0082] The processor and / or the memory include the radiation-resistant magnetic storage unit as described in this embodiment.

[0083] The radiation-resistant magnetic storage unit described in the above embodiments can be provided in a product device having a certain function. A typical implementation device is a computer device. Specifically, the computer device can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0084] In a typical example, a computer device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and / or the memory include the radiation-resistant magnetic storage unit as described in this embodiment.

[0085] Reference below Figure 4 , which shows a structural diagram of a computer device 600 suitable for implementing an embodiment of the present application.

[0086] like Figure 4 As shown, computer device 600 includes a central processing unit (CPU) 601, which can perform various appropriate tasks and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage portion 608 into a random access memory (RAM) 603. Various programs and data required for the operation of system 600 are also stored in RAM 603. CPU 601, ROM 602, and RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to bus 604.

[0087] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, and the like; an output section 607 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and a speaker; a storage section 608 including devices such as a hard disk; and a communication section 609 including a network interface card such as a LAN card or a modem. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. Removable media 611, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 610 as needed, so that computer programs read therefrom can be installed in the storage section 608 as needed.

[0088] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0089] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0090] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0091] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0092] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may be applied in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0093] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communications network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0094] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0095] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A radiation-resistant magnetic storage unit, characterized in that comprising a first switching element, a first isolation unit, a second switching element, a second isolation unit and a magnetic memory; The magnetic memory includes a spin-orbit moment layer and a magnetic tunnel junction provided on the spin-orbit moment layer; The first switch element is connected to the write signal input end of the spin-track moment layer and the memory array bit line respectively, and the first isolation unit is connected to the write signal output end of the spin-track moment layer and the memory array source line respectively; One end of the second switch element is connected to the top of the magnetic tunnel junction through the second isolation unit, and the other end is connected to the memory array bit line, and the second isolation unit is in a conducting state; When writing data, the first switch element conducts the memory array bit line and the spin-orbit moment layer in response to a first write signal, and the first isolation unit conducts the memory array source line and the spin-orbit moment layer in response to a second write signal; when reading data, the second switch element conducts the memory array bit line and the magnetic tunnel junction in response to a first read signal, and the first isolation unit conducts the memory array source line and the spin-orbit moment layer in response to a second read signal; The first switching element is a first transistor; the first isolation unit includes a third switching element, which is a second transistor; the second switching element is a third transistor; the second isolation unit includes a fourth switching element; and the fourth switching element is a fourth transistor.

2. The radiation-resistant magnetic storage unit according to claim 1, wherein: The control end of the first transistor is connected to the first signal end for inputting the first write signal, the first end is connected to the memory array bit line, and the second end is connected to the write signal input end of the spin-track moment layer.

3. The radiation-resistant magnetic storage unit according to claim 1, wherein: The third switch element conducts the memory array source line and the spin-track moment layer in response to a second write signal, and conducts the memory array source line and the spin-track moment layer in response to a second read signal.

4. The radiation-resistant magnetic storage unit according to claim 3, wherein: The control end of the second transistor is respectively connected to the second signal end for inputting the second write signal and the third signal end for inputting the second read signal, the first end is connected to the write signal output end of the spin-track moment layer, and the second end is connected to the storage array source line.

5. The radiation-resistant magnetic storage unit according to claim 1, wherein: The control end of the third transistor is connected to the fourth signal end for inputting the first read signal, the first end is connected to the memory array bit line, the second end is connected to the second isolation unit, the first end is a source end, and the second end is a drain end.

6. The radiation-resistant magnetic storage unit according to claim 1, wherein: The fourth switch element is in a turned-on state based on a preset signal.

7. The radiation-resistant magnetic storage unit according to claim 6, wherein: The control end of the fourth transistor is connected to the preset signal end, is in a conductive state based on a preset signal of the preset signal end, has a first end connected to the second switch element, and has a second end connected to the top of the magnetic tunnel junction.

8. The radiation-resistant magnetic storage unit according to claim 1, wherein: The magnetic memory comprises a reference layer, a barrier layer and a free layer arranged in sequence from top to bottom; The bottom surface of the free layer and the top surface of the spin-orbit moment layer are fixedly arranged; A top surface of the reference layer is connected to the second isolation unit.

9. A radiation-resistant magnetic memory, characterized in that: The invention comprises a plurality of radiation-resistant magnetic storage units according to any one of claims 1 to 8 arranged in an array.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and / or the memory comprises the radiation-resistant magnetic storage unit according to any one of claims 1-8.

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