Static random access memory (SRAM) cells embedded with non-volatile transistors

Abstract

The present invention relates to a static random access memory (SRAM) cell having embedded nonvolatile transistors. The present disclosure relates to a structure comprising: a latch circuit; a first nonvolatile field effect transistor (FET) connected to a first side of the latch circuit and a bit line; and a second nonvolatile field effect transistor (FET) connected to a second side of the latch circuit and a complementary bit line.

Description

Technical Field

[0001] The present disclosure relates to nonvolatile transistors embedded in memory cells, and more particularly to circuits and methods for embedding nonvolatile transistors in static random access memory (SRAM) cells and methods of operation. Background Art

[0002] Memory devices are used as internal storage areas in computers and other electronic devices. One specific type of memory used to store data in computers is random access memory (RAM). RAM is often used as the primary on-chip and off-chip storage unit in computing systems and is typically volatile, meaning that any data stored in RAM is lost once the power is turned off.

[0003] Static random access memory (SRAM) is an example of RAM. SRAM has the advantage of retaining data without refreshing. A typical SRAM device consists of an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value representing a logical data bit (e.g., "0" or "1").

[0004] Charge Trap Transistor (CTT)-based memory arrays are typically standalone arrays with large overhead areas. For example, applications that require both high-speed SRAM and the advantages of a single CTT non-volatile memory array can result in high standalone peripheral costs. Summary of the Invention

[0005] In one aspect of the present disclosure, a structure includes: a latch circuit; a first nonvolatile field effect transistor (FET) connected to a first side of the latch circuit and a bit line; and a second nonvolatile field effect transistor (FET) connected to a second side of the latch circuit and a complementary bit line.

[0006] In another aspect of the present disclosure, a circuit includes: a latch circuit including a first PMOS transistor connected in series with a first NMOS transistor and a second PMOS transistor connected in series with a second NMOS transistor; a first nonvolatile transistor connected to the first PMOS transistor connected in series with the first NMOS transistor; a second nonvolatile transistor connected to the second PMOS transistor connected in series with the second NMOS transistor; and a word line connected to the first nonvolatile transistor and the second nonvolatile transistor.

[0007] In another aspect of the present disclosure, a method includes writing data into at least one nonvolatile field effect transistor (FET) of a memory bit cell circuit by changing a threshold voltage of the at least one nonvolatile FET; and reading the data in the at least one nonvolatile FET of the memory bit cell circuit by using differential sensing of the at least one nonvolatile FET. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0009] Figure 1 A charge trap transistor (CTT) circuit embedded in a static random access memory (SRAM) cell is shown according to some aspects of the present disclosure.

[0010] Figure 2 A two-bit data per SRAM cell circuit is shown in accordance with aspects of the present disclosure.

[0011] Figure 3A The first step of a write operation into a CTT circuit of a two-bit data per SRAM circuit is shown according to aspects of the present disclosure.

[0012] Figure 3B The second step of a write operation into the CTT circuit of the two-bit data per SRAM circuit is shown according to aspects of the present disclosure.

[0013] Figure 4A A read operation of a CTT circuit from a two-bit data per SRAM circuit is shown, in accordance with aspects of the present disclosure.

[0014] Figure 4B A diagram illustrating a read operation of a CTT circuit from a two-bit data per SRAM circuit, according to aspects of the present disclosure.

[0015] Figure 5A A read operation from an SRAM cell is shown in accordance with aspects of the present disclosure.

[0016] Figure 5B A diagram illustrating a read operation from an SRAM cell, according to aspects of the present disclosure.

[0017] Figure 6 A write operation into an SRAM cell is shown according to some aspects of the present disclosure.

[0018] Figure 7 A non-volatile memory circuit embedded in an SRAM cell according to another aspect of the present disclosure is shown. DETAILED DESCRIPTION

[0019] The present disclosure relates to a non-volatile transistor embedded in a memory cell, and more particularly to circuits and methods of operating a non-volatile transistor embedded in a static random access memory (SRAM) cell. More specifically, the present disclosure includes an SRAM cell having a charge trap transistor (CTT) device. It will be understood by those skilled in the art that the non-volatile transistor can be used in any non-volatile transistor technology (i.e., ferroelectric field effect transistor (FET), magnetoelectric transistor, etc.). Advantageously, in addition to the other advantages described herein, the non-volatile transistor described herein provides reduced area overhead and increased capacity in an SRAM array (e.g., an SRAM array can be used as a lookup table or storage for network weights of a neural network).

[0020] In known circuits, SRAM cells have fast performance but cannot store data when powered off, while charge trap transistors (CTTs) have slow performance but can store data when powered off. In known circuits, CTT circuits are independent and require a larger area overhead due to the dual peripheral circuits and dedicated CTT arrays. However, known circuits do not have CTT circuits combined with SRAM cells. Furthermore, in the present disclosure, incorporating CTTs into SRAM cells facilitates near-memory computation between the CTTs and data stored in the SRAM cells, thereby increasing memory density.

[0021] To overcome these and other problems and by way of specific examples, the present disclosure includes a structure having a memory circuit including a latch circuit connected to at least two nonvolatile field effect transistors (FETs) configured to perform read operations and / or write operations. The present disclosure also includes a circuit including a latch circuit having a plurality of field effect transistors (FETs) and at least two charge trap transistors (CTTs) connected to the latch circuit and configured to perform read operations and / or write operations. The present disclosure also includes a method for writing data in at least one nonvolatile field effect transistor (FET) of a memory bit cell circuit by changing the threshold voltage of at least one FET, and a method for reading data in at least one nonvolatile FET of a memory bit cell circuit using differential sensing of the at least one nonvolatile FET.

[0022] Figure 1 A charge trap transistor (CTT) circuit embedded in a static random access memory (SRAM) cell according to some aspects of the present disclosure is shown. Figure 1In the embodiment, CTT circuits 20 and 30 are embedded in the SRAM cell 10. In this embodiment, the CTT circuits 20 and 30 replace access transistors. The SRAM cell 10 includes the CTT circuit 20, a PMOS transistor 40, and an NMOS transistor 60 connected to the bit line BL. The SRAM cell 10 also includes the CTT circuit 30, a PMOS transistor 50, and an NMOS transistor 70 connected to the complementary bit line BLB. In the SRAM cell 10, the PMOS transistors 40 and 50 and the NMOS transistors 60 and 70 form a latch circuit for storing bits. In particular, the SRAM cell 10 uses the CTT circuits 20 and 30 to store "0" or "1" at the storage nodes A and B using a write operation. In addition, in a read operation, the CTT circuits 20 and 30 are used to read the storage nodes A and B.

[0023] Figure 2 Two-bit data per SRAM cell circuit according to some aspects of the present disclosure is shown. More specifically, Figure 2 In FIG. 1 , SRAM cells 10, 80, 150, and 220 are shown, each of which has a similar structure. For example, similar to Figure 1 The structure of SRAM cell 10 is shown. SRAM cell 80 has CTT circuits 90 and 100; PMOS transistors 110 and 120; and NMOS transistors 130 and 140. SRAM cells 10 and 80 have CTT circuits 20, 30, 90, and 100, each of which has a gate connected to word line WL1. Similarly, SRAM cell 150 has CTT circuits 160 and 170; PMOS transistors 180 and 190; and NMOS transistors 200 and 210. SRAM cell 220 has CTT circuits 230 and 240; PMOS transistors 250 and 260; and NMOS transistors 270 and 280. SRAM cells 150 and 220 have CTT circuits 160, 170, 230, and 240, each of which has a gate connected to word line WL2. In an embodiment, bit line BL- 0 is connected to CTT circuits 20 and 160 , bit line BLB- 0 is connected to CTT circuits 30 and 170 , bit line BL- 1 is connected to CTT circuits 90 and 230 , and bit line BLB- 1 is connected to CTT circuits 100 and 240 .

[0024] exist Figure 2 In the operation of the SRAM cell 10, the threshold voltages (i.e., Vt) of the CTT circuits 20 and 30 are symmetrically increased, as represented by Vt+Δ. This allows the CTT data in the SRAM cell 10 to store "1". In a non-limiting example of the present disclosure, the delta (i.e., Δ) may be approximately 250 millivolts. In addition, Figure 2In the operation of the SRAM cell 80, the threshold voltage (ie, Vt) of the CTT circuits 90, 100 is not raised, which is represented by Vt+0. This results in the CTT data in the SRAM cell 20 storing "0".

[0025] Figure 3A The first step of a write operation into a CTT circuit of a two-bit data per SRAM circuit is shown according to aspects of the present disclosure. Figure 3A Includes SRAM cells 10, 80, 150, and 220 (similar to Figure 2 ). In operation, bit lines BL-0 and BLB-0 are set to ground (ie, GND) and bit lines BL-1 and BLB-1 are precharged. Figure 3A In the first step of the write operation, the word line WL1 is turned on at a voltage value greater than the voltage value of the power supply VDD (ie, VDD+) and the word line WL2 is turned off. Figure 3A In the first step of the write operation, the SRAM cell 10 receives a raised VDD and the threshold voltage (ie, Vt) of the CTT circuit 30 is raised to a predetermined increment (eg, 250 mV) to store “1” in the CTT circuit 30. Figure 3A In the first step of the write operation, since the SRAM cell 80 does not have an increased VDD, the threshold voltage (ie, Vt) of the CTT circuit 100 is not increased. Note that in order to write the CTT 30, the bit cell 10 is pre-programmed with 0 and 1, as shown in FIG. Figure 3A shown.

[0026] Figure 3B The second step of the write operation into the CTT circuit of the two-bit data circuit per SRAM according to some aspects of the present disclosure is shown. In operation, the bit lines BL-0 and BLB-0 are set to ground (i.e., GND) and the bit lines BL-1 and BLB-1 are precharged. Figure 3B In the second step of the write operation, the word line WL1 is turned on at a voltage value greater than the voltage value of the power supply VDD (ie, VDD+) and the word line WL2 is turned off. Figure 3B In the second step of the write operation, the SRAM cell 10 receives the boosted VDD and the threshold voltage (i.e., Vt) of the CTT circuit 20 is raised to a predetermined increment (e.g., 250 mV) to store “1” in the CTT circuit 20. When the CTT circuit 30 has had its threshold voltage (i.e., Vt) raised from the first step of the write operation, the CTT circuit 30 stores “0”. Figure 3A In the second step of the write operation, since the SRAM cell 80 does not have an increased VDD, the threshold voltage (ie, Vt) of the CTT circuit 90 is not increased. Note that in order to write to the CTT 20, the bit cell 10 is pre-programmed with 1 and 0, as shown in FIG. Figure 3A shown.

[0027] Figure 4A A read operation of a CTT circuit from a two-bit data per SRAM circuit is shown, in accordance with aspects of the present disclosure. Figure 4A Includes SRAM cells 10, 80, 150, and 220 (similar to Figure 2 ). The read operation of the CTT circuit 10, 80 uses large signal sensing. In particular, the bit lines BL-0, BLB-0, BL-1, and BLB-1 are precharged for the read operation mode. For example, bit line BL-0 is precharged high, and bit line BLB-0 discharges through storage node B. In addition, bit line BLB-1 is precharged high, and bit line BLB-1 discharges through storage node D. A read operation then occurs and the sense amplifier of the corresponding SRAM cell (i.e., SRAM cell 10, 80, 150, or 220) is enabled to sense the difference between the bit line (e.g., BL-0 or BL-1) and the corresponding complementary bit line (e.g., BLB-0 or BLB-1). The CTT data of the CTT circuit (e.g., CTT circuit 10 or CTT 100) can then be read during a read operation.

[0028] Figure 4B Graph 290 shows bit lines BL- 0 and BLB- 1 as a function of voltage (y-axis) and time (x-axis). Figure 4B Also shown is a graph 300 of bit lines BL-1 and BLB-1 as a function of voltage (y-axis) and time (x-axis). In graph 290, bit line BL-0 is held at a constant voltage and complementary bit line BLB-0 is discharged. In graph 300, bit line BLB-1 is held at a constant voltage and complementary bit line BLB-1 is discharged. Further, Figure 4A Reading of mid-CTT data can be performed by looking at the discharge rate difference between the complementary bit line BLB-0 and the complementary bit line BLB-1 or by absolute discharge rate.

[0029] exist Figure 4B In the example, when examining the difference in discharge rates between complementary bit lines BLB-0 and BLB-1, a differential sense amplifier can be used to perform current sensing or single-ended sensing. When performing single-ended sensing, the inverter can detect that the discharge rate of complementary bit line BLB-0 in graph 290 is slower than the discharge rate of complementary bit line BLB-1 in graph 300. Since the discharge rate of complementary bit line BLB-0 in graph 290 is slower than that of BLB-1 in graph 300, a "1" is read from the CTT data of CTT circuit 20. Since the discharge rate of complementary bit line BLB-1 is faster than that of BLB-0, a "0" is read from the CTT data of CTT circuit 90.

[0030] Figure 5A A read operation from an SRAM cell is shown in accordance with aspects of the present disclosure. Figure 5A Includes SRAM cells 10, 80, 150, and 220 (similar to Figure 2 ). Figure 5A The read operation in

[0014] uses SRAM-based differential sensing together with a delayed sense amplifier trigger that can sense the SRAM data.

[0031] exist Figure 5A In the read mode, word line WL1 is turned on and word line WL2 is turned off. Bit lines BL-0, BLB-0, BL-1, and BLB-1 are precharged for the read mode of operation. For example, bit line BL-0 is precharged high and bit line BLB-0 is discharged through storage node B. In addition, bit line BLB-1 is precharged high and bit line BLB-1 is discharged through storage node D. In an embodiment, the delay overhead should be minimal, for example, less than 1 nanosecond.

[0032] Figure 5B Graph 310 shows bit lines BL-0 and BLB-1 as a function of voltage (y-axis) and time (x-axis). Figure 5B Also shown is a graph 320 of bit lines BL-1 and BLB-1 as a function of voltage (y-axis) and time (x-axis). Figure 5B , when looking at the difference in discharge rates between complementary bit line BLB-0 and complementary bit line BLB-1, SRAM-based differential sensing can detect that the discharge rate of complementary bit line BLB-0 in graph 310 is slower than the discharge rate of complementary bit line BLB-1 in graph 320. Since the discharge rate of complementary bit line BLB-0 in graph 310 is slower than the discharge rate of BLB-1 in graph 320, a "1" will be read from the SRAM data of SRAM cell 10. Since complementary bit line BLB-1 has a faster discharge rate compared to BLB-0, a "0" will be read from the SRAM data of SRAM cell 80. In the present disclosure, the read operation of the SRAM bit is a typical read operation in which both the BL and BLB are precharged to Vdd. Based on the data stored in the storage node of the bit cell, one of the BL or BLB will discharge while the other will remain at Vdd. The difference between the BL and BLB can then be sensed using a differential sense amplifier. The sense amplifier activation time for sensing will be determined by the bit cell with the CTT element storing "1", resulting in a slow discharge rate. In addition, the sense amplifier activation control circuit will be designed using a predetermined voltage divider (e.g., 100 mV).

[0033] Figure 6 A write operation into an SRAM cell is shown according to some aspects of the present disclosure. Figure 6Includes SRAM cells 10, 80, 150, and 220 (similar to Figure 2 ). Figure 6 In the write operation of the SRAM cell, word line WL1 is turned on and word line WL2 is turned off. Figure 6 In a write operation, each of the SRAM cells 10, 80, 150, and 220 can be written to by means of a threshold voltage plus increment (Vt+Δ) access transistor, even using known word line boost write assist techniques.

[0034] Figure 7 Non-volatile memory (NVM) circuitry embedded in a static random access memory (SRAM) cell is shown according to further aspects of the present disclosure. Figure 7 There are SRAM cells 10', 80', 150' and 220', which are similar to Figure 2 The SRAM primitive shown is the same as that shown in FIG. 1 , but the CTT device is replaced by another non-volatile memory (NVM) device (e.g., ferroelectric field effect transistor, magnetoelectric transistor, etc.). More specifically, Figure 7 The SRAM cells 10', 80', 150' and 220' in the Figure 2 10, 80, 150, and 220, but each CTT device is replaced by a corresponding non-volatile memory (NVM) device, i.e., NVM devices 330, 340 for SRAM cell 10′, NVM devices 350, 360 for SRAM cell 80′, NVM devices 370, 380 for SRAM cell 150′, and NVM devices 390, 400 for SRAM cell 220′.

[0035] exist Figure 7 In the operation of the SRAM cell 10', the threshold voltages (i.e., Vt) of the additional NVM devices 330, 340 are symmetrically raised, represented by Vt+Δ. This allows the CTT data in the SRAM cell 10' to store "1". In a non-limiting example of the present disclosure, the increment (i.e., Δ) may be approximately 250 millivolts. In addition, Figure 7 In the operation of the SRAM cell 80', the threshold voltages (ie, Vt) of the additional NVM devices 350, 360 are symmetrically lowered, as represented by Vt-Δ. This results in the CTT data in the SRAM cell 20 storing "0".

[0036] Furthermore, by changing the polarization by passing current in the other direction, the threshold voltage (i.e., Vt) of the additional NVM devices 350, 360 is lowered. In other words, current is caused to flow from the additional NVM devices 350, 360 to the corresponding SRAM storage nodes C, D. This lowered threshold voltage (i.e., Vt) will increase the difference between the threshold voltage (i.e., Vt+Δ) of the additional NVM devices 330, 340 and the threshold voltage (i.e., Vt-Δ) of the additional NVM devices 350, 360 to perform the read and write operations described above. Figure 7 In an alternative embodiment, ferroelectric field effect transistors, magnetoelectric transistors, and additional NVM devices 330, 340, 350, 360, 370, 380, and 390 are used to lower the voltage threshold (ie, Vt-Δ) because Figure 2 The CTT circuits 20 , 30 , 90 , 100 , 160 , 170 , 230 and 240 cannot change the current direction and lower the voltage threshold (ie, Vt−Δ).

[0037] The circuits and methods for embedding non-volatile transistors in static random access memory (SRAM) cells disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, these methods and tools are used to form structures with dimensions in the micrometer and nanometer range. The methodology (i.e., technology) for manufacturing the circuits and methods for embedding non-volatile transistors in static random access memory (SRAM) cells disclosed herein has been adopted from integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented by patterning a film of material by performing a photolithographic process on top of the wafer. In particular, the manufacture of the circuits and methods for embedding non-volatile transistors in static random access memory (SRAM) cells uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film by photolithographic imaging, and (iii) selectively etching the film against the mask.

[0038] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units. In addition, the circuits and methods for in-memory logic computing disclosed herein can have a wide range of applications in high-throughput processors for machine learning and artificial intelligence.

[0039] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: Latch circuit; a first nonvolatile field effect transistor (FET) connected to a first side of the latch circuit and a bit line; a second nonvolatile field effect transistor (FET) connected to a second side of the latch circuit and a complementary bit line; as well as a word line directly connected to the gate of the first nonvolatile field effect transistor and directly connected to the gate of the second nonvolatile field effect transistor, The first nonvolatile field effect transistor (FET) is located between the latch circuit and the bit line, directly connected to the latch circuit, and directly connected to the bit line.

2. The structure of claim 1, wherein the second nonvolatile field effect transistor is located between the latch circuit and the complementary bit line.

3. The structure of claim 1, further comprising a first storage node located between the first nonvolatile field effect transistor and the latch circuit and a second storage node located between the second nonvolatile field effect transistor and the latch circuit.

4. The structure of claim 1, wherein the latch circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. 5 . The structure of claim 4 , wherein each gate of the first PMOS transistor and the second PMOS transistor is connected to a storage node and a gate of one of the first NMOS transistor and the second NMOS transistor.

6. The structure of claim 1 wherein the first nonvolatile field effect transistor and the second nonvolatile field effect transistor comprise charge trap transistors (CTTs).

7. The structure of claim 1 wherein the first nonvolatile field effect transistor and the second nonvolatile field effect transistor comprise ferroelectric field effect transistors (FETs).

8. The structure of claim 1 wherein the first nonvolatile field effect transistor and the second nonvolatile field effect transistor comprise magnetoelectric transistors.

9. The structure of claim 1, wherein the latch circuit and the first and second nonvolatile field effect transistors (FETs) comprise static random access memories (SRAMs).

10. The structure of claim 9, wherein the SRAM is configured to perform a write operation that changes threshold voltages (Vt) of the first and second nonvolatile field effect transistors to write data into the SRAM.

11. The structure of claim 10, wherein the write operation uses boosting of the word line directly connected to the gate of the first nonvolatile field effect transistor and the gate of the second nonvolatile field effect transistor to write the data to the SRAM.

12. The structure of claim 9, wherein the SRAM is configured to perform a read operation that reads data from the SRAM using differential sensing of the first nonvolatile field effect transistor and the second nonvolatile field effect transistor.

13. The structure of claim 12 wherein the read operation uses the differential sensing of the first and second nonvolatile field effect transistors together with delayed sense amplifier triggering to read the data from the SRAM.

14. A circuit comprising: A latch circuit comprising a first PMOS transistor connected in series with a first NMOS transistor and a second PMOS transistor connected in series with a second NMOS transistor; a first nonvolatile transistor connected to the first PMOS transistor in series with the first NMOS transistor; a second nonvolatile transistor connected to the second PMOS transistor in series with the second NMOS transistor; as well as a word line directly connected to the gate of the first nonvolatile transistor and directly connected to the gate of the second nonvolatile transistor, The first nonvolatile field effect transistor is located between the latch circuit and the bit line, and is directly connected to the latch circuit and the bit line.

15. The circuit of claim 14, wherein the first nonvolatile transistor and the second nonvolatile transistor comprise charge trap transistors (CTTs). 16 . The circuit of claim 15 , further comprising a first storage node located between the first nonvolatile field effect transistor and the latch circuit.

17. The circuit of claim 15, further comprising a second storage node located between the second nonvolatile field effect transistor and the latch circuit.

18. The circuit of claim 15 , wherein the charge trap transistor (CTT) is configured to perform a read operation to read data from the circuit using differential sensing of the charge trap transistor (CTT), and to perform a write operation to write the data to the circuit by changing a threshold voltage (Vt) of the charge trap transistor (CTT).

19. The circuit of claim 18, wherein each of the charge trap transistors (CTT) has a gate connected to the word line.

20. A method of operating a semiconductor structure, comprising: Writing data into at least one nonvolatile field effect transistor FET of a memory bit cell circuit by changing a threshold voltage of the at least one nonvolatile field effect transistor FET; as well as reading said data in said at least one nonvolatile field effect transistor by using differential sensing of said at least one nonvolatile field effect transistor of said memory bit cell circuit, wherein the word line is directly connected to the gate of a first nonvolatile field effect transistor among the at least one nonvolatile field effect transistor, and is directly connected to the gate of a second nonvolatile field effect transistor among the at least one nonvolatile field effect transistor, and The first non-volatile field effect transistor in the at least one non-volatile field effect transistor FET is located between a latch circuit and a bit line, and is directly connected to the latch circuit and the bit line.

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