Managing programming convergence associated with memory cells of a memory sub-system

Abstract

The present application relates to managing programming convergence associated with memory cells of a memory sub-system. A first program pulse is caused to be applied to a word line associated with a memory cell of a memory sub-system. In response to the first program pulse, a program verify operation is caused to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sense node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sense node is identified. A bit line voltage matching the measured threshold voltage is caused to be applied to a bit line associated with the memory cell.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to managing programming convergence associated with memory cells of a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store and retrieve data at the memory devices. SUMMARY

[0003] In one aspect, the present application relates to a method comprising: causing a first program pulse to be applied to a word line associated with a memory cell of a memory device; in response to the first program pulse, causing a program verify operation to be performed on the memory cell to determine a measured threshold voltage associated with the memory cell; storing the measured threshold voltage associated with the memory cell in a sense node associated with the memory cell; determining that the measured threshold voltage of the memory cell satisfies a condition; identifying the measured threshold voltage stored in the sense node; and causing a bit line voltage matching the measured threshold voltage to be applied to a bit line associated with the memory cell.

[0004] In another aspect, the present application relates to a non-transitory computer- readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: causing a first program pulse to be generated that is to be applied to a memory cell of a memory device; causing a program verify operation to be performed on the memory cell that compares a threshold voltage of the memory cell to a program verify threshold voltage; in response to a condition being satisfied, identifying the threshold voltage of the memory cell stored in a storage location associated with the memory cell; and causing a bit line voltage matching the threshold voltage to be applied to a bit line associated with the memory cell during a second program pulse.

[0005] In another aspect, the application relates to a memory device comprising: a memory array; and control logic operatively coupled with the memory array to perform operations comprising: causing a first program pulse to be applied to a word line associated with a memory cell of the memory array; in response to the first program pulse, causing a program verify operation to be performed on the memory cell to determine a measured threshold voltage associated with the memory cell; storing the measured threshold voltage associated with the memory cell in a sense node associated with the memory cell; determining that the measured threshold voltage of the memory cell satisfies a condition; identifying the measured threshold voltage stored in the sense node; and causing a bit line voltage matching the measured threshold voltage to be applied to a bit line associated with the memory cell. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which various embodiments of the present disclosure are illustrated.

[0007] Figure 1 An example computing system including a memory sub-system according to some embodiments of the present disclosure is illustrated.

[0008] Figure 2 is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system according to one or more embodiments of the present disclosure.

[0009] Figure 3 is a flow diagram of an example method 300 for managing program convergence associated with a memory cell of a memory sub-system according to one or more embodiments of the present disclosure.

[0010] Figure 4 An example graph including a representation of managing program convergence associated with a memory cell using a bit line voltage proportional to a threshold voltage of the memory cell according to one or more embodiments of the present disclosure is illustrated.

[0011] Figure 5 An example graph including a representation of managing program convergence associated with a memory cell using a bit line voltage proportional to a threshold voltage of the memory cell according to one or more embodiments of the present disclosure is illustrated.

[0012] Figure 6 is a flow diagram of an example method 600 for managing program convergence associated with a memory cell of a memory sub-system according to one or more embodiments of the present disclosure.

[0013] Figure 7 An example sensing circuitry in communication with a program convergence management component of a memory sub-system according to one or more embodiments of the present disclosure is illustrated.

[0014] Figure 8 is a block diagram of an example computer system in which implementations of the present disclosure can operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to managing programming convergence associated with memory cells of a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Below, reference is made to a storage device. However, the below description is applicable to a memory module as well. Figure 1 Example storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0016] The memory sub-system can include a high-density non-volatile memory device in which the retention of data is required when no power is supplied to the memory device. One example of a non-volatile memory device is a NAND memory device. Below, reference is made to a NAND memory device. However, the below description is applicable to a NOR memory device as well. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more memory dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a collection of physical blocks. Each block is composed of a collection of pages. Each page is composed of a collection of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and has various logical states related to the number of bits stored. The logical states can be represented by binary values (e.g., “0” and “1”) or combinations of such values.

[0017] A memory device can be composed of bits arranged in a two-dimensional grid or a three-dimensional grid. Memory cells are formed onto a silicon die in an array of columns (also referred to below as “bit lines”) and rows (also referred to below as “word lines”). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. Below, a block refers to a cell of a memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell.

[0018] To program data to a memory sub-system, an internal controller of the NAND can issue control signals to one or more row drivers to cause the row drivers to apply a voltage to the trap charge (e.g., electrons) in the charge trap region of the NAND across the gates of the NAND device. The memory controller can apply the voltage in pulses, referred to as program pulses. The amount of voltage and the width of the pulses can determine the amount of charge to be stored at the NAND device, and in turn, program the state of the NAND. In some cases, the memory controller can apply a program pulse, verify the state of the NAND, and subsequently apply another program pulse if needed to bring the cell to the intended voltage level. This pulse-verify-pulse sequence can ensure that the NAND is properly programmed without applying larger voltages that can cause more damage to the NAND.

[0019] As a memory sub-system ages, the voltage (Vt) distribution of the NAND state of the memory cells tends to widen, and thus towards the end of the life of the memory sub-system, higher program pulses can be needed to ensure that data can be properly read. Thus, the memory controller in conventional memory systems uses program pulses that consider end-of-life conditions (i.e., start with larger program pulse voltages and / or widths). However, using larger program pulses at the beginning of the life of the memory sub-system can reduce the life span of the memory components because larger program pulses can unnecessarily cause more damage to the NAND components compared to using lower program pulses instead.

[0020] Certain memory access operations performed on a block of a memory device involve applying certain voltages to a word line, and a pre-charge of a bit line. To confirm whether a memory cell in the block is in an erased state "1" or a programmed state "0", it can be difficult to identify a change in potential unless a certain level of potential is provided to the bit line. Thus, certain devices apply a pre-charge voltage to advance the voltage of the bit line to a predetermined value, and then detect a change in the voltage of the bit line when the bit line is applied to the memory cell by comparing the voltage of the bit line to the pre-charged voltage used as a reference. This pre-charge is frequently performed during memory access operations, and thus, the time needed for the pre-charge has a large impact on data access time.

[0021] During certain memory access operations, one or more calculations are performed on the memory device prior to initiating a pre-charge. One approach involves the use of selective slow program convergence (SSPC) to improve program threshold voltage distribution width. In this approach, a plurality of pre-verify voltage levels are calculated prior to initiating a pre-charge. Memory cells are programmed with incrementally increasing program pulses applied to a word line to which the memory cells are coupled. After each pulse, a program verify operation determines a threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the V t of the cell is biased with a fixed or static intermediate voltage that changes. Other cells continue to be programmed at their normal speed. As the V t for each cell reaches the pre-verify level, it is biased with the intermediate voltage. As the threshold voltage of all bit lines reaches the verify voltage threshold, they are biased with the inhibit voltage.

[0022] According to this approach, in response to a threshold voltage of an associated memory cell reaching a pre-verify threshold voltage, each bit line coupled to one of a plurality of memory cells is selectively biased with a first bit line voltage. The pre-verify threshold voltage is less than a verify threshold voltage. The applied bit line voltage is a fixed digital voltage (e.g., a voltage in the range of 0.5V to 0.9V) that is generally greater than 0V and less than an inhibit voltage (e.g., V CC ).

[0023] In this approach, the application of a fixed bit line voltage to memory cells that reach a pre-verify threshold level results in program state width that is adversely affected by several factors including program gate steps, toxic program noise, random sense noise (e.g., random telegraph signal noise), charge alteration, etc. In particular, the use of a uniform bit line voltage requires the application of smaller program gate steps to maintain a target program state width, resulting in a large number of program pulses and slower programming time.

[0024] Aspects of the present disclosure solve the above and other deficiencies by applying a tracked or matched analog or continuous voltage on a bit line that tracks or matches a threshold voltage associated with one or more memory cells of a memory sub-system. According to aspects of the present disclosure, a program threshold voltage width target for a distribution of memory cells for a program state is managed and maintained. In response to a command for execution of a program operation associated with one or more target memory cells of a selected word line, a program pulse is generated and applied to the selected word line.

[0025] After the program pulse, a program verify operation (e.g., a read of the memory cell to determine its contents and a comparison of the read data to the desired data) is performed to determine whether the memory cell has been properly programmed. If the program verify operation determines that the memory cell has not been programmed with the desired data, the threshold voltage for the memory cell is checked to determine whether it has reached the pre-verify voltage level for that particular program state. When the threshold voltage for that particular program state reaches the corresponding pre-verify voltage level, the programming of that particular cell is slowed down during a subsequent program pulse by applying an analog voltage level to the bit line coupled to the cell (e.g., biasing the bit line).

[0026] Advantageously, the analog or continuous voltage level on the bit line (an "analog bit line voltage level" or "continuous bit line voltage level" herein) is an analog match to the threshold voltage of the target memory cell. A sense node of the sense circuit associated with the target memory cell can be used to store the threshold voltage of the target memory cell after the program verify operation and comparison of the measured threshold voltage of the memory cell to the pre-verify voltage level. After the program verify operation, the sense node associated with the target memory cell can store the measured threshold voltage of the target memory cell.

[0027] During the next program pulse at the stepped or increased level, the sense node is sensed to identify the measured threshold voltage and set the continuous bit line voltage level to match the measured threshold voltage. Thus, during the phase where the threshold voltage of the target memory cell is between the pre-verify voltage level and the program verify threshold voltage, an analog bit line voltage level that matches the threshold voltage as sensed using the sense node is applied to the bit line associated with the memory cell to slow down the programming of the target memory cell. Advantageously, the programming of each cell that has passed the pre-verify threshold is selectively slowed down for the particular state programmed into the memory cell by applying an analog bit line voltage level based on the threshold voltage level of the memory cell. Other cells that are programmed are not affected by the biasing of the bit line of the target memory cell at the analog bit line voltage level and are allowed to program at their normal programming speed. This results in an improved narrowing of the threshold voltage distribution to maintain a target distribution width using a larger program gate step level, resulting in fewer program pulses and faster programming time without reducing program throughput.

[0028] In one embodiment, the isolation element and the dynamic memory element are contained in a logic element (e.g., a sense amplifier (SA) latch) in a page buffer circuit between one or more bit line drivers used to perform a pre-charge operation on a bit line of the memory device. In one embodiment, the logic element performs any calculations (e.g., refinements) associated with a current memory access operation and passes the results of the calculations to the dynamic memory element, which is designed to store the results for a given time period. In one embodiment, the dynamic memory element can include one or more semiconductor devices, and associated signal routing, which can be sized to present sufficient capacitance to store the results for a given time period. Once the results are stored in the dynamic memory element, the isolation element can disconnect the logic element from the dynamic memory element. During a subsequent given time period, the one or more bit line drivers can access the dynamic memory element and perform a pre-charge operation on a bit line of the memory device based at least in part on the results of the calculations stored in the dynamic memory element. Because the logic element is isolated from the dynamic memory element during the given time period, the logic element can initiate the performance of a subsequent calculation when the pre-charge occurs using the results of the previous calculation. Once the simultaneous pre-charge and subsequent calculation are complete, the isolation element can reconnect the logic element to the dynamic memory element so that the results of the subsequent calculation will be stored in the dynamic memory element and a subsequent pre-charge operation can be performed without the delay normally associated with performing the subsequent calculation.

[0029] Advantages of this approach include, but are not limited to, the ability to perform a pre-charge of a bit line using the results of a previous calculation while simultaneously performing a subsequent calculation to be used for a subsequent pre-charge operation. As a result, the latency associated with memory access operations is reduced and the performance of the memory device is improved.

[0030] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the present disclosure is illustrated. The memory sub-system 110 can include media such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of these.

[0031] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a solid state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a Secure Digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMM).

[0032] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) capable device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device.

[0033] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 One example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0034] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and to read data from the memory sub-system 110.

[0035] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, serial attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0036] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs) such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0037] Some examples of non-volatile memory devices (e.g., the memory devices 130) include negative-and (NAND) type flash memories and in-place writeable memories such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. Additionally, cross-point non-volatile memories can perform in-place write operations in which non-volatile memory cells can be programmed without being previously erased in comparison to many flash-based memories. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, a single-level cell (SLC), can store one bit per cell. Other types of memory cells, for example, multi-level cells (MLCs), tri-level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, for example, SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0039] While 3D cross-point arrays of non-volatile memory cells, such as NAND-type flash memory (e.g., 2D NAND, 3D NAND), are described, the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non- (NOR) flash memory, as well as electrically erasable programmable read-only memory (EEPROM).

[0040] The memory sub-system controller 115 (or, for simplicity, the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0041] The memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0042] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the local memory 119 of the memory sub-system controller 115 is illustrated as including both a volatile component (e.g., RAM) and a non-volatile component (e.g., ROM), in other embodiments, the local memory 119 can include only a volatile component, only a non-volatile component, or a combination of both. Figure 1 The example memory sub-system 110 of FIG. 1 has been illustrated as including the memory sub-system controller 115, but in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0043] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address (e.g., logical block address (LBA), namespace) and a physical block address (e.g., physical block address) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system 120 into command instructions to access the memory devices 130, as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0044] The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive an address from the memory sub-system controller 115 and decode the address to access the memory devices 130.

[0045] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory sub-system controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device that includes a raw memory device 130 with control logic on-die (e.g., the local media controller 135) and a controller (e.g., the memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0046] In one embodiment, the local media controller 135 of the memory device 130 includes a program convergence management component 113 that can be used to manage program convergence associated with memory cells of the memory device 130. In some embodiments, the local media controller 135 includes at least a portion of the program convergence management component 113.

[0047] In some embodiments, the memory sub-system controller 115 includes at least a portion of the program convergence management component 113. For example, the controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the program convergence management component 113 is part of the host system 110, an application, or an operating system.

[0048] The program convergence management component 113 can reduce a program threshold voltage distribution width of a program distribution by slowing program convergence associated with selected memory cells of the memory sub-system. The program convergence management component 113 manages convergence by causing an analog or continuous voltage level proportional to or matching a threshold voltage associated with the same or multiple selected memory cells to be biased to a bit line of the one or more selected memory cells to reduce a voltage drop across a memory cell transistor, thereby reducing an effective program voltage applied to the one or more selected memory cells. Reducing the program voltage applied during a subsequent program pulse causes a slowing of a movement of a threshold voltage for the one or more selected memory cells. In one embodiment, a bit line bias voltage (V BL ) is adjusted or set to a value determined by sensing a node (e.g., a sense node) storing a threshold voltage value identified during a previous program verify operation.

[0049] In one embodiment, the program convergence management component 113 identifies a requested operation (e.g., a request for a program operation received from the host system 120) and causes a first program pulse to be applied to a memory cell (also referred to as a "target memory cell"). The program convergence management component 113 causes a program verify operation to be performed on the target memory cell to determine whether the threshold voltage of the target memory cell reaches or exceeds a program voltage level (e.g., to determine whether the target memory cell has been programmed). In one embodiment, the program convergence management component 113 determines that the measured threshold voltage of the target memory cell is less than the program threshold voltage.

[0050] In one embodiment, the program convergence management component 113 manages a storage location (e.g., a cache location or node) of the sensing circuitry (e.g., the sensing circuitry 700) associated with the target memory cell (referred to herein as a "sensing node"). In one embodiment, the sensing node stores a measured voltage level associated with the program verify operation. In one embodiment, the measured voltage level matches or is proportional to the threshold voltage of the memory cell. Figure 7

[0051] In one embodiment, the measured voltage level identified during the program verify operation is compared to a pre-verify voltage level. In one embodiment, each program state is associated with a pre-verify voltage level such that when the measured threshold voltage for that particular state reaches the corresponding pre-verify voltage level, the program convergence management component 113 determines that the programming of that particular memory cell will be slowed down by biasing the bit line coupled to the memory cell with the bit line voltage.

[0052] In one embodiment, the program convergence management component 113 identifies one or more selected memory cells that have not been programmed and have a measured voltage level that exceeds a pre-verify voltage level (e.g., the memory cells have a measured voltage between the pre-verify voltage level and the program voltage level) as determined by the program verify operation.

[0053] ​In one embodiment, the program convergence management component 113 slows the programming of the selected memory cell by causing an adjusted bit line voltage to be applied to the bit line corresponding to the selected memory cell. In one embodiment, the program convergence management component 113 identifies a measured voltage level stored in the sense node that matches or is proportional to the threshold voltage of the memory cell and causes the bit line voltage to be adjusted or set to the measured voltage level. In one embodiment, the program convergence management component 113 causes the adjusted bit line voltage to be applied to the bit line in conjunction with one or more subsequent programming pulses until the memory cell is programmed. In one embodiment, once the memory cell is programmed, the program convergence management component 113 causes a bias to be applied to the bit line with a suppress voltage level (e.g., V cc ) to suppress or block programming of the memory cell. Further details regarding the operation of the program convergence management component 113 are described below.

[0054] Figure 2 is a simplified block diagram of a first device in the form of a memory device 130 in communication with a second device in the form of a memory sub-system controller 115 of a memory sub-system (e.g., memory sub-system 110) in accordance with one embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile telephones, and the like. The memory sub-system controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device. Figure 1

[0055] The memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. The memory cells in a logical row are typically connected to the same access line (e.g., word line), while the memory cells in a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. The memory cells of at least a portion of the array 204 (not shown in FIG. 1) are capable of being programmed to one of at least two target data states. Figure 2

[0056] ​​Row decode circuitry 208 and column decode circuitry 210 are provided to decode address signals. Address signals are received and decoded to access the memory cell array 204. The memory device 130 also includes input / output (I / O) control circuitry 212 to manage the input of commands, addresses, and data to the memory device 130 and the output of data and status information from the memory device 130. Address registers 214 are in communication with the I / O control circuitry 212 and the row decode circuitry 208 and column decode circuitry 210 to latch address signals prior to decoding. Command registers 224 are in communication with the I / O control circuitry 212 and control logic 216 to latch incoming commands.

[0057] A controller (e.g., a local media controller 135 internal to the memory device 130) controls access to the memory cell array 204 in response to commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 204. The local media controller 135 is in communication with the row decode circuitry 208 and column decode circuitry 210 to control the row decode circuitry 208 and column decode circuitry 210 in response to addresses.

[0058] The local media controller 135 is also in communication with a cache register 218. The cache register 218 latches incoming or outgoing data as directed by the local media controller 135 to temporarily store data while the memory cell array 204 is busy writing or reading other data, respectively. During a program operation (e.g., a write operation), data can be transferred from the cache register 218 to a data register 220 for transfer to the memory cell array 204; new data can subsequently be latched from the I / O control circuitry 212 in the cache register 218. During a read operation, data can be transferred from the cache register 218 to the I / O control circuitry 212 for output to the memory sub-system controller 115; new data can subsequently be transferred from the data register 220 to the cache register 218. The cache register 218 and / or data register 220 can form a page buffer (e.g., can form part of) of the memory device 130. The page buffer can further include sensing means (not shown in FIG. 1) to sense data states of memory cells of the memory cell array 204, e.g., by sensing a state of a data line connected to the memory cell. A status register 222 can be in communication with the I / O control circuitry 212 and the local memory controller 135 to latch status information for output to the memory sub-system controller 115. Figure 2

[0059] ​Memory device 130 receives control signals at memory subsystem controller 115 from local media controller 135 on a control link 232. For example, the control signals can include chip enable CE#, command latch enable CLE, address latch enable ALE, write enable WE#, read enable RE#, and write protect WP#. Additional or alternative control signals (not shown) can further be received on control link 232, depending on the nature of memory device 130. Memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory subsystem controller 115 on a multiplexed input / output (I / O) bus 234 and outputs data to memory subsystem controller 115 on I / O bus 234.

[0060] For example, a command can be received at I / O control circuitry 212 on input / output (I / O) pins [7:0] of I / O bus 234 and can then be written into command register 224. An address can be received at I / O control circuitry 212 on input / output (I / O) pins [7:0] of I / O bus 234 and can then be written into address register 214. Data can be received at I / O control circuitry 212 on input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and can then be written into cache register 218. Data can then be written into data register 220 for programming memory cell array 204.

[0061] In one embodiment, cache register 218 can be omitted and data can be written directly into data register 220. Data can also be output on input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While reference can be made to I / O pins, they can include any electrically conductive node that enables electrical connection to memory device 130 by an external device (e.g., memory subsystem controller 115), such as commonly used electrically conductive pads or electrically conductive bumps.

[0062] It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the Figure 2 memory device 130 has been simplified for this discussion. Figure 2 It will be appreciated by those skilled in the art that the functionality of the various block components described with reference to Figure 2The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component.

[0063] In addition, although specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that combinations of other I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0064] Figure 3 This is a flowchart of an example method 300 for managing programming convergence associated with memory cells of a memory subsystem, according to some embodiments of the present disclosure. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by... Figure 1 The program convergence management component 113 is managed. In one embodiment, the program convergence management component 113 issues commands to cause one or more row drivers of the memory device 130 to apply programming pulses. In one embodiment, the program convergence management component 113 uses aspects of the sensing circuit system management method 300, in Figure 7 An example of the sensing circuit system is shown in the figure.

[0065] At operation 310, a programming pulse is applied. For example, processing logic (e.g., program convergence management component 113) causes a first programming pulse to be applied to a word line associated with a memory cell of the memory subsystem. In one embodiment, the processing logic issues a command to cause one or more row drivers associated with the memory cell to apply a programming pulse to the word line. In one embodiment, the first programming pulse is applied in response to a programming operation request received from the host system. In one embodiment, the programming operation identifies desired data or a programming value to be stored in the memory cell. In one embodiment, a first programming pulse is generated and applied to the word line of the selected memory cell. In one embodiment, the first programming pulse is the initial pulse of a series of incremental voltage programming pulses and has a first or initial voltage value based on a predetermined programming voltage associated with the desired data value.

[0066] In operation 320, a program verification operation is performed. For example, in response to a first programming pulse, processing logic initiates the execution of the program verification operation to determine a measured threshold voltage associated with a memory cell. In one embodiment, the program verification operation is performed by a combination of processing logic associated with a memory cell of the memory subsystem and a sensing circuitry system. The measured value of Vt is also stored by elements of the sensing circuitry system.

[0067] In one embodiment, the program verification operation involves applying a read operation to a memory cell to determine whether the data stored in the memory cell matches a desired data value. In another embodiment, the processing logic determines that the memory cell is not programmed to the desired data value (e.g., the measured threshold voltage of the memory cell is less than a programming threshold level associated with the desired programming state, also known as a pre-verification voltage level (V)). pv ))).

[0068] In one embodiment, the sensing node associated with the memory cell (e.g., Figure 7 The sensing node 718 stores the measured threshold voltage associated with the memory cell. In one embodiment, the sensing node may be a sensing circuit associated with the memory cell (e.g., Figure 7 The temporary storage location (e.g., a cache memory area) of the sensing circuit 700. In one embodiment, the measured threshold voltage is identified during a program verification operation that matches or scales to the threshold voltage of the memory cell.

[0069] In operation 330, a determination is made. For example, the processing logic determines that the measured threshold voltage of the memory cell meets a condition. In one embodiment, if the measured threshold voltage is within a pre-verified voltage level (V... 预先验证 ) and program verification voltage (V pv If the measured threshold voltage is between the pre-verified voltage level and the program verification voltage level, then the condition is met. In one embodiment, each programming state has a pre-verified voltage level that is less than the associated program verification voltage level. In another embodiment, if the measured threshold voltage is greater than the pre-verified voltage level and less than the program verification voltage level, then the condition is met. In response to determining that the condition is met, processing logic identifies or selects an associated memory cell to have its programming slowdown to manage the associated program convergence.

[0070] In operation 340, the threshold voltage is identified. For example, the processing logic identifies the measured threshold voltage stored in the sensing node (e.g., stored in...). Figure 7 (Vt 719 in sensing node 718). As described above with respect to operations 320 and 330, the measured threshold voltage is maintained in the sensing node, which can be accessed or read to identify the measured threshold voltage of the selected memory cell.

[0071] In operation 350, a bit line voltage is applied. For example, the processing logic causes a bit line voltage that matches the measured threshold voltage to be applied to the bit line associated with the memory cell. In one embodiment, the processing logic causes a bias to be applied to the bit line coupled to the memory cell with an adjusted bit line value that tracks or matches the threshold voltage of the memory cell. The application of this analog or adjusted bit line voltage to the bit line reduces the voltage drop across the memory cell transistor, thereby reducing the effective program voltage applied to the cell during a subsequent program pulse (e.g., a second program pulse).

[0072] Figure 4 An example graph 400 illustrating a representation of management of program convergence associated with a memory cell using a bit line voltage proportional to the threshold voltage of the memory cell in accordance with an embodiment is described. As shown, graph 400 includes a plot of the percentage 410 of programmed memory cells of a program distribution as a function of the corresponding threshold voltage 420. In one embodiment, the memory cells are subjected to a series of program pulses (e.g., a first program pulse 430 and a second program pulse 440) to program the respective memory cells to a particular program state. The program pulses 430, 460 are incremented by a step voltage (Vstep) 435, as shown in 跨步 Figure 4

[0073] As described in Figure 3 , a first program pulse 430 is applied at a first voltage level. A program verify operation is performed to compare the measured threshold voltage of the memory cells to a program verify threshold level (VpV) 440. As described, the threshold voltage of the memory cells as measured in the program verify operation following the first program pulse 430 is less than the program verify threshold level 440, and thus none of the memory cells are programmed as a result of the first program pulse 430. pv

[0074] In one embodiment, the measured threshold voltage of each memory cell is compared to a pre-verify threshold level (VpV) 450. As shown, the threshold voltage of the memory cells as measured in the program verify operation following the first program pulse 430 is greater than the pre-verify threshold level 450, and thus none of the memory cells are programmed as a result of the first program pulse 430. 预先验证 ​​​)450. As shown, the pre-verify threshold level 450 is less than the program verify level 440 and can be used to identify memory cells in a slowed programming state that are close to the desired programming. In one embodiment, for one or more memory cells having a measured threshold voltage between the pre-verify threshold level 450 and the program verify level 440, a regulated bit line voltage is applied to the respective bit line during the second program pulse. As shown, during the second program pulse 460, which includes the bit line applying bias voltage, programming of the selected memory cells (e.g., memory cells having a threshold voltage greater than the pre-verify threshold level and less than the program verify threshold level) is slowed, as indicated by line portion 470.

[0075] Figure 5 An example graph 500 representing a representation of a program convergence management scheme according to embodiments including applying a regulated bit line voltage (V bl )510 to selected memory cells to manage programming convergence associated with the memory cells is illustrated. As shown, the graph 500 includes a plot of the regulated bit line voltage 510 applied during a series of program pulses as a function of the corresponding threshold voltage 520. As Figure 5 illustrated in the graph 500, a memory cell is subjected to a series of program pulses (e.g., a first program pulse 530 and a second program pulse 540) to program the respective memory cell to a particular program state.

[0076] During the first program pulse, the regulated bit line voltage is set to 0V (e.g., no applying bias of the bit line is performed). As Figure 5 illustrated in the graph 500, a continuous or analog bit line voltage level 560 is applied to the bit line during the second program pulse of the memory cell for certain identified or selected memory cells. The selected memory cells are identified during a pre-check operation associated with the first program pulse as having a threshold voltage between a pre-verify threshold level 550 and a program verify threshold level 540.

[0077] Figure 6 is a flow diagram of an example method 600 for managing program convergence associated with memory cells of a memory sub-system, according to some embodiments of the present disclosure. The method 600 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the program convergence management component 113 of the memory sub-system 100 of Figure 1 FIG. 1.

[0078] At operation 610, a command is received. For example, processing logic (e.g., program convergence management component 113) receives a command, such as a command to program data to one or more memory cells. In response to the command, at operation 620, a program pulse is generated. For example, processing logic causes a program pulse (e.g., first program pulse 430) to be generated and applied to the selected word line. In one embodiment, during the program pulse applied in operation 620, no bias voltage is applied to the bit line associated with the selected word line. Figure 4

[0079] At operation 630, a program verify operation is performed. For example, processing logic performs a program verify operation to determine whether the memory cell has been properly programmed. In one embodiment, processing logic reads the voltage level stored in the memory cell and compares the level to a required level to confirm whether the voltage level has reached the required level. At operation 640, a determination is made. For example, processing logic can determine whether the cell has been properly programmed. In one embodiment, if the voltage level reading has reached the required level during the program verify operation, processing logic determines that the memory cell has been properly programmed. If the memory cell has been programmed at operation 640, at operation 645, the bit line is biased at a program inhibit voltage level. In one embodiment, the adjusted bit line voltage is increased from the 0V bit line bias used during the first program pulse to an inhibit voltage (e.g., V CC ).

[0080] At operation 635, the threshold voltage is stored. For example, processing logic can store the measured threshold voltage identified during the program verify operation 630 in a storage location (e.g., sense node) associated with the memory cell.

[0081] If at operation 640, processing logic determines that the memory cell has not passed the required data programming, at operation 650, a determination is made. For example, processing logic can check the measured threshold voltage for the memory cell to determine whether it has reached a pre-verify voltage level. In one embodiment, each program state has a pre-verify voltage level, when the threshold voltage for that particular state reaches that level, the programming of that particular memory cell is slowed by applying a bias to the bit line coupled to the memory cell. As shown in Figure 6 Figure 4 If at operation 640, processing logic determines that the memory cell has not passed the required data programming, at operation 650, a determination is made. For example, processing logic can check the measured threshold voltage for the memory cell to determine whether it has reached a pre-verify voltage level. In one embodiment, each program state has a pre-verify voltage level, when the threshold voltage for that particular state reaches that level, the programming of that particular memory cell is slowed by applying a bias to the bit line coupled to the memory cell. As shown in 跨步

[0082] ​​​In one embodiment, if the processing logic determines at operation 650 that the measured threshold level has reached the pre-verify threshold level, the method 600 proceeds to operation 660. In operation 660, a determination is made. For example, the processing logic determines the threshold voltage level stored at the sense node in operation 635. After the measured and stored threshold voltages of the memory cells caused by the program verify operation 630 have been identified, the bit line voltage is set at operation 680. For example, the processing logic sets the adjusted bit line voltage to the stored threshold voltage level.

[0083] In operation 680, the bit line voltage is applied. For example, the processing logic causes the adjusted bit line voltage to be applied to the bit line of the selected memory cell during the next generated program pulse.

[0084] Advantageously, the processing logic selectively slows the programming of each memory cell that has passed the pre-verify threshold for a particular state programmed into the memory cell by applying a continuous bit line voltage corresponding to the measured threshold voltage level. In one embodiment, other memory cells programmed (e.g., memory cells having a measured threshold voltage that is not between the pre-verify threshold level and the program verify threshold level) are not affected by the bit line applied bias and are allowed to be programmed at their normal programming speed, thereby resulting in the beneficial effect of effectively narrowing the threshold voltage distribution without reducing the amount of programming processing.

[0085] Figure 7 is a schematic diagram of an example sense circuit 700 as can be used with embodiments. The sense circuit 700 is shown connected to a particular memory string 706 by a particular data line 704 (e.g., bit line), for example, as shown in more detail in Figure 7 Although the discussion relates to the use of the sense circuit 700 with a NAND string 706 from a source (SRC) 716 associated with the program convergence management component 113, other memory structures and architectures are suitable for use with the sense circuit 700, where a current path can be selectively formed from the data line 704 to the source 716 depending on the data state of the memory cell selected for sensing.

[0086] In one embodiment, the sense circuit 700 includes a plurality of sense nodes (e.g., transistors 710, 712, and 714) to send and store threshold voltages. In one embodiment, node 714 is turned on (e.g., "1") for a target level and turned off (e.g., "0") for a memory cell that has completed a program verify operation such that the sense node 718 stores or maintains threshold voltage information. In one embodiment, after a program verify operation, the sense node 718 can be probed to determine the stored threshold voltage (Vt) 719 (e.g., at operations 635 and 660 of Figure 6

[0087] In one embodiment, the program verify operation is performed by a combination of a program convergence management component (e.g., program convergence management component 113 of Figure 1 Figure 7

[0088] In one embodiment, the sense circuit 700 can be a component of a data register (e.g., data register 220 of Figure 2 and its output sa_out can be provided as an input to a cache register (e.g., cache register 218 of Figure 2 for output of a sensed data state from the memory device 130. The output signal sa_out on output line 722 can include a signal generated by a latch (e.g., latching circuit) that represents a logic level, for example, a logic 'high' (e.g., represented by Vcc) or a logic 'low' (e.g., represented by VSS) level indicative of a sensed data state of a selected memory cell of the NAND string 206, for example.

[0089] In one embodiment, the control signals of the sense circuit 400 can be provided by a program convergence management component 113 of an internal controller (e.g., local media controller 135 of Figure 1 and Figure 2 In one embodiment, the control signals (e.g., both voltage levels and timing) are defined by the sense operation and are different from the signals generated in response to performing the sense operation (e.g., the output signal sa_out or voltage levels generated on the sense node 718).

[0090] Figure 8 An example machine is illustrated in FIG. 8 that is configured to implement one or more of the methods discussed herein. In some embodiments, the computer system 800 can correspond to a host system (e.g., host system 120 of Figure 1 that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of​​​Figure 1 memory subsystem 110) or can be used to perform operations of the controller (e.g., to execute an operating system to perform operations corresponding to Figure 1 In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environments, as a peer machine in peer-to-peer (or distributed) network environments, or as a server or a client machine in cloud computing infrastructure or environments.

[0091] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0092] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0093] Processing device 802 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or

[0094] The data storage system 818 can include a machine-readable storage medium 824 (also known as a computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 can also reside, completely or at least partially, within the main memory 804 and / or within the processing device 802 during execution thereof by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media. The machine-readable storage medium 824, data storage system 818, and / or main memory 804 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0095] In one embodiment, the instructions 826 include instructions to implement functionality corresponding to a selective repositioning component (e.g., program convergence management component 113 of FIG. 1). Figure 1 While the machine-readable storage medium 824 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0096] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These

[0097] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0098] ​The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0099] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0100] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium can include any mechanism for storing information in a form accessible by a machine (e.g., computer, etc.). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., readonly memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.).

[0101] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method for performing memory operations, comprising: This causes the first programming pulse to be applied to the word line associated with the memory cell of the memory device; In response to the first programming pulse, a program verification operation is performed on the memory cell to determine a measured threshold voltage associated with the memory cell; The measured threshold voltage associated with the memory cell is stored in the sensing node associated with the memory cell; Determine that the measured threshold voltage of the memory cell meets the condition; Identify the measured threshold voltage stored in the sensing node; as well as During the second programming pulse, a bit line voltage matching the measured threshold voltage is applied to the bit line associated with the memory cell.

2. The method of claim 1, further comprising comparing the measured threshold voltage with a pre-verified threshold level.

3. The method of claim 2, wherein the condition is satisfied when the measured threshold voltage of the memory cell is greater than the pre-verification threshold level and less than the program verification threshold level associated with the program verification operation.

4. The method of claim 1, further comprising causing the second programming pulse to be applied to the word line associated with the memory cell, wherein the bit line voltage is applied to the bit line associated with the memory cell during the application of the second programming pulse.

5. The method of claim 1, further comprising receiving from a host system a command to perform a programming operation to program the memory cell into a programmed state.

6. The method of claim 1, further comprising: In response to the second programming pulse, another program verification operation is performed on the memory cell.

7. The method of claim 6, further comprising: Taking into account the other program verification operation, it is determined that the memory cell has been programmed to a programmed state; as well as In response to determining that the memory cell has been programmed into the programmed state, a subsequent bit line voltage matching the suppression voltage level is applied to the bit line associated with the memory cell.

8. The method of claim 1, further comprising causing the second programming pulse to be applied to the word line associated with the memory cell.

9. A non-transitory computer-readable medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: This causes the generation of the first programming pulse to be applied to the memory cell of the memory device; This causes a program verification operation to be performed on the memory cell, comparing the threshold voltage of the memory cell with the program verification threshold voltage; In response to a condition being met, the threshold voltage of the memory cell stored in the memory location associated with the memory cell is identified; and During the second programming pulse, a bit line voltage matching the threshold voltage is applied to the bit line associated with the memory cell.

10. The non-transitory computer-readable medium of claim 9, wherein the condition is satisfied in response to any of the following: Considering the program verification operation, it is determined that the threshold voltage is less than the program verification threshold voltage; and The threshold voltage is determined to be greater than the pre-verified threshold voltage, wherein the pre-verified threshold voltage is less than the program verification threshold voltage.

11. The non-transitory computer-readable medium of claim 9, wherein causing the bit line voltage matched with the threshold voltage to be applied to the bit line associated with the memory cell reduces the rate of programming associated with the memory cell.

12. The non-transitory computer-readable medium according to claim 9, In response to the second programming pulse, another program verification operation is performed on the memory cell; Taking into account the other program verification operation, it is determined that the memory cell has been programmed to a programmed state; and In response to determining that the memory cell has been programmed into the programmed state, a subsequent bit line voltage matching the suppression voltage level is applied to the bit line associated with the memory cell.

13. A memory device comprising: Memory array; as well as Control logic, which is operatively coupled to the memory array, performs operations including the following: This causes a first programming pulse to be applied to the word line associated with the memory cell of the memory array; In response to the first programming pulse, a program verification operation is performed on the memory cell to determine a measured threshold voltage associated with the memory cell; The measured threshold voltage associated with the memory cell is stored in the sensing node associated with the memory cell; Determine that the measured threshold voltage of the memory cell meets the condition; Identify the measured threshold voltage stored in the sensing node; as well as During the second programming pulse, a bit line voltage matching the measured threshold voltage is applied to the bit line associated with the memory cell.

14. The memory device of claim 13, the operation further comprising comparing the measured threshold voltage with a pre-verified threshold level.

15. The memory device of claim 14, wherein the condition is satisfied when the measured threshold voltage of the memory cell is greater than the pre-verification threshold level and less than the program verification threshold level associated with the program verification operation.

16. The memory device of claim 13, the operation further comprising causing the second programming pulse to be applied to the word line associated with the memory cell.

17. The memory device of claim 13, the operation further comprising receiving from a host system a command to perform a programming operation to program the memory cell into a programmed state.

18. The memory device of claim 13, wherein the operation further comprises: In response to the second programming pulse, another program verification operation is performed on the memory cell.

19. The memory device of claim 18, wherein the operation further comprises: Taking into account the other program verification operation, it is determined that the memory cell has been programmed to the programming state.

20. The memory device of claim 19, wherein the operation further comprises: In response to determining that the memory cell has been programmed into the programmed state, a subsequent bit line voltage matching the suppression voltage level is applied to the bit line associated with the memory cell.

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