Multi-level cell configuration for nonvolatile memory elements in bit cells

Abstract

The present invention relates to a multi-level cell configuration for non-volatile memory elements in a bit cell, and discloses a structure including a non-volatile memory element and a method for manufacturing a structure including a non-volatile memory element. A first, a second, and a third non-volatile memory element each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.

Description

Technical Field

[0001] The present invention relates to integrated circuit and semiconductor device manufacturing, and more particularly, to a structure including a non-volatile memory element and a method of manufacturing the structure including a non-volatile memory element. Background Art

[0002] Resistive random access memory (ReRAM or RRAM) devices provide an embedded non-volatile memory technology. Because their memory elements are non-volatile, RRAM devices retain stored data when the memory elements are not powered. The non-volatility of RRAM devices contrasts with volatile memory technologies, such as dynamic random access memory (DRAM) devices, where data stored is lost if not periodically refreshed, and static random access memory (SRAM) devices, where data stored is eventually lost when power is removed.

[0003] Data is stored in the memory element of each bit cell of a resistive random access memory device by changing the resistance across the switching layer to provide different resistance states, namely a high resistance state and a low resistance state. The switching layer can be written in the low resistance state by applying a bias voltage sufficient to form one or more filaments that define a conductive path bridged across the thickness of the switching layer. A high resistance state can also be written by applying a bias voltage across the switching layer to destroy the filaments.

[0004] Improved structures including non-volatile memory elements and methods of making structures including non-volatile memory elements are needed. Summary of the invention

[0005] According to one embodiment of the present invention, a structure includes: a first nonvolatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, a second nonvolatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, and a third nonvolatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element. A second bit line is coupled to the first electrode of the third nonvolatile memory element.

[0006] According to another embodiment of the present invention, a method includes: forming a first nonvolatile memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, forming a second nonvolatile memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, and forming a third nonvolatile memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The method also includes forming a first bit line coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element, and forming a second bit line coupled to the first electrode of the third nonvolatile memory element. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention given above and the detailed description of the embodiments given below, are used to explain the embodiments of the present invention. In the accompanying drawings, the same reference numerals represent the same features in different drawings.

[0008] Figure 1 is a diagrammatic top view of the structure of a multi-bit, multi-level bit cell in accordance with an embodiment of the present invention.

[0009] Figure 2 It is roughly along Figure 1 A cross-sectional view taken along line 2-2 in FIG.

[0010] Figure 3 It is roughly along Figure 1 A cross-sectional view taken along line 3-3 in FIG.

[0011] Figure 4 It is roughly along Figure 1 A cross-sectional view taken along line 4-4 in FIG. DETAILED DESCRIPTION

[0012] refer to Figure 1-Figure 4 And according to an embodiment of the present invention, a structure 10 for a multi-bit, multi-level bitcell includes a non-volatile memory element 12, a non-volatile memory element 13, a non-volatile memory element 14, and a field effect transistor 16. The field effect transistor 16 can be fabricated by a complementary metal oxide semiconductor process using a substrate 18 comprising a semiconductor material such as single crystal silicon. The structure 10 can be part of a memory array including a plurality of bitcells, each of which is substantially similar or identical to the structure 10.

[0013] Field effect transistor 16 may include a gate electrode 22, a gate dielectric layer 24, a source region 26, and a drain region 28. Gate electrode 22 may be composed of heavily doped polysilicon deposited as a capping layer over substrate 18 and patterned using photolithography and etching processes, and gate dielectric layer 24 may be composed of silicon dioxide deposited and patterned when patterning gate electrode 22. Alternatively, gate electrode 22 may be a metal gate formed by a gate-first process or a replacement gate process, and gate dielectric layer 24 may be composed of a high-k dielectric material. Gate electrode 22 may include a plurality of fingers interconnected to one another at one end. Source region 26 and drain region 28 may be doped portions of substrate 18. Source region 26 and drain region 28 may be doped with n-type dopants (e.g., phosphorus and / or arsenic) that provide n-type conductivity, or, alternatively, source region 26 and drain region 28 may be doped with p-type dopants (e.g., boron) that provide p-type conductivity.

[0014] The interconnect structure 30 may be formed by middle-of-line processing and back-end-of-line processing over the field effect transistor 16 and the substrate 18. The interconnect structure 30 includes a metallization layer having an interlayer dielectric layer 31 and metal features disposed in the interlayer dielectric layer 31. The interlayer dielectric layer 31 may be composed of a dielectric material, such as carbon-doped silicon dioxide. The conductive features in the different interlayer dielectric layers 31 of the interconnect structure 30 connect the field effect transistor 16 to the non-volatile memory element 14 and provide connections for lines for reading data from and writing data to the structure 10.

[0015] The non-volatile memory elements 12, 13, 14 are arranged in a plane of the structure 10, which is located between a metallization level 80 and one or more metallization levels 82 of the interconnect structure 30. The non-volatile memory elements 12, 14 have a side-by-side arrangement in a horizontal direction within the plane, and the non-volatile memory elements 12, 13 also have a side-by-side arrangement in a different horizontal direction within the plane. The non-volatile memory elements 12, 13, 14 are not stacked in a vertical direction within different planes in the interconnect structure 30.

[0016] In one embodiment, the non-volatile memory element 12, 13, 14 can be configured as a resistive memory element, which includes a bottom electrode 38, a switching layer 40 located on the bottom electrode 38, and a top electrode 42 located on the switching layer 40. The switching layer 40 is located in the vertical direction between the bottom electrode 38 and the top electrode 42. The bottom electrode 38 can be composed of a metal, such as ruthenium, platinum, titanium nitride, or tantalum nitride. The switching layer 40 can be composed of a dielectric material, such as silicon dioxide, silicon nitride, or a metal oxide (e.g., magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, or aluminum oxide). The top electrode 42 can be composed of a metal, such as tantalum, hafnium, titanium, copper, silver, cobalt, or tungsten. The bottom electrode 38, the switching layer 40, and the top electrode 42 of each of the non-volatile memory elements 12, 13, 14 can be formed simultaneously by a common lithography and etching process, which forms a stack of deposited layers of their constituent materials.

[0017] Data is stored in the structure 10 by applying a bias voltage to change the individual resistances of the switching layer 40 of the non-volatile memory elements 12, 13, 14 to provide different total resistance levels. The resistance of the switching layer 40 can be reduced by applying a bias voltage across the switching layer 40 to create one or more wire flows or conductive paths that bridge between the electrodes 38, 42. The resistance of the dielectric material can be increased by applying a bias voltage across the switching layer 40 to destroy the wire flows. In this regard, the wire flows are created to write the low resistance state of each non-volatile memory element 12, 13, 14, and the wire flows are destroyed to write the high resistance state of each non-volatile memory element 12, 13, 14.

[0018] In combination, the low resistance state and the high resistance state of the nonvolatile memory elements 12, 13, 14 can be used to store data in multiple levels (e.g., eight state combinations). In one embodiment, the nonvolatile memory elements 12, 13, 14 can have nominally equal sizes so that their resistance values ​​in the high resistance state are approximately equal and their resistance values ​​in the low resistance state are approximately equal. In one embodiment, at least two of the nonvolatile memory elements 12, 13, 14 can have different sizes so that their resistance values ​​in the high resistance state are different and their resistance values ​​in the low resistance state are different, which can increase the number of state combinations that can be used as levels of the structure 10.

[0019] The interconnect structure 30 includes a select line 44 that is physically and electrically connected (i.e., coupled) to the source region 26 of the field effect transistor 16 through one or more source contacts 46. The interconnect structure 30 also includes one or more drain contacts 48, metal islands, and one or more vias 50 that physically and electrically connect (i.e., couple) the drain region 28 of the field effect transistor 16 to the bottom electrode 38 of the non-volatile memory element 12. A word line 52 is coupled to the gate electrode 22 of the field effect transistor 16 through one or more vias (not shown).

[0020] A bit line strap 54 is physically and electrically connected (i.e., coupled) to the top electrode 42 of the nonvolatile memory element 12, and is also physically and electrically connected (i.e., coupled) to the top electrode 42 of the nonvolatile memory element 14. The bit line strap 54 is physically and electrically connected (i.e., coupled) to the bit line 60 through one or more vias 56. In this manner, the bit line strap 54 collectively connects the bit line 60 with the top electrode 42 of the nonvolatile memory element 12 and the top electrode 42 of the nonvolatile memory element 14.

[0021] The bit line 58 is physically and electrically connected (i.e., coupled) to the bottom electrode 38 of the nonvolatile memory element 13 and the bottom electrode 38 of the nonvolatile memory element 14. In one embodiment, the bit line 58 may be directly coupled to the bottom electrode 38 of the nonvolatile memory element 13 and directly coupled to the bottom electrode 38 of the nonvolatile memory element 14. The bit line 62 is physically and electrically connected (i.e., coupled) to the top electrode 42 of the nonvolatile memory element 13. In one embodiment, the bit line 62 may be directly coupled to the top electrode 42 of the nonvolatile memory element 13.

[0022] The bit line 58 and the bit line 62 control access to the nonvolatile memory element 13, and the bit line 58 and the bit line 60 control access to the nonvolatile memory elements 12, 14. The bit line 58 is located in the vertical direction below the nonvolatile memory elements 12, 13, 14, and the bit line strip 54 and the bit lines 60, 62 are located in the vertical direction above the nonvolatile memory elements 12, 13, 14. The bit line 60 is aligned parallel or substantially parallel to the bit line 58, and the bit line 60 is located in the vertical direction above the bit line 58 and above the bit line 62. The nonvolatile memory element 12 overlaps a portion of the bit line 58. However, the nonvolatile memory element 14 is laterally offset (i.e., horizontally offset) from the bit line 58. The bit line 62 is located in the vertical direction between the bit line 58 and the bit line 60, and is coupled only to the top electrode 42 of the nonvolatile memory element 13 and is not coupled to any of the nonvolatile memory elements 12, 14. The bit line 62 is arranged in the same metallization layer 82 as the bit line strap 54, but is laterally offset (i.e., horizontally offset) from the bit line strap 54. The horizontal direction of the offset of the bit line 62 relative to the bit line strap 54 can be transverse to the horizontal direction of the offset of the non-volatile memory element 14 relative to the bit line 58. The non-volatile memory elements 12, 13, 14, the bit line strap 54, and the bit line 62 are located in the vertical direction between the bit line 58 and the bit line 60. The non-volatile memory element 13 is located in the vertical direction between the bit line 60 and the bit line 62.

[0023] A portion of bit line 62 overlaps nonvolatile memory element 13, and nonvolatile memory element 13 overlaps a portion of bit line 58. Bit line 58 is located below and laterally aligned to bit line 62. In the latter aspect, bit line 58 includes a longitudinal axis 68, and bit line 62 includes a longitudinal axis 72 that is laterally aligned with longitudinal axis 68. Nonvolatile memory elements 12, 14 have a spaced arrangement along longitudinal axis 68 of bit line 58. Bit line 60 is located above and laterally aligned with bit line 62. In the latter aspect, bit line 60 includes a longitudinal axis 70 that is laterally aligned with longitudinal axis 72 of bit line 62.

[0024] Source contact 46 and drain contact 48 may be formed in contact openings defined in one or more interlayer dielectric layers 31 by photolithography and etching. Source contact 46 and drain contact 48 may include a lower portion containing a metal silicide, such as tungsten silicide, titanium silicide, nickel silicide, or cobalt silicide formed by silicide, and an upper portion containing a metal, such as tungsten, deposited and planarized by chemical vapor deposition. Select line 44, via 50, word line 52, bit line strap 54, bit lines 58, 60, 62, and metal islands may be formed by a damascene process that patterns trenches in one or more interlayer dielectric layers 31 and fills the trenches with a conductor such as copper.

[0025] In use, both non-volatile memory elements 12, 14 can be written from a high resistance state to a low resistance state by a set operation in the initial step of a two-step process. One or both or both of the non-volatile memory elements 12, 14 can then be written from a low resistance state to a high resistance state by a reset operation to provide multiple levels with different state combinations. In a subsequent step of the two-step process, the non-volatile memory element 13 can then be read and, if necessary, switched to write a high resistance state or a low resistance state by set and reset operations, respectively, which provides a mechanism to provide additional multiple levels with different state combinations. In an alternative sequence of the two-step process, the non-volatile memory element 13 can be read, written if necessary, followed by a subsequent step of writing the non-volatile memory elements 12, 14. The combination of non-volatile memory elements 12, 13, 14 can be placed in a multi-level characterized by different state combinations, where the non-volatile memory elements 12, 13, 14 have different combinations of low resistance and high resistance states. Thus, the structure 10 can be programmed in any of these multiple levels. The bit lines 60, 62 provide an additional biasing mechanism to control the two step process that provides different state combinations of the multiple levels.

[0026] In an alternative embodiment, the non-volatile memory elements 12, 13, 14 may be phase-change material (PCM) memory elements, wherein the switching layer 40 comprises a phase-change material, such as chalcogenide glass (eg, Ge 2 Sb 2 Te 5 ). The phase change material can be heated above the transition temperature and cooled to provide an amorphous phase or a crystalline phase that defines a high resistance and a low resistance state, respectively. More specifically, the phase change material can be heated by applying a current sufficient to raise the temperature of the switching layer 40 above the transition temperature and then cooled to a temperature below the transition temperature to cause a state change. For example, the state change of the phase change material to the amorphous phase or the crystalline phase may depend on, for example, the cooling rate.

[0027] In an alternative embodiment, the non-volatile memory elements 12, 13, 14 may be ferroelectric memory elements comprising a ferroelectric material as the switching layer 40. The ferroelectric material of the switching layer 40 may comprise, for example, lead zirconate titanate (PZT).

[0028] In an alternative embodiment, the non-volatile memory elements 12, 13, 14 may be magnetic-tunnel-junction memory elements. In this regard, each of the non-volatile memory elements 12, 13, 14 may include a pinned or fixed layer, a tunnel barrier layer, and a free layer arranged in a layer stack between the bottom and top electrodes 38, 42. The fixed layer may include one or more layers, such as a reference layer and a hard layer, which are composed of magnetic materials, such as a cobalt-platinum alloy or a cobalt-iron-boron alloy. The tunnel barrier layer may be composed of a non-magnetic dielectric material, such as magnesium oxide or aluminum oxide. The free layer providing the switching layer 40 may include one or more layers composed of a magnetic alloy, such as a cobalt-iron-boron alloy. The magnetization of the reference layer of the fixed layer is pinned so that the magnetization vector cannot be flipped (i.e., rotated) under the influence of the programming current. The magnetization of the free layer is not fixed so that the magnetization vector can be flipped (i.e., rotated) under the influence of the programming current.

[0029] The field effect transistor 16 and the non-volatile memory elements 12, 13, 14 have a 1T3R (single transistor, three resistor) multi-level cell (MLC) configuration capable of storing multiple bits in a single bit cell, which may result in an increase in density and a reduction in cost-per-bit compared to conventional non-volatile memory bit cells. The non-volatile memory elements 12, 13, 14 may be formed by the same lithography and etching processes, which promotes efficient manufacturing.

[0030] The method described above is used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0031] References herein to terms modified by approximating language, such as "about," "approximately," and "substantially," are not limited to the precise value specified. Approximate language may correspond to the precision of the instrument used to measure the value and may mean + / - 10% of the stated value unless the precision of the instrument is otherwise relied upon.

[0032] References to terms such as "vertical", "horizontal", etc. are made herein by way of example and not limitation to establish a frame of reference. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0033] A feature that is "connected" or "coupled" or "connected" or "coupled" to another feature may be directly connected or coupled to or coupled to the other feature, or alternatively, one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to or "directly coupled to" another feature if there are no intervening features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if there are at least one intervening feature. A feature that is "on" or "contacting" another feature may be directly on or directly contacting the other feature, or alternatively, one or more intervening features may be present. A feature may be "directly on" or "directly in contact with" another feature if there are no intervening features. A feature may be "indirectly on" or "indirectly in contact with" another feature if there are at least one intervening feature.

[0034] The description of various embodiments of the present invention is presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, include: A first nonvolatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; A second nonvolatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; a third nonvolatile memory element, comprising a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; a first bit line coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element; a second bit line coupled to the first electrode of the third nonvolatile memory element; as well as A third bit line is coupled to the second electrode of the first nonvolatile memory element and the second electrode of the third nonvolatile memory element.

2. The semiconductor structure according to claim 1, in, The first bit line includes a first longitudinal axis, and the second bit line includes a second longitudinal axis laterally aligned with the first longitudinal axis of the first bit line.

3. The semiconductor structure according to claim 1, in, The first bit line includes a first longitudinal axis, the second bit line includes a second longitudinal axis laterally aligned with the first longitudinal axis of the first bit line, and the third bit line includes a third longitudinal axis aligned parallel to the first longitudinal axis of the first bit line.

4. The semiconductor structure according to claim 1, in, The third non-volatile memory element is located in a vertical direction between the second bit line and the third bit line.

5. The semiconductor structure according to claim 4, in, The first non-volatile memory element is located in the vertical direction between the first bit line and the third bit line.

6. The semiconductor structure according to claim 1, further comprising: include: a bit line strap coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element, The first bit line is coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element through the bit line strap.

7. The semiconductor structure according to claim 1, further comprising: include: field effect transistor, including a drain, The drain of the field effect transistor is coupled to the second electrode of the second non-volatile memory element.

8. The semiconductor structure according to claim 1, in, The first nonvolatile memory element and the third nonvolatile memory element are arranged in parallel above the third bit line, and the first nonvolatile memory element and the third nonvolatile memory element are placed to be laterally offset relative to the second bit line.

9. The semiconductor structure according to claim 1, in, The third bit line is directly coupled to the second electrode of the first nonvolatile memory element and the second electrode of the third nonvolatile memory element.

10. The semiconductor structure according to claim 1, in, The first nonvolatile memory element is spaced apart from the third nonvolatile memory element along a longitudinal axis of the third bit line.

11. The semiconductor structure according to claim 1, in, The switching layer of the first non-volatile memory element and the switching layer of the second non-volatile memory element each include a dielectric material.

12. The semiconductor structure according to claim 1, in, The switching layer of the first non-volatile memory element and the switching layer of the second non-volatile memory element each include a phase change material.

13. The semiconductor structure according to claim 1, in, The switching layer of the first non-volatile memory element and the switching layer of the second non-volatile memory element each include a ferroelectric material.

14. A semiconductor structure, include: A first nonvolatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; A second nonvolatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; a third nonvolatile memory element, comprising a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; a first bit line coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element, the first bit line comprising a first longitudinal axis; as well as a second bit line coupled to the first electrode of the third nonvolatile memory element, the second bit line comprising a second longitudinal axis, The second longitudinal axis of the second bit line is laterally aligned with the first longitudinal axis of the first bit line.

15. The semiconductor structure according to claim 14, further comprising: include: a bit line strap coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element, The first bit line is coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element through the bit line strap.

16. A method of manufacturing a semiconductor structure, include: forming a first nonvolatile memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; forming a second nonvolatile memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; forming a third nonvolatile memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode; forming a first bit line coupled to the first electrode of the first nonvolatile memory element and the first electrode of the second nonvolatile memory element; forming a second bit line coupled to the first electrode of the third nonvolatile memory element; as well as A third bit line coupled to the second electrode of the first nonvolatile memory element and the second electrode of the third nonvolatile memory element is formed.

17. The method according to claim 16, in, The first nonvolatile memory element, the second nonvolatile memory element, and the third nonvolatile memory element are simultaneously formed by photolithography and etching processes.

18. The method according to claim 16, in, The first bit line includes a first longitudinal axis, the second bit line includes a second longitudinal axis laterally aligned with the first longitudinal axis of the first bit line, and the third bit line includes a third longitudinal axis aligned parallel to the first longitudinal axis of the first bit line.

19. The method according to claim 16, in, The third non-volatile memory element is located in a vertical direction between the second bit line and the third bit line, and the first non-volatile memory element is located in the vertical direction between the first bit line and the third bit line.

20. The method according to claim 16, in, The first bit line includes a first longitudinal axis and the second bit line includes a second longitudinal axis laterally aligned with the first longitudinal axis of the first bit line.

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