Display panel

Abstract

The present application provides a display panel, which includes: a substrate; an auxiliary electrode disposed on one side of the substrate; an insulating layer disposed on the side of the auxiliary electrode away from the substrate, the insulating layer including an undercut structure that penetrates the insulating layer and corresponds to the auxiliary electrode, and the size of the end of the undercut structure away from the substrate is smaller than the size of the end of the undercut structure close to the substrate; and a light-emitting device layer disposed on the side of the insulating layer away from the auxiliary electrode, the light-emitting device layer including a cathode layer, the undercut structure disconnects the part of the cathode layer corresponding to the undercut structure, and a part of the cathode layer extends along the side wall of the undercut structure to contact the auxiliary electrode.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel. Background Art

[0002] When an organic light-emitting diode display panel is applied to a large-size display panel, a phenomenon of uneven brightness occurs, seriously affecting the display effect of the large-size organic light-emitting diode display panel.

[0003] Therefore, it is necessary to propose a technical solution to solve the problem of uneven brightness of large-size organic light-emitting display panels. Summary of the Invention

[0004] The purpose of this application is to provide a display panel to solve the problem of uneven brightness of large-size organic light-emitting diode display panels.

[0005] To achieve the above purpose, the technical solution is as follows:

[0006] A display panel, the display panel includes:

[0007] A substrate;

[0008] An auxiliary electrode disposed on one side of the substrate;

[0009] An insulating layer disposed on the side of the auxiliary electrode away from the substrate, the insulating layer includes an undercut structure, the undercut structure penetrates through the insulating layer and is disposed corresponding to the auxiliary electrode, and the size of the end of the undercut structure away from the substrate is smaller than the size of the end of the undercut structure close to the substrate; and

[0010] A light-emitting device layer disposed on the side of the insulating layer away from the auxiliary electrode, the light-emitting device layer includes a cathode layer, the undercut structure disconnects a part of the cathode layer disposed corresponding to the undercut structure, and a part of the cathode layer extends along the side wall of the undercut structure to contact the auxiliary electrode.

[0011] In some embodiments, the undercut structure includes:

[0012] A protruding portion located at the end of the undercut structure away from the substrate, the protruding portion protrudes towards the center direction of the undercut structure relative to the end of the undercut structure close to the substrate, and the protruding portion disconnects a part of the cathode layer disposed corresponding to the undercut structure; and

[0013] An inclined portion, a part of the inclined portion is located on the auxiliary electrode and is disposed opposite to the protruding portion, the slope of the inclined portion is greater than 0 degree and less than 90 degrees, and a part of the cathode layer extends along the side wall of the inclined portion to contact the auxiliary electrode.

[0014] In some embodiments, the insulating layer includes:

[0015] A passivation layer, the passivation layer is located between the auxiliary electrode and the light-emitting device layer, and the passivation layer includes the protruding portion;

[0016] The display panel further includes a planarization layer, the planarization layer is located between the passivation layer and the light-emitting device layer, the planarization layer includes a first through hole, the first through hole penetrates the planarization layer and communicates with the undercut structure, and the size of the first through hole is larger than the size of the end of the undercut structure away from the substrate.

[0017] In some embodiments, the insulating layer includes:

[0018] A passivation layer, the passivation layer is located between the auxiliary electrode and the light-emitting device layer; and

[0019] A planarization layer, the planarization layer is located between the passivation layer and the light-emitting device layer;

[0020] Wherein, the passivation layer and the planarization layer include the protruding portion.

[0021] In some embodiments, the display panel further includes:

[0022] A pixel definition layer, the pixel definition layer is located between the insulating layer and the cathode layer, the pixel definition layer includes a plurality of pixel openings and dams arranged around the pixel openings, and the dams include:

[0023] A second through hole, the second through hole penetrates the dam and is communicatively arranged with the undercut structure;

[0024] Wherein, the size of the second through hole is larger than the size of the end of the undercut structure away from the substrate.

[0025] In some embodiments, the dam includes:

[0026] A plurality of hydrophilic dams arranged at intervals in a first direction; and

[0027] A plurality of hydrophobic dams arranged at intervals in a second direction, disposed on a side of the plurality of hydrophilic dams away from the substrate, and the second direction is different from the first direction;

[0028] Wherein, the undercut structure is arranged corresponding to the hydrophobic dam;

[0029] At least one of the second through holes penetrates the hydrophobic dam, and / or at least one of the second through holes penetrates the overlapping portion of the hydrophobic dam and the hydrophilic dam.

[0030] In some embodiments, the height of the hydrophobic dam is greater than the height of the hydrophilic dam.

[0031] In some embodiments, the light-emitting device layer further includes an organic light-emitting layer, and the organic light-emitting layer includes:

[0032] A plurality of light-emitting units are disposed in a plurality of the pixel openings. At least two light-emitting units that emit the same color light are disposed between two adjacent hydrophobic dams, and at least two light-emitting units that emit different color lights are disposed between two adjacent hydrophilic dams.

[0033] In some embodiments, the display panel further includes:

[0034] A thin-film transistor array layer is disposed between the insulating layer and the substrate. The thin-film transistor array layer includes a plurality of metal layers, and at least one of the plurality of metal layers of the thin-film transistor array layer includes the auxiliary electrode.

[0035] In some embodiments, the thin-film transistor array layer includes:

[0036] A semiconductor layer is disposed on one side of the substrate;

[0037] A gate metal layer is located on a side of the semiconductor layer away from the substrate. The gate metal layer includes a gate; and

[0038] A source-drain electrode metal layer is located on a side of the gate metal layer away from the semiconductor layer. The source-drain electrode metal layer includes the auxiliary electrode and source-drain electrodes.

[0039] In some embodiments, the light-emitting device layer further includes:

[0040] A functional layer is located between the cathode layer and the auxiliary electrode. The undercut structure disconnects a portion of the functional layer corresponding to the undercut structure. A portion of the cathode layer located in the undercut structure covers the functional layer and contacts the auxiliary electrode.

[0041] Advantageous effects: The present application provides a display panel. The insulating layer between the auxiliary electrode and the cathode layer includes an undercut structure. The undercut structure disconnects a portion of the cathode layer provided corresponding to the undercut structure, and a portion of the cathode layer extends along the sidewall of the undercut structure to contact the auxiliary electrode, so as to improve the problem of resistance voltage drop of the cathode layer and solve the problem of uneven display brightness caused by the resistance voltage drop. In addition, the design of the undercut structure can disconnect the functional layer and prevent the functional layer from covering the auxiliary electrode, resulting in the inability of the cathode layer to contact the auxiliary electrode. Description of the Drawings

[0042] Figure 1Schematic diagram of the display panel according to the first embodiment of the present application;

[0043] Figure 2 is Figure 1 Planar schematic diagram of the pixel definition layer and the organic light-emitting layer shown;

[0044] Figure 3 is Figure 1 Partial enlarged schematic diagram of the undercut structure shown;

[0045] Figure 4 Schematic diagram of the display panel according to the second embodiment of the present application;

[0046] Figure 5 is Figure 4 Partial enlarged schematic diagram of the display panel shown;

[0047] Figures 6A - 6N For manufacturing Figure 4 Process schematic diagram of the display panel shown. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0049] As Figure 1 and Figure 2 shown, Figure 1 is a schematic diagram of the display panel according to the first embodiment of the present application, Figure 2 is Figure 1 Planar schematic diagram of the pixel definition layer and the organic light-emitting layer shown. The display panel 10 has a display area 101 and a pad area 102, and the pad area 102 is located on the periphery of the display area 101.

[0050] The display panel 10 includes a substrate 11, a light-shielding metal layer 12, a buffer layer 13, a semiconductor layer 14, a gate insulating layer 15, a gate metal layer 16, an interlayer insulating layer 17, a source-drain electrode metal layer 18, a passivation layer 19, a planarization layer 20, a pixel definition layer 21, and a light-emitting device layer. Among them, the semiconductor layer 14, the gate insulating layer 15, the gate metal layer 16, the interlayer insulating layer 17, and the source-drain electrode metal layer 18 form a thin-film transistor array layer.

[0051] In this embodiment, the substrate 11 is a glass substrate. In other embodiments, the substrate 11 can be a flexible substrate.

[0052] In this embodiment, the light-shielding metal layer 12 is located on one side of the substrate 11 and is disposed on the substrate 11. The light-shielding metal layer 12 includes light-shielding blocks 121 and lower electrode plates 122, and the light-shielding blocks 121 and the lower electrode plates 122 are spaced apart and disposed in the display area 101. The thickness of the light-shielding metal layer 12 is 1000 Å - 10000 Å. The preparation material of the light-shielding metal layer 12 includes at least one of molybdenum, aluminum, titanium, copper, and silver.

[0053] In this embodiment, the buffer layer 13 covers the light-shielding metal layer 12 and the substrate 11 and extends from the display area 101 to the pad area 102. The thickness of the buffer layer 13 is 1000 Å - 5000 Å. The preparation material of the buffer layer 13 includes at least one of silicon nitride and silicon oxide.

[0054] In this embodiment, the semiconductor layer 14 is located on the side of the buffer layer 13 away from the substrate 11. The semiconductor layer 14 includes active patterns 141 and upper electrode plates 142 that are spaced apart and disposed in the display area 101. The active patterns 141 include channels, the active patterns 141 are disposed corresponding to the light-shielding blocks 121, and the upper electrode plates 142 are disposed corresponding to the lower electrode plates 122. The thickness of the semiconductor layer 14 is 100 Å - 1000 Å. The preparation material of the semiconductor layer 14 is any one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide.

[0055] It should be noted that the upper electrode plate 142 is obtained by conducting part of the semiconductor layer, and the conducting method includes ion implantation and the like. The upper electrode plate 142, the lower electrode plate 122, and the buffer layer 13 between the upper electrode plate 142 and the lower electrode plate 122 form a capacitor.

[0056] In this embodiment, the gate insulating layer 15 is located on the side of the semiconductor layer 14 away from the substrate 11. The gate insulating layer 15 includes a first gate insulating pattern 151 and a second gate insulating pattern 152 that are spaced apart and disposed in the display area 101. The first gate insulating pattern 151 is disposed on the active pattern 141 and corresponds to the channel of the active pattern 141, and the second gate insulating pattern 152 is disposed on the buffer layer 13. The thickness of the gate insulating layer 15 is 1000 Å - 3000 Å, and the preparation material of the gate insulating layer 15 is at least one of silicon nitride or silicon oxide.

[0057] In this embodiment, the gate metal layer 16 is located on the side of the gate insulating layer 15 away from the substrate 11. The gate metal layer 16 includes a gate 161 and a first connection metal block 162. The gate 161 is disposed on the first gate insulating pattern 151 and corresponds to the channel of the active pattern 141. The first connection metal block 162 is disposed on the second gate insulating pattern 152 and is electrically connected to the light-shielding block 121 through a first contact hole 15a penetrating the second gate insulating pattern 152 and the buffer layer 13. The thickness of the gate metal layer 16 is 1000 Å - 10000 Å. The preparation material of the gate metal layer 16 includes at least one of molybdenum, aluminum, titanium, copper, and silver.

[0058] In this embodiment, the interlayer insulating layer 17 covers the gate metal layer 16, the semiconductor layer 14, and the buffer layer 13. The interlayer insulating layer 17 includes a second contact hole 17a, a third contact hole 17b, a fourth contact hole 17c, and a first opening. The second contact hole 17a and the third contact hole 17b are respectively located on opposite sides of the gate 161 and correspond to the active pattern 141. The fourth contact hole 17c corresponds to the first connection metal block 162. The first opening is located in the pad region 102. The thickness of the interlayer insulating layer 17 is 2000 Å - 2 μm. The preparation material of the interlayer insulating layer 17 includes at least one of silicon nitride, silicon oxide, aluminum oxide, and polyimide.

[0059] For example, the interlayer insulating layer 17 includes a first aluminum oxide layer, a silicon oxide layer, a second aluminum oxide layer, and a polyimide layer stacked in sequence. The first aluminum oxide layer is disposed close to the substrate 11, and the polyimide layer is disposed away from the substrate 11. The first aluminum oxide layer, the silicon oxide layer, and the second aluminum oxide layer extend from the display region 101 to the pad region 102, and the polyimide layer is provided with a first opening corresponding to the pad region 102.

[0060] In this embodiment, the source-drain electrode metal layer 18 is located on the side of the interlayer insulating layer 17 away from the substrate 11 and on the interlayer insulating layer 17. The thickness of the source-drain electrode metal layer 18 is 1000 Å - 10000 Å. The preparation material of the source-drain electrode metal layer 18 includes at least one of molybdenum, aluminum, titanium, copper, and silver.

[0061] The source-drain electrode metal layer 18 includes a source electrode 181, a drain electrode 182, an auxiliary electrode 183, and a first conductive pad 184. The source electrode 181, the drain electrode 182, and the auxiliary electrode 183 are all disposed in the display area 101, and the first conductive pad 184 is disposed in the pad area 102. The source electrode 181 and the drain electrode 182 are located on opposite sides of the gate electrode 161. The source electrode 181 is in contact with the active pattern 141 through a second contact hole 17a, the drain electrode 182 is in contact with the active pattern 141 through a third contact hole 17b, and the drain electrode 182 is in contact with the first connection metal block 162 through a fourth contact hole 17c. The auxiliary electrode 183 is located on the interlayer insulating layer 17 in the display area 101. The first conductive pad 184 is located in the first opening and on the interlayer insulating layer 17 in the pad area 102.

[0062] In this embodiment, a passivation layer 19 is disposed on a side of the source-drain electrode metal layer 18 away from the substrate 11. The passivation layer 19 includes a second opening and a fifth contact hole 19a. The second opening is disposed corresponding to the pad area 102, and the second opening communicates with the first opening to expose the first conductive pad 184. The fifth contact hole 19a penetrates through the passivation layer 19 and is disposed corresponding to the drain electrode 182. The thickness of the passivation layer 19 is 1500 Å - 5000 Å. The preparation material of the passivation layer 19 includes at least one of silicon oxide and silicon nitride.

[0063] In this embodiment, the display panel 10 further includes a protection metal layer 26, and the protection metal layer 26 is located on a side of the passivation layer 19 away from the substrate 11. The protection metal layer 26 includes a second connection metal block 261 and a second conductive pad 262. The second connection metal block 261 is disposed in the display area 101 and corresponding to the drain electrode 182. The second connection metal block 261 is in contact with the drain electrode 182 through the fifth contact hole 19a. The second conductive pad 262 is disposed in the pad area 102 and covers the first conductive pad 184. The thickness of the protection metal layer 26 is 500 Å - 2000 Å. The preparation material of the protection metal layer 26 includes at least one of molybdenum and titanium.

[0064] It should be noted that a second conductive pad 262 and a first conductive pad 184 form a pad, and the second conductive pad 262 serves to protect the first conductive pad 184.

[0065] In this embodiment, a planarization layer 20 is disposed on a side of the protection metal layer 26 away from the substrate 11. The planarization layer 20 includes a sixth contact hole 20a and a third opening. The sixth contact hole 20a penetrates through the planarization layer 20 and is disposed corresponding to the second connection metal block 261. The third opening communicates with the second opening to expose the first conductive pad 184. The thickness of the planarization layer 20 is 1.0 μm - 5.0 μm. The preparation material of the planarization layer 20 includes one of polyacrylate and polyimide.

[0066] In this embodiment, the passivation layer 19 and the planarization layer 20 include an undercut structure 191. The undercut structure 191 penetrates through the passivation layer 19 and the planarization layer 20, and the undercut structure 191 is disposed corresponding to the auxiliary electrode 183. The size of the end of the undercut structure 191 away from the substrate 11 is smaller than the size of the end of the undercut structure 191 close to the substrate 11.

[0067] As Figure 3 shown, the undercut structure 191 includes a protruding portion 1911 and an inclined portion 1912, and the protruding portion 1911 and the inclined portion 1912 are oppositely disposed.

[0068] The protruding portion 1911 serves to cut off the functional layer in the following text, preventing the functional layer from covering the auxiliary electrode 183 and causing the cathode layer in the following text to be unable to contact the auxiliary electrode 183. The protruding portion 1911 is located at the end of the undercut structure 191 away from the substrate 11. The protruding portion 1911 protrudes towards the center direction of the undercut structure 191 relative to the end of the undercut structure 191 close to the substrate 11. The protruding portion 1911 includes the planarization layer 20 and the passivation layer 19.

[0069] The design of the inclined portion 1912 is conducive to the cathode layer in the following text extending along the side wall of the inclined portion 1912 to contact the auxiliary electrode 183, thereby improving the problem of uneven display caused by the resistance voltage drop of the cathode layer in the following text. A part of the inclined portion 1912 is located on the auxiliary electrode 183. The slope of the inclined portion 1912 is greater than 0 degrees and less than 90 degrees. The inclined portion 1912 includes the planarization layer 20 and the passivation layer 19. The slope of the inclined portion 1912 can be 45 degrees, 60 degrees, 70 degrees or 80 degrees.

[0070] Specifically, the undercut structure 191 includes a first side wall 191a, a second side wall 191b, a connecting side wall 191c and a third side wall 191d. The first side wall 191a, the second side wall 191b and the third side wall 191d are all inclined relative to the thickness direction of the display panel 10, and the connecting side wall 191c is perpendicular to the thickness direction of the display panel 10. The protruding portion 1911 includes the first side wall 191a and the connecting side wall 191c. The first side wall 191a and the second side wall 191b are located on the same side of the undercut structure 191 and at opposite ends of the undercut structure 191, and the connecting side wall 191c connects the first side wall 191a and the second side wall 191b. The inclined portion 1912 includes the third side wall 191d, and the inclined portion 1912 is connected to both the first side wall 191a and the second side wall 191b.

[0071] Among them, the included angle between the first side wall 191a and the connecting side wall 191c is greater than 0 degrees and less than 90 degrees, such as 45 degrees, 60 degrees, 70 degrees or 80 degrees; the included angle between the second side wall 191b and the connecting side wall 191c is greater than 90 degrees and less than 180 degrees, such as 145 degrees, 120 degrees, 110 degrees or 100 degrees. The third side wall 191d inclines away from the first side wall 191a, and the included angle between the third side wall 191d and the direction perpendicular to the thickness of the display panel 10 is greater than 0 degrees and less than 90 degrees, such as 145 degrees, 120 degrees, 110 degrees or 100 degrees.

[0072] In this embodiment, the pixel definition layer 21 is located on the side of the planarization layer 20 away from the substrate 11 and in the display area 101. The pixel definition layer 21 includes pixel openings 211 and dams 212, and the dams 212 are arranged around the pixel openings 211.

[0073] Among them, the dam 212 includes a second through hole 212a. The second through hole 212a penetrates through the dam 212 and is communicated with the undercut structure 191. The size of the second through hole 212a is larger than the size of the end of the undercut structure 191 away from the substrate 11, so that the cathode layer in the following text can be deposited on the side wall of the second through hole 212a and the side wall of the undercut structure 191, and thus can be overlapped with the auxiliary cathode 183. Among them, the size of the end of the second through hole 212a away from the substrate 11 is larger than the size of the second through hole 212a close to the substrate 11.

[0074] Specifically, the dam 212 includes a plurality of hydrophilic dams 2121, a plurality of hydrophobic dams 2122 and a second through hole 212a.

[0075] The plurality of hydrophilic dams 2121 are arranged at intervals along the first direction, the plurality of hydrophobic dams 2122 are arranged at intervals along the second direction, the second direction is different from the first direction, the plurality of hydrophobic dams 2122 are located on the side of the plurality of hydrophilic dams 2121 away from the substrate 11, and the area enclosed by adjacent two hydrophilic dams 2121 and adjacent two hydrophobic dams 2122 defines the pixel opening 211. The plurality of hydrophilic dams 2121 and the plurality of hydrophobic dams 2122 define a plurality of pixel openings 211.

[0076] Among them, the first direction is perpendicular to the second direction. The longitudinal cross-sections of the hydrophobic dam 2122 and the hydrophilic dam 2121 are both trapezoidal.

[0077] At least one second through-hole 212a penetrates through the hydrophobic dam 2122, and / or, at least one second through-hole 212a penetrates through the overlapping part of the hydrophobic dam 2122 and the hydrophilic dam 2121. Correspondingly, the undercut structure 191 is disposed corresponding to the hydrophobic dam 2122, so as to utilize the hydrophobic property of the hydrophobic dam 2122 to avoid clogging the second through-hole 212a in the following text, which may cause the cathode layer to be unable to effectively contact the auxiliary electrode 183.

[0078] Wherein, the size of one end of the second through-hole 212a close to the substrate 11 is smaller than the size of the other end of the second through-hole 212a far from the substrate 11, so as to ensure that the cathode layer extends along the side wall of the second through-hole 212a to the side wall of the undercut structure 191, and then contacts the auxiliary electrode 183.

[0079] In this embodiment, the height of the hydrophobic dam 2122 is greater than the height of the hydrophilic dam 2121, so as to avoid crosstalk between the light-emitting units emitting different color light in the organic light-emitting layer in the following text.

[0080] Specifically, the height of the hydrophobic dam 2122 is 0.3 micrometers - 1.0 micrometers, and the height of the hydrophilic dam 2121 is 0.5 micrometers - 2.0 micrometers. For example, the height of the hydrophobic dam 2122 is 0.5 micrometers, and the height of the hydrophilic dam 2121 is 1.0 micrometers.

[0081] In this embodiment, the material for preparing the hydrophobic dam 2122 is a hydrophobic organic material, such as an organic compound including an aliphatic chain; the material for preparing the hydrophilic dam 2121 is a hydrophilic organic material, such as an organic compound including a hydrophilic group.

[0082] In addition, the material for preparing the hydrophilic dam 2121 is any one of a positive photoresist or a negative photoresist, and the material for preparing the hydrophobic dam 2122 is any one of a positive photoresist or a negative photoresist.

[0083] In this embodiment, the light-emitting device layer is located on the side of the planarization layer 20 far from the substrate 11. The light-emitting device layer includes an anode layer 231, an organic light-emitting layer 232, a cathode layer 233, and a functional layer 234. The anode layer 231 is located on the planarization layer 20, the organic light-emitting layer 232 is located between the anode layer 231 and the cathode layer 233, and the functional layer 234 is located between the cathode layer 233 and the organic light-emitting layer 232. It can be understood that the functional layer 234 can also be located between the anode layer 231 and the organic light-emitting layer 232.

[0084] In this embodiment, the anode layer 231 includes a plurality of anodes. The pixel definition layer 21 covers a part of each anode, and the pixel opening 211 is disposed corresponding to the anode. The material for preparing the anode layer 231 includes at least one of indium tin oxide, indium, and copper.

[0085] In this embodiment, the organic light-emitting layer 232 includes a plurality of light-emitting units, and the plurality of light-emitting units include light-emitting units that emit at least two different colors of light. For example, it includes a first light-emitting unit R1 that emits red light, a second light-emitting unit G1 that emits green light, and a third light-emitting unit B1 that emits blue light.

[0086] The plurality of light-emitting units are disposed one-to-one in the pixel opening 211 and on the anode. At least two light-emitting units that emit the same color of light are disposed between two adjacent hydrophobic dams 2122, and at least two light-emitting units that emit different colors of light are disposed between two adjacent hydrophilic dams 2121 to avoid crosstalk between light-emitting units that emit different colors.

[0087] For example, the first light-emitting unit R1 that emits red light and the first light-emitting unit R2 that emits red light are disposed between two adjacent hydrophobic dams 2122, and the first light-emitting unit R1 that emits red light, the second light-emitting unit G1 that emits green light, and the third light-emitting unit B1 that emits blue light are all disposed between two adjacent hydrophilic dams 2121.

[0088] In this embodiment, the functional layer 234 is located between the cathode layer 233 and the auxiliary electrode 183. The functional layer 234 at least covers the organic light-emitting layer 232 and the pixel definition layer 21, and the undercut structure 191 disconnects the portion of the functional layer 234 corresponding to the undercut structure 191.

[0089] Wherein, when the functional layer 234 is located between the cathode layer 233 and the organic light-emitting layer 232, the functional layer 234 can be an electron transport layer or a hole blocking layer; when the functional layer 234 is located between the anode layer 231 and the organic light-emitting layer 232, the functional layer 234 can be a hole transport layer or an electron blocking layer.

[0090] In this embodiment, the cathode layer 233 covers the functional layer 234, the undercut structure 191 disconnects the portion of the cathode layer 233 provided corresponding to the undercut structure 191, and a portion of the cathode layer 233 extends along the sidewall of the second through hole 212a and the third sidewall 191d of the inclined portion 1912 to contact the auxiliary electrode 183, so that the portion of the cathode layer 233 in the undercut structure 191 covers the functional layer 234 and contacts the auxiliary electrode. Among them, the preparation material of the cathode layer 233 is a magnesium-silver alloy.

[0091] The display panel of this embodiment includes an undercut structure through a passivation layer and a planarization layer located between the auxiliary electrode and the cathode layer. The undercut structure disconnects a portion of the cathode layer provided corresponding to the undercut structure, and a portion of the cathode layer extends along the sidewall of the undercut structure to contact the auxiliary electrode, so as to improve the problem of resistance voltage drop of the cathode layer and solve the problem of uneven display brightness caused by the resistance voltage drop. In addition, the design of the undercut structure can disconnect the functional layer and prevent the functional layer from covering the auxiliary electrode, resulting in the inability of the cathode layer to contact the auxiliary electrode.

[0092] Please refer to Figure 4 , which is a schematic diagram of the display panel of the second embodiment of this application. Figure 4 The shown display panel is basically similar to the Figure 1 shown display panel. The difference is that the undercut structure 191 only penetrates the passivation layer 19, and the passivation layer 19 includes a protruding portion 1911. The shape of the undercut structure 191 is the same as that of the Figure 1 , which will not be elaborated here; the planarization layer 20 includes a first through hole 20b. The first through hole 20b penetrates the planarization layer 20 and is communicated with the undercut structure 191 and the second through hole 212a. The size of the first through hole 20b is larger than the size of the end of the undercut structure 191 far from the substrate 11, and the size of the second through hole 212a is larger than the size of the first through hole 20b. Among them, the longitudinal section of the first through hole 20b is an inverted trapezoid.

[0093] In this embodiment, as shown in Figure 5 , in the thickness direction perpendicular to the display panel 10, the second sidewall 191b of the protruding portion 1911 is located on the side closer to the fourth sidewall 201 of the protruding portion 1911 and away from the first sidewall 191a of the protruding portion 1911, so as to avoid blocking the undercut structure 191 when preparing the hydrophobic dam 2122 using positive photoresist.

[0094] Furthermore, the distance H between the first sidewall 191a of the protruding portion 1911 and the fourth sidewall 201 of the first through hole 20b close to the protruding portion 1911 is greater than or equal to 2 microns and less than or equal to 10 microns, such as 3 microns, 4 microns, 5 microns or 7 microns, so as to avoid blocking the undercut structure 191 when preparing the hydrophobic dam 2122 using positive photoresist and avoid the first through hole 20b occupying too much space.

[0095] The display panel of this embodiment is provided with an undercut structure on the passivation layer, a first through hole on the planarization layer, and a second through hole on the pixel definition layer. The first through hole is communicated with the undercut structure and the second through hole, so that the cathode layer contacts the auxiliary electrode.

[0096] This application also provides a process schematic diagram of manufacturing the Figure 4 shown display panel. The manufacturing method includes the following steps:

[0097] S101: Form a light-shielding metal layer on the substrate.

[0098] Specifically, provide a substrate 11, on which a display area 101 and a pad area 102 are defined. A first metal film layer covering the entire surface is formed on the substrate 11 by physical deposition, and the first metal film layer is patterned by a first lithography process to obtain a light-shielding metal layer. The light-shielding metal layer includes a light-shielding block 121 and a lower electrode plate 122 disposed in the display area 101, as Figure 6A shown. Among them, the thickness of the light-shielding metal layer is 1000 Å - 10000 Å, and the preparation materials of the light-shielding metal layer include at least one of molybdenum, aluminum, titanium, copper, and silver.

[0099] S102: Form a semiconductor layer on the side of the light-shielding metal layer away from the substrate.

[0100] Specifically, a buffer layer 13 covering the light-shielding metal layer and the substrate 11 is formed by chemical vapor deposition. The buffer layer 13 extends from the display area 101 to the pad area 102. Among them, the thickness of the buffer layer 13 is 1000 Å - 5000 Å. The preparation materials of the buffer layer 13 include at least one of silicon nitride and silicon oxide.

[0101] Then, a semiconductor film layer covering the entire surface is formed by chemical vapor deposition and patterned by a second lithography process to obtain a patterned semiconductor film layer. The patterned semiconductor film layer includes a first semiconductor pattern 143 and a second semiconductor pattern 144, as Figure 6B shown. Among them, the thickness of the patterned semiconductor film layer is 100 Å - 1000 Å. The preparation materials of the patterned semiconductor film layer include any one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide.

[0102] S103: Form a gate metal layer on the side of the patterned semiconductor film layer away from the substrate.

[0103] Specifically, a gate insulating film layer covering the entire surface of the first semiconductor pattern 143, the second semiconductor pattern 144, and the buffer layer 13 is formed by chemical vapor deposition, and the entire surface of the gate insulating film layer is patterned by a third lithography process to obtain a gate insulating layer. The gate insulating layer includes a first gate insulating pattern 151 and a second gate insulating pattern 152. The first gate insulating pattern 151 is disposed on the first semiconductor pattern 143, and the second gate insulating pattern 152 is disposed on the buffer layer 13; then, the second gate insulating pattern 152 and the buffer layer 13 are patterned by a fourth lithography process to obtain a first contact hole 15a penetrating the second gate insulating pattern 152 and the buffer layer 13. Among them, the thickness of the gate insulating layer is 1000 Å - 3000 Å, and the preparation materials of the gate insulating layer include at least one of silicon nitride or silicon oxide.

[0104] Next, a second metal film layer covering the entire surfaces of the first gate insulating pattern 151, the second gate insulating pattern 152, the patterned semiconductor film layer, and the buffer layer 13 is formed by physical deposition. The second metal film layer covering the entire surface is patterned using a fifth lithography process to obtain a gate metal layer. The gate metal layer includes a gate 161 and a first connection metal block 162. The gate 161 is disposed on the first gate insulating pattern 151 and corresponds to the first semiconductor pattern 143. The first connection metal block 162 is disposed on the second gate insulating pattern 152 and is electrically connected to the lower electrode plate 122 through a first contact hole 15a. Among them, the thickness of the gate metal layer is 1000 Å - 10000 Å. The preparation material of the gate metal layer includes at least one of molybdenum, aluminum, titanium, copper, and silver.

[0105] Finally, using the gate 161 as a mask, the first semiconductor pattern 143 is ion-doped to obtain an active pattern 141. The active pattern 141 includes a channel 1411 and two doped portions 1412. The two doped portions 1412 are respectively located on opposite sides of the channel 1411; the second semiconductor pattern 144 is ion-doped to conduct the second semiconductor pattern 144 to obtain an upper electrode plate 142, as Figure 6C shown.

[0106] S104: A source-drain electrode metal layer is formed on the side of the gate metal layer away from the substrate.

[0107] Specifically, an interlayer insulating film layer covering the entire surfaces of the gate metal layer, the buffer layer 13, the upper electrode plate 142, and the active pattern 141 is formed by chemical vapor deposition and coating. The interlayer insulating film layer is patterned using a sixth lithography process to obtain an interlayer insulating layer. The interlayer insulating layer includes a second contact hole 17a, a third contact hole 17b, a fourth contact hole 17c, and a first opening 17d. The second contact hole 17a, the third contact hole 17b, and the fourth contact hole 17c all penetrate the interlayer insulating layer. The depth of the first opening 17d is less than the thickness of the interlayer insulating layer. The second contact hole 17a and the third contact hole 17b are respectively located on opposite sides of the gate 161 and correspond to the two doped portions 1412 of the active pattern 141. The fourth contact hole 17c corresponds to the first connection metal block 162. The first opening 17d is located in the pad region 102.

[0108] Among them, the thickness of the interlayer insulating layer is 2000 Å - 2 μm. The preparation material of the interlayer insulating layer includes at least one of silicon nitride, silicon oxide, aluminum oxide, and polyimide.

[0109] Next, a whole third metal film layer is formed by physical deposition on the second contact hole 17a, the third contact hole 17b, the fourth contact hole 17c, the first opening 17d, and the interlayer insulating layer. The whole third metal film layer is patterned by the seventh lithography process to obtain a source-drain electrode metal layer. The source-drain electrode metal layer includes a source electrode 181, a drain electrode 182, an auxiliary electrode 183, and a first conductive pad 184. The source electrode 181, the drain electrode 182, and the auxiliary electrode 183 are all disposed in the display area 101, and the first conductive pad 184 is disposed in the pad area 102.

[0110] The source electrode 181 and the drain electrode 182 are located on opposite sides of the gate electrode 161. The source electrode 181 is in contact with one doping portion 1412 of the active pattern 141 through the second contact hole 17a, and the drain electrode 182 is in contact with the other doping portion 1412 of the active pattern 141 through the third contact hole 17b. Moreover, the drain electrode 182 is in contact with the first connection metal block 162 through the fourth contact hole 17c. The auxiliary electrode 183 is located on the interlayer insulating layer 17 in the display area 101. The first conductive pad 184 is located in the first opening 17d and on the interlayer insulating layer in the pad area 102, as Figure 6D shown.

[0111] Among them, the thickness of the source-drain electrode metal layer is 1000 Å - 10000 Å. The preparation materials of the source-drain electrode metal layer include at least one of molybdenum, aluminum, titanium, copper, and silver.

[0112] S105: A sacrificial pattern is formed on the auxiliary electrode.

[0113] A sacrificial film layer covering the source-drain electrode metal layer and the interlayer insulating layer is formed by physical deposition. The sacrificial film layer is patterned by the eighth lithography process to obtain a sacrificial pattern SL. The sacrificial pattern SL is located on the auxiliary electrode 183, and the area of the sacrificial pattern SL is smaller than the area of the auxiliary electrode 183, as Figure 6E shown.

[0114] Among them, the thickness of the sacrificial pattern SL is 500 Å - 5000 Å, and the preparation material of the sacrificial pattern SL is any one of indium tin oxide, zinc oxide, and indium gallium zinc oxide.

[0115] S106: A protective metal layer 26 is formed on the side of the sacrificial pattern away from the substrate.

[0116] Specifically, a passivation film layer covering the entire surface of the sacrificial pattern SL, the source-drain electrode metal layer, and the interlayer insulating layer is formed by chemical vapor deposition. The passivation film layer is patterned using a ninth lithography process to obtain a passivation layer. The passivation layer includes a fifth contact hole 19a, a preliminary through hole 19b, and a second opening 19c that penetrate the passivation layer. The fifth contact hole 19a is disposed corresponding to the drain 182, the preliminary through hole 19b is disposed corresponding to the auxiliary electrode 183 and exposes a part of the sacrificial pattern SL, and the second opening 19c is disposed in the pad region 102 and communicates with the first opening 17d. Among them, the thickness of the passivation layer is 1500 Å - 5000 Å. The preparation material of the passivation layer includes at least one of silicon oxide or silicon nitride.

[0117] Next, a fourth metal film layer covering the entire surface is formed in the fifth contact hole 19a, the preliminary through hole 19b, on the passivation layer, and in the second opening 19c. The fourth metal film layer is patterned using a tenth lithography process to obtain a protective metal layer. The protective metal layer includes a second connection metal block 261 and a second conductive pad 262. The second connection metal block 261 is disposed in the display region 101 and corresponds to the drain 182. The second connection metal block 261 contacts the drain 182 through the fifth contact hole 19a. The second conductive pad 262 is disposed in the pad region 102 and covers the first conductive pad 184, as Figure 6F shown. Among them, the thickness of the protective metal layer is 500 Å - 2000 Å. The preparation material of the protective metal layer includes at least one of molybdenum and titanium.

[0118] S107: An anode layer is formed on the side of the protective metal layer away from the substrate.

[0119] Specifically, a first photoresist layer covering the entire surface is formed by coating. The first photoresist layer is exposed and developed using an eleventh lithography process to obtain a planarization layer. The planarization layer includes a sixth contact hole 20a, a first through hole 20b, and a third opening 20c that penetrate the planarization layer. The sixth contact hole 20a is disposed corresponding to the second connection metal block 261, the first through hole 20b communicates with the preliminary through hole 19b, and the third opening 20c is located in the pad region 102 and communicates with the second opening 19c, as Figure 6G shown. Among them, the thickness of the planarization layer is 1.0 μm - 5.0 μm. The preparation material of the planarization layer includes one of polyacrylate and polyimide.

[0120] Next, a physical deposition is used to form an anode film layer covering the entire surface in the sixth contact hole 20a, the first through hole 20b, the third opening 20c, and on the planarization layer. The anode film layer is patterned using a twelfth lithography process to obtain an anode layer 231. The anode layer 231 includes a plurality of anodes. The anodes are electrically connected to the second connection metal block 261 through the sixth contact hole 20a, as Figure 6HAs shown. Among them, the anode layer 231 includes two silver layers and an indium tin oxide layer located between the two silver layers.

[0121] S108: Form a plurality of hydrophilic dams on the side of the anode layer away from the substrate.

[0122] Specifically, a second photoresist layer 213 covering the entire surface of the planarization layer and the anode layer is formed by coating, and the second photoresist layer 213 is patterned by the thirteenth lithography process to obtain a plurality of hydrophilic dams 2121 located in the display area 101 and arranged along the first direction. The hydrophilic dam 2121 includes a first sub-through hole 2121a, and the first sub-through hole 2121a is arranged corresponding to the first through hole 20b, as Figure 6I and Figure 6J shown. Among them, the height of the hydrophilic dam 2121 is 0.3 μm - 1.0 μm. The preparation material of the hydrophilic dam 2121 is one of negative photoresist or positive photoresist.

[0123] The longitudinal section of the first sub-through hole 2121a is an inverted trapezoid, and the size of the first sub-through hole 2121a is larger than the size of the first through hole 20b.

[0124] It should be noted that, as Figure 6I shown, when the second photoresist layer 213 is a negative photoresist, the second photoresist layer 213 irradiated by the ultraviolet light of the photomask is crosslinked and cured, and the second photoresist layer 213 not irradiated by the ultraviolet light is removed after being treated with the developer.

[0125] Then, the sacrificial pattern SL is patterned by a wet etching process to obtain an undercut structure 191, and the undercut structure 191 communicates with the first sub-through hole 2121a and the first through hole 20b. The solution used in the wet etching process can be oxalic acid, etc.

[0126] S109: Form a plurality of hydrophobic dams on the side of the plurality of hydrophilic dams away from the substrate.

[0127] Specifically, a third photoresist layer 214 covering the plurality of hydrophilic dams 2121, the anode layer 231 and filling the undercut structure 191, the first sub-through hole 2121a and the first through hole 20b is formed by coating, and the third photoresist layer 214 is patterned by the fourteenth lithography process to obtain a plurality of hydrophobic dams 2122 located in the display area and arranged along the second direction. The hydrophobic dam 2122 includes a second sub-through hole 2122a, and the second sub-through hole 2122a is located at the overlapping position of the hydrophobic dam 2122 and the hydrophilic dam 2121 and is arranged corresponding to the first sub-through hole 2121a, as Figure 6K shown. Among them, the second direction is perpendicular to the first direction; the height of the hydrophobic dam 2122 is 0.5 μm - 2.0 μm.

[0128] The longitudinal cross-section of the second sub-through hole 2122a is an inverted trapezoid, and the size of the second sub-through hole 2122a is larger than that of the first sub-through hole 2121a. The second sub-through hole 2122a and the first sub-through hole 2121a form the second through hole 212a.

[0129] As Figure 6L shown, when the third photoresist layer 214 is a negative photoresist, using a photomask as a mask plate and ultraviolet light with a wavelength of 300 nm - 450 nm as a light source, the ultraviolet light passing through the photomask irradiates the third photoresist layer to crosslink and cure, while the third photoresist layer 214 not irradiated by the ultraviolet light is removed by the developer.

[0130] As Figure 6M shown, when the third photoresist layer 214 is a positive photoresist, the third photoresist layer 214 irradiated by the ultraviolet light decomposes and is removed after being developed by the developer, while the third photoresist layer 214 not irradiated by the ultraviolet light remains.

[0131] Compared with the third photoresist layer 214 being a positive photoresist, the third photoresist layer 214 being a negative photoresist is more beneficial to avoid the third photoresist layer from clogging the undercut structure 191. The main reason is that when the third photoresist layer is a negative photoresist, the third photoresist layer in the undercut structure 191 can be removed by the developer without ultraviolet light irradiation; while when the third photoresist layer is a positive photoresist layer, part of the third photoresist layer in the undercut structure 191 may be blocked by the planarization layer, and the planarization layer will absorb the ultraviolet light, resulting in the light not being able to irradiate part of the third photoresist layer in the undercut structure 191, causing part of the third photoresist layer in the undercut structure 191 to remain after development and clogging the undercut structure 191.

[0132] It should be noted that the area defined by the intersection of two adjacent hydrophilic dams 2121 and two adjacent hydrophobic dams 2122 is the pixel opening 211, and multiple hydrophilic dams 2121 and multiple hydrophobic dams 2122 define multiple pixel openings 211.

[0133] S110: Form a light-emitting device layer on the side of the multiple hydrophobic dams away from the substrate.

[0134] Specifically, multiple light-emitting units are formed in the pixel openings 211 by vacuum evaporation. At least two light-emitting units emitting the same color light are arranged between two adjacent hydrophobic dams 2122, and at least two light-emitting units emitting different color lights are arranged between two adjacent hydrophilic dams 2121 to avoid crosstalk between light-emitting units emitting different colors.

[0135] Next, a functional layer covering the entire surface of the multiple light-emitting units, the multiple hydrophilic dams 2121, and the multiple hydrophobic dams 2122 is formed by vacuum evaporation, and the undercut structure 191 disconnects the part of the functional layer 234 corresponding to the undercut structure 191.

[0136] Finally, a cathode layer covering the entire functional layer is formed by vacuum evaporation or sputter deposition. The cathode layer 233 covers the functional layer 234. The undercut structure 191 disconnects the portion of the cathode layer 233 corresponding to the undercut structure 191, and a portion of the cathode layer 233 extends along the sidewall of the second sub-through hole 2122a, the sidewall of the first sub-through hole 2121a, the sidewall of the first through hole 20b, and the third sidewall 191d of the inclined portion 1912 to contact the auxiliary electrode 183, as Figure 6N shown.

[0137] It should be noted that the first to tenth patterning processes and the twelfth patterning process in the above text are all implemented by using traditional yellow light processes and etching processes. The traditional yellow light processes and etching processes are all conventional technologies and will not be elaborated in this application.

[0138] The description of the above embodiments is only used to help understand the technical solutions and their core ideas of the present application. Those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, The display panel includes: a substrate; auxiliary electrodes disposed on one side of the substrate; an insulating layer disposed on a side of the auxiliary electrodes away from the substrate, the insulating layer including an undercut structure that penetrates the insulating layer and corresponds to the auxiliary electrodes, and a size of an end of the undercut structure away from the substrate being smaller than a size of an end of the undercut structure close to the substrate; and a light-emitting device layer disposed on a side of the insulating layer away from the auxiliary electrodes, the light-emitting device layer including a cathode layer, the undercut structure disconnecting a portion of the cathode layer corresponding to the undercut structure, and a portion of the cathode layer extending along a sidewall of the undercut structure to contact the auxiliary electrodes; a pixel definition layer located between the insulating layer and the cathode layer, the pixel definition layer including a plurality of pixel openings and dams surrounding the pixel openings, the dams including: a plurality of hydrophilic dams arranged at intervals in a first direction; a plurality of hydrophobic dams arranged at intervals in a second direction, the undercut structure corresponding to the hydrophobic dams, the second direction being different from the first direction; and a second through hole communicating with the undercut structure, at least one of the second through holes penetrating the hydrophobic dams, and / or at least one of the second through holes penetrating a portion where the hydrophobic dams and the hydrophilic dams overlap.

2. The display panel according to claim 1, characterized in that, The undercut structure includes: a protrusion located at an end of the undercut structure away from the substrate, the protrusion protruding toward a center direction of the undercut structure relative to an end of the undercut structure close to the substrate, the protrusion disconnecting a portion of the cathode layer corresponding to the undercut structure; and an inclined portion, a part of the inclined portion being located on the auxiliary electrodes and being disposed opposite to the protrusion, a slope of the inclined portion being greater than 0 degree and less than 90 degrees, and a portion of the cathode layer extending along a sidewall of the inclined portion to contact the auxiliary electrodes.

3. The display panel according to claim 2, characterized in that, The insulating layer includes: a passivation layer, the passivation layer being located between the auxiliary electrodes and the light-emitting device layer, and the passivation layer including the protrusion; The display panel further includes a planarization layer located between the passivation layer and the light-emitting device layer, the planarization layer including a first through hole that penetrates the planarization layer and communicates with the undercut structure, and a size of the first through hole being greater than a size of an end of the undercut structure away from the substrate.

4. The display panel according to claim 2, characterized in that, The insulating layer includes: a passivation layer, the passivation layer being located between the auxiliary electrodes and the light-emitting device layer; and a planarization layer, the planarization layer being located between the passivation layer and the light-emitting device layer; wherein, the passivation layer and the planarization layer include the protrusion.

5. The display panel according to claim 1, characterized in that, A size of the second through hole is greater than a size of an end of the undercut structure away from the substrate.

6. The display panel according to claim 1, characterized in that, A plurality of the hydrophobic dams arranged at intervals in the second direction are disposed on a side of the plurality of the hydrophilic dams away from the substrate.

7. The display panel according to claim 1, characterized in that, A height of the hydrophobic dams is greater than a height of the hydrophilic dams.

8. The display panel according to claim 1, characterized in that, The light-emitting device layer further includes an organic light-emitting layer, and the organic light-emitting layer includes: A plurality of light-emitting units are disposed in the plurality of pixel openings. At least two light-emitting units that emit the same color light are disposed between two adjacent hydrophobic dams, and at least two light-emitting units that emit different color lights are disposed between two adjacent hydrophilic dams.

9. The display panel according to claim 1, characterized in that, The display panel further includes: A thin-film transistor array layer is disposed between the insulating layer and the substrate. The thin-film transistor array layer includes a plurality of metal layers, and at least one of the plurality of metal layers of the thin-film transistor array layer includes the auxiliary electrode.

10. The display panel according to claim 9, characterized in that, The thin-film transistor array layer includes: A semiconductor layer is disposed on one side of the substrate; A gate metal layer, the gate metal layer is located on the side of the semiconductor layer away from the substrate, and the gate metal layer includes a gate; and A source-drain electrode metal layer, the source-drain electrode metal layer is located on the side of the gate metal layer away from the semiconductor layer, and the source-drain electrode metal layer includes the auxiliary electrode and source-drain electrodes.

11. The display panel according to claim 1, wherein The light-emitting device layer further includes: A functional layer, the functional layer is located between the cathode layer and the auxiliary electrode. The undercut structure disconnects the portion of the functional layer corresponding to the undercut structure, and the portion of the cathode layer in the undercut structure covers the functional layer and contacts the auxiliary electrode.

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