Super junction device and manufacturing method

Abstract

The present invention provides a super junction device and a manufacturing method, comprising: 1) etching a first groove and a second groove on the first main surface of a first substrate and a second substrate, the groove being in an inverted trapezoidal shape; 2) bonding the first substrate to the second substrate; 3) thinning the first substrate and retaining a support layer; 4) oxidizing the support layer, corroding and removing the oxide layer to reveal the groove, the groove being in a spindle-shaped structure. The present invention forms a spindle-shaped groove structure by bonding the first substrate and the second substrate, each of which is etched to form an inverted trapezoidal groove, and reveals the spindle-shaped groove structure by thinning. The spindle-shaped groove structure can reduce the charge gap between the P-type column and the N-type column in the super junction structure, so that the super junction device achieves charge balance, thereby improving the withstand voltage performance of the super junction device and reducing the on-resistance of the super junction device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device design and manufacturing, and in particular relates to a super junction device and a manufacturing method thereof. Background Art

[0002] In the field of power semiconductors, a vertical metal oxide semiconductor field effect transistor (MOSFET) formed by a vertical double diffusion process is called a VDMOSFET, or VDMOS for short. For traditional VDMOS, the breakdown voltage is generally increased by increasing the thickness of the epitaxial layer and reducing the doping concentration of the epitaxial layer. However, this method will significantly increase the resistance of the epitaxial layer. The super junction metal oxide semiconductor field effect transistor (SJ-MOSFET) is an improved structure of the VDMOS device. It forms a P-type column and an N-type column by adding an alternating PN structure in the epitaxial layer. When the device is in a blocking state, the longitudinal electric field in the epitaxial layer is almost constant, which greatly reduces the dependence of the device's on-resistance on the breakdown voltage, thereby reducing the device's on-state loss. Therefore, this structure is widely used in devices with high breakdown voltage. Summary of the invention

[0003] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a super junction device and a manufacturing method, which is used to solve the problem in the prior art that the grooves etched are inverted trapezoidal structures, resulting in a large difference in charge between the super junction P-type columns and N-type columns, which is not conducive to charge balance and causes a decrease in the device's withstand voltage.

[0004] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for manufacturing a super junction device, the manufacturing method comprising: 1) providing a first substrate and a second substrate, the first substrate and the second substrate both comprising a first main surface and a second main surface relative to each other, etching a first groove on the first main surface of the first substrate by a photolithography-etching process based on a photomask, the first groove being in an inverted trapezoidal shape; etching a second groove on the first main surface of the second substrate by a photolithography-etching process based on a photomask, the second groove being in an inverted trapezoidal shape; 2) bonding the first main surface of the first substrate to the first main surface of the second substrate; 3) thinning the first substrate from the second main surface of the first substrate so that a supporting layer is retained between the second main surface of the first substrate and the first groove; 4) oxidizing the supporting layer to form an oxide layer, and removing the oxide layer by corrosion to expose the first groove, the first groove and the second groove forming a spindle-shaped groove structure.

[0005] Optionally, the manufacturing method also includes step 5), based on a hard mask plate with the same photomask pattern as that of step 1), directly etching the bottom of the first groove after aligning the hard mask plate with the exposed first groove to increase the bottom width of the first groove so that the morphology of the first groove is roughly rectangular.

[0006] Optionally, the bottom width of the first groove in step 1) is between one quarter and three quarters of the top width, and the bottom width of the second groove is between one quarter and three quarters of the top width.

[0007] Optionally, the depth of the first groove is between 1 and 30 microns, and the depth of the second groove is between 1 and 30 microns.

[0008] Optionally, the depth of the first groove is between 15 and 25 microns, and the depth of the second groove is between 15 and 25 microns.

[0009] Optionally, the etching method in step 1) includes one of reactive ion etching (RIE) and deep silicon etching (ICP).

[0010] Optionally, in step 3), the first substrate is thinned by a chemical mechanical polishing process, and the thickness of the support layer after thinning is between 0.5 microns and 2 microns.

[0011] Optionally, the manufacturing method further includes the steps of: the first substrate and the second substrate are doped with the first conductivity type, and a semiconductor material layer doped with the second conductivity type is filled in the first trench and the second trench to form a super junction structure together with the first substrate and the second substrate.

[0012] Preferably, the manufacturing method also includes the steps of: forming a second conductive type body region on the super junction structure; forming a first conductive type source region in the second conductive type body region; manufacturing a gate structure on the first conductive type source region and the second conductive type body region; forming an insulating layer and an electrode lead-out structure; wherein the second substrate includes a first conductive type drain region.

[0013] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.

[0014] The present invention also provides a super junction device, which includes: a first conductive type drain region; a super junction structure located on the first conductive type drain region, including a first conductive type column and a second conductive type column arranged in sequence, and the second conductive type column has a spindle-shaped morphology; a second conductive type body region formed on the super junction structure; a first conductive type source region formed in the second conductive type body region; a gate structure formed on the first conductive type source region and the second conductive type body region; an insulating layer and an electrode lead-out structure located on the first conductive type source region and the gate structure.

[0015] Optionally, it also includes a second conductivity type contact region formed in the first conductivity type source region.

[0016] Optionally, the depth of the super junction structure is between 30 and 45 microns.

[0017] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.

[0018] As described above, the super junction device and the manufacturing method of the present invention have the following beneficial effects:

[0019] The present invention forms a spindle-shaped groove structure by bonding a first substrate and a second substrate respectively etched to form an inverted trapezoidal groove, and thins the substrate to reveal the spindle-shaped groove structure by chemical mechanical grinding, oxidation, and removal of the oxide layer. The spindle-shaped groove structure can reduce the charge gap between the P-type column and the N-type column in the super junction structure, so that the super junction device reaches charge balance, thereby improving the withstand voltage performance of the super junction device and reducing the on-resistance of the super junction device. At the same time, the present invention thins the substrate by chemical mechanical grinding, oxidation, and removal of the oxide layer. Compared with directly grinding to reveal the groove, the retained support layer can provide support for the groove and its sidewall during grinding, which can effectively avoid the risk of the groove sidewall collapsing easily caused by direct grinding to reveal the groove, and improve the process stability.

[0020] The present invention can thin the back of the first substrate to expose the bottom of the inverted trapezoidal first groove, and then etch from the bottom of the first groove with a smaller width to increase the size of the bottom of the first groove, so that the first groove is rectangular, which can further reduce the charge gap between the P-type column and the N-type column in the super junction structure, so that the super junction device reaches charge balance, thereby improving the withstand voltage performance of the super junction device and reducing the on-resistance of the super junction device. The present invention uses a hard mask with the same pattern as that of etching the inverted trapezoidal first groove, directly etches the bottom of the inverted trapezoidal first groove to make the first groove rectangular, does not need to perform a photolithography step, and can greatly save process costs.

[0021] The super junction device manufactured by the present invention has the advantages of high process stability, strong voltage resistance and low on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 12 Shown is a schematic structural diagram of each step of a method for manufacturing a super junction device according to an embodiment of the present invention.

[0023] Component number description

[0024] 101 First Substrate

[0025] 102 First Groove

[0026] 103 Second substrate

[0027] 104 Support layer

[0028] 105 Oxide layer

[0029] 106 Hard Mask

[0030] 107 Second Groove

[0031] 201 Leakage Area

[0032] 202 Drain electrode

[0033] 203 N-type column

[0034] 204 P-type column

[0035] 205 Body Area

[0036] 206 Source Area

[0037] 207 Contact Zone

[0038] 208 Gate structure

[0039] 209 Insulation layer

[0040] 210 Electrode lead structure DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0043] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0044] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0045] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0046] The key to superjunction devices achieving high withstand voltage and low on-resistance is to achieve PN charge balance by forming N-type and P-type conductive areas in the substrate. Therefore, the ideal P-type conductive area is a rectangle, but due to the limitation of the etching process, the etched groove can only be an inverted trapezoidal structure, which results in a large difference in charge between the P-type column and the N-type column at different depths, which is not conducive to charge balance and has a certain impact on the withstand voltage of the device.

[0047] In order to solve the problem that there is a large difference in charge between the P-type column 204 and the N-type column 203, which is not conducive to charge balance, this embodiment provides a method for manufacturing a super junction device, and the manufacturing method includes the following steps:

[0048] like Figure 1 to Figure 4As shown, firstly, step 1) is performed to provide a first substrate 101, wherein the first substrate 101 includes a first main surface and a second main surface opposite to each other, and a first groove 102 is etched on the first main surface of the first substrate 101 by a photolithography-etching process based on a photomask, and the first groove 102 is in an inverted trapezoidal shape. At the same time, a second substrate 103 is provided, wherein the second substrate 103 includes a first main surface and a second main surface opposite to each other, and a second groove 107 is etched on the first main surface of the second substrate 103 by a photolithography-etching process based on a photomask, and the second groove 107 is in an inverted trapezoidal shape.

[0049] The first substrate 101 and the second substrate 103 may be semiconductor substrates such as a silicon substrate, a silicon germanium substrate, a germanium substrate, etc. In the present embodiment, the first substrate 101 and the second substrate 103 are N-type lightly doped silicon substrates.

[0050] The etching method may be, for example, one of ordinary plasma etching, reactive ion etching RIE and deep silicon etching ICP. Since the first trench 102 and the second trench 107 have a high aspect ratio, such as 10:1 or more, and due to the limitation of the etching process, the sidewalls of the etched first trench 102 and the second trench 107 are inclined inward from the top of the first trench 102 and the second trench 107 to the bottom of the first trench 102 and the second trench 107, so that the first trench 102 and the second trench 107 are inverted trapezoidal. For example, the bottom width of the inverted trapezoidal first trench 102 and the second trench 107 is between one quarter and three quarters of the top width. In a specific implementation process, the bottom width of the inverted trapezoidal first trench 102 and the second trench 107 is one quarter of the top width.

[0051] According to the size requirements of the device, the depth of the first groove 102 may be between 1 and 30 microns. Preferably, the depth of the first groove 102 is between 10 and 25 microns. The depth of the second groove 107 may be between 1 and 30 microns. Preferably, the depth of the second groove 107 is between 10 and 25 microns.

[0052] In this embodiment, after relatively shallow first grooves 102 and second grooves 107 are formed on two substrates respectively, alignment bonding is performed so that the two shallower first grooves 102 and second grooves 107 form a deeper spindle-shaped groove structure. On the one hand, the charge difference between the P-type column and the N-type column in the super junction structure can be reduced, so that the super junction device can achieve charge balance, thereby improving the voltage resistance of the super junction device and reducing the on-resistance of the super junction device. On the other hand, the requirements for the deep trench etching process can be greatly reduced, and the etching difficulty and cost can be greatly reduced.

[0053] like Figure 5 and Figure 6As shown, step 2) is then performed to bond the first main surface of the first substrate 101 to the first main surface of the second substrate 103 .

[0054] In this embodiment, the second substrate 103 is made of the same material as the first substrate 101, and the first substrate 101 and the second substrate 103 are N-type lightly doped silicon substrates. The bonding method of the first substrate 101 and the second substrate 103 can be a silicon-silicon direct bonding process.

[0055] like Figure 7 As shown, step 3) is then performed to thin the first substrate 101 from the second main surface of the first substrate 101 so that a support layer 104 is retained between the second main surface of the first substrate 101 and the first groove 102 .

[0056] For example, a chemical mechanical polishing process can be used to thin the first substrate 101 from the second main surface of the first substrate 101, so that a support layer 104 is retained between the second main surface of the first substrate 101 and the first groove 102. The thickness of the thinned support layer 104 is between 0.5 microns and 2 microns. In a specific embodiment, the thickness of the thinned support layer 104 is 1 micron.

[0057] like Figure 8-Figure 9 As shown, step 4 is then performed to oxidize the support layer 104 to form an oxide layer 105, and remove the oxide layer 105 by etching to expose the first groove 102. The first groove and the second groove form a spindle-shaped groove structure.

[0058] In this embodiment, the support layer 104 is oxidized by a thermal oxidation process so that the support layer 104 is completely oxidized to form an oxide layer 105. Then, the oxide layer 105 is removed by a wet etching process to expose the first groove 102. The etching solution used in the wet etching has a high selectivity for silicon dioxide and silicon. For example, the etching solution can be hydrofluoric acid (HF).

[0059] The present invention thins the substrate by chemical mechanical grinding, oxidation, and removal of the oxide layer 105. Compared with direct grinding to reveal the first groove 102, the retained support layer 104 can provide support for the first groove 102 and its sidewalls during grinding, which can effectively avoid the risk of collapse of the sidewalls of the first groove 102 that is easily caused by direct grinding to reveal the first groove 102, thereby improving process stability.

[0060] The present invention forms a spindle-shaped groove structure by bonding a first substrate and a second substrate respectively etched to form an inverted trapezoidal groove, and thins the substrate to reveal the spindle-shaped groove structure by chemical mechanical grinding, oxidation, and removal of the oxide layer. Compared with the inverted trapezoidal groove structure, the spindle-shaped groove structure can reduce the charge gap between the P-type column and the N-type column in the super junction structure, so that the super junction device reaches charge balance, thereby improving the withstand voltage performance of the super junction device and reducing the on-resistance of the super junction device. At the same time, the present invention thins the substrate by chemical mechanical grinding, oxidation, and removal of the oxide layer. Compared with direct grinding to reveal the groove, the retained support layer can provide support for the groove and its sidewall during grinding, which can effectively avoid the risk of the groove sidewall collapsing easily caused by direct grinding to reveal the groove, and improve the process stability.

[0061] like Figure 10-11 As shown, step 5) is then performed. Based on the hard mask plate 106 having the same photomask pattern as that of step 1), after the hard mask plate 106 is aligned with the first groove 102, the bottom of the first groove 102 is directly etched to increase the bottom width of the first groove 102 so that the morphology of the first groove 102 is roughly rectangular.

[0062] The etching method shown can be one of ordinary plasma etching, reactive ion etching RIE and deep silicon etching ICP. The etching depth can be set to be the same as the depth of the first groove 102 to ensure that the morphology of the first groove 102 is roughly rectangular, and the roughly rectangular means that the first groove 102 is roughly rectangular, which may include a certain degree of morphological change caused by errors caused by technical or process limitations, and such morphological changes should not be excluded from the scope of the claims of this application.

[0063] According to the present invention, after thinning the back side of the first substrate to expose the bottom of the inverted trapezoidal first trench 102, etching is performed from the bottom of the first trench 102 with a smaller width to increase the size of the bottom of the first trench 102, thereby making the first trench 102 rectangular, which can further reduce the charge difference between the P-type column and the N-type column in the super junction structure, so that the super junction device achieves charge balance, thereby improving the voltage resistance performance of the super junction device and reducing the on-resistance of the super junction device.

[0064] The present invention uses a hard mask 106 having the same pattern as that of etching the inverted trapezoidal first trench 102, and directly etches the bottom of the inverted trapezoidal first trench 102 to make the first trench 102 rectangular, without the need for photolithography, which can greatly save process costs.

[0065] like Fig.12As shown, step 6 is then performed: the first substrate 101 and the second substrate 103 are doped with the first conductivity type, and a semiconductor material layer doped with the second conductivity type is filled in the first trench 102 and the second trench 107 to form a super junction structure together with the first substrate 101.

[0066] For example, the second conductive type doped semiconductor material layer may be a P-type silicon layer, which, together with the N-type doped first substrate 101 and the second substrate 103 , is arranged to form a super junction structure in which the P-type columns 204 and the N-type columns 203 are alternately arranged.

[0067] like Fig.12 As shown, step 7) is then performed to form a second conductivity type body region 205 on the super junction structure.

[0068] For example, the P-type body region 205 may be formed on the super junction structure by an ion implantation process.

[0069] like Fig.12 As shown, step 8) is then performed to form a first conductivity type source region 206 in the second conductivity type body region 205 .

[0070] For example, an N-type source region 206 may be formed in the P-type body region 205 by photolithography and ion implantation. In this step, a P-type contact region 207 may be formed in the N-type source region 206 by ion implantation to facilitate subsequent electrical extraction of the N-type source region 206.

[0071] like Fig.12 As shown, step 9 is then performed to form a gate structure 208 on the first conductivity type source region 206 and the second conductivity type body region 205 .

[0072] like Fig.12 As shown, step 10) is finally performed to form an insulating layer 209 and an electrode lead structure 210.

[0073] It should be noted that, in the present embodiment, a first conductive type drain region 201 is formed in the second substrate 103, and a first conductive type drift region may also be formed on the first conductive type drain region 201. After the first conductive type drift is bonded to the first substrate 101, they jointly form the drift region of the super junction device, and a drain electrode 202 is also formed on the first conductive type drain region 201.

[0074] In this embodiment, the first conductivity type is N type, and the second conductivity type is P type. Of course, in other embodiments, the first conductivity type may also be P type, and the second conductivity type may also be N type.

[0075] like Fig.12As shown, this embodiment also provides a super junction device, which includes: a first conductive type drain region 201; a super junction structure, located on the first conductive type drain region, including an N-type column 203 and a P-type column 204 arranged in sequence, and the P-type column 204 has a spindle-shaped morphology; a second conductive type body region 205, formed on the super junction structure; a first conductive type source region 206, formed in the second conductive type body region 205; a gate structure 208, formed on the first conductive type source region 206 and the second conductive type body region 205; an insulating layer 209 and an electrode lead-out structure 210, located on the first conductive type source region 206 and the gate structure 208.

[0076] In this embodiment, the super junction device further includes a second conductivity type contact region 207 formed in the first conductivity type source region 206 .

[0077] In this embodiment, the depth of the super junction structure is between 30 and 45 microns.

[0078] In this embodiment, the first conductivity type is N type, and the second conductivity type is P type. Of course, in other embodiments, the first conductivity type may also be P type, and the second conductivity type may also be N type.

[0079] As described above, the super junction device and the manufacturing method of the present invention have the following beneficial effects:

[0080] The present invention forms a spindle-shaped groove structure by bonding a first substrate and a second substrate respectively etched to form an inverted trapezoidal groove, and thins the substrate to reveal the spindle-shaped groove structure by chemical mechanical grinding, oxidation, and removal of the oxide layer. The spindle-shaped groove structure can reduce the charge gap between the P-type column and the N-type column in the super junction structure, so that the super junction device reaches charge balance, thereby improving the withstand voltage performance of the super junction device and reducing the on-resistance of the super junction device. At the same time, the present invention thins the substrate by chemical mechanical grinding, oxidation, and removal of the oxide layer. Compared with directly grinding to reveal the groove, the retained support layer can provide support for the groove and its sidewall during grinding, which can effectively avoid the risk of the groove sidewall collapsing easily caused by direct grinding to reveal the groove, and improve the process stability.

[0081] The present invention can thin the back of the first substrate to expose the bottom of the inverted trapezoidal first groove, and then etch from the bottom of the first groove with a smaller width to increase the size of the bottom of the first groove, so that the first groove is rectangular, which can further reduce the charge gap between the P-type column and the N-type column in the super junction structure, so that the super junction device reaches charge balance, thereby improving the withstand voltage performance of the super junction device and reducing the on-resistance of the super junction device. The present invention uses a hard mask with the same pattern as that of etching the inverted trapezoidal first groove, directly etches the bottom of the inverted trapezoidal first groove to make the first groove rectangular, does not need to perform a photolithography step, and can greatly save process costs.

[0082] The super junction device manufactured by the present invention has the advantages of high process stability, strong voltage resistance and low on-resistance.

[0083] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a super junction device, characterized in that: The production method comprises: 1) providing a first substrate and a second substrate, wherein the first substrate and the second substrate each include a first main surface and a second main surface opposite to each other, etching a first groove on the first main surface of the first substrate by a photolithography-etching process based on a photomask, wherein the first groove is in an inverted trapezoidal shape; etching a second groove on the first main surface of the second substrate by a photolithography-etching process based on a photomask, wherein the second groove is in an inverted trapezoidal shape; 2) bonding the first main surface of the first substrate to the first main surface of the second substrate; 3) thinning the first substrate from the second main surface of the first substrate so that a supporting layer is retained between the second main surface of the first substrate and the first groove; 4) oxidizing the support layer to form an oxide layer, and removing the oxide layer by etching to expose the first groove, wherein the first groove and the second groove form a spindle-shaped groove structure; 5) Based on a hard mask plate with the same photomask pattern as that of step 1), after aligning the hard mask plate with the exposed first groove, directly etching the bottom of the first groove to increase the bottom width of the first groove so that the morphology of the first groove is roughly rectangular.

2. The method for manufacturing a super junction device according to claim 1, characterized in that: In step 1), the bottom width of the first groove is between one quarter and three quarters of the top width, and the bottom width of the second groove is between one quarter and three quarters of the top width.

3. The method for manufacturing a super junction device according to claim 1, characterized in that: The depth of the first groove is between 1 and 30 micrometers, and the depth of the second groove is between 1 and 30 micrometers.

4. The method for manufacturing a super junction device according to claim 3, characterized in that: The depth of the first groove is between 15 and 25 micrometers, and the depth of the second groove is between 15 and 25 micrometers.

5. The method for manufacturing a super junction device according to claim 1, characterized in that: The etching method of step 1) includes one of reactive ion etching (RIE) and deep silicon etching (ICP).

6. The method for manufacturing a super junction device according to claim 1, characterized in that: In step 3), the first substrate is thinned by a chemical mechanical polishing process, and the thickness of the support layer after thinning is between 0.5 microns and 2 microns.

7. The method for manufacturing a super junction device according to any one of claims 1 to 6, characterized in that: Also includes the steps: The first substrate and the second substrate are doped with a first conductivity type, and a semiconductor material layer doped with a second conductivity type is filled in the first trench and the second trench to form a super junction structure together with the first substrate and the second substrate.

8. The method for manufacturing a super junction device according to claim 7, characterized in that: Also includes the steps: forming a second conductivity type body region on the super junction structure; forming a first conductivity type source region in the second conductivity type body region; Fabricating a gate structure on the first conductive type source region and the second conductive type body region; forming an insulating layer and an electrode lead-out structure; Wherein, the second substrate includes a first conductivity type drain region.

9. The method for manufacturing a super junction device according to claim 7, characterized in that: The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.

10. A super junction device, characterized in that: The super junction device is prepared by the method for preparing a super junction device according to any one of claims 1 to 9, and the super junction device comprises: a first conductivity type drain region; A super junction structure, located on the first conductive type drain region, comprising first conductive type columns and second conductive type columns arranged in sequence, wherein the second conductive type columns are spindle-shaped, and the spindle shape comprises an inverted trapezoidal second groove and a rectangular first groove on the second groove; A second conductive type body region formed on the super junction structure; A first conductivity type source region formed in the second conductivity type body region; A gate structure formed on the first conductive type source region and the second conductive type body region; The insulating layer and the electrode lead-out structure are located on the first conductive type source region and the gate structure.

11. The super junction device according to claim 10, characterized in that: Also included is a second conductivity type contact region formed in the first conductivity type source region.

12. The super junction device according to claim 10, characterized in that: The depth of the super junction structure is between 30 and 45 microns.

13. The super junction device according to claim 10, characterized in that: The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.

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