Thin film transistor, preparation method thereof, display panel and display device

Abstract

The application provides a thin film transistor and a preparation method thereof, a display panel and a display device. The thin film transistor comprises an active layer, a source electrode, a drain electrode and a gate electrode. The gate electrode comprises an aluminum alloy layer and an auxiliary layer which are arranged in layers. The material of the auxiliary layer is selected from TiN or Ti. The thickness of the auxiliary layer is 10nm-60nm. The thin film transistor provided by the application has a gate electrode with low resistance and no hillock problem, thereby being beneficial to improving the display performance of the display panel and the display device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a thin film transistor, a preparation method thereof, a display panel and a display device. BACKGROUND

[0002] An organic light-emitting display device is listed as the next generation display technology with great development prospects due to its advantages of thinness, bendability, low power consumption, wide color gamut, high contrast ratio and the like, and is widely applied to display devices such as mobile phones, tablet computers and displays. The thin film transistor as an important component in the organic light-emitting display device will directly affect the performance of the organic light-emitting display device.

[0003] At present, the gate electrode in the thin film transistor is mostly made of Mo metal, which has a large resistance. With the growth of the gate trace, the scanning signal delay will result in insufficient gate opening time, so that the display panel or display device has problems such as poor display effect and uneven brightness. At the same time, aluminum metal is also used as a gate material due to its low resistance, but the aluminum metal layer is easily affected by water vapor and temperature in the external environment, and hillocks are formed on the surface, which will also affect the display performance of the display panel or display device. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a thin film transistor, a preparation method thereof, a thin film transistor, a display panel and a display device, so as to reduce the resistance of the gate electrode and improve the hillock problem, thereby improving the display performance of the display panel or display device. The specific technical solutions are as follows:

[0005] The first aspect of the present application provides a thin film transistor, which comprises an active layer, a source electrode, a drain electrode and a gate electrode, the gate electrode comprises an aluminum alloy layer and an auxiliary layer which are stacked, the material of the auxiliary layer is selected from TiN or Ti, and the thickness of the auxiliary layer is 10-60 nm.

[0006] In some embodiments of the present application, the thickness of the aluminum alloy layer is 200-700 nm.

[0007] The second aspect of the present application provides a preparation method of a thin film transistor, which comprises the following steps: providing an active layer, a source electrode, a drain electrode and a gate electrode; the preparation method of the gate electrode comprises the following steps: forming an auxiliary layer on the surface of the aluminum alloy layer to obtain the gate electrode, the material of the auxiliary layer is selected from TiN or Ti, and the thickness of the auxiliary layer is 10-60 nm.

[0008] In some embodiments of the present application, the step of forming the auxiliary layer on the surface of the aluminum alloy layer comprises forming the auxiliary layer on the surface of the aluminum alloy layer by a plasma sputtering deposition method, wherein the plasma sputtering deposition method uses a mixture of nitrogen and argon as a protective gas.

[0009] In some embodiments of the present application, the material of the auxiliary layer is TiN, and the volume concentration of the nitrogen is 50%-85%.

[0010] In some embodiments of the present application, the material of the auxiliary layer is Ti, and the volume concentration of the nitrogen is 0%.

[0011] A third aspect of the present application provides a display panel, comprising a substrate and a pixel unit arranged on the substrate, the pixel unit comprising a thin film transistor, a pixel electrode connected to the thin film transistor, and a common electrode arranged opposite to the pixel electrode in a thickness direction of the display panel, the thin film transistor being the thin film transistor in any one of the preceding embodiments.

[0012] A fourth aspect of the present application provides a display device, comprising the display panel in any one of the preceding embodiments.

[0013] Advantages of the embodiments of the present application:

[0014] The thin film transistor provided by the present application comprises an active layer, a source electrode, a drain electrode and a gate electrode, the gate electrode comprises an aluminum alloy layer and an auxiliary layer arranged in a stack, the material of the auxiliary layer is selected from TiN or Ti, and the thickness of the auxiliary layer is 10 nm-60 nm. The thin film transistor provided by the present application has a gate electrode with low resistance and no hillock problem, thereby being beneficial to improving the display performance of the display panel and the display device.

[0015] Of course, implementing any product or method of the present application does not necessarily require achieving all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other embodiments can also be obtained by those skilled in the art based on these drawings.

[0017] Figure 1 A cross-sectional structure schematic diagram of the gate electrode in an embodiment of the present application;

[0018] Figure 2 A cross-sectional structure schematic diagram of the display panel in an embodiment of the present application;

[0019] Figure 3 A cross-sectional structure schematic diagram of a display panel in another embodiment of the present application;

[0020] Figure 4a A 3D microscope photo of a sample in Comparative Example 2;

[0021] Figure 4b A 3D microscope photo of a sample in Example 2;

[0022] Figure 4c A 3D microscope photo of a sample in Example 1;

[0023] Figure 4d A 3D microscope photo of a sample in Example 3;

[0024] Figure 4e A 3D microscope photo of a sample in Example 5;

[0025] Figure 5a A scanning electron microscope photo of sample A before being etched by HF;

[0026] Figure 5b A scanning electron microscope photo of sample A after being etched by HF;

[0027] Figure 5c A scanning electron microscope photo of sample B before being etched by HF;

[0028] Figure 5d A scanning electron microscope photo of sample B after being etched by HF. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0030] A first aspect of the present application provides a thin film transistor comprising an active layer, a source, a drain and a gate, as shown in Figure 1As shown, the gate electrode 50 comprises an aluminum alloy layer 51 and an auxiliary layer 52 arranged in a stack. It can be understood that the auxiliary layer is arranged on one surface of the aluminum alloy layer along the thickness direction of the aluminum alloy layer. The surface can be the entire region of the aluminum alloy layer or a partial region of the aluminum alloy layer, which is not particularly limited in the present application as long as the object of the present application can be achieved. In the gate electrode provided by the present application, the aluminum alloy layer is less likely to cause hillock problem and has lower resistance than the pure aluminum metal layer. In addition, by arranging the auxiliary layer on the surface of the aluminum alloy layer, the hillock problem of the aluminum alloy layer can be effectively improved. The material of the auxiliary layer is selected from TiN or Ti, and the thickness of the auxiliary layer is 10 nm-60 nm. Specifically, the thermal expansion coefficient of the material of the auxiliary layer matches the thermal expansion coefficient of the aluminum alloy layer, which can effectively improve the hillock problem. At the same time, when the thickness of the auxiliary layer is too small (for example, less than 10 nm), the improvement of the hillock problem of the aluminum alloy layer is not obvious. When the thickness of the auxiliary layer is too large (for example, greater than 60 nm), material waste will be formed to increase the cost. By adjusting the thickness of the auxiliary layer within the above range, for example, the thickness of the auxiliary layer can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 55 nm, 60 nm or a range formed by any two values therebetween, which can effectively improve the hillock problem of the aluminum alloy layer. Overall, the gate electrode in the thin-film transistor provided by the present application has lower resistance and is less likely to cause hillock problem, and the obtained thin-film transistor also has good electrical performance, thereby being beneficial to improving the display performance of the display panel and the display device.

[0031] In some embodiments of the present application, the thickness of the aluminum alloy layer is 200 nm-700 nm. When the thickness of the aluminum alloy layer is too small (for example, less than 200 nm), the resistance of the gate electrode cannot meet the needs of device switching. When the thickness of the aluminum alloy layer is too large (for example, greater than 700 nm), the thickness of the thin-film transistor increases, the cost increases, and mass production is not conducive. By adjusting the thickness of the aluminum alloy layer within the above range, for example, the thickness of the aluminum alloy layer is 200 nm, 225 nm, 250 nm, 275 nm, 300 nm, 325 nm, 350 nm, 375 nm, 400 nm, 500 nm, 600 nm, 700 nm or a range formed by any two values therebetween, which neither affects the performance of the thin-film transistor itself nor is conducive to cost control.

[0032] The material of the aluminum alloy layer is not particularly limited in the present application, as long as it has good electrical conductivity and can achieve the purpose of the present application. Exemplarily, the material of the aluminum alloy layer can adopt commercially available aluminum alloys that meet the above requirements, such as 5052 aluminum alloy, 5005 aluminum alloy, 5083 aluminum alloy, 5A05 aluminum alloy. The width of the gate electrode is not particularly limited in the present application and can be selected according to actual conditions, which is not limited in the present application.

[0033] The second aspect of the present application provides a method for preparing a thin film transistor, which comprises the following steps: providing a source layer, a source electrode, a drain electrode and a gate electrode; the method for preparing the gate electrode comprises the following steps: forming an auxiliary layer on the surface of the aluminum alloy layer to obtain the gate electrode, the material of the auxiliary layer is selected from TiN or Ti, and the thickness of the auxiliary layer is 10 nm-60 nm. Preferably, the step of forming the auxiliary layer on the surface of the aluminum alloy layer comprises: forming the auxiliary layer on the surface of the aluminum alloy layer by plasma sputter deposition, wherein the protective gas used in the plasma sputter deposition is a mixture of nitrogen and argon. Specifically, the material of the auxiliary layer is TiN, and the volume concentration of nitrogen is 50%-85%, for example, the volume concentration of nitrogen is 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85% or a range formed by any two of them. The material of the auxiliary layer is Ti, and the volume concentration of nitrogen is 0%. In the present application, when the annealing temperature of the thin film transistor during preparation is less than or equal to 400℃, the material of the auxiliary layer can be TiN or Ti; when the annealing temperature of the thin film transistor during preparation is greater than 400℃, the material of the auxiliary layer is TiN. The preparation method of the aluminum alloy layer can use the known preparation method of the gate electrode in the art, for example, the preparation method of the aluminum alloy layer can include but is not limited to plasma sputter deposition, atomic layer deposition (ALD) and the like.

[0034] It can be understood that the gate electrode also includes other steps known in the art during preparation, which is not limited in the present application. For example, the gate electrode also includes an etching process during preparation, and the setting of the auxiliary layer can effectively alleviate the damage problem caused by etching of the aluminum alloy layer, which is beneficial to improve the structural stability of the gate electrode itself.

[0035] It can be understood that the thin film transistor can also include other necessary or optional components or structures known in the art, which is not limited in the present application.

[0036] A third aspect of this application provides a display panel including a substrate and pixel units disposed on the substrate. Each pixel unit includes a thin-film transistor (TFT), a pixel electrode connected to the TFT, and a common electrode disposed opposite to the pixel electrode in the thickness direction of the display panel. The TFT is any of the TFTs described in the foregoing embodiments. This application does not specifically limit the display panel; it can be any display panel known in the art, and this application does not limit its scope. Exemplarily, the display panel can include, but is not limited to, any component with display functionality, such as a liquid crystal display panel. It is understood that the display panel may also include other necessary or optional components or structures known in the prior art, and this application does not limit its scope in this regard.

[0037] Specifically, such as Figure 2 The diagram shows a schematic of a display panel, comprising a first substrate 11, a polyimide layer 12, a buffer layer 13, a first gate insulating layer 141, a second gate insulating layer 142, a first interlayer insulating layer 16, a first planarization layer 17, a pixel definition layer 18, a first pixel electrode 25, a light-emitting layer 26, a common electrode 20, a first encapsulation layer 211, a second encapsulation layer 212, a third encapsulation layer 213, a first active layer 22 disposed in the first gate insulating layer 141, a first gate 151 and a third gate 153 disposed in the second gate insulating layer 142, a second gate 152 disposed in the first interlayer insulating layer 16, and a source 23 and a drain 24 disposed between the first gate insulating layer 141, the second gate insulating layer 142, the first interlayer insulating layer 16, and the first planarization layer 17. Alternatively, as shown... Figure 3As shown, it is a structural schematic diagram of another display panel, which includes a second substrate 31, a barrier layer 32, a first buffer layer 331, a third gate insulating layer 341, a second buffer layer 332, a fourth gate insulating layer 342, a second interlayer insulating layer 36, an inorganic protective layer 37, a second planarization layer 38, a light shielding layer 46 arranged in the first buffer layer 331, a second active layer 43 arranged in the third gate insulating layer 341, a fourth gate 351 and a fifth gate 352 arranged in the second buffer layer 332, a third active layer 40 arranged in the fourth gate insulating layer 342, a sixth gate 353 arranged in the second interlayer insulating layer 36, a seventh gate 354 (pixel electrode) arranged in the inorganic protective layer 37 and the second planarization layer 38, a first pixel definition layer 391, a second pixel definition layer 392 and a second common electrode 41 arranged on the second planarization layer 38, and a spacing layer 42 arranged on the second pixel definition layer 392, a first source 441 and a first drain 451 penetrating between the third gate insulating layer 341, the second buffer layer 332, the fourth gate insulating layer 342, the second interlayer insulating layer 36 and the inorganic protective layer 37, a second source 442 and a second drain 452 penetrating between the fourth gate insulating layer 342, the second interlayer insulating layer 36 and the inorganic protective layer 37. It can be understood that the above structure is only an example and does not impose any limitation on the present application. It can be understood that the materials and preparation methods of the above layers can adopt the materials and preparation methods known in the art, which are not limited in the present application.

[0038] The gate in the thin film transistor in any of the above embodiments can be used as at least one of the first gate 151, the second gate 152 and the third gate 153 in the display panel in the display device in the third aspect of the present application, and the aluminum alloy layer of the gate is closer to the first substrate 11 than the auxiliary layer. Figure 2 The gate in the thin film transistor in any of the above embodiments can be used as at least one of the fourth gate 351, the fifth gate 352, the sixth gate 353 and the seventh gate 354 in the display panel in the display device in the third aspect of the present application, and the aluminum alloy layer of the gate is closer to the second substrate 31 than the auxiliary layer. Figure 3 The gate in the thin film transistor in any of the above embodiments can be used as at least one of the fourth gate 351, the fifth gate 352, the sixth gate 353 and the seventh gate 354 in the display panel in the display device in the third aspect of the present application, and the aluminum alloy layer of the gate is closer to the second substrate 31 than the auxiliary layer.

[0039] The fourth aspect of the present application provides a display device including the display panel in any of the above embodiments. The display device is not particularly limited in the present application, and the display device can be a display panel and a display device known in the art, for example, the display device can include but is not limited to any product or component with display function such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

[0040] Test method and apparatus:

[0041] Test of sheet resistance (RS):

[0042] The samples in the examples and comparative examples were tested for sheet resistance by a four-probe tester (RT-3000).

[0043] Example 1

[0044] A sample was prepared by depositing an aluminum alloy layer with a thickness of 300 nm on a glass substrate by a plasma sputtering deposition method, and then forming an auxiliary layer with a thickness of 30 nm on the aluminum alloy layer by a plasma sputtering deposition method, wherein the protective gas during deposition of the aluminum alloy layer was argon; the protective gas during deposition of the auxiliary layer was a mixed gas of nitrogen and argon, the volume concentration of nitrogen was 0%; and the material of the aluminum alloy layer was 5052 aluminum alloy.

[0045] Examples 2 to 9

[0046] The rest was the same as Example 1 except that the relevant preparation parameters were adjusted according to Table 1.

[0047] Comparative Example 1

[0048] A sample was prepared by depositing a Mo metal layer with a thickness of 330 nm on a glass substrate by a plasma sputtering deposition method, wherein the protective gas during deposition of the Mo metal layer was argon.

[0049] Comparative Example 2

[0050] The rest was the same as Example 1 except that no auxiliary layer was deposited.

[0051] The relevant preparation parameters and performance tests of each example and comparative example are shown in Table 1.

[0052] Table 1

[0053]

[0054] Note: " / " in Table 1 indicates that the corresponding parameter does not exist.

[0055] As can be seen from Examples 1 to 9 and Comparative Example 1, the sample in the examples of the present application has a lower sheet resistance, indicating that the sample formed by the aluminum alloy layer and the auxiliary layer in the examples of the present application has a lower resistance as a gate electrode.

[0056] In addition, the 3D microscope photos of the samples in Comparative Example 2, Examples 1 to 3, and Example 5 are as follows: Figures 4a to 4eAs shown, it can be seen that the sample in Comparative Example 2 still has a significant hillock problem (i.e. there are many black spots in the 3D microscope photo), the hillock problem of the sample in Example 2 has been improved compared with Comparative Example 2, and the samples in Example 1, Example 3 and Example 5 basically do not have hillock problem, thereby indicating that the sample formed by the aluminum alloy layer and the auxiliary layer in the application can effectively improve the hillock problem as the gate electrode.

[0057] Etching test:

[0058] A sample A was prepared by depositing an aluminum alloy layer with a thickness of 466 nm on a glass substrate by plasma sputtering deposition method, and the preparation method was referred to Comparative Example 2; a sample B was prepared by first depositing an aluminum alloy layer with a thickness of 460 nm on a glass substrate by plasma sputtering deposition method, and then depositing a TiN auxiliary layer with a thickness of 49 nm, and the preparation method was referred to Example 3.

[0059] Figure 5a And Figure 5b The scanning electron microscope photos of sample A before and after etching are shown, and after HF etching for 20 s, the aluminum alloy damage thickness is 85 nm, and the thickness change rate is 18.2%. Figure 5c And Figure 5d The scanning electron microscope photos of sample B before and after etching are shown, and after HF etching for 20 s, the thickness change of sample B is only 6 nm, and the thickness change rate is only 1.9%. Thus, the sample provided in the application as the gate electrode can effectively alleviate the damage problem caused by etching, and is beneficial to improve the structural stability of the gate electrode itself. In addition, it should be noted that, in order to ensure the accuracy of the test, Figure 5a And Figure 5c The thicknesses of sample A and sample B in Comparative Example are thicker than those of the samples in the examples and comparative examples.

[0060] The sample in Example 3 was applied as a gate electrode in a display panel with the structure shown, and the specific preparation steps were as follows: Figure 2 The sample in Example 3 was applied as a gate electrode in a display panel with the structure shown, and the specific preparation steps were as follows:

[0061] (1) The glass substrate was initially cleaned, coated with polyimide (PI), and cured at 350°C to form a PI film with a thickness of 10 μm;

[0062] (2) then a buffer layer (the buffer layer is a SiN / SiO2 double-layer structure film) is deposited on the PI film by a plasma enhanced chemical vapor deposition (PECVD) method, a 200 nm silicon nitride layer is first deposited, and then a 200 nm silicon dioxide layer is deposited. Then, a 20 nm amorphous silicon layer (P-Si) is deposited, after the deposition of the amorphous silicon layer, the amorphous silicon layer is heated at a temperature of 400 ℃ for 2 hours. Then, the amorphous silicon layer is subjected to an excimer laser annealing (ELA) process, a polycrystalline silicon pattern is formed into a channel, and ion implantation is performed;

[0063] (3) then a GI1 layer is deposited, and the specific manufacturing process of the GI1 layer is as follows: a dielectric layer (the dielectric layer is a double-layer structure SiO 2 / SiN film) is deposited by a PECVD method, a 200 nm silicon oxide layer is first deposited, and then a 200 nm silicon nitride layer is deposited, and then an aluminum alloy layer is first deposited by a plasma sputtering (Sputter) method, and then an auxiliary layer is deposited to obtain a gate Gate1 (for a specific preparation method, refer to Embodiment 3), and then the gate Gate1 is patterned;

[0064] (4) then a GI2 film layer is deposited, and the specific manufacturing process of the film layer is as follows: a 200 nm SiN is deposited by a PECVD method, and then an aluminum alloy layer is first deposited by a plasma sputtering (Sputter) method, and then an auxiliary layer is deposited to obtain a gate Gate2 (for a specific preparation method, refer to Embodiment 3), and then the gate Gate2 is patterned;

[0065] (5) then an ILD layer is deposited, and the specific manufacturing process of the ILD layer is as follows: a dielectric layer (the dielectric layer is a double-layer structure SiO2 / SiN film) is deposited by a PECVD method, a 200 nm silicon oxide layer is first deposited, and then a 200 nm silicon nitride layer is deposited, the ILD layer is patterned, etching is performed by a one-step etching method, and then hydrogenation is performed;

[0066] (6) then an SD layer is deposited, and the specific manufacturing process is as follows: the SD layer is deposited by a Sputter method, 30 nm of Ti is first deposited, then 300 nm of Al is deposited, and then 30 nm of Ti is deposited, after patterning, annealing is performed in a N2 atmosphere at 100 ℃;

[0067] (7) then a PLN layer is deposited for planarization, and the specific manufacturing process is as follows: 1.5 μm of DL-1000-C (photoresist) is deposited by a Sputter method;

[0068] (8) then an AND layer is deposited, and the specific manufacturing process is as follows: 5 nm of indium tin oxide (ITO) is first deposited by a Sputter method, then 200 nm of Ag is deposited, and then 5 nm of ITO is deposited;

[0069] (9) Finally, a PDL layer is deposited and patterned. The detailed manufacturing process is as follows: a 1.5 μm DL-1000-C is deposited by sputtering to obtain the display panel 1.

[0070] The display panel 2 is prepared by using Mo metal (the detailed preparation method is referred to Comparative Example 1) as the material of Gate 1 and Gate 2, and the rest of the preparation method is the same as the above steps (1)-(9).

[0071] The display panel 1 and the display panel 2 obtained above are subjected to IV test, and the test results show that the display panel 1 using the sample in Example 3 as the gate electrode has a drift of 0.1, compared with the display panel 2 using the sample in Comparative Example 1 as the gate electrode, i.e., the current characteristic is more stable, which indicates that the sample in the above example applied to the display panel can improve the display performance of the display panel, and thus is conducive to improving the display performance of the display device.

[0072] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity from another entity, and do not necessarily require or imply any actual relationship or order between the entities. Moreover, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment.

[0073] Each embodiment in the specification is described in a relevant manner, and the same or similar parts between each embodiment can be referred to each other, and each embodiment focuses on the difference from other embodiments.

[0074] The above only describes the preferred embodiments of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of fabricating a thin film transistor comprising the steps of: A source layer, a source electrode, a drain electrode and a gate electrode are provided; The gate electrode is composed of an aluminum alloy layer and an auxiliary layer which are arranged in layers, and a preparation method of the gate electrode comprises the following steps: forming the auxiliary layer on the surface of the aluminum alloy layer to obtain the gate electrode, the material of the auxiliary layer is selected from TiN, and the thickness of the auxiliary layer is 10nm-60nm; The step of forming the auxiliary layer on the surface of the aluminum alloy layer comprises: forming the auxiliary layer on the surface of the aluminum alloy layer by a plasma sputtering deposition method, wherein the protective gas used in the plasma sputtering deposition method is a mixed gas of nitrogen and argon; and the volume concentration of the nitrogen is 50%-85%.

2. The production method according to claim 1, wherein The thickness of the aluminum alloy layer is 200nm-700nm.

3. A display panel comprising a substrate and a pixel unit arranged on the substrate, the pixel unit comprising a thin film transistor, a pixel electrode connected with the thin film transistor, and a common electrode arranged opposite to the pixel electrode in the thickness direction of the display panel, the thin film transistor being obtained by the preparation method according to any one of claims 1-2.

4. A display device comprising the display panel according to claim 3.

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