A semiconductor field effect transistor completely eliminating substrate assisted depletion effect

Abstract

The application relates to the field effect transistor technology field and discloses a semiconductor field effect transistor capable of completely eliminating the substrate auxiliary depletion effect, which comprises a P-type substrate, a super junction above the P-type substrate, an N-type buffer layer above the right side of the P-type substrate, a drain N heavy doping area above the right side of the N-type buffer layer, the drain N heavy doping area enabling the drain electrode to form an ohmic contact with the N-type buffer layer and the super junction comprising super junction P columns and super junction N columns, a P-type heavy doping area above the left side of the P-type substrate, a P well formed on the right side of the P-type heavy doping area, a source N heavy doping area formed in the P well, and the source electrode, the gate electrode and the drain electrode being distributed on the upper surface of the whole device. The application makes the surface electric field distribution of the substrate and the super junction consistent, eliminates the adverse effect of the substrate auxiliary depletion effect, improves the conduction characteristics of the device, increases the breakdown voltage of the device, effectively reduces the leakage current from the super junction to the substrate, and makes the device closer to the theoretical limit of the ideal super junction.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of field effect transistor technology, and particularly relates to a super-junction lateral double-diffused metal-oxide-semiconductor field effect transistor which completely eliminates substrate-assisted depletion effect. BACKGROUND

[0002] As the mainstream power semiconductor switching device in the field of small and medium-sized power electronics and the core electronic device of DC-DC conversion, the lateral double-diffused metal-oxide-semiconductor field effect transistor (LDMOS) has always been a research hotspot. When the power-exponent relationship between the specific on-resistance (R on,sp ) and the breakdown voltage (BV) representing the on-state characteristics of the LDMOS approaches the theoretical limit of silicon, the development of the LDMOS encounters a bottleneck. The emergence of the super-junction (SJ) concept provides a new way for the development of the LDMOS and has been widely studied. The main problem of the current super-junction LDMOS (SJ-LDMOS) is the influence of the substrate-assisted depletion effect on the super-junction N pillars and the super-junction P pillars in the super-junction. In recent years, researchers have proposed many optimization techniques for this problem. For example, a sapphire or diamond substrate is used, an SOI process is used, or an N-type buffer layer is added between the SJ layer and the substrate. The current difficulty is to reduce the R on,sp of the SJ-LDMOS in the lateral direction while ensuring the BV. The prior art CN104716190B discloses a new SJ-LDMOS device, which is manufactured on an N-type substrate epitaxial layer and introduces a P-type buried layer on the semi-super junction region. Compared with the traditional super-junction, the N region and the P-type buried layer jointly compensate for the charge imbalance between the N-type pillar region and the P-type pillar region in the super-junction, overcome the substrate-assisted effect, and improve the breakdown voltage. However, the inventors have found through further research that the presence of the substrate still hinders the SJ structure from achieving the theoretically optimal performance in the lateral device because the scheme sacrifices a part of the channel region and also reduces the concentration of the SJ due to compensation. In addition, the concentration of the P-type doped layer in the scheme is limited, and a large space charge region will be formed if the concentration is too large, which makes it difficult for the device to have the ideal characteristics of the SJ. SUMMARY

[0003] In view of the above problems in the prior art, the present application aims to provide a super-junction lateral double-diffused metal-oxide-semiconductor field effect transistor which completely eliminates the adverse effects of the substrate on the SJ layer and has a better relationship between the breakdown voltage and the specific on-resistance than the current SJ-LDMOS technology.

[0004] To achieve the above object, the present application adopts the following technical scheme:

[0005] The application discloses a semiconductor field effect transistor which completely eliminates the substrate auxiliary depletion effect, and comprises a P-type substrate, a super junction above the P-type substrate and containing super junction P columns and super junction N columns, an N-type buffer layer above the right of the P-type substrate, a drain N heavily doped region above the right of the N-type buffer layer and used for forming an ohmic contact between a drain electrode and the N-type buffer layer and the super junction containing the super junction P columns and the super junction N columns, a P-type heavily doped region above the left of the P-type substrate, a P well formed on the right of the P-type heavily doped region, a source N heavily doped region formed in the P well, and a source electrode, a gate electrode and a drain electrode distributed on the upper surface of the whole device, wherein the P-type heavily doped region is connected with the source electrode, and the drain N heavily doped region is connected with the drain electrode.

[0006] Preferably, the depth of the super junction is 3 microns, and the length of the super junction N column and the super junction P column is 15-25 microns.

[0007] Preferably, the width of the super junction N column and the super junction P column is 0.5 micron, the doping concentration of the super junction N column is 3*10 16 cm -3 , and the doping concentration of the super junction P column is 3*10 16 cm -3 .

[0008] Preferably, the length of the N-type buffer layer is 12 microns, the depth is 6 microns, and the doping concentration is 3*10 15 cm -3 .

[0009] Preferably, the length of the P-type buffer layer is 6 microns, the depth is 3 microns, and the doping concentration is 8*10 16 cm -3 .

[0010] Preferably, the length of the P-type heavily doped region is 3 microns, the depth is 5 microns, and the doping concentration is 8*10 16 cm -3 .

[0011] Preferably, the depth of the P well is 3 microns, and the length is 4 microns, and a source N heavily doped region is formed above the left of the P well.

[0012] Compared with the prior art, the application has the following beneficial effects

[0013] (1) The substrate auxiliary depletion effect is completely eliminated: in the application, the N-type buffer layer relieves the substrate auxiliary depletion effect through electric field modulation and forms a new electric field peak on the surface. Meanwhile, the substrate is connected with the source electrode and the drain electrode through ohmic contact on the left and right sides of the substrate, so that the substrate has source-drain voltage and is independently depleted, finally, the electric field distribution formed on the surface of the substrate through electric field modulation is similar to a rectangular electric field, the influence of the substrate on the electric field of the super junction layer is eliminated, and finally the substrate auxiliary depletion effect is completely eliminated.

[0014] (2) Breakdown voltage is greatly improved: N-type buffer layer can reduce the substrate to the super junction N column of depletion, reduce the super junction P column to the N-type heavily doped region of the drain of the electric field absorption, increase a new electric field peak on the device surface to improve the surface electric field distribution, the P heavily doped region is added to make the electric field distribution of the device close to the ideal rectangular, rather than the traditional triangular structure, thereby greatly improving the breakdown voltage of the device.

[0015] (3) On-state characteristics are greatly improved: N-type buffer layer increases the breakdown voltage by adding a new electric field peak. The surface electric field of the super junction layer has a similar distribution with the substrate electric field, which relieves the substrate auxiliary depletion effect to some extent, but does not completely eliminate. The proposed device connects the substrate with the source electrode and the drain electrode, and changes the substrate surface potential from zero to the same high voltage as the drain, so that the N-type buffer layer and the P well will completely deplete the substrate surface and form a similar electric field distribution with the super junction layer, thereby greatly reducing Ron,sp and improving the on-state characteristics.

[0016] (4) Can effectively weaken the leakage current from the super junction to the substrate: by adjusting the size and concentration of the left P-type heavily doped region, P well and right N-type buffer layer and N-type heavily doped region, the P-type substrate upper surface has the same electric field distribution as the upper surface of the super junction, and the equipotential line along the super junction and the substrate surface is vertically distributed, which can effectively suppress the leakage current from the super junction to the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0017] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the following drawings:

[0018] Figure 1 A schematic diagram of a semiconductor field effect transistor structure for completely eliminating the substrate auxiliary depletion effect of the present application;

[0019] In the figure: 1-P-type substrate, 2-P-type heavily doped region, 3-P well, 4-source N-type heavily doped region, 5-source electrode, 6-gate electrode, 7-drain electrode, 8-super junction P column, 9-super junction N column, 10-drain N heavily doped region, 11-N-type buffer layer. DETAILED DESCRIPTION

[0020] The present application will be described in detail below with specific embodiments. The following examples will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made. These all belong to the protection scope of the present application.

[0021] A semiconductor field effect transistor completely eliminating the substrate auxiliary depletion effect, comprising a P-type substrate 1, a super junction above the P-type substrate 1 and comprising super junction P columns 8 and super junction N columns 9, an N-type buffer layer 11 above the right of the P-type substrate 1, a drain N heavily doped region 10 above the right of the N-type buffer layer 11, the drain N heavily doped region 10 being used to form an ohmic contact between a drain electrode 7 and the N-type buffer layer 11 and the super junction comprising the super junction P columns 8 and the super junction N columns 9, a P-type heavily doped region 2 above the left of the P-type substrate 1, a P well 3 formed on the right of the P-type heavily doped region 2, a source N heavily doped region 4 formed in the P well 3, a source electrode 5, a gate electrode 6 and the drain electrode 7 distributed on the upper surface of the whole device, the P-type heavily doped region 2 being connected with the source electrode 5, and the drain N heavily doped region 10 being connected with the drain electrode 7.

[0022] The depth of the super junction is 3 microns, the length of the super junction N column and the super junction P column is 15-25 microns, the width of the super junction N column and the super junction P column is 0.5 microns, the doping concentration of the super junction N column is 3*10 16 cm -3 , the doping concentration of the super junction P column is 3*10 16 cm -3 ; the length of the N-type buffer layer is 12 microns, the depth is 6 microns, and the doping concentration is 3*10 15 cm -3 ; the length of the P-type buffer layer 2 is 6 microns, the depth is 3 microns, and the doping concentration is 8*10 16 cm -3 ; the length of the P-type heavily doped region is 3 microns, the depth is 5 microns, and the doping concentration is 8*10 16 cm -3 ; the depth of the P well is 3 microns, and the length is 4 microns, and the source N heavily doped region is formed above the left of the P well.

[0023] The simulation experiment results show that when the length of the super junction N column and the super junction P column is 20 microns, the breakdown voltage of the ordinary SJ-LDMOS device is 362.5 V, and the specific on-resistance is 29.04 mΩ*cm 2 . Under the same length of the super junction N column and the super junction P column, the breakdown voltage of the SJ-LDMOS proposed in the application is 470.7 V, and the specific on-resistance is 11.28 mΩ*cm 2 . The device of the application can reduce the specific on-resistance by 61.16% and increase the breakdown voltage by 108.2 V.

[0024] In addition, the main processes involved in the preparation of the device of the application include epitaxy, etching, ion implantation and diffusion, which are compatible with the current mainstream silicon-based processes, so the process difficulty and cost are relatively low, and it is more conducive to application and production.

[0025] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the specific embodiments described above, and various modifications or changes can be made by those skilled in the art within the scope of the claims, which do not affect the essence of the present application.

Claims

1. A semiconductor field-effect transistor that completely eliminates substrate-assisted depletion effect, characterized in that, The substrate includes a P-type substrate, above which is a superjunction comprising superjunction P-pillars and superjunction N-pillars. Above and to the right of the P-type substrate is an N-type buffer layer, which has a length of 12 μm, a depth of 6 μm, and a doping concentration of 3 × 10⁻⁶. 15 cm -3 The upper right of the N-type buffer layer is a heavily doped N-type drain region, which is used to form an ohmic contact between the drain electrode and the N-type buffer layer and the superjunction containing the superjunction P-pillar and the superjunction N-pillar. The upper left of the P-type substrate is a heavily doped P-type region, which is 3 μm long, 5 μm deep, and has a doping concentration of 8 × 10⁻⁶. 16 cm -3 A P-well is formed on the right side of the P-type heavily doped region. The P-well has a depth of 3 μm and a length of 4 μm. A source N-type heavily doped region is formed on the upper left of the P-well. The source electrode, gate electrode, and drain electrode are distributed on the entire upper surface of the device. The P-type heavily doped region is connected to the source electrode, and the drain N-type heavily doped region is connected to the drain electrode.

2. The semiconductor field-effect transistor that completely eliminates substrate-assisted depletion effect according to claim 1, characterized in that, The superjunction depth is 3 μm, and the lengths of the superjunction N-pillar and superjunction P-pillar are 15-25 μm.

3. The semiconductor field-effect transistor that completely eliminates substrate-assisted depletion effect according to claim 1, characterized in that, The width of both the superjunction N-pillar and the superjunction P-pillar is 0.5 μm, and the doping concentration of the superjunction N-pillar is 3 × 10⁻⁶. 16 cm -3 The doping concentration of the superjunction P-pillar is 3 × 10⁻⁶. 16 cm -3 .

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