Polysilicon-insulator-polysilicon capacitor and manufacturing method thereof

Abstract

The present invention discloses a polysilicon-insulator-polysilicon capacitor and a manufacturing method thereof, wherein the polysilicon-insulator-polysilicon capacitor includes a substrate having a capacitor forming region; a first capacitor dielectric layer disposed on the capacitor forming region; a first polysilicon electrode disposed on the first capacitor dielectric layer; a second capacitor dielectric layer disposed on the first polysilicon electrode; a second polysilicon electrode disposed on the second capacitor dielectric layer; a third polysilicon electrode disposed on a first sidewall adjacent to the second polysilicon electrode; a third capacitor dielectric layer disposed between the third polysilicon electrode and the second polysilicon electrode; a fourth polysilicon electrode disposed on a second sidewall adjacent to the second polysilicon electrode; and a fourth capacitor dielectric layer disposed between the fourth polysilicon electrode and the second polysilicon electrode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a polysilicon-insulator-poly (PIP) capacitor and a manufacturing method thereof. Background Art

[0002] As semiconductor device integration increases, device size gradually shrinks, which in turn reduces the space available for integrated capacitors within semiconductor chips. This reduces the capacitance of these capacitors, and the problem of reduced capacitance becomes even more severe as we move into deep sub-micron processes.

[0003] With current 55 nanometer technology nodes, the integrated capacitor in the semiconductor chip mainly adopts metal-oxide-metal (metal-oxide-metal, MOM) multilayer stack structure of lateral coupling to make.In order to withstand higher operating voltage, need to have wider width between the metal stack of high voltage (>5V) MOM capacitor, so unit capacitance can be littler, and MOM capacitor can take up a large amount of area.For very high voltage (for example, >10V) MOM capacitor, the vertical breakdown between the upper and lower metal becomes bottleneck, and in order to increase breakdown voltage BV, sometimes need to skip middle metal layer, cause unit capacitance value further to reduce. Summary of the Invention

[0004] The main purpose of the present invention is to provide a high-voltage resistant polysilicon-insulator-polysilicon (PIP) capacitor and a manufacturing method thereof, so as to solve the above-mentioned deficiencies and shortcomings of the prior art.

[0005] In one aspect, the present invention provides a PIP capacitor, comprising: a semiconductor substrate having a capacitor formation region thereon; a first capacitor dielectric layer disposed on the capacitor formation region; a first polysilicon electrode disposed on the first capacitor dielectric layer; a second capacitor dielectric layer disposed on the first polysilicon electrode; a second polysilicon electrode disposed on the second capacitor dielectric layer, wherein the first polysilicon electrode includes a contact portion that protrudes beyond an end surface of the second polysilicon electrode; a third polysilicon electrode disposed adjacent to a first sidewall of the second polysilicon electrode; a third capacitor dielectric layer disposed between the third polysilicon electrode and the second polysilicon electrode; a fourth polysilicon electrode disposed adjacent to a second sidewall of the second polysilicon electrode, wherein the second sidewall and the first sidewall are opposite; and a fourth capacitor dielectric layer disposed between the fourth polysilicon electrode and the second polysilicon electrode.

[0006] According to an embodiment of the present invention, the first polysilicon electrode, the third polysilicon electrode, and the fourth polysilicon electrode are electrically connected to an anode.

[0007] According to an embodiment of the present invention, the second polysilicon electrode is electrically connected to a cathode, and wherein the third polysilicon electrode, the third capacitor dielectric layer and the second polysilicon electrode constitute a first capacitor, the first polysilicon electrode, the second capacitor dielectric layer and the second polysilicon electrode constitute a second capacitor, and the second polysilicon electrode, the fourth capacitor dielectric layer and the fourth polysilicon electrode constitute a third capacitor.

[0008] According to an embodiment of the present invention, an ion trap is arranged in the capacitor forming area and is electrically connected to the cathode, wherein the third polysilicon electrode, the first capacitor dielectric layer and the ion trap constitute a fourth capacitor, and the first polysilicon electrode, the first capacitor dielectric layer and the ion trap constitute a fifth capacitor.

[0009] According to an embodiment of the present invention, the fifth capacitor dielectric layer is arranged between the fourth polysilicon electrode and the semiconductor substrate, wherein the fifth capacitor dielectric layer is thicker than the first capacitor dielectric layer, and wherein the fourth polysilicon electrode, the fifth capacitor dielectric layer and the ion trap constitute a sixth capacitor.

[0010] According to the embodiment of the present invention, a width of the first polysilicon electrode is greater than a width of the second polysilicon electrode.

[0011] According to an embodiment of the present invention, the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer include oxide-nitride-oxide dielectric layers.

[0012] According to an embodiment of the present invention, a hard mask layer is further included, covering the second polysilicon electrode, wherein a top surface of the hard mask layer is flush with a top surface of the fourth polysilicon electrode.

[0013] According to an embodiment of the present invention, the third capacitor dielectric layer and the fourth capacitor dielectric layer directly contact a top surface of the first polysilicon electrode.

[0014] According to an embodiment of the present invention, the capacitor forming region is a trench isolation region.

[0015] Another aspect of the present invention provides a method for forming a PIP capacitor, comprising: providing a semiconductor substrate including a capacitor forming region; forming a first capacitor dielectric layer on the capacitor forming region; forming a first polysilicon electrode on the first capacitor dielectric layer; forming a second capacitor dielectric layer on the first polysilicon electrode; forming a second polysilicon electrode on the second capacitor dielectric layer; forming a third polysilicon electrode adjacent to a first sidewall of the second polysilicon electrode; forming a third capacitor dielectric layer between the third polysilicon electrode and the second polysilicon electrode; forming a fourth polysilicon electrode adjacent to a second sidewall of the second polysilicon electrode, wherein the second sidewall and the first sidewall are opposite; and forming a fourth capacitor dielectric layer between the fourth polysilicon electrode and the second polysilicon electrode.

[0016] According to an embodiment of the present invention, the first polysilicon electrode, the third polysilicon electrode, and the fourth polysilicon electrode are electrically connected to an anode.

[0017] According to an embodiment of the present invention, the second polysilicon electrode is electrically connected to a cathode, and wherein the third polysilicon electrode, the third capacitor dielectric layer and the second polysilicon electrode constitute a first capacitor, the first polysilicon electrode, the second capacitor dielectric layer and the second polysilicon electrode constitute a second capacitor, and the second polysilicon electrode, the fourth capacitor dielectric layer and the fourth polysilicon electrode constitute a third capacitor.

[0018] According to an embodiment of the present invention, it further includes: forming an ion trap in the capacitor forming area, wherein the ion trap is electrically connected to the cathode, and wherein the third polysilicon electrode, the first capacitor dielectric layer and the ion trap constitute a fourth capacitor, and the first polysilicon electrode, the first capacitor dielectric layer and the ion trap constitute a fifth capacitor.

[0019] According to an embodiment of the present invention, the method further includes forming a fifth capacitor dielectric layer between the fourth polysilicon electrode and the semiconductor substrate, wherein the fifth capacitor dielectric layer is thicker than the first capacitor dielectric layer, and wherein the fourth polysilicon electrode, the fifth capacitor dielectric layer and the ion trap constitute a sixth capacitor.

[0020] According to the embodiment of the present invention, a width of the first polysilicon electrode is greater than a width of the second polysilicon electrode.

[0021] According to an embodiment of the present invention, the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer include oxide-nitride-oxide dielectric layers.

[0022] According to an embodiment of the present invention, the method further includes forming a hard mask layer to cover the second polysilicon electrode, wherein a top surface of the hard mask layer is flush with a top surface of the fourth polysilicon electrode.

[0023] According to an embodiment of the present invention, the third capacitor dielectric layer and the fourth capacitor dielectric layer directly contact a top surface of the first polysilicon electrode.

[0024] According to an embodiment of the present invention, the capacitor forming region is a trench isolation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A cross-sectional schematic diagram of a PIP capacitor according to an embodiment of the present invention;

[0026] Figure 2 for Figure 1 Side perspective view of the PIP capacitor;

[0027] Figure 3 for Figure 1 Equivalent circuit diagram of PIP capacitor;

[0028] Figures 4 to 8 FIG2 is a cross-sectional schematic diagram of a method for forming a PIP capacitor according to an embodiment of the present invention.

[0029] Explanation of symbols

[0030] 1 integrated capacitor

[0031] 1a, 1b PIP capacitors

[0032] 100 semiconductor substrate

[0033] 101 Ion Trap

[0034] C1 first capacitor

[0035] C2 Second capacitor

[0036] C3 third capacitor

[0037] C4 fourth capacitor

[0038] C5 fifth capacitor

[0039] C6 Sixth capacitor

[0040] CA Capacitance formation area

[0041] CL midline

[0042] CP contact part

[0043] CT, CT1~CT4 contact plugs

[0044] DL1 first capacitor dielectric layer

[0045] DL2 Second capacitor dielectric layer

[0046] DL3 third capacitor dielectric layer

[0047] DL4 fourth capacitor dielectric layer

[0048] DL5 Fifth capacitor dielectric layer

[0049] ES end face

[0050] HM hard mask layer

[0051] IL interlayer dielectric layer

[0052] P1 first polysilicon electrode

[0053] P2 second polysilicon electrode

[0054] P3 third polysilicon electrode

[0055] P4 fourth polysilicon electrode

[0056] PL1 first polysilicon layer

[0057] PL2 second polysilicon layer

[0058] Top surfaces of S1, S2, and S4

[0059] SP1 First spacer

[0060] SP2 Second spacer

[0061] ST1 first stacking structure

[0062] ST2 Second stacking structure

[0063] SW1 First side wall

[0064] SW2 Second side wall DETAILED DESCRIPTION

[0065] Hereinafter, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a manner that describes specific examples of the embodiments that can be implemented. The following embodiments are described in sufficient detail to enable a person skilled in the art to implement them.

[0066] Of course, other embodiments may be employed, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments contained therein are to be defined by the appended claims.

[0067] See also Figures 1 to 3 ,in, Figure 1 FIG. 1 is a cross-sectional diagram of a PIP capacitor according to an embodiment of the present invention. Figure 2 for Figure 1 Side view of the PIP capacitor. Figure 3 for Figure 1 Equivalent circuit diagram of PIP capacitor. Figure 1 As shown, the integrated capacitor 1 of the present invention includes two PIP capacitors 1a and 1b that are mirror-symmetrical with respect to the center line CL, and are formed in the capacitor forming region CA of the semiconductor substrate 100. According to an embodiment of the present invention, the capacitor forming region CA may include an ion well 101, such as an N-type well. In other embodiments, the capacitor forming region CA may include a trench isolation region, such as a shallow trench isolation structure. The following description takes the PIP capacitor 1a as an example. Figure 2 , only the PIP capacitor 1a is shown for illustration.

[0068] like Figure 1 and Figure 2 As shown, a first capacitor dielectric layer DL1 is formed on the capacitor forming area CA. A first polysilicon electrode P1 is provided on the first capacitor dielectric layer DL1. A second capacitor dielectric layer DL2 is provided on the first polysilicon electrode P1. A second polysilicon electrode P2 is provided on the second capacitor dielectric layer DL2. Figure 2 As shown, the first polysilicon electrode P1 includes a contact portion CP, and the contact portion CP protrudes beyond an end surface ES of the second polysilicon electrode P2. A third polysilicon electrode P3 is disposed on a first sidewall SW1 adjacent to the second polysilicon electrode P2. A third capacitor dielectric layer DL3 is disposed between the third polysilicon electrode P3 and the second polysilicon electrode P2. A fourth polysilicon electrode P4 is disposed on a second sidewall SW2 adjacent to the second polysilicon electrode P2. The second sidewall SW2 and the first sidewall SW1 are opposite sidewalls. A fourth capacitor dielectric layer DL4 is disposed between the fourth polysilicon electrode P4 and the second polysilicon electrode P2.

[0069] According to an embodiment of the present invention, Figure 2 As shown, the first polysilicon electrode P1, the third polysilicon electrode P3 and the fourth polysilicon electrode P4 are electrically connected to an anode through contact plugs CT1, CT3 and CT4, respectively. Figure 2 As shown, the second polysilicon electrode P2 is electrically connected to a cathode through a contact plug CT2, wherein Figure 1As shown, the third polysilicon electrode P3, the third capacitor dielectric layer DL3, and the second polysilicon electrode P2 form a first capacitor C1, the first polysilicon electrode P1, the second capacitor dielectric layer DL2, and the second polysilicon electrode P2 form a second capacitor C2, and the second polysilicon electrode P2, the fourth capacitor dielectric layer DL4, and the fourth polysilicon electrode P4 form a third capacitor C3. According to an embodiment of the present invention, the ion trap 101 is electrically connected to the cathode via a contact plug CT, wherein the third polysilicon electrode P3, the first capacitor dielectric layer DL1, and the ion trap 101 form a fourth capacitor C4, and the first polysilicon electrode P1, the first capacitor dielectric layer DL1, and the ion trap 101 form a fifth capacitor C5.

[0070] According to an embodiment of the present invention, a fifth capacitor dielectric layer DL5 is disposed between the fourth polysilicon electrode P4 and the ion well 101 of the semiconductor substrate 100, wherein the fifth capacitor dielectric layer DL5 is thicker than the first capacitor dielectric layer DL1, and wherein the fourth polysilicon electrode P4, the fifth capacitor dielectric layer DL5 and the ion well 101 constitute a sixth capacitor C6. Figure 3 As shown, the first capacitor C1 to the sixth capacitor C6 constitute a parallel capacitor configuration.

[0071] According to an embodiment of the present invention, Figure 1 As shown, the width of the first polysilicon electrode P1 is slightly greater than the width of the second polysilicon electrode P2. According to an embodiment of the present invention, the second capacitor dielectric layer DL2, the third capacitor dielectric layer DL3, and the fourth capacitor dielectric layer DL4 comprise oxide-nitride-oxide (ONO) dielectric layers. According to an embodiment of the present invention, the PIP capacitor 1a further includes a hard mask layer HM covering the second polysilicon electrode P2, wherein a top surface S2 of the hard mask layer HM is flush with a top surface S4 of the fourth polysilicon electrode P4. According to an embodiment of the present invention, the third capacitor dielectric layer DL3 and the fourth capacitor dielectric layer DL4 directly contact a top surface S1 of the first polysilicon electrode P1.

[0072] See also Figures 4 to 8 , which is a cross-sectional schematic diagram of a method for forming a PIP capacitor according to an embodiment of the present invention, wherein the same regions, layers and components are still represented by the same reference numerals. Figure 4As shown, first, a semiconductor substrate 100 is provided, which includes a capacitor forming region CA. The capacitor forming region CA of the semiconductor substrate 100 may include an ion well 101, such as an N-type well. In other embodiments, the capacitor forming region CA may include a trench isolation region, such as a trench insulation structure. A first capacitor dielectric layer DL1, a first polysilicon layer PL1, a second capacitor dielectric layer DL2, a second polysilicon layer PL2, and a hard mask layer HM are sequentially formed on the capacitor forming region CA. According to an embodiment of the present invention, for example, the first capacitor dielectric layer DL1 may be a silicon oxide layer.

[0073] The second capacitor dielectric layer DL2 may be an ONO dielectric layer, and the hard mask layer HM may be a silicon nitride layer, but is not limited thereto. According to an embodiment of the present invention, for example, the second polysilicon layer PL2 may be thicker than the first polysilicon layer PL1, but is not limited thereto.

[0074] like Figure 5 As shown, photolithography and etching processes are then performed to etch the hard mask layer HM, the second polysilicon layer PL2, and the second capacitor dielectric layer DL2. A first stacked structure ST1 is defined on the first polysilicon layer PL1, comprising the second capacitor dielectric layer DL2, the second polysilicon electrode P2, and the hard mask layer HM. Next, first spacers SP1, such as silicon oxide-nitride (ON) spacers, are formed on opposite sidewalls of the first stacked structure ST1.

[0075] like Figure 6 As shown, the photolithography and etching process is continued to etch the first polysilicon layer PL1, and a second stacked structure ST2 is defined on the first capacitor dielectric layer DL1, including a first polysilicon electrode P1, a second capacitor dielectric layer DL2, a second polysilicon electrode P2, a hard mask layer HM and a first spacer SP1. According to an embodiment of the present invention, the sidewall of the first polysilicon electrode P1 is approximately flush with the outer surface of the first spacer SP1. According to an embodiment of the present invention, the width of the first polysilicon electrode P1 is greater than the width of the second polysilicon electrode P2. According to an embodiment of the present invention, Figure 2 As shown, the first polysilicon electrode P1 includes a contact portion CP, and the contact portion CP protrudes beyond an end surface ES of the second polysilicon electrode P2.

[0076] like Figure 7As shown, second spacers SP2, such as silicon oxide spacers, are then formed on both side walls of the second stacked structure ST2. Then, a third polysilicon electrode P3 and a fourth polysilicon electrode P4 are formed on both sides of the second stacked structure ST2. The third polysilicon electrode P3 and the fourth polysilicon electrode P4 can be formed, for example, by first depositing a polysilicon layer over the entire surface and then performing a chemical mechanical polishing (CMP) process to flatten the polysilicon layer until the hard mask layer HM is exposed. According to an embodiment of the present invention, a top surface S2 of the hard mask layer HM is flush with a top surface S4 of the fourth polysilicon electrode P4.

[0077] like Figure 8 As shown, a deposition process is finally performed, such as a chemical vapor deposition (CVD) process, to deposit an interlayer dielectric layer IL on the semiconductor substrate 100. Then, a development process and an etching process are used to form contact plugs CT, CT1-CT2 in the interlayer dielectric layer IL. T4 , so that the first polysilicon electrode P1, the third polysilicon electrode P3 and the fourth polysilicon electrode P4 are electrically connected to the anode through the contact plugs CT1, CT3 and CT4 respectively, and the ion trap 101 and the second polysilicon electrode P2 are electrically connected to the cathode through the contact plugs CT and CT2 respectively.

[0078] The primary advantage of the present invention is that it can form high-density PIP capacitors with high capacitance and high voltage resistance (e.g., >10V) in the front-end of a semiconductor fabrication process. Furthermore, the PIP capacitor fabrication method of the present invention is compatible with embedded flash memory fabrication processes, such as the ESF3 (third-generation SuperFlash) platform.

[0079] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A polysilicon-insulator-polysilicon capacitor, characterized in that: Include: a semiconductor substrate having a capacitor forming region thereon; A first capacitor dielectric layer is provided on the capacitor forming region; a first polysilicon electrode, disposed on the first capacitor dielectric layer; a second capacitor dielectric layer, disposed on the first polysilicon electrode; a second polysilicon electrode disposed on the second capacitor dielectric layer, wherein the first polysilicon electrode includes a contact portion protruding beyond an end surface of the second polysilicon electrode; a third polysilicon electrode disposed adjacent to the first sidewall of the second polysilicon electrode, wherein the third polysilicon electrode faces the third sidewall of the first polysilicon electrode; a third capacitor dielectric layer, disposed between the third polysilicon electrode and the second polysilicon electrode; a fourth polysilicon electrode disposed adjacent to a second sidewall of the second polysilicon electrode, wherein the second sidewall is opposite to the first sidewall; as well as A fourth capacitor dielectric layer is arranged between the fourth polysilicon electrode and the second polysilicon electrode, wherein the first polysilicon electrode, the third polysilicon electrode and the fourth polysilicon electrode are electrically connected to the anode, and the second polysilicon electrode is electrically connected to the cathode, and wherein the third polysilicon electrode, the third capacitor dielectric layer and the second polysilicon electrode constitute a first capacitor, the first polysilicon electrode, the second capacitor dielectric layer and the second polysilicon electrode constitute a second capacitor, the second polysilicon electrode, the fourth capacitor dielectric layer and the fourth polysilicon electrode constitute a third capacitor, and an ion trap is arranged in the capacitor formation area and is electrically connected to the cathode, and wherein the third polysilicon electrode, the first capacitor dielectric layer and the ion trap constitute a fourth capacitor, and the first polysilicon electrode, the first capacitor dielectric layer and the ion trap constitute a fifth capacitor.

2. The polysilicon-insulator-polysilicon capacitor according to claim 1, wherein: The fourth polysilicon electrode faces the fourth side wall of the first polysilicon electrode, the fourth side wall and the third side wall of the first polysilicon electrode are opposite, and the fifth capacitor dielectric layer is arranged between the fourth polysilicon electrode and the semiconductor substrate, wherein the fifth capacitor dielectric layer is thicker than the first capacitor dielectric layer, and wherein the fourth polysilicon electrode, the fifth capacitor dielectric layer and the ion trap constitute a sixth capacitor.

3. The polysilicon-insulator-polysilicon capacitor according to claim 1, wherein: The width of the first polysilicon electrode is greater than the width of the second polysilicon electrode.

4. The polysilicon-insulator-polysilicon capacitor according to claim 1, wherein: The second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer include oxide-nitride-oxide dielectric layers.

5. The polysilicon-insulator-polysilicon capacitor of claim 1, wherein: The invention further comprises a hard mask layer covering the second polysilicon electrode, wherein the top surface of the hard mask layer is flush with the top surface of the fourth polysilicon electrode.

6. The polysilicon-insulator-polysilicon capacitor of claim 1, wherein: The third capacitor dielectric layer and the fourth capacitor dielectric layer directly contact the top surface of the first polysilicon electrode.

7. The polysilicon-insulator-polysilicon capacitor of claim 1, wherein: The capacitance forming region is a trench isolation region.

8. A method of forming a polysilicon-insulator-polysilicon capacitor, comprising: Providing a semiconductor substrate including a capacitor forming region; forming a first capacitor dielectric layer on the capacitor forming region; forming a first polysilicon electrode on the first capacitor dielectric layer; forming a second capacitor dielectric layer on the first polysilicon electrode; forming a second polysilicon electrode on the second capacitor dielectric layer; forming a third polysilicon electrode adjacent to the first sidewall of the second polysilicon electrode, wherein the third polysilicon electrode faces the third sidewall of the first polysilicon electrode; forming a third capacitor dielectric layer between the third polysilicon electrode and the second polysilicon electrode; forming a fourth polysilicon electrode adjacent to a second sidewall of the second polysilicon electrode, wherein the second sidewall is opposite to the first sidewall; A fourth capacitor dielectric layer is formed between the fourth polysilicon electrode and the second polysilicon electrode, wherein: The first polysilicon electrode, the third polysilicon electrode, and the fourth polysilicon electrode are electrically connected to an anode, and the second polysilicon electrode is electrically connected to a cathode, wherein the third polysilicon electrode, the third capacitor dielectric layer, and the second polysilicon electrode constitute a first capacitor, the first polysilicon electrode, the second capacitor dielectric layer, and the second polysilicon electrode constitute a second capacitor, and the second polysilicon electrode, the fourth capacitor dielectric layer, and the fourth polysilicon electrode constitute a third capacitor; and An ion trap is formed in the capacitor forming region, wherein the ion trap is electrically connected to the cathode, and wherein the third polysilicon electrode, the first capacitor dielectric layer and the ion trap constitute a fourth capacitor, and the first polysilicon electrode, the first capacitor dielectric layer and the ion trap constitute a fifth capacitor.

9. The method of claim 8, further comprising: A fifth capacitor dielectric layer is formed between the fourth polysilicon electrode and the semiconductor substrate, wherein the fourth polysilicon electrode faces the fourth sidewall of the first polysilicon electrode, the fourth sidewall and the third sidewall of the first polysilicon electrode are opposite, the fifth capacitor dielectric layer is thicker than the first capacitor dielectric layer, and the fourth polysilicon electrode, the fifth capacitor dielectric layer and the ion trap constitute a sixth capacitor.

10. The method of claim 8, wherein: The width of the first polysilicon electrode is greater than the width of the second polysilicon electrode.

11. The method of claim 8, wherein: The second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer include oxide-nitride-oxide dielectric layers.

12. The method of claim 8, further comprising: A hard mask layer is formed to cover the second polysilicon electrode, wherein a top surface of the hard mask layer is flush with a top surface of the fourth polysilicon electrode.

13. The method of claim 8, wherein: The third capacitor dielectric layer and the fourth capacitor dielectric layer directly contact the top surface of the first polysilicon electrode.

14. The method of claim 8, wherein: The capacitance forming region is a trench isolation region.

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